Changeset 103589 in vbox
- Timestamp:
- Feb 27, 2024 4:14:12 PM (7 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 5 edited
-
VMMAll/IEMAllInstOneByte.cpp.h (modified) (5 diffs)
-
VMMAll/IEMAllInstPython.py (modified) (1 diff)
-
VMMAll/IEMAllInstTwoByte0f.cpp.h (modified) (2 diffs)
-
VMMAll/IEMAllN8veRecompiler.cpp (modified) (2 diffs)
-
include/IEMN8veRecompiler.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h
r103548 r103589 10355 10355 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 0); 10356 10356 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 1); 10357 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, 0, iemCImpl_fldenv, enmEffOpSize, iEffSeg, GCPtrEffSrc); 10357 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw), 10358 iemCImpl_fldenv, enmEffOpSize, iEffSeg, GCPtrEffSrc); 10358 10359 IEM_MC_END(); 10359 10360 } … … 10375 10376 IEM_MC_FETCH_MEM_U16(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 10376 10377 10377 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_FPU, 0, iemCImpl_fldcw, u16Fsw); 10378 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw), 10379 iemCImpl_fldcw, u16Fsw); 10378 10380 IEM_MC_END(); 10379 10381 } … … 11723 11725 IEMOP_MNEMONIC(fninit, "fninit"); 11724 11726 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11725 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_FPU, 0, iemCImpl_finit, false /*fCheckXcpts*/); 11727 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw), 11728 iemCImpl_finit, false /*fCheckXcpts*/); 11726 11729 } 11727 11730 … … 12264 12267 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 0); 12265 12268 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 1); 12266 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, 0, iemCImpl_frstor, enmEffOpSize, iEffSeg, GCPtrEffSrc); 12269 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw), 12270 iemCImpl_frstor, enmEffOpSize, iEffSeg, GCPtrEffSrc); 12267 12271 IEM_MC_END(); 12268 12272 } … … 12283 12287 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 0); 12284 12288 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 1); 12285 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, 0, iemCImpl_fnsave, enmEffOpSize, iEffSeg, GCPtrEffDst); 12289 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw), 12290 iemCImpl_fnsave, enmEffOpSize, iEffSeg, GCPtrEffDst); 12286 12291 IEM_MC_END(); 12287 12292 } -
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r103588 r103589 2962 2962 'IEM_MC_FETCH_EFLAGS': (McBlock.parseMcGeneric, False, False, True, ), 2963 2963 'IEM_MC_FETCH_EFLAGS_U8': (McBlock.parseMcGeneric, False, False, False, ), 2964 'IEM_MC_FETCH_FCW': (McBlock.parseMcGeneric, False, False, False,),2964 'IEM_MC_FETCH_FCW': (McBlock.parseMcGeneric, False, False, True, ), 2965 2965 'IEM_MC_FETCH_FSW': (McBlock.parseMcGeneric, False, False, False, ), 2966 2966 'IEM_MC_FETCH_GREG_U16': (McBlock.parseMcGeneric, False, False, True, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h
r103588 r103589 10029 10029 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0); 10030 10030 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/pVCpu->iem.s.enmEffOpSize, 2); 10031 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, 0, iemCImpl_fxrstor, iEffSeg, GCPtrEff, enmEffOpSize); 10031 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw), 10032 iemCImpl_fxrstor, iEffSeg, GCPtrEff, enmEffOpSize); 10032 10033 IEM_MC_END(); 10033 10034 } … … 10152 10153 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0); 10153 10154 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 2); 10154 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, 0, iemCImpl_xrstor, iEffSeg, GCPtrEff, enmEffOpSize); 10155 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw), 10156 iemCImpl_xrstor, iEffSeg, GCPtrEff, enmEffOpSize); 10155 10157 IEM_MC_END(); 10156 10158 } -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
r103588 r103589 3499 3499 /* [kIemNativeGstReg_Pc] = */ { CPUMCTX_OFF_AND_SIZE(rip), "rip", }, 3500 3500 /* [kIemNativeGstReg_Cr0] = */ { CPUMCTX_OFF_AND_SIZE(cr0), "cr0", }, 3501 /* [kIemNativeGstReg_ LivenessPadding18] = */ { UINT32_MAX / 4, 0, "pad18", },3501 /* [kIemNativeGstReg_FpuFcw] = */ { CPUMCTX_OFF_AND_SIZE(XState.x87.FCW), "fcw", }, 3502 3502 /* [kIemNativeGstReg_LivenessPadding19] = */ { UINT32_MAX / 4, 0, "pad19", }, 3503 3503 /* [kIemNativeGstReg_SegBaseFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[0].u64Base), "es_base", }, … … 13259 13259 return off; 13260 13260 } 13261 13262 13263 13264 /********************************************************************************************************************************* 13265 * Emitters for FPU related operations. * 13266 *********************************************************************************************************************************/ 13267 13268 #define IEM_MC_FETCH_FCW(a_u16Fcw) \ 13269 off = iemNativeEmitFetchFpuFcw(pReNative, off, a_u16Fcw) 13270 13271 /** Emits code for IEM_MC_FETCH_FCW. */ 13272 DECL_INLINE_THROW(uint32_t) 13273 iemNativeEmitFetchFpuFcw(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar) 13274 { 13275 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar); 13276 Assert(pReNative->Core.aVars[idxDstVar].cbVar == sizeof(uint16_t)); 13277 13278 /* Allocate a temporary FCW register. */ 13279 uint8_t const idxFcwReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_FpuFcw, kIemNativeGstRegUse_ReadOnly); 13280 13281 off = iemNativeEmitLoadGprFromGpr16(pReNative, off, idxDstVar, idxFcwReg); 13282 13283 /* Free but don't flush the FCW register. */ 13284 iemNativeRegFreeTmp(pReNative, idxFcwReg); 13285 13286 return off; 13287 } 13288 13261 13289 13262 13290 -
trunk/src/VBox/VMM/include/IEMN8veRecompiler.h
r103588 r103589 688 688 kIemNativeGstReg_Pc, 689 689 kIemNativeGstReg_Cr0, 690 kIemNativeGstReg_ LivenessPadding18,690 kIemNativeGstReg_FpuFcw, 691 691 kIemNativeGstReg_LivenessPadding19, 692 692 kIemNativeGstReg_SegBaseFirst,
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