Changeset 103548 in vbox
- Timestamp:
- Feb 23, 2024 3:32:19 PM (7 months ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 4 edited
-
IEMAllInstCommonBodyMacros.h (modified) (7 diffs)
-
IEMAllInstOneByte.cpp.h (modified) (8 diffs)
-
IEMAllInstTwoByte0f.cpp.h (modified) (4 diffs)
-
IEMAllThrdPython.py (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstCommonBodyMacros.h
r101850 r103548 39 39 * @note Used both in OneByte and TwoByte0f. 40 40 */ 41 #define IEMOP_BODY_BINARY_rv_rm(a_fnNormalU16, a_fnNormalU32, a_fnNormalU64, a_fModifiesDstReg, a_f16BitMcFlag) \ 42 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \ 43 \ 41 #define IEMOP_BODY_BINARY_rv_rm(a_bRm, a_fnNormalU16, a_fnNormalU32, a_fnNormalU64, a_fModifiesDstReg, a_f16BitMcFlag) \ 44 42 /* \ 45 43 * If rm is denoting a register, no more instruction bytes. \ 46 44 */ \ 47 if (IEM_IS_MODRM_REG_MODE( bRm)) \45 if (IEM_IS_MODRM_REG_MODE(a_bRm)) \ 48 46 { \ 49 47 switch (pVCpu->iem.s.enmEffOpSize) \ … … 56 54 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 57 55 \ 58 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, bRm)); \59 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \56 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \ 57 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 60 58 IEM_MC_REF_EFLAGS(pEFlags); \ 61 59 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \ … … 72 70 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 73 71 \ 74 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); \75 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \72 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \ 73 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 76 74 IEM_MC_REF_EFLAGS(pEFlags); \ 77 75 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \ 78 76 \ 79 77 if (a_fModifiesDstReg) \ 80 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \78 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 81 79 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 82 80 IEM_MC_END(); \ … … 90 88 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 91 89 \ 92 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); \93 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \90 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \ 91 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 94 92 IEM_MC_REF_EFLAGS(pEFlags); \ 95 93 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \ … … 116 114 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 117 115 \ 118 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \116 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \ 119 117 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 120 118 IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 121 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \119 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 122 120 IEM_MC_REF_EFLAGS(pEFlags); \ 123 121 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \ … … 134 132 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 135 133 \ 136 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \134 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \ 137 135 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 138 136 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 139 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \137 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 140 138 IEM_MC_REF_EFLAGS(pEFlags); \ 141 139 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \ 142 140 \ 143 141 if (a_fModifiesDstReg) \ 144 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \142 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 145 143 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 146 144 IEM_MC_END(); \ … … 154 152 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 155 153 \ 156 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \154 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \ 157 155 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 158 156 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 159 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \157 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 160 158 IEM_MC_REF_EFLAGS(pEFlags); \ 161 159 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \ -
trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h
r103513 r103548 770 770 { 771 771 IEMOP_MNEMONIC2(RM, ADD, add, Gv, Ev, DISOPTYPE_HARMLESS, 0); 772 IEMOP_BODY_BINARY_rv_rm(iemAImpl_add_u16, iemAImpl_add_u32, iemAImpl_add_u64, 1, 0); 772 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 773 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_add_u16, iemAImpl_add_u32, iemAImpl_add_u64, 1, 0); 773 774 } 774 775 … … 896 897 IEMOP_MNEMONIC2(RM, OR, or, Gv, Ev, DISOPTYPE_HARMLESS, 0); 897 898 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 898 IEMOP_BODY_BINARY_rv_rm(iemAImpl_or_u16, iemAImpl_or_u32, iemAImpl_or_u64, 1, 0); 899 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 900 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_or_u16, iemAImpl_or_u32, iemAImpl_or_u64, 1, 0); 899 901 } 900 902 … … 1049 1051 { 1050 1052 IEMOP_MNEMONIC2(RM, ADC, adc, Gv, Ev, DISOPTYPE_HARMLESS, 0); 1051 IEMOP_BODY_BINARY_rv_rm(iemAImpl_adc_u16, iemAImpl_adc_u32, iemAImpl_adc_u64, 1, 0); 1053 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1054 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_adc_u16, iemAImpl_adc_u32, iemAImpl_adc_u64, 1, 0); 1052 1055 } 1053 1056 … … 1153 1156 { 1154 1157 IEMOP_MNEMONIC2(RM, SBB, sbb, Gv, Ev, DISOPTYPE_HARMLESS, 0); 1155 IEMOP_BODY_BINARY_rv_rm(iemAImpl_sbb_u16, iemAImpl_sbb_u32, iemAImpl_sbb_u64, 1, 0); 1158 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1159 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_sbb_u16, iemAImpl_sbb_u32, iemAImpl_sbb_u64, 1, 0); 1156 1160 } 1157 1161 … … 1261 1265 IEMOP_MNEMONIC2(RM, AND, and, Gv, Ev, DISOPTYPE_HARMLESS, 0); 1262 1266 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 1263 IEMOP_BODY_BINARY_rv_rm(iemAImpl_and_u16, iemAImpl_and_u32, iemAImpl_and_u64, 1, 0); 1267 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1268 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_and_u16, iemAImpl_and_u32, iemAImpl_and_u64, 1, 0); 1264 1269 } 1265 1270 … … 1372 1377 { 1373 1378 IEMOP_MNEMONIC2(RM, SUB, sub, Gv, Ev, DISOPTYPE_HARMLESS, 0); 1374 IEMOP_BODY_BINARY_rv_rm(iemAImpl_sub_u16, iemAImpl_sub_u32, iemAImpl_sub_u64, 1, 0); 1379 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1380 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_sub_u16, iemAImpl_sub_u32, iemAImpl_sub_u64, 1, 0); 1375 1381 } 1376 1382 … … 1485 1491 IEMOP_MNEMONIC2(RM, XOR, xor, Gv, Ev, DISOPTYPE_HARMLESS, 0); 1486 1492 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 1487 IEMOP_BODY_BINARY_rv_rm(iemAImpl_xor_u16, iemAImpl_xor_u32, iemAImpl_xor_u64, 1, 0); 1493 1494 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1495 1496 /* 1497 * Deal with special case of 'xor rN, rN' which sets rN to zero and has a known EFLAGS outcome. 1498 */ 1499 if ( (bRm >> X86_MODRM_REG_SHIFT) == ((bRm & X86_MODRM_RM_MASK) | (X86_MOD_REG << X86_MODRM_REG_SHIFT)) 1500 && pVCpu->iem.s.uRexReg == pVCpu->iem.s.uRexB) 1501 { 1502 switch (pVCpu->iem.s.enmEffOpSize) 1503 { 1504 case IEMMODE_16BIT: 1505 IEM_MC_BEGIN(1, 0, 0, 0); 1506 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1507 IEM_MC_STORE_GREG_U16_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 1508 IEM_MC_LOCAL(uint32_t, fEFlags); 1509 IEM_MC_FETCH_EFLAGS(fEFlags); 1510 IEM_MC_AND_LOCAL_U32(fEFlags, ~(uint32_t)X86_EFL_STATUS_BITS); 1511 IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); 1512 IEM_MC_COMMIT_EFLAGS(fEFlags); 1513 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1514 IEM_MC_END(); 1515 break; 1516 1517 case IEMMODE_32BIT: 1518 IEM_MC_BEGIN(1, 0, IEM_MC_F_MIN_386, 0); 1519 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1520 IEM_MC_STORE_GREG_U32_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 1521 IEM_MC_LOCAL(uint32_t, fEFlags); 1522 IEM_MC_FETCH_EFLAGS(fEFlags); 1523 IEM_MC_AND_LOCAL_U32(fEFlags, ~(uint32_t)X86_EFL_STATUS_BITS); 1524 IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); 1525 IEM_MC_COMMIT_EFLAGS(fEFlags); 1526 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1527 IEM_MC_END(); 1528 break; 1529 1530 case IEMMODE_64BIT: 1531 IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT, 0); 1532 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1533 IEM_MC_STORE_GREG_U64_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 1534 IEM_MC_LOCAL(uint32_t, fEFlags); 1535 IEM_MC_FETCH_EFLAGS(fEFlags); 1536 IEM_MC_AND_LOCAL_U32(fEFlags, ~(uint32_t)X86_EFL_STATUS_BITS); 1537 IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); 1538 IEM_MC_COMMIT_EFLAGS(fEFlags); 1539 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1540 IEM_MC_END(); 1541 break; 1542 1543 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 1544 } 1545 } 1546 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_xor_u16, iemAImpl_xor_u32, iemAImpl_xor_u64, 1, 0); 1488 1547 } 1489 1548 … … 1624 1683 { 1625 1684 IEMOP_MNEMONIC(cmp_Gv_Ev, "cmp Gv,Ev"); 1626 IEMOP_BODY_BINARY_rv_rm(iemAImpl_cmp_u16, iemAImpl_cmp_u32, iemAImpl_cmp_u64, 0, 0); 1685 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1686 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_cmp_u16, iemAImpl_cmp_u32, iemAImpl_cmp_u64, 0, 0); 1627 1687 } 1628 1688 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h
r103256 r103548 10439 10439 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF); 10440 10440 const IEMOPBINSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_eflags); 10441 IEMOP_BODY_BINARY_rv_rm(pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_MIN_386); 10441 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 10442 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_MIN_386); 10442 10443 } 10443 10444 … … 10945 10946 #endif 10946 10947 const IEMOPBINSIZES * const pImpl = IEM_SELECT_HOST_OR_FALLBACK(fPopCnt, &s_Native, &s_Fallback); 10947 IEMOP_BODY_BINARY_rv_rm(pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER); 10948 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 10949 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER); 10948 10950 } 10949 10951 … … 11619 11621 const IEMOPBINSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(s_iemAImpl_tzcnt_eflags, 11620 11622 IEM_GET_HOST_CPU_FEATURES(pVCpu)->fBmi1); 11621 IEMOP_BODY_BINARY_rv_rm(pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER); 11623 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 11624 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER); 11622 11625 } 11623 11626 … … 11673 11676 const IEMOPBINSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(s_iemAImpl_lzcnt_eflags, 11674 11677 IEM_GET_HOST_CPU_FEATURES(pVCpu)->fBmi1); 11675 IEMOP_BODY_BINARY_rv_rm(pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER); 11678 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 11679 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER); 11676 11680 } 11677 11681 -
trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py
r103542 r103548 1647 1647 'IEM_MC_STORE_MEM_U128_NO_AC': '__mem128', 1648 1648 'IEM_MC_STORE_MEM_U16': '__mem16', 1649 'IEM_MC_STORE_MEM_U16_CONST': '__mem16 ',1649 'IEM_MC_STORE_MEM_U16_CONST': '__mem16c', 1650 1650 'IEM_MC_STORE_MEM_U256': '__mem256', 1651 1651 'IEM_MC_STORE_MEM_U256_ALIGN_AVX': '__mem256', 1652 1652 'IEM_MC_STORE_MEM_U256_NO_AC': '__mem256', 1653 1653 'IEM_MC_STORE_MEM_U32': '__mem32', 1654 'IEM_MC_STORE_MEM_U32_CONST': '__mem32 ',1654 'IEM_MC_STORE_MEM_U32_CONST': '__mem32c', 1655 1655 'IEM_MC_STORE_MEM_U64': '__mem64', 1656 'IEM_MC_STORE_MEM_U64_CONST': '__mem64 ',1656 'IEM_MC_STORE_MEM_U64_CONST': '__mem64c', 1657 1657 'IEM_MC_STORE_MEM_U8': '__mem8', 1658 'IEM_MC_STORE_MEM_U8_CONST': '__mem8 ',1658 'IEM_MC_STORE_MEM_U8_CONST': '__mem8c', 1659 1659 1660 1660 'IEM_MC_MEM_MAP_D80_WO': '__mem80', … … 1713 1713 'IEM_MC_STORE_GREG_U64': '__greg64', 1714 1714 'IEM_MC_STORE_GREG_I64': '__greg64', 1715 'IEM_MC_STORE_GREG_U8_CONST': '__greg8 ',1716 'IEM_MC_STORE_GREG_U16_CONST': '__greg16 ',1717 'IEM_MC_STORE_GREG_U32_CONST': '__greg32 ',1718 'IEM_MC_STORE_GREG_U64_CONST': '__greg64 ',1715 'IEM_MC_STORE_GREG_U8_CONST': '__greg8c', 1716 'IEM_MC_STORE_GREG_U16_CONST': '__greg16c', 1717 'IEM_MC_STORE_GREG_U32_CONST': '__greg32c', 1718 'IEM_MC_STORE_GREG_U64_CONST': '__greg64c', 1719 1719 'IEM_MC_STORE_GREG_PAIR_U32': '__greg32', 1720 1720 'IEM_MC_STORE_GREG_PAIR_U64': '__greg64',
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