- Timestamp:
- Feb 16, 2024 12:04:24 AM (8 months ago)
- Location:
- trunk
- Files:
-
- 8 edited
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include/VBox/vmm/stam.h (modified) (1 diff)
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src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp (modified) (14 diffs)
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src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp (modified) (20 diffs)
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src/VBox/VMM/VMMR3/IEMR3.cpp (modified) (4 diffs)
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src/VBox/VMM/VMMR3/STAM.cpp (modified) (6 diffs)
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src/VBox/VMM/include/IEMInternal.h (modified) (2 diffs)
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src/VBox/VMM/include/IEMN8veRecompiler.h (modified) (10 diffs)
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src/VBox/VMM/include/STAMInternal.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/vmm/stam.h
r102840 r103393 1356 1356 const char *pszDesc, const char *pszName, va_list va) RT_IPRT_FORMAT_ATTR(5, 0); 1357 1357 VMMR3DECL(int) STAMR3RegisterPctOfSum(PUVM pUVM, STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszValue, 1358 const char *pszSummandPattern, const char *pszDesc, const char *pszName, ...); 1358 bool fAddValueToSum, const char *pszSummandPattern, const char *pszDesc, 1359 const char *pszName, ...); 1359 1360 VMMR3DECL(int) STAMR3RegisterPctOfSumV(PUVM pUVM, STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszValue, 1360 const char *pszSummandPattern, const char *pszDesc, const char *pszName, va_list va); 1361 bool fAddValueToSum, const char *pszSummandPattern, const char *pszDesc, 1362 const char *pszName, va_list va); 1361 1363 1362 1364 VMMR3DECL(int) STAMR3Deregister(PUVM pUVM, const char *pszPat); -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp
r103334 r103393 51 51 * BEGIN & END as well as internal workers. 52 52 */ 53 #define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fMcFlags, a_fCImplFlags) \ 53 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 54 # define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fMcFlags, a_fCImplFlags) \ 54 55 { \ 55 56 /* Define local variables that we use to accumulate the liveness state changes in. */ \ … … 58 59 IEMLIVENESSBIT LiveMask = { 0 }; \ 59 60 bool fDoneXpctOrCall = false 60 61 #else 62 # define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fMcFlags, a_fCImplFlags) \ 63 { \ 64 /* Define local variables that we use to accumulate the liveness state changes in. */ \ 65 IEMLIVENESSENTRY LiveState = { { 0, 0, 0, 0 } }; \ 66 IEMLIVENESSBIT LiveMask = { 0 }; \ 67 bool fDoneXpctOrCall = false 68 #endif 69 70 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 61 71 AssertCompile(IEMLIVENESS_STATE_INPUT == IEMLIVENESS_STATE_MASK); 62 72 AssertCompile(IEMLIVENESSBIT0_XCPT_OR_CALL == 0 && IEMLIVENESSBIT1_XCPT_OR_CALL != 0); 63 # define IEM_LIVENESS_MARK_XCPT_OR_CALL() do { \73 # define IEM_LIVENESS_MARK_XCPT_OR_CALL() do { \ 64 74 if (!fDoneXpctOrCall) \ 65 75 { \ … … 71 81 } \ 72 82 } while (0) 73 74 83 #else 84 # define IEM_LIVENESS_MARK_XCPT_OR_CALL() do { \ 85 if (!fDoneXpctOrCall) \ 86 { \ 87 LiveState.aBits[IEMLIVENESS_BIT_READ].bm64 |= pIncoming->aBits[IEMLIVENESS_BIT_READ].bm64 & ~LiveMask.bm64; \ 88 LiveState.aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 |= IEMLIVENESSBIT_MASK; \ 89 LiveMask.bm64 |= IEMLIVENESSBIT_MASK; \ 90 fDoneXpctOrCall = true; \ 91 } \ 92 } while (0) 93 #endif 94 95 96 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 75 97 AssertCompile(IEMLIVENESS_STATE_CLOBBERED == 0); 76 # define IEM_LIVENESS_ALL_EFLAGS_CLOBBERED() do { \98 # define IEM_LIVENESS_ALL_EFLAGS_CLOBBER() do { \ 77 99 LiveMask.bm64 |= IEMLIVENESSBIT_ALL_EFL_MASK; \ 78 100 } while (0) 79 101 AssertCompile(IEMLIVENESS_STATE_INPUT == IEMLIVENESS_STATE_MASK); 80 # define IEM_LIVENESS_ALL_EFLAGS_INPUT() do { \102 # define IEM_LIVENESS_ALL_EFLAGS_INPUT() do { \ 81 103 LiveStateBit0.bm64 |= IEMLIVENESSBIT_ALL_EFL_MASK; \ 82 104 LiveStateBit1.bm64 |= IEMLIVENESSBIT_ALL_EFL_MASK; \ 83 105 LiveMask.bm64 |= IEMLIVENESSBIT_ALL_EFL_MASK; \ 84 106 } while (0) 85 86 87 #define IEM_LIVENESS_ONE_EFLAG_CLOBBERED(a_Name) do { \ 107 # define IEM_LIVENESS_ALL_EFLAGS_MODIFY() IEM_LIVENESS_ALL_EFLAGS_INPUT() 108 #else 109 # define IEM_LIVENESS_ALL_EFLAGS_CLOBBER() do { \ 110 LiveState.aBits[IEMLIVENESS_BIT_WRITE].bm64 |= IEMLIVENESSBIT_ALL_EFL_MASK; \ 111 LiveMask.bm64 |= IEMLIVENESSBIT_ALL_EFL_MASK; \ 112 } while (0) 113 # define IEM_LIVENESS_ALL_EFLAGS_INPUT() do { \ 114 LiveState.aBits[IEMLIVENESS_BIT_READ].bm64 |= IEMLIVENESSBIT_ALL_EFL_MASK; \ 115 LiveMask.bm64 |= IEMLIVENESSBIT_ALL_EFL_MASK; \ 116 } while (0) 117 # define IEM_LIVENESS_ALL_EFLAGS_MODIFY() do { \ 118 LiveState.aBits[IEMLIVENESS_BIT_READ].bm64 |= IEMLIVENESSBIT_ALL_EFL_MASK; \ 119 LiveState.aBits[IEMLIVENESS_BIT_WRITE].bm64 |= IEMLIVENESSBIT_ALL_EFL_MASK; \ 120 LiveMask.bm64 |= IEMLIVENESSBIT_ALL_EFL_MASK; \ 121 } while (0) 122 #endif 123 124 125 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 126 # define IEM_LIVENESS_ONE_EFLAG_CLOBBER(a_Name) do { \ 88 127 LiveMask.a_Name |= 1; \ 89 128 } while (0) 90 # define IEM_LIVENESS_ONE_EFLAG_INPUT(a_Name) do { \129 # define IEM_LIVENESS_ONE_EFLAG_INPUT(a_Name) do { \ 91 130 LiveStateBit0.a_Name |= 1; \ 92 131 LiveStateBit1.a_Name |= 1; \ 93 132 LiveMask.a_Name |= 1; \ 94 133 } while (0) 134 # define IEM_LIVENESS_ONE_EFLAG_MODIFY(a_Name) IEM_LIVENESS_ONE_EFLAG_INPUT(a_Name) 135 #else 136 # define IEM_LIVENESS_ONE_EFLAG_CLOBBER(a_Name) do { \ 137 LiveState.aBits[IEMLIVENESS_BIT_WRITE].a_Name |= 1; \ 138 LiveMask.a_Name |= 1; \ 139 } while (0) 140 # define IEM_LIVENESS_ONE_EFLAG_INPUT(a_Name) do { \ 141 LiveState.aBits[IEMLIVENESS_BIT_READ].a_Name |= 1; \ 142 LiveMask.a_Name |= 1; \ 143 } while (0) 144 # define IEM_LIVENESS_ONE_EFLAG_MODIFY(a_Name) do { \ 145 LiveState.aBits[IEMLIVENESS_BIT_READ].a_Name |= 1; \ 146 LiveState.aBits[IEMLIVENESS_BIT_WRITE].a_Name |= 1; \ 147 LiveMask.a_Name |= 1; \ 148 } while (0) 149 #endif 95 150 96 151 97 152 /* Generic bitmap (bmGpr, bmSegBase, ++) setters. */ 98 #define IEM_LIVENESS_BITMAP_MEMBER_CLOBBERED(a_Part, a_bmMember, a_iElement) do { \ 153 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 154 # define IEM_LIVENESS_BITMAP_MEMBER_CLOBBER(a_bmMember, a_iElement) do { \ 99 155 LiveMask.a_bmMember |= RT_BIT_64(a_iElement); \ 100 156 } while (0) 101 # define IEM_LIVENESS_BITMAP_MEMBER_INPUT(a_Part,a_bmMember, a_iElement) do { \157 # define IEM_LIVENESS_BITMAP_MEMBER_INPUT(a_bmMember, a_iElement) do { \ 102 158 LiveStateBit0.a_bmMember |= RT_BIT_64(a_iElement); \ 103 159 LiveStateBit1.a_bmMember |= RT_BIT_64(a_iElement); \ 104 160 LiveMask.a_bmMember |= RT_BIT_64(a_iElement); \ 105 161 } while (0) 106 107 108 #define IEM_LIVENESS_GPR_CLOBBERED(a_idxGpr) IEM_LIVENESS_BITMAP_MEMBER_CLOBBERED(1, bmGprs, a_idxGpr) 109 #define IEM_LIVENESS_GPR_INPUT(a_idxGpr) IEM_LIVENESS_BITMAP_MEMBER_INPUT( 1, bmGprs, a_idxGpr) 110 111 112 #define IEM_LIVENESS_SEG_BASE_CLOBBERED(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_CLOBBERED(1, bmSegBase, a_iSeg) 113 #define IEM_LIVENESS_SEG_BASE_INPUT(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_INPUT( 1, bmSegBase, a_iSeg) 114 115 116 #define IEM_LIVENESS_SEG_ATTRIB_CLOBBERED(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_CLOBBERED(1, bmSegAttrib, a_iSeg) 117 #define IEM_LIVENESS_SEG_ATTRIB_INPUT(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_INPUT( 1, bmSegAttrib, a_iSeg) 118 119 120 #define IEM_LIVENESS_SEG_LIMIT_CLOBBERED(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_CLOBBERED(2, bmSegLimit, a_iSeg) 121 #define IEM_LIVENESS_SEG_LIMIT_INPUT(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_INPUT( 2, bmSegLimit, a_iSeg) 122 123 124 #define IEM_LIVENESS_SEG_SEL_CLOBBERED(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_CLOBBERED(2, bmSegSel, a_iSeg) 125 #define IEM_LIVENESS_SEG_SEL_INPUT(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_INPUT( 2, bmSegSel, a_iSeg) 162 # define IEM_LIVENESS_BITMAP_MEMBER_MODIFY(a_bmMember, a_iElement) IEM_LIVENESS_BITMAP_MEMBER_INPUT(a_bmMember, a_iElement) 163 #else 164 # define IEM_LIVENESS_BITMAP_MEMBER_CLOBBER(a_bmMember, a_iElement) do { \ 165 LiveState.aBits[IEMLIVENESS_BIT_WRITE].a_bmMember |= RT_BIT_64(a_iElement); \ 166 LiveMask.a_bmMember |= RT_BIT_64(a_iElement); \ 167 } while (0) 168 # define IEM_LIVENESS_BITMAP_MEMBER_INPUT(a_bmMember, a_iElement) do { \ 169 LiveState.aBits[IEMLIVENESS_BIT_READ].a_bmMember |= RT_BIT_64(a_iElement); \ 170 LiveMask.a_bmMember |= RT_BIT_64(a_iElement); \ 171 } while (0) 172 # define IEM_LIVENESS_BITMAP_MEMBER_MODIFY(a_bmMember, a_iElement) do { \ 173 LiveState.aBits[IEMLIVENESS_BIT_READ].a_bmMember |= RT_BIT_64(a_iElement); \ 174 LiveState.aBits[IEMLIVENESS_BIT_WRITE].a_bmMember |= RT_BIT_64(a_iElement); \ 175 LiveMask.a_bmMember |= RT_BIT_64(a_iElement); \ 176 } while (0) 177 #endif 178 179 180 #define IEM_LIVENESS_GPR_CLOBBER(a_idxGpr) IEM_LIVENESS_BITMAP_MEMBER_CLOBBER(bmGprs, a_idxGpr) 181 #define IEM_LIVENESS_GPR_INPUT(a_idxGpr) IEM_LIVENESS_BITMAP_MEMBER_INPUT( bmGprs, a_idxGpr) 182 #define IEM_LIVENESS_GPR_MODIFY(a_idxGpr) IEM_LIVENESS_BITMAP_MEMBER_MODIFY( bmGprs, a_idxGpr) 183 184 185 #define IEM_LIVENESS_SEG_BASE_CLOBBER(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_CLOBBER(bmSegBase, a_iSeg) 186 #define IEM_LIVENESS_SEG_BASE_INPUT(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_INPUT( bmSegBase, a_iSeg) 187 #define IEM_LIVENESS_SEG_BASE_MODIFY(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_MODIFY( bmSegBase, a_iSeg) 188 189 190 #define IEM_LIVENESS_SEG_ATTRIB_CLOBBER(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_CLOBBER(bmSegAttrib, a_iSeg) 191 #define IEM_LIVENESS_SEG_ATTRIB_INPUT(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_INPUT( bmSegAttrib, a_iSeg) 192 #define IEM_LIVENESS_SEG_ATTRIB_MODIFY(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_MODFIY( bmSegAttrib, a_iSeg) 193 194 195 #define IEM_LIVENESS_SEG_LIMIT_CLOBBER(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_CLOBBER(bmSegLimit, a_iSeg) 196 #define IEM_LIVENESS_SEG_LIMIT_INPUT(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_INPUT( bmSegLimit, a_iSeg) 197 #define IEM_LIVENESS_SEG_LIMIT_MODIFY(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_MODIFY( bmSegLimit, a_iSeg) 198 199 200 #define IEM_LIVENESS_SEG_SEL_CLOBBER(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_CLOBBER(bmSegSel, a_iSeg) 201 #define IEM_LIVENESS_SEG_SEL_INPUT(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_INPUT( bmSegSel, a_iSeg) 202 #define IEM_LIVENESS_SEG_SEL_MODIFY(a_iSeg) IEM_LIVENESS_BITMAP_MEMBER_MODIFY( bmSegSel, a_iSeg) 126 203 127 204 … … 137 214 #define IEM_LIVENESS_STACK() do { \ 138 215 IEM_LIVENESS_MEM(X86_SREG_SS); \ 139 IEM_LIVENESS_GPR_ INPUT(X86_GREG_xSP); \216 IEM_LIVENESS_GPR_MODIFY(X86_GREG_xSP); \ 140 217 } while (0) 141 218 142 219 #define IEM_LIVENESS_STACK_FLAT() do { \ 143 220 IEM_LIVENESS_MEM_FLAT(); \ 144 IEM_LIVENESS_GPR_ INPUT(X86_GREG_xSP); \221 IEM_LIVENESS_GPR_MODIFY(X86_GREG_xSP); \ 145 222 } while (0) 146 223 … … 155 232 #define IEM_LIVENESS_PC64_JMP_WITH_FLAGS() IEM_LIVENESS_MARK_XCPT_OR_CALL(); IEM_LIVENESS_ONE_EFLAG_INPUT(fEflOther) 156 233 157 #define IEM_MC_END() \ 234 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 235 # define IEM_MC_END() \ 158 236 /* Combine the incoming state with what we've accumulated in this block. */ \ 159 237 /* We can help the compiler by skipping OR'ing when having applied XPCT_OR_CALL, */ \ … … 170 248 } \ 171 249 } 250 #else 251 # define IEM_MC_END() \ 252 /* Combine the incoming state with what we've accumulated in this block. */ \ 253 /* We can help the compiler by skipping OR'ing when having applied XPCT_OR_CALL, */ \ 254 /* since that already imports all the incoming state. Saves a lot with cl.exe. */ \ 255 if (!fDoneXpctOrCall) \ 256 { \ 257 pOutgoing->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 = LiveState.aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 \ 258 | (~LiveMask.bm64 & pIncoming->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64); \ 259 pOutgoing->aBits[IEMLIVENESS_BIT_READ].bm64 = LiveState.aBits[IEMLIVENESS_BIT_READ].bm64 \ 260 | (~LiveMask.bm64 & pIncoming->aBits[IEMLIVENESS_BIT_READ].bm64); \ 261 pOutgoing->aBits[IEMLIVENESS_BIT_WRITE].bm64 = LiveState.aBits[IEMLIVENESS_BIT_WRITE].bm64 \ 262 | (~LiveMask.bm64 & pIncoming->aBits[IEMLIVENESS_BIT_WRITE].bm64); \ 263 pOutgoing->aBits[IEMLIVENESS_BIT_OTHER].bm64 = LiveState.aBits[IEMLIVENESS_BIT_OTHER].bm64 \ 264 | (~LiveMask.bm64 & pIncoming->aBits[IEMLIVENESS_BIT_OTHER].bm64); \ 265 } \ 266 else \ 267 *pOutgoing = LiveState; \ 268 } 269 #endif 172 270 173 271 /* … … 318 416 #define IEM_MC_FETCH_GREG_U8_SX_U32_THREADED(a_u32Dst, a_iGRegEx) IEM_LIVENESS_GPR_INPUT(a_iGRegEx & 15) 319 417 #define IEM_MC_FETCH_GREG_U8_SX_U64_THREADED(a_u64Dst, a_iGRegEx) IEM_LIVENESS_GPR_INPUT(a_iGRegEx & 15) 320 #define IEM_MC_STORE_GREG_U8_THREADED(a_iGRegEx, a_u8Value) IEM_LIVENESS_GPR_ INPUT(a_iGRegEx & 15)321 #define IEM_MC_STORE_GREG_U8_CONST_THREADED(a_iGRegEx, a_u8Value) IEM_LIVENESS_GPR_ INPUT(a_iGRegEx & 15)322 #define IEM_MC_REF_GREG_U8_THREADED(a_pu8Dst, a_iGRegEx) IEM_LIVENESS_GPR_ INPUT(a_iGRegEx & 15)418 #define IEM_MC_STORE_GREG_U8_THREADED(a_iGRegEx, a_u8Value) IEM_LIVENESS_GPR_MODIFY(a_iGRegEx & 15) 419 #define IEM_MC_STORE_GREG_U8_CONST_THREADED(a_iGRegEx, a_u8Value) IEM_LIVENESS_GPR_MODIFY(a_iGRegEx & 15) 420 #define IEM_MC_REF_GREG_U8_THREADED(a_pu8Dst, a_iGRegEx) IEM_LIVENESS_GPR_MODIFY(a_iGRegEx & 15) 323 421 #define IEM_MC_ADD_GREG_U8_TO_LOCAL_THREADED(a_u8Value, a_iGRegEx) IEM_LIVENESS_GPR_INPUT(a_iGRegEx & 15) 324 #define IEM_MC_AND_GREG_U8_THREADED(a_iGRegEx, a_u8Value) IEM_LIVENESS_GPR_ INPUT(a_iGRegEx & 15)325 #define IEM_MC_OR_GREG_U8_THREADED(a_iGRegEx, a_u8Value) IEM_LIVENESS_GPR_ INPUT(a_iGRegEx & 15)422 #define IEM_MC_AND_GREG_U8_THREADED(a_iGRegEx, a_u8Value) IEM_LIVENESS_GPR_MODIFY(a_iGRegEx & 15) 423 #define IEM_MC_OR_GREG_U8_THREADED(a_iGRegEx, a_u8Value) IEM_LIVENESS_GPR_MODIFY(a_iGRegEx & 15) 326 424 327 425 … … 413 511 #define IEM_MC_FETCH_FCW(a_u16Fcw) NOP() 414 512 415 #define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) IEM_LIVENESS_GPR_ INPUT(a_iGReg)416 #define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) IEM_LIVENESS_GPR_CLOBBER ED(a_iGReg)417 #define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) IEM_LIVENESS_GPR_CLOBBER ED(a_iGReg)418 #define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) IEM_LIVENESS_GPR_CLOBBER ED(a_iGReg)419 #define IEM_MC_STORE_GREG_U16_CONST(a_iGReg, a_u16Const) IEM_LIVENESS_GPR_ INPUT(a_iGReg)420 #define IEM_MC_STORE_GREG_U32_CONST(a_iGReg, a_u32Const) IEM_LIVENESS_GPR_CLOBBER ED(a_iGReg)421 #define IEM_MC_STORE_GREG_U64_CONST(a_iGReg, a_u32Const) IEM_LIVENESS_GPR_CLOBBER ED(a_iGReg)513 #define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 514 #define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) IEM_LIVENESS_GPR_CLOBBER(a_iGReg) 515 #define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) IEM_LIVENESS_GPR_CLOBBER(a_iGReg) 516 #define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) IEM_LIVENESS_GPR_CLOBBER(a_iGReg) 517 #define IEM_MC_STORE_GREG_U16_CONST(a_iGReg, a_u16Const) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 518 #define IEM_MC_STORE_GREG_U32_CONST(a_iGReg, a_u32Const) IEM_LIVENESS_GPR_CLOBBER(a_iGReg) 519 #define IEM_MC_STORE_GREG_U64_CONST(a_iGReg, a_u32Const) IEM_LIVENESS_GPR_CLOBBER(a_iGReg) 422 520 #define IEM_MC_STORE_GREG_PAIR_U32(a_iGRegLo, a_iGRegHi, a_u64Value) \ 423 do { IEM_LIVENESS_GPR_CLOBBER ED(a_iGRegLo); IEM_LIVENESS_GPR_CLOBBERED(a_iGRegHi); } while(0)521 do { IEM_LIVENESS_GPR_CLOBBER(a_iGRegLo); IEM_LIVENESS_GPR_CLOBBER(a_iGRegHi); } while(0) 424 522 #define IEM_MC_STORE_GREG_PAIR_U64(a_iGRegLo, a_iGRegHi, a_u128Value) \ 425 do { IEM_LIVENESS_GPR_CLOBBER ED(a_iGRegLo); IEM_LIVENESS_GPR_CLOBBERED(a_iGRegHi); } while(0)426 #define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) IEM_LIVENESS_GPR_ INPUT(a_iGReg) /** @todo This isn't always the case... */427 428 #define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) IEM_LIVENESS_SEG_BASE_CLOBBER ED(a_iSReg)429 #define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) IEM_LIVENESS_SEG_BASE_CLOBBER ED(a_iSReg)523 do { IEM_LIVENESS_GPR_CLOBBER(a_iGRegLo); IEM_LIVENESS_GPR_CLOBBER(a_iGRegHi); } while(0) 524 #define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) IEM_LIVENESS_GPR_MODIFY(a_iGReg) /** @todo This isn't always the case... */ 525 526 #define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) IEM_LIVENESS_SEG_BASE_CLOBBER(a_iSReg) 527 #define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) IEM_LIVENESS_SEG_BASE_CLOBBER(a_iSReg) 430 528 #define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) NOP() 431 529 432 530 433 #define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT(a_iGReg) 434 #define IEM_MC_REF_GREG_U16_CONST(a_pu16Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT(a_iGReg) 435 #define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT(a_iGReg) 436 #define IEM_MC_REF_GREG_U32_CONST(a_pu32Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT(a_iGReg) 437 #define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT(a_iGReg) 438 #define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT(a_iGReg) 439 #define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT(a_iGReg) 440 #define IEM_MC_REF_GREG_U64_CONST(a_pu64Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT(a_iGReg) 441 #define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT(a_iGReg) 442 #define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT(a_iGReg) 443 #define IEM_MC_REF_EFLAGS(a_pEFlags) IEM_LIVENESS_ALL_EFLAGS_INPUT() 531 #define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 532 #define IEM_MC_REF_GREG_U16_CONST(a_pu16Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT( a_iGReg) 533 #define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 534 #define IEM_MC_REF_GREG_U32_CONST(a_pu32Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT( a_iGReg) 535 #define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 536 #define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT( a_iGReg) 537 #define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 538 #define IEM_MC_REF_GREG_U64_CONST(a_pu64Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT( a_iGReg) 539 #define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 540 #define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) IEM_LIVENESS_GPR_INPUT( a_iGReg) 541 #define IEM_MC_REF_EFLAGS(a_pEFlags) IEM_LIVENESS_ALL_EFLAGS_MODIFY() 542 #undef IEM_MC_REF_EFLAGS /* unused */ 444 543 #define IEMLIVENESS_EFL_HLP(a_fEflInput, a_fEflOutput, a_fEfl, a_Member) \ 445 if ((a_fEflInput) & (a_fEfl)) IEM_LIVENESS_ONE_EFLAG_INPUT(a_Member); \ 446 else if ((a_fEflOutput) & (a_fEfl)) IEM_LIVENESS_ONE_EFLAG_CLOBBERED(a_Member) 544 if ((a_fEflInput) & (a_fEfl)) { \ 545 if ((a_fEflOutput) & (a_fEfl)) IEM_LIVENESS_ONE_EFLAG_MODIFY(a_Member); \ 546 else IEM_LIVENESS_ONE_EFLAG_INPUT(a_Member); \ 547 } else if ((a_fEflOutput) & (a_fEfl)) IEM_LIVENESS_ONE_EFLAG_CLOBBER(a_Member) 447 548 #define IEM_MC_REF_EFLAGS_EX(a_pEFlags, a_fEflInput, a_fEflOutput) do { \ 448 549 IEMLIVENESS_EFL_HLP(a_fEflInput, a_fEflOutput, X86_EFL_CF, fEflCf); \ … … 460 561 461 562 462 #define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) IEM_LIVENESS_GPR_ INPUT(a_iGReg)463 #define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) IEM_LIVENESS_GPR_ INPUT(a_iGReg)464 #define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) IEM_LIVENESS_GPR_ INPUT(a_iGReg)465 466 #define IEM_MC_SUB_GREG_U16(a_iGReg, a_u8Const) IEM_LIVENESS_GPR_ INPUT(a_iGReg)467 #define IEM_MC_SUB_GREG_U32(a_iGReg, a_u8Const) IEM_LIVENESS_GPR_ INPUT(a_iGReg)468 #define IEM_MC_SUB_GREG_U64(a_iGReg, a_u8Const) IEM_LIVENESS_GPR_ INPUT(a_iGReg)563 #define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 564 #define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 565 #define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 566 567 #define IEM_MC_SUB_GREG_U16(a_iGReg, a_u8Const) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 568 #define IEM_MC_SUB_GREG_U32(a_iGReg, a_u8Const) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 569 #define IEM_MC_SUB_GREG_U64(a_iGReg, a_u8Const) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 469 570 #define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) NOP() 470 571 471 #define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) IEM_LIVENESS_GPR_ INPUT(a_iGReg)472 #define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) IEM_LIVENESS_GPR_ INPUT(a_iGReg)473 #define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) IEM_LIVENESS_GPR_ INPUT(a_iGReg)572 #define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 573 #define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 574 #define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 474 575 #define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) NOP() 475 576 #define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) NOP() … … 503 604 #define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) NOP() 504 605 505 #define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) IEM_LIVENESS_GPR_ INPUT(a_iGReg)506 #define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) IEM_LIVENESS_GPR_ INPUT(a_iGReg)507 #define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) IEM_LIVENESS_GPR_ INPUT(a_iGReg)508 509 #define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) IEM_LIVENESS_GPR_ INPUT(a_iGReg)510 #define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) IEM_LIVENESS_GPR_ INPUT(a_iGReg)511 #define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) IEM_LIVENESS_GPR_ INPUT(a_iGReg)606 #define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 607 #define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 608 #define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 609 610 #define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 611 #define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 612 #define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) IEM_LIVENESS_GPR_MODIFY(a_iGReg) 512 613 513 614 #define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) NOP() … … 526 627 } while (0) 527 628 #define IEM_MC_FLIP_EFL_BIT(a_fBit) do { \ 528 if ((a_fBit) == X86_EFL_CF) IEM_LIVENESS_ONE_EFLAG_ INPUT(fEflCf); \529 else { AssertFailed(); IEM_LIVENESS_ALL_EFLAG_ INPUT(); } \629 if ((a_fBit) == X86_EFL_CF) IEM_LIVENESS_ONE_EFLAG_MODIFY(fEflCf); \ 630 else { AssertFailed(); IEM_LIVENESS_ALL_EFLAG_MODIFY(); } \ 530 631 } while (0) 531 632 … … 797 898 #define IEM_MC_PUSH_U64(a_u64Value) IEM_LIVENESS_STACK() 798 899 799 #define IEM_MC_POP_GREG_U16(a_iGReg) do { IEM_LIVENESS_STACK(); IEM_LIVENESS_GPR_ INPUT(a_iGReg); } while (0)800 #define IEM_MC_POP_GREG_U32(a_iGReg) do { IEM_LIVENESS_STACK(); IEM_LIVENESS_GPR_CLOBBER ED(a_iGReg); } while (0)801 #define IEM_MC_POP_GREG_U64(a_iGReg) do { IEM_LIVENESS_STACK(); IEM_LIVENESS_GPR_CLOBBER ED(a_iGReg); } while (0)900 #define IEM_MC_POP_GREG_U16(a_iGReg) do { IEM_LIVENESS_STACK(); IEM_LIVENESS_GPR_MODIFY(a_iGReg); } while (0) 901 #define IEM_MC_POP_GREG_U32(a_iGReg) do { IEM_LIVENESS_STACK(); IEM_LIVENESS_GPR_CLOBBER(a_iGReg); } while (0) 902 #define IEM_MC_POP_GREG_U64(a_iGReg) do { IEM_LIVENESS_STACK(); IEM_LIVENESS_GPR_CLOBBER(a_iGReg); } while (0) 802 903 803 904 /* 32-bit flat stack push and pop: */ … … 806 907 #define IEM_MC_FLAT32_PUSH_U32_SREG(a_uSegVal) IEM_LIVENESS_STACK_FLAT() 807 908 808 #define IEM_MC_FLAT32_POP_GREG_U16(a_iGReg) do { IEM_LIVENESS_STACK_FLAT(); IEM_LIVENESS_GPR_ INPUT(a_iGReg); } while (0)809 #define IEM_MC_FLAT32_POP_GREG_U32(a_iGReg) do { IEM_LIVENESS_STACK_FLAT(); IEM_LIVENESS_GPR_CLOBBER ED(a_iGReg); } while (0)909 #define IEM_MC_FLAT32_POP_GREG_U16(a_iGReg) do { IEM_LIVENESS_STACK_FLAT(); IEM_LIVENESS_GPR_MODIFY(a_iGReg); } while (0) 910 #define IEM_MC_FLAT32_POP_GREG_U32(a_iGReg) do { IEM_LIVENESS_STACK_FLAT(); IEM_LIVENESS_GPR_CLOBBER(a_iGReg); } while (0) 810 911 811 912 /* 64-bit flat stack push and pop: */ … … 813 914 #define IEM_MC_FLAT64_PUSH_U64(a_u64Value) IEM_LIVENESS_STACK_FLAT() 814 915 815 #define IEM_MC_FLAT64_POP_GREG_U16(a_iGReg) do { IEM_LIVENESS_STACK_FLAT(); IEM_LIVENESS_GPR_ INPUT(a_iGReg); } while (0)816 #define IEM_MC_FLAT64_POP_GREG_U64(a_iGReg) do { IEM_LIVENESS_STACK_FLAT(); IEM_LIVENESS_GPR_CLOBBER ED(a_iGReg); } while (0)916 #define IEM_MC_FLAT64_POP_GREG_U16(a_iGReg) do { IEM_LIVENESS_STACK_FLAT(); IEM_LIVENESS_GPR_MODIFY(a_iGReg); } while (0) 917 #define IEM_MC_FLAT64_POP_GREG_U64(a_iGReg) do { IEM_LIVENESS_STACK_FLAT(); IEM_LIVENESS_GPR_CLOBBER(a_iGReg); } while (0) 817 918 818 919 -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
r103377 r103393 3621 3621 PCIEMLIVENESSENTRY const pLivenessEntry = &pReNative->paLivenessEntries[idxCurCall - 1]; 3622 3622 3623 # ifndef IEMLIVENESS_EXTENDED_LAYOUT 3623 3624 /* Construct a mask of the guest registers in the UNUSED and XCPT_OR_CALL state. */ 3624 3625 AssertCompile(IEMLIVENESS_STATE_UNUSED == 1 && IEMLIVENESS_STATE_XCPT_OR_CALL == 2); 3625 # if 03626 IEMLIVENESSBIT Tmp = { pLivenessEntry->Bit0.bm64 ^ pLivenessEntry->Bit1.bm64 }; /* mask of regs in either UNUSED */3627 Tmp.fEflOther &= Tmp.fEflCf; /** @todo optimize this (pair of 3 (status), pair of 4 (in other), pair of 2, pair of 1). */3628 Tmp.fEflOther &= Tmp.fEflPf;3629 Tmp.fEflOther &= Tmp.fEflAf;3630 Tmp.fEflOther &= Tmp.fEflZf;3631 Tmp.fEflOther &= Tmp.fEflSf;3632 Tmp.fEflOther &= Tmp.fEflOf;3633 Tmp.fEflCf = 0; /* not necessary, but better safe. */3634 Tmp.fEflPf = 0;3635 Tmp.fEflAf = 0;3636 Tmp.fEflZf = 0;3637 Tmp.fEflSf = 0;3638 Tmp.fEflOf = 0;3639 uint64_t fToFreeMask = Tmp.bm64;3640 # else3641 3626 uint64_t fToFreeMask = pLivenessEntry->Bit0.bm64 ^ pLivenessEntry->Bit1.bm64; /* mask of regs in either UNUSED */ 3627 #else 3628 /* Construct a mask of the registers not in the read or write state. 3629 Note! We could skips writes, if they aren't from us, as this is just 3630 a hack to prevent trashing registers that have just been written 3631 or will be written when we retire the current instruction. */ 3632 uint64_t fToFreeMask = ~pLivenessEntry->aBits[IEMLIVENESS_BIT_READ].bm64 3633 & ~pLivenessEntry->aBits[IEMLIVENESS_BIT_WRITE].bm64 3634 & IEMLIVENESSBIT_MASK; 3635 #endif 3636 /* Merge EFLAGS. */ 3642 3637 uint64_t fTmp = fToFreeMask & (fToFreeMask >> 3); /* AF2,PF2,CF2,Other2 = AF,PF,CF,Other & OF,SF,ZF,AF */ 3643 3638 fTmp &= fTmp >> 2; /* CF3,Other3 = AF2,PF2 & CF2,Other2 */ … … 3645 3640 fToFreeMask &= RT_BIT_64(kIemNativeGstReg_EFlags) - 1; 3646 3641 fToFreeMask |= fTmp & RT_BIT_64(kIemNativeGstReg_EFlags); 3647 # endif3648 3642 3649 3643 /* If it matches any shadowed registers. */ … … 3980 3974 } 3981 3975 3982 3976 #ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS 3977 3978 # ifndef IEMLIVENESS_EXTENDED_LAYOUT 3983 3979 /** 3984 3980 * Helper for iemNativeLivenessGetStateByGstReg. … … 4010 4006 return IEMLIVENESS_STATE_UNUSED; 4011 4007 } 4012 4013 #ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS 4008 # endif /* !IEMLIVENESS_EXTENDED_LAYOUT */ 4009 4014 4010 4015 4011 DECL_FORCE_INLINE(uint32_t) 4016 4012 iemNativeLivenessGetStateByGstRegEx(PCIEMLIVENESSENTRY pLivenessEntry, unsigned enmGstRegEx) 4017 4013 { 4014 # ifndef IEMLIVENESS_EXTENDED_LAYOUT 4018 4015 return ((pLivenessEntry->Bit0.bm64 >> enmGstRegEx) & 1) 4019 4016 | (((pLivenessEntry->Bit1.bm64 >> enmGstRegEx) << 1) & 2); 4017 # else 4018 return ( (pLivenessEntry->Bit0.bm64 >> enmGstRegEx) & 1) 4019 | (((pLivenessEntry->Bit1.bm64 >> enmGstRegEx) << 1) & 2) 4020 | (((pLivenessEntry->Bit2.bm64 >> enmGstRegEx) << 2) & 4) 4021 | (((pLivenessEntry->Bit3.bm64 >> enmGstRegEx) << 2) & 8); 4022 # endif 4020 4023 } 4021 4024 … … 4024 4027 iemNativeLivenessGetStateByGstReg(PCIEMLIVENESSENTRY pLivenessEntry, IEMNATIVEGSTREG enmGstReg) 4025 4028 { 4026 uint32_t uRet = ((pLivenessEntry->Bit0.bm64 >> (unsigned)enmGstReg) & 1) 4027 | (((pLivenessEntry->Bit1.bm64 >> (unsigned)enmGstReg) << 1) & 2); 4029 uint32_t uRet = iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, (unsigned)enmGstReg); 4028 4030 if (enmGstReg == kIemNativeGstReg_EFlags) 4029 4031 { 4030 4032 /* Merge the eflags states to one. */ 4033 # ifndef IEMLIVENESS_EXTENDED_LAYOUT 4031 4034 uRet = RT_BIT_32(uRet); 4032 4035 uRet |= RT_BIT_32(pLivenessEntry->Bit0.fEflCf | (pLivenessEntry->Bit1.fEflCf << 1)); … … 4037 4040 uRet |= RT_BIT_32(pLivenessEntry->Bit0.fEflOf | (pLivenessEntry->Bit1.fEflOf << 1)); 4038 4041 uRet = iemNativeLivenessMergeExpandedEFlagsState(uRet); 4042 # else 4043 AssertCompile(IEMLIVENESSBIT_IDX_EFL_OTHER == (unsigned)kIemNativeGstReg_EFlags); 4044 uRet |= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_CF); 4045 uRet |= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_PF); 4046 uRet |= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_AF); 4047 uRet |= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_ZF); 4048 uRet |= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_SF); 4049 uRet |= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_OF); 4050 # endif 4039 4051 } 4040 4052 return uRet; … … 4265 4277 || (enmIntendedUse == kIemNativeGstRegUse_ForFullWrite 4266 4278 ? IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg)) 4267 : IEMLIVENESS_STATE_IS_ACCESS_EXPECTED(iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg)) ), 4279 : enmIntendedUse == kIemNativeGstRegUse_ForUpdate 4280 ? IEMLIVENESS_STATE_IS_MODIFY_EXPECTED( iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg)) 4281 : IEMLIVENESS_STATE_IS_INPUT_EXPECTED( iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg)) ), 4268 4282 ("%s - %u\n", g_aGstShadowInfo[enmGstReg].pszName, iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg))); 4269 4283 #endif … … 4440 4454 #ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS 4441 4455 AssertMsg( pReNative->idxCurCall == 0 4442 || IEMLIVENESS_STATE_IS_ ACCESS_EXPECTED(iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg))4456 || IEMLIVENESS_STATE_IS_INPUT_EXPECTED(iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg)) 4443 4457 || enmGstReg == kIemNativeGstReg_Pc, 4444 4458 ("%s - %u\n", g_aGstShadowInfo[enmGstReg].pszName, iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg))); … … 5430 5444 5431 5445 /** 5432 * Emits code to check if th e content of @a idxAddrReg is within the limit of5433 * idxSegReg, raising a \#GP(0) if it isn't.5446 * Emits code to check if that the content of @a idxAddrReg is within the limit 5447 * of CS, raising a \#GP(0) if it isn't. 5434 5448 * 5435 5449 * @returns New code buffer offset; throws VBox status code on error. … … 5438 5452 * @param idxAddrReg The host register (32-bit) with the address to 5439 5453 * check. 5440 * @param idxSegReg The segment register (X86_SREG_XXX) to check5441 * against.5442 5454 * @param idxInstr The current instruction. 5443 5455 */ 5444 5456 DECL_HIDDEN_THROW(uint32_t) 5445 iemNativeEmitCheckGpr32Against SegLimitMaybeRaiseGp0(PIEMRECOMPILERSTATE pReNative, uint32_t off,5446 uint8_t idxAddrReg, uint8_t idxSegReg, uint8_t idxInstr)5457 iemNativeEmitCheckGpr32AgainstCsSegLimitMaybeRaiseGp0(PIEMRECOMPILERSTATE pReNative, uint32_t off, 5458 uint8_t idxAddrReg, uint8_t idxInstr) 5447 5459 { 5448 5460 /* … … 5458 5470 #endif 5459 5471 5460 AssertStmt(idxSegReg == X86_SREG_CS, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_EMIT_CASE_NOT_IMPLEMENTED_1)); 5461 5462 uint8_t const iTmpLimReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, 5463 (IEMNATIVEGSTREG)(kIemNativeGstReg_SegLimitFirst + idxSegReg), 5464 kIemNativeGstRegUse_ForUpdate); 5465 5466 off = iemNativeEmitCmpGpr32WithGpr(pReNative, off, idxAddrReg, iTmpLimReg); 5472 uint8_t const idxRegCsLim = iemNativeRegAllocTmpForGuestReg(pReNative, &off, 5473 (IEMNATIVEGSTREG)(kIemNativeGstReg_SegLimitFirst + X86_SREG_CS), 5474 kIemNativeGstRegUse_ReadOnly); 5475 5476 off = iemNativeEmitCmpGpr32WithGpr(pReNative, off, idxAddrReg, idxRegCsLim); 5467 5477 off = iemNativeEmitJaToNewLabel(pReNative, off, kIemNativeLabelType_RaiseGp0); 5468 5478 5469 iemNativeRegFreeTmp(pReNative, i TmpLimReg);5479 iemNativeRegFreeTmp(pReNative, idxRegCsLim); 5470 5480 return off; 5471 5481 } … … 6124 6134 #ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS 6125 6135 AssertMsg( pReNative->idxCurCall == 0 6126 || IEMLIVENESS_STATE_IS_ ACCESS_EXPECTED(iemNativeLivenessGetStateByGstRegEx(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], kIemNativeGstReg_EFlags/*_Other*/)),6127 ("Efl_Other - %u\n", iemNativeLivenessGetStateByGstRegEx(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], kIemNativeGstReg_EFlags/*_Other*/)));6136 || IEMLIVENESS_STATE_IS_INPUT_EXPECTED(iemNativeLivenessGetStateByGstRegEx(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], IEMLIVENESSBIT_IDX_EFL_OTHER)), 6137 ("Efl_Other - %u\n", iemNativeLivenessGetStateByGstRegEx(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], IEMLIVENESSBIT_IDX_EFL_OTHER))); 6128 6138 #endif 6129 6139 … … 6378 6388 /* Perform limit checking, potentially raising #GP(0) and exit the TB. */ 6379 6389 /** @todo we can skip this in 32-bit FLAT mode. */ 6380 off = iemNativeEmitCheckGpr32Against SegLimitMaybeRaiseGp0(pReNative, off, idxPcReg, X86_SREG_CS, idxInstr);6390 off = iemNativeEmitCheckGpr32AgainstCsSegLimitMaybeRaiseGp0(pReNative, off, idxPcReg, idxInstr); 6381 6391 6382 6392 off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip)); … … 6430 6440 off = iemNativeEmitAddGpr32Imm(pReNative, off, idxPcReg, offDisp + cbInstr); 6431 6441 off = iemNativeEmitClear16UpGpr(pReNative, off, idxPcReg); 6432 off = iemNativeEmitCheckGpr32Against SegLimitMaybeRaiseGp0(pReNative, off, idxPcReg, X86_SREG_CS, idxInstr);6442 off = iemNativeEmitCheckGpr32AgainstCsSegLimitMaybeRaiseGp0(pReNative, off, idxPcReg, idxInstr); 6433 6443 off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip)); 6434 6444 … … 6533 6543 if (!f64Bit) 6534 6544 /** @todo we can skip this test in FLAT 32-bit mode. */ 6535 off = iemNativeEmitCheckGpr32Against SegLimitMaybeRaiseGp0(pReNative, off, idxPcReg, X86_SREG_CS, idxInstr);6545 off = iemNativeEmitCheckGpr32AgainstCsSegLimitMaybeRaiseGp0(pReNative, off, idxPcReg, idxInstr); 6536 6546 /* Check that the address is canonical, raising #GP(0) + exit TB if it isn't. */ 6537 6547 else if (cbVar > sizeof(uint32_t)) … … 9792 9802 { 9793 9803 PVMCPUCC const pVCpu = pReNative->pVCpu; 9804 # ifndef IEMLIVENESS_EXTENDED_LAYOUT 9794 9805 IEMLIVENESSBIT const LivenessBit0 = pReNative->paLivenessEntries[pReNative->idxCurCall].Bit0; 9795 9806 IEMLIVENESSBIT const LivenessBit1 = pReNative->paLivenessEntries[pReNative->idxCurCall].Bit1; 9796 9807 AssertCompile(IEMLIVENESS_STATE_CLOBBERED == 0); 9797 # define CHECK_FLAG_AND_UPDATE_STATS(a_fEfl, a_fLivenessMember, a_CoreStatName) \9808 # define CHECK_FLAG_AND_UPDATE_STATS(a_fEfl, a_fLivenessMember, a_CoreStatName) \ 9798 9809 if (fEflOutput & (a_fEfl)) \ 9799 9810 { \ 9800 9811 if (LivenessBit0.a_fLivenessMember | LivenessBit1.a_fLivenessMember) \ 9801 STAM_COUNTER_INC(&pVCpu->iem.s. a_CoreStatName ## Required); \9812 STAM_COUNTER_INC(&pVCpu->iem.s.a_CoreStatName ## Required); \ 9802 9813 else \ 9803 STAM_COUNTER_INC(&pVCpu->iem.s. a_CoreStatName ## Skippable); \9814 STAM_COUNTER_INC(&pVCpu->iem.s.a_CoreStatName ## Skippable); \ 9804 9815 } else do { } while (0) 9816 # else 9817 PCIEMLIVENESSENTRY const pLivenessEntry = &pReNative->paLivenessEntries[pReNative->idxCurCall]; 9818 IEMLIVENESSBIT const LivenessClobbered = 9819 { 9820 pLivenessEntry->aBits[IEMLIVENESS_BIT_WRITE].bm64 9821 & ~( pLivenessEntry->aBits[IEMLIVENESS_BIT_READ].bm64 9822 | pLivenessEntry->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 9823 | pLivenessEntry->aBits[IEMLIVENESS_BIT_OTHER].bm64) 9824 }; 9825 IEMLIVENESSBIT const LivenessDelayable = 9826 { 9827 pLivenessEntry->aBits[IEMLIVENESS_BIT_WRITE].bm64 9828 & pLivenessEntry->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 9829 & ~( pLivenessEntry->aBits[IEMLIVENESS_BIT_READ].bm64 9830 | pLivenessEntry->aBits[IEMLIVENESS_BIT_OTHER].bm64) 9831 }; 9832 # define CHECK_FLAG_AND_UPDATE_STATS(a_fEfl, a_fLivenessMember, a_CoreStatName) \ 9833 if (fEflOutput & (a_fEfl)) \ 9834 { \ 9835 if (LivenessClobbered.a_fLivenessMember) \ 9836 STAM_COUNTER_INC(&pVCpu->iem.s.a_CoreStatName ## Skippable); \ 9837 else if (LivenessDelayable.a_fLivenessMember) \ 9838 STAM_COUNTER_INC(&pVCpu->iem.s.a_CoreStatName ## Delayable); \ 9839 else \ 9840 STAM_COUNTER_INC(&pVCpu->iem.s.a_CoreStatName ## Required); \ 9841 } else do { } while (0) 9842 # endif 9805 9843 CHECK_FLAG_AND_UPDATE_STATS(X86_EFL_CF, fEflCf, StatNativeLivenessEflCf); 9806 9844 CHECK_FLAG_AND_UPDATE_STATS(X86_EFL_PF, fEflPf, StatNativeLivenessEflPf); … … 9809 9847 CHECK_FLAG_AND_UPDATE_STATS(X86_EFL_SF, fEflSf, StatNativeLivenessEflSf); 9810 9848 CHECK_FLAG_AND_UPDATE_STATS(X86_EFL_OF, fEflOf, StatNativeLivenessEflOf); 9811 CHECK_FLAG_AND_UPDATE_STATS(~X86_EFL_STATUS_BITS, fEflOther, StatNativeLivenessEflOther);9849 //CHECK_FLAG_AND_UPDATE_STATS(~X86_EFL_STATUS_BITS, fEflOther, StatNativeLivenessEflOther); 9812 9850 # undef CHECK_FLAG_AND_UPDATE_STATS 9813 9851 } … … 9836 9874 PCIEMLIVENESSENTRY const pLivenessEntry = &pReNative->paLivenessEntries[pReNative->idxCurCall - 1]; 9837 9875 uint32_t const fBoth = fEflInput | fEflOutput; 9838 # define ASSERT_ONE_EFL(a_fElfConst, a_ offField) \9876 # define ASSERT_ONE_EFL(a_fElfConst, a_idxField) \ 9839 9877 AssertMsg( !(fBoth & (a_fElfConst)) \ 9840 9878 || (!(fEflInput & (a_fElfConst)) \ 9841 ? IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, kIemNativeGstReg_EFlags + (a_offField))) \ 9842 : IEMLIVENESS_STATE_IS_ACCESS_EXPECTED( iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, kIemNativeGstReg_EFlags + (a_offField))) ), \ 9843 ("%s - %u\n", #a_fElfConst, iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, kIemNativeGstReg_EFlags + (a_offField)))) 9844 ASSERT_ONE_EFL(~(uint32_t)X86_EFL_STATUS_BITS, 0); 9845 ASSERT_ONE_EFL(X86_EFL_CF, 1); 9846 ASSERT_ONE_EFL(X86_EFL_PF, 2); 9847 ASSERT_ONE_EFL(X86_EFL_AF, 3); 9848 ASSERT_ONE_EFL(X86_EFL_ZF, 4); 9849 ASSERT_ONE_EFL(X86_EFL_SF, 5); 9850 ASSERT_ONE_EFL(X86_EFL_OF, 6); 9879 ? IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, a_idxField)) \ 9880 : !(fEflOutput & (a_fElfConst)) \ 9881 ? IEMLIVENESS_STATE_IS_INPUT_EXPECTED( iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, a_idxField)) \ 9882 : IEMLIVENESS_STATE_IS_MODIFY_EXPECTED( iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, a_idxField)) ), \ 9883 ("%s - %u\n", #a_fElfConst, iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, a_idxField))) 9884 ASSERT_ONE_EFL(~(uint32_t)X86_EFL_STATUS_BITS, IEMLIVENESSBIT_IDX_EFL_OTHER); 9885 ASSERT_ONE_EFL(X86_EFL_CF, IEMLIVENESSBIT_IDX_EFL_CF); 9886 ASSERT_ONE_EFL(X86_EFL_PF, IEMLIVENESSBIT_IDX_EFL_PF); 9887 ASSERT_ONE_EFL(X86_EFL_AF, IEMLIVENESSBIT_IDX_EFL_AF); 9888 ASSERT_ONE_EFL(X86_EFL_ZF, IEMLIVENESSBIT_IDX_EFL_ZF); 9889 ASSERT_ONE_EFL(X86_EFL_SF, IEMLIVENESSBIT_IDX_EFL_SF); 9890 ASSERT_ONE_EFL(X86_EFL_OF, IEMLIVENESSBIT_IDX_EFL_OF); 9851 9891 # undef ASSERT_ONE_EFL 9852 9892 } … … 13670 13710 /* The initial (final) entry. */ 13671 13711 idxCall--; 13672 paLivenessEntries[idxCall].Bit0.bm64 = IEMLIVENESSBIT0_ALL_UNUSED; 13673 paLivenessEntries[idxCall].Bit1.bm64 = IEMLIVENESSBIT1_ALL_UNUSED; 13712 IEM_LIVENESS_RAW_INIT_AS_UNUSED(&paLivenessEntries[idxCall]); 13674 13713 13675 13714 /* Loop backwards thru the calls and fill in the other entries. */ … … 13782 13821 { 13783 13822 PCIEMLIVENESSENTRY pLivenessEntry = &pReNative->paLivenessEntries[idxCurCall]; 13823 # ifndef IEMLIVENESS_EXTENDED_LAYOUT 13784 13824 static const char s_achState[] = "CUXI"; 13825 # else 13826 static const char s_achState[] = "UxRrWwMmCcQqKkNn"; 13827 # endif 13785 13828 13786 13829 char szGpr[17]; -
trunk/src/VBox/VMM/VMMR3/IEMR3.cpp
r103318 r103393 51 51 #include <iprt/string.h> 52 52 53 #ifdef VBOX_WITH_IEM_RECOMPILER 54 # include "IEMN8veRecompiler.h" 55 #endif 56 53 57 54 58 /********************************************************************************************************************************* … … 340 344 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/DataTlb-SafeTotal", idCpu); 341 345 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/DataTlb-Hits-*", idCpu); 342 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PPM, szVal, szPat,346 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PPM, szVal, true, szPat, 343 347 "Data TLB actual miss rate", "/IEM/CPU%u/DataTlb-SafeRate", idCpu); 344 348 … … 453 457 "/IEM/CPU%u/re/NativeRegFindFreeLivenessHelped", idCpu); 454 458 455 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippable", idCpu); 456 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfSkippable", idCpu); 457 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfSkippable", idCpu); 458 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfSkippable", idCpu); 459 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfSkippable", idCpu); 460 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfSkippable", idCpu); 461 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOtherSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.OTHER updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOtherSkippable", idCpu); 462 463 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfRequired", idCpu); 464 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfRequired", idCpu); 465 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfRequired", idCpu); 466 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfRequired", idCpu); 467 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfRequired", idCpu); 468 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfRequired", idCpu); 469 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOtherRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.OTHER updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOtherRequired", idCpu); 470 471 /* Sum up all status bits*/ 459 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippable", idCpu); 460 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfSkippable", idCpu); 461 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfSkippable", idCpu); 462 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfSkippable", idCpu); 463 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfSkippable", idCpu); 464 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfSkippable", idCpu); 465 466 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfRequired", idCpu); 467 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfRequired", idCpu); 468 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfRequired", idCpu); 469 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfRequired", idCpu); 470 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfRequired", idCpu); 471 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfRequired", idCpu); 472 473 # ifdef IEMLIVENESS_EXTENDED_LAYOUT 474 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfDelayable", idCpu); 475 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfDelayable", idCpu); 476 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfDelayable", idCpu); 477 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfDelayable", idCpu); 478 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfDelayable", idCpu); 479 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfDelayable", idCpu); 480 # endif 481 482 /* Sum up all status bits ('_' is a sorting hack). */ 472 483 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fSkippable*", idCpu); 473 484 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total skippable EFLAGS status bit updating", 474 "/IEM/CPU%u/re/NativeLivenessEFlags StatusSkippable", idCpu);485 "/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippable", idCpu); 475 486 476 487 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fRequired*", idCpu); 477 488 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total required STATUS status bit updating", 478 "/IEM/CPU%u/re/NativeLivenessEFlagsStatusRequired", idCpu); 489 "/IEM/CPU%u/re/NativeLivenessEFlags_StatusRequired", idCpu); 490 491 # ifdef IEMLIVENESS_EXTENDED_LAYOUT 492 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fDelayable*", idCpu); 493 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total potentially delayable STATUS status bit updating", 494 "/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayable", idCpu); 495 # endif 496 497 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?f*", idCpu); 498 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total STATUS status bit events of any kind", 499 "/IEM/CPU%u/re/NativeLivenessEFlags_StatusTotal", idCpu); 479 500 480 501 /* Ratio of the status bit skippables. */ 481 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags Status*", idCpu);482 RTStrPrintf(szVal, sizeof(sz Pat), "/IEM/CPU%u/re/NativeLivenessEFlagsStatusSkippable", idCpu);483 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, szPat,502 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusTotal", idCpu); 503 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippable", idCpu); 504 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat, 484 505 "Total skippable EFLAGS status bit updating percentage", 485 "/IEM/CPU%u/re/NativeLivenessEFlagsStatusSkippablePct", idCpu); 506 "/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippablePct", idCpu); 507 508 # ifdef IEMLIVENESS_EXTENDED_LAYOUT 509 /* Ratio of the status bit skippables. */ 510 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayable", idCpu); 511 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat, 512 "Total potentially delayable EFLAGS status bit updating percentage", 513 "/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayablePct", idCpu); 514 # endif 486 515 487 516 /* Ratios of individual bits. */ … … 490 519 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippable", idCpu); 491 520 Assert(szVal[offFlagChar] == 'C'); 492 szPat[offFlagChar] = szVal[offFlagChar] = 'C'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, szPat, "Skippable EFLAGS.CF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippablePct", idCpu);493 szPat[offFlagChar] = szVal[offFlagChar] = 'P'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, szPat, "Skippable EFLAGS.PF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsPfSkippablePct", idCpu);494 szPat[offFlagChar] = szVal[offFlagChar] = 'A'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, szPat, "Skippable EFLAGS.AF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsAfSkippablePct", idCpu);495 szPat[offFlagChar] = szVal[offFlagChar] = 'Z'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, szPat, "Skippable EFLAGS.ZF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsZfSkippablePct", idCpu);496 szPat[offFlagChar] = szVal[offFlagChar] = 'S'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, szPat, "Skippable EFLAGS.SF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsSfSkippablePct", idCpu);497 szPat[offFlagChar] = szVal[offFlagChar] = 'O'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, szPat, "Skippable EFLAGS.OF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsOfSkippablePct", idCpu);521 szPat[offFlagChar] = szVal[offFlagChar] = 'C'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.CF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippablePct", idCpu); 522 szPat[offFlagChar] = szVal[offFlagChar] = 'P'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.PF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsPfSkippablePct", idCpu); 523 szPat[offFlagChar] = szVal[offFlagChar] = 'A'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.AF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsAfSkippablePct", idCpu); 524 szPat[offFlagChar] = szVal[offFlagChar] = 'Z'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.ZF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsZfSkippablePct", idCpu); 525 szPat[offFlagChar] = szVal[offFlagChar] = 'S'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.SF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsSfSkippablePct", idCpu); 526 szPat[offFlagChar] = szVal[offFlagChar] = 'O'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.OF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsOfSkippablePct", idCpu); 498 527 499 528 # endif /* VBOX_WITH_STATISTICS */ -
trunk/src/VBox/VMM/VMMR3/STAM.cpp
r102853 r103393 987 987 * Sum it up with the rest. 988 988 */ 989 uint64_t uSum = uValue;989 uint64_t uSum = pSum->fAddValueToSum ? uValue : 0; 990 990 uintptr_t i = pSum->cSummands; 991 991 while (i-- > 1) … … 1197 1197 * calculating the percentage. These must have 1198 1198 * compatible types. 1199 * 1200 * The @a pszName is implicitly included in the sum.1201 * 1199 * @param fAddValueToSum Whether to add @a pszValue to the values that 1200 * @a pszSummandPattern specifies (@c true) or not 1201 * (@c false). 1202 1202 * @param pszDesc Sample description. 1203 1203 * @param pszName The sample name format string. … … 1205 1205 */ 1206 1206 VMMR3DECL(int) STAMR3RegisterPctOfSumV(PUVM pUVM, STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszValue, 1207 const char *pszSummandPattern, const char *pszDesc, const char *pszName, va_list va) 1207 bool fAddValueToSum, const char *pszSummandPattern, const char *pszDesc, 1208 const char *pszName, va_list va) 1208 1209 { 1209 1210 char szFormattedName[STAM_MAX_NAME_LEN + 8]; … … 1234 1235 pSum->enmType = STAMTYPE_COUNTER; 1235 1236 pSum->enmUnit = enmUnit; 1237 pSum->fAddValueToSum = fAddValueToSum; 1236 1238 1237 1239 STAM_LOCK_WR(pUVM); … … 1282 1284 * calculating the percentage. These must have 1283 1285 * compatible types. 1284 * 1285 * The @a pszName is implicitly included in the sum.1286 * 1286 * @param fAddValueToSum Whether to add @a pszValue to the values that 1287 * @a pszSummandPattern specifies (@c true) or not 1288 * (@c false). 1287 1289 * @param pszDesc Sample description. 1288 1290 * @param pszName The sample name format string. … … 1290 1292 */ 1291 1293 VMMR3DECL(int) STAMR3RegisterPctOfSum(PUVM pUVM, STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszValue, 1292 const char *pszSummandPattern, const char *pszDesc, const char *pszName, ...) 1294 bool fAddValueToSum, const char *pszSummandPattern, const char *pszDesc, 1295 const char *pszName, ...) 1293 1296 { 1294 1297 va_list va; 1295 1298 va_start(va, pszName); 1296 int rc = STAMR3RegisterPctOfSumV(pUVM, enmVisibility, enmUnit, pszValue, pszSummandPattern, pszDesc, pszName, va); 1299 int rc = STAMR3RegisterPctOfSumV(pUVM, enmVisibility, enmUnit, pszValue, fAddValueToSum, pszSummandPattern, 1300 pszDesc, pszName, va); 1297 1301 va_end(va); 1298 1302 return rc; -
trunk/src/VBox/VMM/include/IEMInternal.h
r103377 r103393 1818 1818 /** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */ 1819 1819 STAMCOUNTER StatNativeLivenessEflOfSkippable; 1820 /** Native recompiler: Number of opportunities to skip EFLAGS.OTHER updating. */1821 STAMCOUNTER StatNativeLivenessEflOtherSkippable;1822 1820 /** Native recompiler: Number of required EFLAGS.CF updates. */ 1823 1821 STAMCOUNTER StatNativeLivenessEflCfRequired; … … 1832 1830 /** Native recompiler: Number of required EFLAGS.OF updates. */ 1833 1831 STAMCOUNTER StatNativeLivenessEflOfRequired; 1834 /** Native recompiler: Number of required EFLAGS.OTHER updates. */ 1835 STAMCOUNTER StatNativeLivenessEflOtherRequired; 1836 1837 uint64_t au64Padding[7]; 1832 /** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */ 1833 STAMCOUNTER StatNativeLivenessEflCfDelayable; 1834 /** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */ 1835 STAMCOUNTER StatNativeLivenessEflPfDelayable; 1836 /** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */ 1837 STAMCOUNTER StatNativeLivenessEflAfDelayable; 1838 /** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */ 1839 STAMCOUNTER StatNativeLivenessEflZfDelayable; 1840 /** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */ 1841 STAMCOUNTER StatNativeLivenessEflSfDelayable; 1842 /** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */ 1843 STAMCOUNTER StatNativeLivenessEflOfDelayable; 1844 1845 uint64_t au64Padding[3]; 1838 1846 /** @} */ 1839 1847 -
trunk/src/VBox/VMM/include/IEMN8veRecompiler.h
r103334 r103393 48 48 #if 1 || defined(DOXYGEN_RUNNING) 49 49 # define IEMNATIVE_WITH_LIVENESS_ANALYSIS 50 /*# define IEMLIVENESS_EXTENDED_LAYOUT*/ 50 51 #endif 51 52 … … 413 414 AssertCompileSize(IEMLIVENESSBIT, 8); 414 415 416 #define IEMLIVENESSBIT_IDX_EFL_OTHER ((unsigned)kIemNativeGstReg_EFlags + 0) 417 #define IEMLIVENESSBIT_IDX_EFL_CF ((unsigned)kIemNativeGstReg_EFlags + 1) 418 #define IEMLIVENESSBIT_IDX_EFL_PF ((unsigned)kIemNativeGstReg_EFlags + 2) 419 #define IEMLIVENESSBIT_IDX_EFL_AF ((unsigned)kIemNativeGstReg_EFlags + 3) 420 #define IEMLIVENESSBIT_IDX_EFL_ZF ((unsigned)kIemNativeGstReg_EFlags + 4) 421 #define IEMLIVENESSBIT_IDX_EFL_SF ((unsigned)kIemNativeGstReg_EFlags + 5) 422 #define IEMLIVENESSBIT_IDX_EFL_OF ((unsigned)kIemNativeGstReg_EFlags + 6) 423 415 424 416 425 /** … … 423 432 typedef union IEMLIVENESSENTRY 424 433 { 434 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 425 435 uint64_t bm64[16 / 8]; 426 436 uint16_t bm32[16 / 4]; 427 437 uint16_t bm16[16 / 2]; 428 uint8_t bm8[16 / 1]; 438 uint8_t bm8[ 16 / 1]; 439 IEMLIVENESSBIT aBits[2]; 440 #else 441 uint64_t bm64[32 / 8]; 442 uint16_t bm32[32 / 4]; 443 uint16_t bm16[32 / 2]; 444 uint8_t bm8[ 32 / 1]; 445 IEMLIVENESSBIT aBits[4]; 446 #endif 429 447 RT_GCC_EXTENSION struct 430 448 { … … 433 451 /** Bit \#1 of the register states. */ 434 452 IEMLIVENESSBIT Bit1; 453 #ifdef IEMLIVENESS_EXTENDED_LAYOUT 454 /** Bit \#2 of the register states. */ 455 IEMLIVENESSBIT Bit2; 456 /** Bit \#3 of the register states. */ 457 IEMLIVENESSBIT Bit3; 458 #endif 435 459 }; 436 460 } IEMLIVENESSENTRY; 461 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 437 462 AssertCompileSize(IEMLIVENESSENTRY, 16); 463 #else 464 AssertCompileSize(IEMLIVENESSENTRY, 32); 465 #endif 438 466 /** Pointer to a liveness state entry. */ 439 467 typedef IEMLIVENESSENTRY *PIEMLIVENESSENTRY; … … 445 473 #define IEMLIVENESSBIT_MASK UINT64_C(0x0007fffffff0ffff) 446 474 447 #define IEMLIVENESSBIT0_XCPT_OR_CALL UINT64_C(0x0000000000000000) 448 #define IEMLIVENESSBIT1_XCPT_OR_CALL IEMLIVENESSBIT_MASK 449 450 #define IEMLIVENESSBIT0_ALL_UNUSED IEMLIVENESSBIT_MASK 451 #define IEMLIVENESSBIT1_ALL_UNUSED UINT64_C(0x0000000000000000) 475 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 476 # define IEMLIVENESSBIT0_XCPT_OR_CALL UINT64_C(0x0000000000000000) 477 # define IEMLIVENESSBIT1_XCPT_OR_CALL IEMLIVENESSBIT_MASK 478 479 # define IEMLIVENESSBIT0_ALL_UNUSED IEMLIVENESSBIT_MASK 480 # define IEMLIVENESSBIT1_ALL_UNUSED UINT64_C(0x0000000000000000) 481 #endif 452 482 453 483 #define IEMLIVENESSBIT_ALL_EFL_MASK UINT64_C(0x0007f00000000000) 454 484 455 #define IEMLIVENESSBIT0_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK 456 #define IEMLIVENESSBIT1_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK 485 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 486 # define IEMLIVENESSBIT0_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK 487 # define IEMLIVENESSBIT1_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK 488 #endif 457 489 /** @} */ 458 490 … … 475 507 * 476 508 * @{ */ 509 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 477 510 /** The register will be clobbered and the current value thrown away. 478 511 * … … 481 514 * preserve the high priority IEMLIVENESS_STATE_XCPT_OR_CALL and 482 515 * IEMLIVENESS_STATE_INPUT states. */ 483 # define IEMLIVENESS_STATE_CLOBBERED0516 # define IEMLIVENESS_STATE_CLOBBERED 0 484 517 /** The register is unused in the remainder of the TB. 485 518 * 486 519 * This is an initial state and can not be set by any of the 487 520 * iemNativeLivenessFunc_xxxx callbacks. */ 488 # define IEMLIVENESS_STATE_UNUSED1521 # define IEMLIVENESS_STATE_UNUSED 1 489 522 /** The register value is required in a potential call or exception. 490 523 * … … 501 534 * 4. mask = ~0; 502 535 */ 503 # define IEMLIVENESS_STATE_XCPT_OR_CALL2536 # define IEMLIVENESS_STATE_XCPT_OR_CALL 2 504 537 /** The register value is used as input. 505 538 * … … 513 546 * When applying this state we just or in the value in the outgoing state and 514 547 * mask. */ 515 # define IEMLIVENESS_STATE_INPUT3548 # define IEMLIVENESS_STATE_INPUT 3 516 549 /** Mask of the state bits. */ 517 # define IEMLIVENESS_STATE_MASK3550 # define IEMLIVENESS_STATE_MASK 3 518 551 /** The number of bits per state. */ 519 #define IEMLIVENESS_STATE_BIT_COUNT 2 520 /** Check if we're expecting accesses to a register with the given (previous) liveness state. 521 * . */ 522 #define IEMLIVENESS_STATE_IS_ACCESS_EXPECTED(a_uState) ((uint32_t)((a_uState) - 1U) >= (uint32_t)(IEMLIVENESS_STATE_INPUT - 1U)) 552 # define IEMLIVENESS_STATE_BIT_COUNT 2 553 /** Check if we're expecting read & write accesses to a register with the given (previous) liveness state. */ 554 # define IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState) ((uint32_t)((a_uState) - 1U) >= (uint32_t)(IEMLIVENESS_STATE_INPUT - 1U)) 555 /** Check if we're expecting read accesses to a register with the given (previous) liveness state. */ 556 # define IEMLIVENESS_STATE_IS_INPUT_EXPECTED(a_uState) IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState) 523 557 /** Check if a register clobbering is expected given the (previous) liveness state. 524 558 * The state must be either CLOBBERED or XCPT_OR_CALL, but it may also 525 559 * include INPUT if the register is used in more than one place. */ 526 #define IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(a_uState) ((uint32_t)(a_uState) != IEMLIVENESS_STATE_UNUSED) 560 # define IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(a_uState) ((uint32_t)(a_uState) != IEMLIVENESS_STATE_UNUSED) 561 562 #else /* IEMLIVENESS_EXTENDED_LAYOUT */ 563 /** The register is not used any more. */ 564 # define IEMLIVENESS_STATE_UNUSED 0 565 /** Flag: The register is required in a potential exception or call. */ 566 # define IEMLIVENESS_STATE_POT_XCPT_OR_CALL 1 567 # define IEMLIVENESS_BIT_POT_XCPT_OR_CALL 0 568 /** Flag: The register is read. */ 569 # define IEMLIVENESS_STATE_READ 2 570 # define IEMLIVENESS_BIT_READ 1 571 /** Flag: The register is written. */ 572 # define IEMLIVENESS_STATE_WRITE 4 573 # define IEMLIVENESS_BIT_WRITE 2 574 /** Flag: Unconditional call (not needed, can be redefined for research). */ 575 # define IEMLIVENESS_STATE_CALL 8 576 # define IEMLIVENESS_BIT_CALL 3 577 # define IEMLIVENESS_BIT_OTHER 3 /**< More convenient name for this one. */ 578 # define IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState) \ 579 ( ((a_uState) & (IEMLIVENESS_STATE_WRITE | IEMLIVENESS_STATE_READ)) == (IEMLIVENESS_STATE_WRITE | IEMLIVENESS_STATE_READ) ) 580 # define IEMLIVENESS_STATE_IS_INPUT_EXPECTED(a_uState) RT_BOOL((a_uState) & IEMLIVENESS_STATE_READ) 581 # define IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(a_uState) RT_BOOL((a_uState) & IEMLIVENESS_STATE_WRITE) 582 #endif /* IEMLIVENESS_EXTENDED_LAYOUT */ 527 583 /** @} */ 528 584 … … 533 589 * 534 590 * @{ */ 591 /** Initializing the state as all unused. */ 592 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 593 # define IEM_LIVENESS_RAW_INIT_AS_UNUSED(a_pOutgoing) \ 594 do { \ 595 (a_pOutgoing)->Bit0.bm64 = IEMLIVENESSBIT0_ALL_UNUSED; \ 596 (a_pOutgoing)->Bit1.bm64 = IEMLIVENESSBIT1_ALL_UNUSED; \ 597 } while (0) 598 #else 599 # define IEM_LIVENESS_RAW_INIT_AS_UNUSED(a_pOutgoing) \ 600 do { \ 601 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 = 0; \ 602 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ ].bm64 = 0; \ 603 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_WRITE ].bm64 = 0; \ 604 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_OTHER ].bm64 = 0; \ 605 } while (0) 606 #endif 607 535 608 /** Initializing the outgoing state with a potential xcpt or call state. 536 609 * This only works when all later changes will be IEMLIVENESS_STATE_INPUT. */ 537 #define IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(a_pOutgoing, a_pIncoming) \ 610 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 611 # define IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(a_pOutgoing, a_pIncoming) \ 538 612 do { \ 539 613 (a_pOutgoing)->Bit0.bm64 = (a_pIncoming)->Bit0.bm64 & (a_pIncoming)->Bit1.bm64; \ 540 614 (a_pOutgoing)->Bit1.bm64 = IEMLIVENESSBIT1_XCPT_OR_CALL; \ 541 615 } while (0) 616 #else 617 # define IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(a_pOutgoing, a_pIncoming) \ 618 do { \ 619 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 = IEMLIVENESSBIT_MASK; \ 620 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ ].bm64 = (a_pIncoming)->aBits[IEMLIVENESS_BIT_READ].bm64; \ 621 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_WRITE ].bm64 = 0; \ 622 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_OTHER ].bm64 = 0; \ 623 } while (0) 624 #endif 542 625 543 626 /** Adds a segment base register as input to the outgoing state. */ 544 #define IEM_LIVENESS_RAW_SEG_BASE_INPUT(a_pOutgoing, a_iSReg) do { \ 627 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 628 # define IEM_LIVENESS_RAW_SEG_BASE_INPUT(a_pOutgoing, a_iSReg) do { \ 545 629 (a_pOutgoing)->Bit0.bmSegBase |= RT_BIT_64(a_iSReg); \ 546 630 (a_pOutgoing)->Bit1.bmSegBase |= RT_BIT_64(a_iSReg); \ 547 631 } while (0) 632 #else 633 # define IEM_LIVENESS_RAW_SEG_BASE_INPUT(a_pOutgoing, a_iSReg) do { \ 634 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegBase |= RT_BIT_64(a_iSReg); \ 635 } while (0) 636 #endif 548 637 549 638 /** Adds a segment attribute register as input to the outgoing state. */ 550 #define IEM_LIVENESS_RAW_SEG_ATTRIB_INPUT(a_pOutgoing, a_iSReg) do { \ 639 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 640 # define IEM_LIVENESS_RAW_SEG_ATTRIB_INPUT(a_pOutgoing, a_iSReg) do { \ 551 641 (a_pOutgoing)->Bit0.bmSegAttrib |= RT_BIT_64(a_iSReg); \ 552 642 (a_pOutgoing)->Bit1.bmSegAttrib |= RT_BIT_64(a_iSReg); \ 553 643 } while (0) 554 644 #else 645 # define IEM_LIVENESS_RAW_SEG_ATTRIB_INPUT(a_pOutgoing, a_iSReg) do { \ 646 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegAttrib |= RT_BIT_64(a_iSReg); \ 647 } while (0) 648 #endif 555 649 556 650 /** Adds a segment limit register as input to the outgoing state. */ 557 #define IEM_LIVENESS_RAW_SEG_LIMIT_INPUT(a_pOutgoing, a_iSReg) do { \ 651 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 652 # define IEM_LIVENESS_RAW_SEG_LIMIT_INPUT(a_pOutgoing, a_iSReg) do { \ 558 653 (a_pOutgoing)->Bit0.bmSegLimit |= RT_BIT_64(a_iSReg); \ 559 654 (a_pOutgoing)->Bit1.bmSegLimit |= RT_BIT_64(a_iSReg); \ 560 655 } while (0) 656 #else 657 # define IEM_LIVENESS_RAW_SEG_LIMIT_INPUT(a_pOutgoing, a_iSReg) do { \ 658 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegLimit |= RT_BIT_64(a_iSReg); \ 659 } while (0) 660 #endif 561 661 562 662 /** Adds a segment limit register as input to the outgoing state. */ 563 #define IEM_LIVENESS_RAW_EFLAGS_ONE_INPUT(a_pOutgoing, a_fEflMember) do { \ 663 #ifndef IEMLIVENESS_EXTENDED_LAYOUT 664 # define IEM_LIVENESS_RAW_EFLAGS_ONE_INPUT(a_pOutgoing, a_fEflMember) do { \ 564 665 (a_pOutgoing)->Bit0.a_fEflMember |= 1; \ 565 666 (a_pOutgoing)->Bit1.a_fEflMember |= 1; \ 566 667 } while (0) 668 #else 669 # define IEM_LIVENESS_RAW_EFLAGS_ONE_INPUT(a_pOutgoing, a_fEflMember) do { \ 670 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].a_fEflMember |= 1; \ 671 } while (0) 672 #endif 567 673 /** @} */ 568 674 -
trunk/src/VBox/VMM/include/STAMInternal.h
r102828 r103393 99 99 uint8_t enmTypeFirst; 100 100 /** Used to decide the unit when gathering summands during registration. */ 101 uint8_t enmUnit; 101 uint8_t enmUnit : 7; 102 /** Used by pct-of-sum to decide whether to include the value in the sum. */ 103 uint8_t fAddValueToSum : 1; 102 104 /** Max number of items paSummands can hold. */ 103 105 uint8_t cSummandsAlloc;
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