Changeset 101083 in vbox
- Timestamp:
- Sep 11, 2023 4:50:06 PM (13 months ago)
- File:
-
- 1 edited
-
trunk/include/iprt/armv8.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/iprt/armv8.h
r100119 r101083 1146 1146 1147 1147 1148 /** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0. 1149 * @{ */ 1150 /* Bit 0 - 3 - Reserved. */ 1151 /** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */ 1152 #define ARMV8_ID_AA64ISAR0_EL1_AES (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1153 #define ARMV8_ID_AA64ISAR0_EL1_AES_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_AES) >> 4) 1154 /** No AES instructions implemented. */ 1155 # define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0 1156 /** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */ 1157 # define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1 1158 /** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */ 1159 # define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2 1160 /** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */ 1161 #define ARMV8_ID_AA64ISAR0_EL1_SHA1 (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1162 #define ARMV8_ID_AA64ISAR0_EL1_SHA1_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_SHA1) >> 8) 1163 /** No SHA1 instructions implemented. */ 1164 # define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0 1165 /** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */ 1166 # define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1 1167 /** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */ 1168 #define ARMV8_ID_AA64ISAR0_EL1_SHA2 (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1169 #define ARMV8_ID_AA64ISAR0_EL1_SHA2_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_SHA2) >> 12) 1170 /** No SHA2 instructions implemented. */ 1171 # define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0 1172 /** SHA256 instructions implemented (FEAT_SHA256). */ 1173 # define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1 1174 /** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */ 1175 # define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2 1176 /** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */ 1177 #define ARMV8_ID_AA64ISAR0_EL1_CRC32 (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1178 #define ARMV8_ID_AA64ISAR0_EL1_CRC32_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_CRC32) >> 16) 1179 /** No CRC32 instructions implemented. */ 1180 # define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0 1181 /** CRC32 instructions implemented (FEAT_CRC32). */ 1182 # define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1 1183 /** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */ 1184 #define ARMV8_ID_AA64ISAR0_EL1_ATOMIC (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1185 #define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_ATOMIC) >> 20) 1186 /** No Atomic instructions implemented. */ 1187 # define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0 1188 /** Atomic instructions implemented (FEAT_LSE). */ 1189 # define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2 1190 /** Bit 24 - 27 - Indicates support for TME instructions. */ 1191 #define ARMV8_ID_AA64ISAR0_EL1_TME (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1192 #define ARMV8_ID_AA64ISAR0_EL1_TME_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_TME) >> 24) 1193 /** TME instructions are not implemented. */ 1194 # define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0 1195 /** TME instructions are implemented. */ 1196 # define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1 1197 /** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */ 1198 #define ARMV8_ID_AA64ISAR0_EL1_RDM (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1199 #define ARMV8_ID_AA64ISAR0_EL1_RDM_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_RDM) >> 28) 1200 /** No RDMA instructions implemented. */ 1201 # define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0 1202 /** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */ 1203 # define ARMV8_ID_AA64ISAR0_EL1_RAS_SUPPORTED 1 1204 /** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */ 1205 #define ARMV8_ID_AA64ISAR0_EL1_SHA3 (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1206 #define ARMV8_ID_AA64ISAR0_EL1_SHA3_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_SHA3) >> 32) 1207 /** No SHA3 instructions implemented. */ 1208 # define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0 1209 /** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */ 1210 # define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1 1211 /** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */ 1212 #define ARMV8_ID_AA64ISAR0_EL1_SM3 (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1213 #define ARMV8_ID_AA64ISAR0_EL1_SM3_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_SM3) >> 36) 1214 /** No SM3 instructions implemented. */ 1215 # define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0 1216 /** SM3 instructions implemented (FEAT_SM3). */ 1217 # define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1 1218 /** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */ 1219 #define ARMV8_ID_AA64ISAR0_EL1_SM4 (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 1220 #define ARMV8_ID_AA64ISAR0_EL1_SM4_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_SM4) >> 40) 1221 /** No SM4 instructions implemented. */ 1222 # define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0 1223 /** SM4 instructions implemented (FEAT_SM4). */ 1224 # define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1 1225 /** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */ 1226 #define ARMV8_ID_AA64ISAR0_EL1_DP (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47)) 1227 #define ARMV8_ID_AA64ISAR0_EL1_DP_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_DP) >> 44) 1228 /** No Dot Product instructions implemented. */ 1229 # define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0 1230 /** UDOT and SDOT instructions implemented (FEAT_DotProd). */ 1231 # define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1 1232 /** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */ 1233 #define ARMV8_ID_AA64ISAR0_EL1_FHM (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51)) 1234 #define ARMV8_ID_AA64ISAR0_EL1_FHM_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_DIT) >> 48) 1235 /** FMLAL and FMLSL instructions are not implemented. */ 1236 # define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0 1237 /** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */ 1238 # define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1 1239 /** Bit 52 - 55 - Indicates support for flag manipulation instructions. */ 1240 #define ARMV8_ID_AA64ISAR0_EL1_TS (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55)) 1241 #define ARMV8_ID_AA64ISAR0_EL1_TS_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_TS) >> 52) 1242 /** No flag manipulation instructions implemented. */ 1243 # define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0 1244 /** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */ 1245 # define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1 1246 /** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */ 1247 # define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2 1248 /** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */ 1249 #define ARMV8_ID_AA64ISAR0_EL1_TLB (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59)) 1250 #define ARMV8_ID_AA64ISAR0_EL1_TLB_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_TLB) >> 56) 1251 /** Outer Sahreable and TLB range maintenance instructions are not implemented. */ 1252 # define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0 1253 /** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */ 1254 # define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1 1255 /** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */ 1256 # define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2 1257 /** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */ 1258 #define ARMV8_ID_AA64ISAR0_EL1_RNDR (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63)) 1259 #define ARMV8_ID_AA64ISAR0_EL1_RNDR_GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_RNDR) >> 60) 1260 /** No Random Number instructions implemented. */ 1261 # define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0 1262 /** RNDR and RDNRRS registers are implemented . */ 1263 # define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1 1264 /** @} */ 1265 1266 1267 /** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0. 1268 * @{ */ 1269 /** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */ 1270 #define ARMV8_ID_AA64ISAR1_EL1_DPB (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1271 #define ARMV8_ID_AA64ISAR1_EL1_DPB_GET(a_IdAa64Isar1El1) ((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_DPB) 1272 /** DC CVAP not supported. */ 1273 # define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0 1274 /** DC CVAP supported (FEAT_DPB). */ 1275 # define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1 1276 /** DC CVAP and DC CVADP supported (FEAT_DPB2). */ 1277 # define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2 1278 /** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */ 1279 #define ARMV8_ID_AA64ISAR1_EL1_APA (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1280 #define ARMV8_ID_AA64ISAR1_EL1_APA_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_APA) >> 4) 1281 /** Address Authentication using the QARMA5 algorithm is not implemented. */ 1282 # define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0 1283 /** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */ 1284 # define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1 1285 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */ 1286 # define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2 1287 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */ 1288 # define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3 1289 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */ 1290 # define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4 1291 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */ 1292 # define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5 1293 /** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */ 1294 #define ARMV8_ID_AA64ISAR1_EL1_API (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1295 #define ARMV8_ID_AA64ISAR1_EL1_API_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_API) >> 8) 1296 /** Address Authentication using the QARMA5 algorithm is not implemented. */ 1297 # define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0 1298 /** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */ 1299 # define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1 1300 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */ 1301 # define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2 1302 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */ 1303 # define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3 1304 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */ 1305 # define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4 1306 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */ 1307 # define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5 1308 /** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */ 1309 #define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1310 #define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_FJCVTZS) >> 12) 1311 /** No FJCVTZS instruction implemented. */ 1312 # define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0 1313 /** FJCVTZS instruction implemented (FEAT_JSCVT). */ 1314 # define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1 1315 /** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */ 1316 #define ARMV8_ID_AA64ISAR1_EL1_FCMA (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1317 #define ARMV8_ID_AA64ISAR1_EL1_FCMA_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_FCMA) >> 16) 1318 /** No FCMLA and FCADD instructions implemented. */ 1319 # define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0 1320 /** FCMLA and FCADD instructions implemented (FEAT_FCMA). */ 1321 # define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1 1322 /** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */ 1323 #define ARMV8_ID_AA64ISAR1_EL1_LRCPC (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1324 #define ARMV8_ID_AA64ISAR1_EL1_LRCPC_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_LRCPC) >> 20) 1325 /** No RCpc instructions implemented. */ 1326 # define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0 1327 /** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */ 1328 # define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1 1329 /** The no ffset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */ 1330 # define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2 1331 /** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */ 1332 #define ARMV8_ID_AA64ISAR1_EL1_GPA (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1333 #define ARMV8_ID_AA64ISAR1_EL1_GPA_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_GPA) >> 24) 1334 /** Generic Authentication using the QARMA5 algorithm is not implemented. */ 1335 # define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0 1336 /** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */ 1337 # define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1 1338 /** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */ 1339 #define ARMV8_ID_AA64ISAR1_EL1_GPI (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1340 #define ARMV8_ID_AA64ISAR1_EL1_GPI_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_GPI) >> 28) 1341 /** Generic Authentication using an implementation defined algorithm is not implemented. */ 1342 # define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0 1343 /** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */ 1344 # define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1 1345 /** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */ 1346 #define ARMV8_ID_AA64ISAR1_EL1_FRINTTS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1347 #define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_FRINTTS) >> 32) 1348 /** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */ 1349 # define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0 1350 /** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */ 1351 # define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1 1352 /** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */ 1353 #define ARMV8_ID_AA64ISAR1_EL1_SB (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1354 #define ARMV8_ID_AA64ISAR1_EL1_SB_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_SB) >> 36) 1355 /** No SB instructions implemented. */ 1356 # define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0 1357 /** SB instructions implemented (FEAT_SB). */ 1358 # define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1 1359 /** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */ 1360 #define ARMV8_ID_AA64ISAR1_EL1_SPECRES (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 1361 #define ARMV8_ID_AA64ISAR1_EL1_SPECRES_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_SPECRES) >> 40) 1362 /** Prediction invalidation instructions are not implemented. */ 1363 # define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0 1364 /** Prediction invalidation instructions are implemented (FEAT_SPECRES). */ 1365 # define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1 1366 /** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */ 1367 #define ARMV8_ID_AA64ISAR1_EL1_BF16 (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47)) 1368 #define ARMV8_ID_AA64ISAR1_EL1_BF16_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_DP) >> 44) 1369 /** BFloat16 instructions are not implemented. */ 1370 # define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0 1371 /** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */ 1372 # define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1 1373 /** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */ 1374 # define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2 1375 /** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */ 1376 #define ARMV8_ID_AA64ISAR1_EL1_DGH (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51)) 1377 #define ARMV8_ID_AA64ISAR1_EL1_DGH_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_DGH) >> 48) 1378 /** Data Gathering Hint instructions are not implemented. */ 1379 # define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0 1380 /** Data Gathering Hint instructions are implemented (FEAT_DGH). */ 1381 # define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1 1382 /** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */ 1383 #define ARMV8_ID_AA64ISAR1_EL1_I8MM (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55)) 1384 #define ARMV8_ID_AA64ISAR1_EL1_I8MM_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_I8MM) >> 52) 1385 /** No Int8 matrix multiplication instructions implemented. */ 1386 # define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0 1387 /** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */ 1388 # define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1 1389 /** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */ 1390 #define ARMV8_ID_AA64ISAR1_EL1_XS (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59)) 1391 #define ARMV8_ID_AA64ISAR1_EL1_XS_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_XS) >> 56) 1392 /** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */ 1393 # define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0 1394 /** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */ 1395 # define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1 1396 /** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */ 1397 #define ARMV8_ID_AA64ISAR1_EL1_LS64 (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63)) 1398 #define ARMV8_ID_AA64ISAR1_EL1_LS64_GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_LS64) >> 60) 1399 /** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */ 1400 # define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0 1401 /** The LD64B and ST64B instructions are supported (FEAT_LS64). */ 1402 # define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1 1403 /** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */ 1404 # define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2 1405 /** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */ 1406 # define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3 1407 /** @} */ 1408 1409 1410 /** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0. 1411 * @{ */ 1412 /** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */ 1413 #define ARMV8_ID_AA64ISAR2_EL1_WFXT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1414 #define ARMV8_ID_AA64ISAR2_EL1_WFXT_GET(a_IdAa64Isar2El1) ((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_WFXT) 1415 /** WFET and WFIT are not supported. */ 1416 # define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0 1417 /** WFET and WFIT are supported (FEAT_WFxT). */ 1418 # define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2 1419 /** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */ 1420 #define ARMV8_ID_AA64ISAR2_EL1_RPRES (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1421 #define ARMV8_ID_AA64ISAR2_EL1_RPRES_GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_RPRES) >> 4) 1422 /** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */ 1423 # define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0 1424 /** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */ 1425 # define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1 1426 /** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */ 1427 #define ARMV8_ID_AA64ISAR2_EL1_GPA3 (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1428 #define ARMV8_ID_AA64ISAR2_EL1_GPA3_GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_API) >> 8) 1429 /** Generic Authentication using the QARMA3 algorithm is not implemented. */ 1430 # define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0 1431 /** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */ 1432 # define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1 1433 /** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */ 1434 #define ARMV8_ID_AA64ISAR2_EL1_APA3 (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1435 #define ARMV8_ID_AA64ISAR2_EL1_APA3_GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_APA3) >> 12) 1436 /** Address Authentication using the QARMA3 algorithm is not implemented. */ 1437 # define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0 1438 /** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */ 1439 # define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1 1440 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */ 1441 # define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2 1442 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */ 1443 # define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3 1444 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */ 1445 # define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4 1446 /** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */ 1447 # define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5 1448 /** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */ 1449 #define ARMV8_ID_AA64ISAR2_EL1_MOPS (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1450 #define ARMV8_ID_AA64ISAR2_EL1_MOPS_GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_MOPS) >> 16) 1451 /** No Memory Copy and Memory Set instructions implemented. */ 1452 # define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0 1453 /** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */ 1454 # define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1 1455 /** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */ 1456 #define ARMV8_ID_AA64ISAR2_EL1_BC (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1457 #define ARMV8_ID_AA64ISAR2_EL1_BC_GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_BC) >> 20) 1458 /** BC instruction is not implemented. */ 1459 # define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0 1460 /** BC instruction is implemented (FEAT_HBC). */ 1461 # define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1 1462 /** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */ 1463 #define ARMV8_ID_AA64ISAR2_EL1_PACFRAC (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1464 #define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_PACFRAC) >> 24) 1465 /** ConstPACField() returns FALSE. */ 1466 # define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0 1467 /** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */ 1468 # define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1 1469 /* Bit 28 - 63 - Reserved. */ 1470 /** @} */ 1471 1472 1473 /** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0. 1474 * @{ */ 1475 /** Bit 0 - 3 - EL0 Exception level handling. */ 1476 #define ARMV8_ID_AA64PFR0_EL1_EL0 (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1477 #define ARMV8_ID_AA64PFR0_EL1_EL0_GET(a_IdAa64Pfr0El1) ((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_EL0) 1478 /** EL0 can be executed in AArch64 state only. */ 1479 # define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1 1480 /** EL0 can be executed in AArch64 and AArch32 state. */ 1481 # define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2 1482 /** Bit 4 - 7 - EL1 Exception level handling. */ 1483 #define ARMV8_ID_AA64PFR0_EL1_EL1 (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1484 #define ARMV8_ID_AA64PFR0_EL1_EL1_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_EL1) >> 4) 1485 /** EL1 can be executed in AArch64 state only. */ 1486 # define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1 1487 /** EL1 can be executed in AArch64 and AArch32 state. */ 1488 # define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2 1489 /** Bit 8 - 11 - EL2 Exception level handling. */ 1490 #define ARMV8_ID_AA64PFR0_EL1_EL2 (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1491 #define ARMV8_ID_AA64PFR0_EL1_EL2_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_EL2) >> 8) 1492 /** EL2 is not implemented. */ 1493 # define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0 1494 /** EL2 can be executed in AArch64 state only. */ 1495 # define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1 1496 /** EL2 can be executed in AArch64 and AArch32 state. */ 1497 # define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2 1498 /** Bit 12 - 15 - EL3 Exception level handling. */ 1499 #define ARMV8_ID_AA64PFR0_EL1_EL3 (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1500 #define ARMV8_ID_AA64PFR0_EL1_EL3_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_EL3) >> 12) 1501 /** EL3 is not implemented. */ 1502 # define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0 1503 /** EL3 can be executed in AArch64 state only. */ 1504 # define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1 1505 /** EL3 can be executed in AArch64 and AArch32 state. */ 1506 # define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2 1507 /** Bit 16 - 19 - Floating-point support. */ 1508 #define ARMV8_ID_AA64PFR0_EL1_FP (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1509 #define ARMV8_ID_AA64PFR0_EL1_FP_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_EL3) >> 16) 1510 /** Floating-point is implemented and support single and double precision. */ 1511 # define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0 1512 /** Floating-point is implemented and support single, double and half precision. */ 1513 # define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1 1514 /** Floating-point is not implemented. */ 1515 # define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf 1516 /** Bit 20 - 23 - Advanced SIMD support. */ 1517 #define ARMV8_ID_AA64PFR0_EL1_ADVSIMD (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1518 #define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_ADVSIMD) >> 20) 1519 /** Advanced SIMD is implemented and support single and double precision. */ 1520 # define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0 1521 /** Advanced SIMD is implemented and support single, double and half precision. */ 1522 # define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1 1523 /** Advanced SIMD is not implemented. */ 1524 # define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf 1525 /** Bit 24 - 27 - System register GIC CPU interface support. */ 1526 #define ARMV8_ID_AA64PFR0_EL1_GIC (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1527 #define ARMV8_ID_AA64PFR0_EL1_GIC_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_GIC) >> 24) 1528 /** GIC CPU interface system registers are not implemented. */ 1529 # define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0 1530 /** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */ 1531 # define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1 1532 /** System register interface to version 4.1 of the GIC CPU interface is supported. */ 1533 # define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3 1534 /** Bit 28 - 31 - RAS Extension version. */ 1535 #define ARMV8_ID_AA64PFR0_EL1_RAS (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1536 #define ARMV8_ID_AA64PFR0_EL1_RAS_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_RAS) >> 28) 1537 /** No RAS extension. */ 1538 # define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0 1539 /** RAS Extension implemented. */ 1540 # define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1 1541 /** FEAT_RASv1p1 implemented. */ 1542 # define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2 1543 /** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */ 1544 #define ARMV8_ID_AA64PFR0_EL1_SVE (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1545 #define ARMV8_ID_AA64PFR0_EL1_SVE_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_SVE) >> 32) 1546 /** SVE is not supported. */ 1547 # define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0 1548 /** SVE is supported. */ 1549 # define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1 1550 /** Bit 36 - 39 - Secure EL2 support. */ 1551 #define ARMV8_ID_AA64PFR0_EL1_SEL2 (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1552 #define ARMV8_ID_AA64PFR0_EL1_SEL2_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_SEL2) >> 36) 1553 /** Secure EL2 is not supported. */ 1554 # define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0 1555 /** Secure EL2 is implemented. */ 1556 # define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1 1557 /** Bit 40 - 43 - MPAM support. */ 1558 #define ARMV8_ID_AA64PFR0_EL1_MPAM (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 1559 #define ARMV8_ID_AA64PFR0_EL1_MPAM_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_MPAM) >> 40) 1560 /** MPAM extension major version number is 0. */ 1561 # define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0 1562 /** MPAM extension major version number is 1. */ 1563 # define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1 1564 /** Bit 44 - 47 - Activity Monitor Extension support. */ 1565 #define ARMV8_ID_AA64PFR0_EL1_AMU (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47)) 1566 #define ARMV8_ID_AA64PFR0_EL1_AMU_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_AMU) >> 44) 1567 /** Activity Monitor extension is not implemented. */ 1568 # define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0 1569 /** Activity Monitor extension is implemented as of FEAT_AMUv1. */ 1570 # define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1 1571 /** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */ 1572 # define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2 1573 /** Bit 48 - 51 - Data Independent Timing support. */ 1574 #define ARMV8_ID_AA64PFR0_EL1_DIT (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51)) 1575 #define ARMV8_ID_AA64PFR0_EL1_DIT_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_DIT) >> 48) 1576 /** AArch64 does not guarantee constant execution time of any instructions. */ 1577 # define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0 1578 /** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */ 1579 # define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1 1580 /** Bit 52 - 55 - Realm Management Extension support. */ 1581 #define ARMV8_ID_AA64PFR0_EL1_RME (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55)) 1582 #define ARMV8_ID_AA64PFR0_EL1_RME_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_RME) >> 52) 1583 /** Realm Management Extension not implemented. */ 1584 # define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0 1585 /** RMEv1 is implemented (FEAT_RME). */ 1586 # define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1 1587 /** Bit 56 - 59 - Speculative use out of context branch targets support. */ 1588 #define ARMV8_ID_AA64PFR0_EL1_CSV2 (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59)) 1589 #define ARMV8_ID_AA64PFR0_EL1_CSV2_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_CSV2) >> 56) 1590 /** Implementation does not disclose whether FEAT_CSV2 is implemented. */ 1591 # define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0 1592 /** FEAT_CSV2 is implemented. */ 1593 # define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1 1594 /** FEAT_CSV2_2 is implemented. */ 1595 # define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2 1596 /** FEAT_CSV2_3 is implemented. */ 1597 # define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3 1598 /** Bit 60 - 63 - Speculative use of faulting data support. */ 1599 #define ARMV8_ID_AA64PFR0_EL1_CSV3 (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63)) 1600 #define ARMV8_ID_AA64PFR0_EL1_CSV3_GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_CSV3) >> 60) 1601 /** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */ 1602 # define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0 1603 /** FEAT_CSV3 is supported . */ 1604 # define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1 1605 /** @} */ 1606 1607 1608 /** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1. 1609 * @{ */ 1610 /** Bit 0 - 3 - Branch Target Identification support. */ 1611 #define ARMV8_ID_AA64PFR1_EL1_BT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1612 #define ARMV8_ID_AA64PFR1_EL1_BT_GET(a_IdAa64Pfr1El1) ((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_BT) 1613 /** The Branch Target Identification mechanism is not implemented. */ 1614 # define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0 1615 /** The Branch Target Identifcation mechanism is implemented. */ 1616 # define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1 1617 /** Bit 4 - 7 - Speculative Store Bypassing control support. */ 1618 #define ARMV8_ID_AA64PFR1_EL1_SSBS (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1619 #define ARMV8_ID_AA64PFR1_EL1_SSBS_GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_SSBS) >> 4) 1620 /** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */ 1621 # define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0 1622 /** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */ 1623 # define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1 1624 /** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions 1625 * to directly read and write the PSTATE.SSBS field. */ 1626 # define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2 1627 /** Bit 8 - 11 - Memory Tagging Extension support. */ 1628 #define ARMV8_ID_AA64PFR1_EL1_MTE (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1629 #define ARMV8_ID_AA64PFR1_EL1_MTE_GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_MTE) >> 8) 1630 /** MTE is not implemented. */ 1631 # define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0 1632 /** Instruction only Memory Tagging Extensions implemented. */ 1633 # define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1 1634 /** Full Memory Tagging Extension implemented. */ 1635 # define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2 1636 /** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */ 1637 # define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3 1638 /** Bit 12 - 15 - RAS Extension fractional field. */ 1639 #define ARMV8_ID_AA64PFR1_EL1_RASFRAC (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1640 #define ARMV8_ID_AA64PFR1_EL1_RASFRAC_GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_RASFRAC) >> 12) 1641 /** RAS Extension is implemented. */ 1642 # define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0 1643 /** FEAT_RASv1p1 is implemented. */ 1644 # define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1 1645 /** Bit 16 - 19 - MPAM minor version number. */ 1646 #define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1647 #define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_MPAMFRAC) >> 16) 1648 /** The minor version of number of the MPAM extension is 0. */ 1649 # define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0 1650 /** The minor version of number of the MPAM extension is 1. */ 1651 # define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1 1652 /* Bit 20 - 23 - Reserved. */ 1653 /** Bit 24 - 27 - Scalable Matrix Extension support. */ 1654 #define ARMV8_ID_AA64PFR1_EL1_SME (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1655 #define ARMV8_ID_AA64PFR1_EL1_SME_GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_SME) >> 24) 1656 /** Scalable Matrix Extensions are not implemented. */ 1657 # define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0 1658 /** Scalable Matrix Extensions are implemented (FEAT_SME). */ 1659 # define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1 1660 /** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */ 1661 # define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2 1662 /** Bit 28 - 31 - Random Number trap to EL3 support. */ 1663 #define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1664 #define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_RNDRTRAP) >> 28) 1665 /** Trapping of RNDR and RNDRRS to EL3 is not supported. */ 1666 # define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0 1667 /** Trapping of RNDR and RDNRRS to EL3 is supported. */ 1668 # define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1 1669 /** Bit 32 - 35 - CSV2 fractional field. */ 1670 #define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1671 #define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_CSV2FRAC) >> 32) 1672 /** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */ 1673 # define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0 1674 /** FEAT_CSV2_1p1 is implemented. */ 1675 # define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1 1676 /** FEAT_CSV2_1p2 is implemented. */ 1677 # define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2 1678 /** Bit 36 - 39 - Non-maskable Interrupt support. */ 1679 #define ARMV8_ID_AA64PFR1_EL1_NMI (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1680 #define ARMV8_ID_AA64PFR1_EL1_NMI_GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_NMI) >> 36) 1681 /** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */ 1682 # define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0 1683 /** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */ 1684 # define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1 1685 /** @} */ 1686 1687 1688 /** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0. 1689 * @{ */ 1690 /** Bit 0 - 3 - Physical Address range supported. */ 1691 #define ARMV8_ID_AA64MMFR0_EL1_PARANGE (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1692 #define ARMV8_ID_AA64MMFR0_EL1_PARANGE_GET(a_IdAa64Mmfr0El1) ((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_PARANGE) 1693 /** Physical Address range is 32 bits, 4GiB. */ 1694 # define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0 1695 /** Physical Address range is 36 bits, 64GiB. */ 1696 # define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1 1697 /** Physical Address range is 40 bits, 1TiB. */ 1698 # define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2 1699 /** Physical Address range is 42 bits, 4TiB. */ 1700 # define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3 1701 /** Physical Address range is 44 bits, 16TiB. */ 1702 # define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4 1703 /** Physical Address range is 48 bits, 256TiB. */ 1704 # define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5 1705 /** Physical Address range is 52 bits, 4PiB. */ 1706 # define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6 1707 /** Bit 4 - 7 - Number of ASID bits. */ 1708 #define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1709 #define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_ASIDBITS) >> 4) 1710 /** ASID bits is 8. */ 1711 # define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0 1712 /** ASID bits is 16. */ 1713 # define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2 1714 /** Bit 8 - 11 - Indicates support for mixed-endian configuration. */ 1715 #define ARMV8_ID_AA64MMFR0_EL1_BIGEND (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1716 #define ARMV8_ID_AA64MMFR0_EL1_BIGEND_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_BIGEND) >> 8) 1717 /** No mixed-endian support. */ 1718 # define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0 1719 /** Mixed-endian supported. */ 1720 # define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1 1721 /** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */ 1722 #define ARMV8_ID_AA64MMFR0_EL1_SNSMEM (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1723 #define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_SNSMEM) >> 12) 1724 /** No distinction between Secure and Non-secure Memory supported. */ 1725 # define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0 1726 /** Distinction between Secure and Non-secure Memory supported. */ 1727 # define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1 1728 /** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */ 1729 #define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0 (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1730 #define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0) >> 16) 1731 /** No mixed-endian support at EL0. */ 1732 # define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0 1733 /** Mixed-endian support at EL0. */ 1734 # define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1 1735 /** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */ 1736 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16 (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1737 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN16) >> 20) 1738 /** 16KiB granule size not supported. */ 1739 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0 1740 /** 16KiB granule size is supported. */ 1741 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1 1742 /** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */ 1743 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2 1744 /** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */ 1745 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64 (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1746 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN64) >> 24) 1747 /** 64KiB granule supported. */ 1748 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0 1749 /** 64KiB granule not supported. */ 1750 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf 1751 /** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */ 1752 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4 (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1753 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN4) >> 28) 1754 /** 4KiB granule supported. */ 1755 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0 1756 /** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */ 1757 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1 1758 /** 4KiB granule not supported. */ 1759 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf 1760 /** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */ 1761 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2 (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1762 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2) >> 32) 1763 /** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */ 1764 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0 1765 /** 16KiB granule not supported at stage 2. */ 1766 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1 1767 /** 16KiB granule supported at stage 2. */ 1768 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2 1769 /** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */ 1770 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3 1771 /** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */ 1772 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2 (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1773 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2) >> 36) 1774 /** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */ 1775 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0 1776 /** 64KiB granule not supported at stage 2. */ 1777 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1 1778 /** 64KiB granule supported at stage 2. */ 1779 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2 1780 /** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */ 1781 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2 (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 1782 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2) >> 40) 1783 /** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */ 1784 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0 1785 /** 4KiB granule not supported at stage 2. */ 1786 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1 1787 /** 4KiB granule supported at stage 2. */ 1788 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2 1789 /** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */ 1790 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3 1791 /** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */ 1792 #define ARMV8_ID_AA64MMFR0_EL1_EXS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47)) 1793 #define ARMV8_ID_AA64MMFR0_EL1_EXS_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_EXS) >> 44) 1794 /** All exception entries and exits are context synchronization events. */ 1795 # define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0 1796 /** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */ 1797 # define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1 1798 /* Bit 48 - 55 - Reserved. */ 1799 /** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */ 1800 #define ARMV8_ID_AA64MMFR0_EL1_FGT (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59)) 1801 #define ARMV8_ID_AA64MMFR0_EL1_FGT_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_FGT) >> 56) 1802 /** Fine-grained trap controls are not implemented. */ 1803 # define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0 1804 /** Fine-grained trap controls are implemented (FEAT_FGT). */ 1805 # define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1 1806 /** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */ 1807 #define ARMV8_ID_AA64MMFR0_EL1_ECV (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63)) 1808 #define ARMV8_ID_AA64MMFR0_EL1_ECV_GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_ECV) >> 60) 1809 /** Enhanced Counter Virtualization is not implemented. */ 1810 # define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0 1811 /** Enhanced Counter Virtualization is implemented (FEAT_ECV). */ 1812 # define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1 1813 /** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */ 1814 # define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2 1815 /** @} */ 1816 1817 1818 /** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1. 1819 * @{ */ 1820 /** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */ 1821 #define ARMV8_ID_AA64MMFR1_EL1_HAFDBS (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1822 #define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_GET(a_IdAa64Mmfr1El1) ((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_HAFDBS) 1823 /** Hardware update of the Access flag and dirty state are not supported. */ 1824 # define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0 1825 /** Support for hardware update of the Access flag for Block and Page descriptors. */ 1826 # define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1 1827 /** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */ 1828 # define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2 1829 /** Bit 4 - 7 - EL1 Exception level handling. */ 1830 #define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1831 #define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_VMIDBITS) >> 4) 1832 /** VMID bits is 8. */ 1833 # define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0 1834 /** VMID bits is 16 (FEAT_VMID16). */ 1835 # define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2 1836 /** Bit 8 - 11 - Virtualization Host Extensions support. */ 1837 #define ARMV8_ID_AA64MMFR1_EL1_VHE (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1838 #define ARMV8_ID_AA64MMFR1_EL1_VHE_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_VHE) >> 8) 1839 /** Virtualization Host Extensions are not supported. */ 1840 # define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0 1841 /** Virtualization Host Extensions are supported. */ 1842 # define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1 1843 /** Bit 12 - 15 - Hierarchical Permission Disables. */ 1844 #define ARMV8_ID_AA64MMFR1_EL1_HPDS (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1845 #define ARMV8_ID_AA64MMFR1_EL1_HPDS_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_HPDS) >> 12) 1846 /** Disabling of hierarchical controls not supported. */ 1847 # define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0 1848 /** Disabling of hierarchical controls supported (FEAT_HPDS). */ 1849 # define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1 1850 /** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */ 1851 # define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2 1852 /** Bit 16 - 19 - LORegions support. */ 1853 #define ARMV8_ID_AA64MMFR1_EL1_LO (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1854 #define ARMV8_ID_AA64MMFR1_EL1_LO_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_LO) >> 16) 1855 /** LORegions not supported. */ 1856 # define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0 1857 /** LORegions supported. */ 1858 # define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1 1859 /** Bit 20 - 23 - Privileged Access Never support. */ 1860 #define ARMV8_ID_AA64MMFR1_EL1_PAN (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1861 #define ARMV8_ID_AA64MMFR1_EL1_PAN_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_PAN) >> 20) 1862 /** PAN not supported. */ 1863 # define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0 1864 /** PAN supported (FEAT_PAN). */ 1865 # define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1 1866 /** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */ 1867 # define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2 1868 /** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */ 1869 # define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3 1870 /** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */ 1871 #define ARMV8_ID_AA64MMFR1_EL1_SPECSEI (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1872 #define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_SPECSEI) >> 24) 1873 /** The PE never generates an SError interrupt due to an External abort on a speculative read. */ 1874 # define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0 1875 /** The PE might generate an SError interrupt due to an External abort on a speculative read. */ 1876 # define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1 1877 /** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */ 1878 #define ARMV8_ID_AA64MMFR1_EL1_XNX (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1879 #define ARMV8_ID_AA64MMFR1_EL1_XNX_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_XNX) >> 28) 1880 /** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */ 1881 # define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0 1882 /** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */ 1883 # define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1 1884 /** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */ 1885 #define ARMV8_ID_AA64MMFR1_EL1_TWED (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1886 #define ARMV8_ID_AA64MMFR1_EL1_TWED_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_TWED) >> 32) 1887 /** Configurable delayed trapping of WFE is not supported. */ 1888 # define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0 1889 /** Configurable delayed trapping of WFE is supported (FEAT_TWED). */ 1890 # define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1 1891 /** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */ 1892 #define ARMV8_ID_AA64MMFR1_EL1_ETS (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1893 #define ARMV8_ID_AA64MMFR1_EL1_ETS_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_ETS) >> 36) 1894 /** Enhanced Translation Synchronization is not supported. */ 1895 # define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0 1896 /** Enhanced Translation Synchronization is implemented. */ 1897 # define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1 1898 /** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */ 1899 #define ARMV8_ID_AA64MMFR1_EL1_HCX (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 1900 #define ARMV8_ID_AA64MMFR1_EL1_HCX_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_MPAM) >> 40) 1901 /** HCRX_EL2 and its associated EL3 trap are not supported. */ 1902 # define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0 1903 /** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */ 1904 # define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1 1905 /** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */ 1906 #define ARMV8_ID_AA64MMFR1_EL1_AFP (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47)) 1907 #define ARMV8_ID_AA64MMFR1_EL1_AFP_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_AFP) >> 44) 1908 /** The FPCR.{AH,FIZ,NEP} fields are not supported. */ 1909 # define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0 1910 /** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */ 1911 # define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1 1912 /** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */ 1913 #define ARMV8_ID_AA64MMFR1_EL1_NTLBPA (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51)) 1914 #define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_NTLBPA) >> 48) 1915 /** The intermediate caching of translation table walks might include non-coherent physical translation caches. */ 1916 # define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0 1917 /** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */ 1918 # define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1 1919 /** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */ 1920 #define ARMV8_ID_AA64MMFR1_EL1_TIDCP1 (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55)) 1921 #define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_TIDCP1_GET) >> 52) 1922 /** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */ 1923 # define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0 1924 /** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */ 1925 # define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1 1926 /** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */ 1927 #define ARMV8_ID_AA64MMFR1_EL1_CMOW (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59)) 1928 #define ARMV8_ID_AA64MMFR1_EL1_CMOW_GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_CMOW) >> 56) 1929 /** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */ 1930 # define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0 1931 /** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */ 1932 # define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1 1933 /* Bit 60 - 63 - Reserved. */ 1934 /** @} */ 1935 1936 1148 1937 /** @} */ 1149 1938
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