- Timestamp:
- Sep 5, 2023 9:11:24 AM (13 months ago)
- File:
-
- 1 edited
-
trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp (modified) (5 diffs)
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trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
r100992 r101017 4764 4764 4765 4765 /** 4766 * Get L2 cache associativity.4766 * Get L2/L3 cache associativity. 4767 4767 */ 4768 static const char *getL2 CacheAss(unsigned u)4768 static const char *getL23CacheAss(unsigned u) 4769 4769 { 4770 4770 switch (u) … … 4773 4773 case 1: return "direct"; 4774 4774 case 2: return "2 way "; 4775 case 3: return " res3";4775 case 3: return "3 way "; 4776 4776 case 4: return "4 way "; 4777 case 5: return " res5";4777 case 5: return "6 way "; 4778 4778 case 6: return "8 way "; 4779 4779 case 7: return "res7 "; 4780 4780 case 8: return "16 way"; 4781 case 9: return " res9 ";4782 case 10: return " res10";4783 case 11: return " res11";4784 case 12: return " res12";4785 case 13: return " res13";4786 case 14: return " res14";4781 case 9: return "tpoext"; /* Overridden by Fn8000_001D */ 4782 case 10: return "32 way"; 4783 case 11: return "48 way"; 4784 case 12: return "64 way"; 4785 case 13: return "96 way"; 4786 case 14: return "128way"; 4787 4787 case 15: return "fully "; 4788 4788 default: return "????"; … … 5741 5741 uint32_t uEAX = pCurLeaf->uEax; 5742 5742 uint32_t uEBX = pCurLeaf->uEbx; 5743 uint32_t uECX = pCurLeaf->uEcx; 5743 5744 uint32_t uEDX = pCurLeaf->uEdx; 5744 5745 … … 5746 5747 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n" 5747 5748 "L2 TLB 2/4M Data: %s %4d entries\n", 5748 getL2 CacheAss((uEAX >> 12) & 0xf),(uEAX >> 0) & 0xfff,5749 getL2 CacheAss((uEAX >> 28) & 0xf),(uEAX >> 16) & 0xfff);5749 getL23CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff, 5750 getL23CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff); 5750 5751 pHlp->pfnPrintf(pHlp, 5751 5752 "L2 TLB 4K Instr/Uni: %s %4d entries\n" 5752 5753 "L2 TLB 4K Data: %s %4d entries\n", 5753 getL2 CacheAss((uEBX >> 12) & 0xf),(uEBX >> 0) & 0xfff,5754 getL2 CacheAss((uEBX >> 28) & 0xf),(uEBX >> 16) & 0xfff);5754 getL23CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff, 5755 getL23CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff); 5755 5756 pHlp->pfnPrintf(pHlp, 5756 5757 "L2 Cache Line Size: %d bytes\n" … … 5758 5759 "L2 Cache Associativity: %s\n" 5759 5760 "L2 Cache Size: %d KB\n", 5761 (uECX >> 0) & 0xff, 5762 (uECX >> 8) & 0xf, 5763 getL23CacheAss((uECX >> 12) & 0xf), 5764 (uECX >> 16) & 0xffff); 5765 pHlp->pfnPrintf(pHlp, 5766 "L3 Cache Line Size: %d bytes\n" 5767 "L3 Cache Lines Per Tag: %d\n" 5768 "L3 Cache Associativity: %s\n" 5769 "L3 Cache Size: %d KB\n", 5760 5770 (uEDX >> 0) & 0xff, 5761 5771 (uEDX >> 8) & 0xf, 5762 getL2 CacheAss((uEDX >> 12) & 0xf),5763 ( uEDX >> 16) & 0xffff);5772 getL23CacheAss((uEDX >> 12) & 0xf), 5773 ((uEDX >> 18) & 0x3fff) * 512); 5764 5774 } 5765 5775
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