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source: vbox/trunk/src/recompiler/softmmu_header.h@ 35273

Last change on this file since 35273 was 33656, checked in by vboxsync, 14 years ago

*: rebrand Sun (L)GPL disclaimers
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1/*
2 * Software MMU support
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29
30#if DATA_SIZE == 8
31#define SUFFIX q
32#define USUFFIX q
33#define DATA_TYPE uint64_t
34#elif DATA_SIZE == 4
35#define SUFFIX l
36#define USUFFIX l
37#define DATA_TYPE uint32_t
38#elif DATA_SIZE == 2
39#define SUFFIX w
40#define USUFFIX uw
41#define DATA_TYPE uint16_t
42#define DATA_STYPE int16_t
43#elif DATA_SIZE == 1
44#define SUFFIX b
45#define USUFFIX ub
46#define DATA_TYPE uint8_t
47#define DATA_STYPE int8_t
48#else
49#error unsupported data size
50#endif
51
52#if ACCESS_TYPE < (NB_MMU_MODES)
53
54#define CPU_MMU_INDEX ACCESS_TYPE
55#define MMUSUFFIX _mmu
56
57#elif ACCESS_TYPE == (NB_MMU_MODES)
58
59#define CPU_MMU_INDEX (cpu_mmu_index(env))
60#define MMUSUFFIX _mmu
61
62#elif ACCESS_TYPE == (NB_MMU_MODES + 1)
63
64#define CPU_MMU_INDEX (cpu_mmu_index(env))
65#define MMUSUFFIX _cmmu
66
67#else
68#error invalid ACCESS_TYPE
69#endif
70
71#if DATA_SIZE == 8
72#define RES_TYPE uint64_t
73#else
74#define RES_TYPE int
75#endif
76
77#if ACCESS_TYPE == (NB_MMU_MODES + 1)
78#define ADDR_READ addr_code
79#else
80#define ADDR_READ addr_read
81#endif
82
83#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
84 (ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU) && !defined(VBOX)
85
86static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
87{
88 int res;
89
90 asm volatile ("movl %1, %%edx\n"
91 "movl %1, %%eax\n"
92 "shrl %3, %%edx\n"
93 "andl %4, %%eax\n"
94 "andl %2, %%edx\n"
95 "leal %5(%%edx, %%ebp), %%edx\n"
96 "cmpl (%%edx), %%eax\n"
97 "movl %1, %%eax\n"
98 "je 1f\n"
99 "movl %6, %%edx\n"
100 "call %7\n"
101 "movl %%eax, %0\n"
102 "jmp 2f\n"
103 "1:\n"
104 "addl 12(%%edx), %%eax\n"
105#if DATA_SIZE == 1
106 "movzbl (%%eax), %0\n"
107#elif DATA_SIZE == 2
108 "movzwl (%%eax), %0\n"
109#elif DATA_SIZE == 4
110 "movl (%%eax), %0\n"
111#else
112#error unsupported size
113#endif
114 "2:\n"
115 : "=r" (res)
116 : "r" (ptr),
117 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
118 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
119 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
120 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
121 "i" (CPU_MMU_INDEX),
122 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
123 : "%eax", "%ecx", "%edx", "memory", "cc");
124 return res;
125}
126
127#if DATA_SIZE <= 2
128static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
129{
130 int res;
131
132 asm volatile ("movl %1, %%edx\n"
133 "movl %1, %%eax\n"
134 "shrl %3, %%edx\n"
135 "andl %4, %%eax\n"
136 "andl %2, %%edx\n"
137 "leal %5(%%edx, %%ebp), %%edx\n"
138 "cmpl (%%edx), %%eax\n"
139 "movl %1, %%eax\n"
140 "je 1f\n"
141 "movl %6, %%edx\n"
142 "call %7\n"
143#if DATA_SIZE == 1
144 "movsbl %%al, %0\n"
145#elif DATA_SIZE == 2
146 "movswl %%ax, %0\n"
147#else
148#error unsupported size
149#endif
150 "jmp 2f\n"
151 "1:\n"
152 "addl 12(%%edx), %%eax\n"
153#if DATA_SIZE == 1
154 "movsbl (%%eax), %0\n"
155#elif DATA_SIZE == 2
156 "movswl (%%eax), %0\n"
157#else
158#error unsupported size
159#endif
160 "2:\n"
161 : "=r" (res)
162 : "r" (ptr),
163 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
164 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
165 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
166 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
167 "i" (CPU_MMU_INDEX),
168 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
169 : "%eax", "%ecx", "%edx", "memory", "cc");
170 return res;
171}
172#endif
173
174static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
175{
176 asm volatile ("movl %0, %%edx\n"
177 "movl %0, %%eax\n"
178 "shrl %3, %%edx\n"
179 "andl %4, %%eax\n"
180 "andl %2, %%edx\n"
181 "leal %5(%%edx, %%ebp), %%edx\n"
182 "cmpl (%%edx), %%eax\n"
183 "movl %0, %%eax\n"
184 "je 1f\n"
185#if DATA_SIZE == 1
186 "movzbl %b1, %%edx\n"
187#elif DATA_SIZE == 2
188 "movzwl %w1, %%edx\n"
189#elif DATA_SIZE == 4
190 "movl %1, %%edx\n"
191#else
192#error unsupported size
193#endif
194 "movl %6, %%ecx\n"
195 "call %7\n"
196 "jmp 2f\n"
197 "1:\n"
198 "addl 8(%%edx), %%eax\n"
199#if DATA_SIZE == 1
200 "movb %b1, (%%eax)\n"
201#elif DATA_SIZE == 2
202 "movw %w1, (%%eax)\n"
203#elif DATA_SIZE == 4
204 "movl %1, (%%eax)\n"
205#else
206#error unsupported size
207#endif
208 "2:\n"
209 :
210 : "r" (ptr),
211#if DATA_SIZE == 1
212 "q" (v),
213#else
214 "r" (v),
215#endif
216 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
217 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
218 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
219 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
220 "i" (CPU_MMU_INDEX),
221 "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
222 : "%eax", "%ecx", "%edx", "memory", "cc");
223}
224#else
225
226/* generic load/store macros */
227
228#ifndef VBOX
229static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
230#else
231DECLINLINE(RES_TYPE) glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
232#endif
233{
234
235 int page_index;
236 RES_TYPE res;
237 target_ulong addr;
238 unsigned long physaddr;
239 int mmu_idx;
240
241 addr = ptr;
242 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
243 mmu_idx = CPU_MMU_INDEX;
244 if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
245 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
246 res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
247 } else {
248 physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
249 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
250 }
251 return res;
252}
253
254#if DATA_SIZE <= 2
255#ifndef VBOX
256static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
257#else
258DECLINLINE(int) glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
259#endif
260{
261 int res, page_index;
262 target_ulong addr;
263 unsigned long physaddr;
264 int mmu_idx;
265
266 addr = ptr;
267 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
268 mmu_idx = CPU_MMU_INDEX;
269 if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
270 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
271 res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
272 } else {
273 physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
274 res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
275 }
276 return res;
277}
278#endif
279
280#if ACCESS_TYPE != (NB_MMU_MODES + 1)
281
282/* generic store macro */
283#ifndef VBOX
284static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
285#else
286DECLINLINE(void) glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
287#endif
288{
289 int page_index;
290 target_ulong addr;
291 unsigned long physaddr;
292 int mmu_idx;
293
294 addr = ptr;
295 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
296 mmu_idx = CPU_MMU_INDEX;
297 if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
298 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
299 glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
300 } else {
301 physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
302 glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
303 }
304}
305
306#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
307
308#endif /* !asm */
309
310#if ACCESS_TYPE != (NB_MMU_MODES + 1)
311
312#if DATA_SIZE == 8
313#ifndef VBOX
314static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
315#else
316DECLINLINE(float64) glue(ldfq, MEMSUFFIX)(target_ulong ptr)
317#endif
318{
319 union {
320 float64 d;
321 uint64_t i;
322 } u;
323 u.i = glue(ldq, MEMSUFFIX)(ptr);
324 return u.d;
325}
326
327#ifndef VBOX
328static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
329#else
330DECLINLINE(void) glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
331#endif
332{
333 union {
334 float64 d;
335 uint64_t i;
336 } u;
337 u.d = v;
338 glue(stq, MEMSUFFIX)(ptr, u.i);
339}
340#endif /* DATA_SIZE == 8 */
341
342#if DATA_SIZE == 4
343#ifndef VBOX
344static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
345#else
346DECLINLINE(float32) glue(ldfl, MEMSUFFIX)(target_ulong ptr)
347#endif
348{
349 union {
350 float32 f;
351 uint32_t i;
352 } u;
353 u.i = glue(ldl, MEMSUFFIX)(ptr);
354 return u.f;
355}
356
357#ifndef VBOX
358static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
359#else
360DECLINLINE(void) glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
361#endif
362{
363 union {
364 float32 f;
365 uint32_t i;
366 } u;
367 u.f = v;
368 glue(stl, MEMSUFFIX)(ptr, u.i);
369}
370#endif /* DATA_SIZE == 4 */
371
372#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
373
374#undef RES_TYPE
375#undef DATA_TYPE
376#undef DATA_STYPE
377#undef SUFFIX
378#undef USUFFIX
379#undef DATA_SIZE
380#undef CPU_MMU_INDEX
381#undef MMUSUFFIX
382#undef ADDR_READ
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