[1] | 1 | /*
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| 2 | * virtual page mapping and translated block handling
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[6532] | 3 | *
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[1] | 4 | * Copyright (c) 2003 Fabrice Bellard
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| 5 | *
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| 6 | * This library is free software; you can redistribute it and/or
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| 7 | * modify it under the terms of the GNU Lesser General Public
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| 8 | * License as published by the Free Software Foundation; either
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| 9 | * version 2 of the License, or (at your option) any later version.
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| 10 | *
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| 11 | * This library is distributed in the hope that it will be useful,
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| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | * Lesser General Public License for more details.
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| 15 | *
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| 16 | * You should have received a copy of the GNU Lesser General Public
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[36175] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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[1] | 18 | */
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[11982] | 19 |
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| 20 | /*
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[33656] | 21 | * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
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| 22 | * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
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[11982] | 23 | * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
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| 24 | * a choice of LGPL license versions is made available with the language indicating
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| 25 | * that LGPLv2 or any later version may be used, or where a choice of which version
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| 26 | * of the LGPL is applied is otherwise unspecified.
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| 27 | */
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[33656] | 28 |
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[1] | 29 | #include "config.h"
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[2422] | 30 | #ifndef VBOX
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[1] | 31 | #ifdef _WIN32
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| 32 | #include <windows.h>
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| 33 | #else
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| 34 | #include <sys/types.h>
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| 35 | #include <sys/mman.h>
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| 36 | #endif
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| 37 | #include <stdlib.h>
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| 38 | #include <stdio.h>
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| 39 | #include <stdarg.h>
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| 40 | #include <string.h>
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| 41 | #include <errno.h>
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| 42 | #include <unistd.h>
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| 43 | #include <inttypes.h>
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[2422] | 44 | #else /* VBOX */
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| 45 | # include <stdlib.h>
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| 46 | # include <stdio.h>
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| 47 | # include <iprt/alloc.h>
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| 48 | # include <iprt/string.h>
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| 49 | # include <iprt/param.h>
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[35346] | 50 | # include <VBox/vmm/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
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[76474] | 51 | # include <iprt/errcore.h>
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[2422] | 52 | #endif /* VBOX */
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[1] | 53 |
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| 54 | #include "cpu.h"
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| 55 | #include "exec-all.h"
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[36140] | 56 | #include "qemu-common.h"
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| 57 | #include "tcg.h"
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| 58 | #ifndef VBOX
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| 59 | #include "hw/hw.h"
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[37689] | 60 | #include "hw/qdev.h"
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| 61 | #endif /* !VBOX */
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[36140] | 62 | #include "osdep.h"
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[36170] | 63 | #include "kvm.h"
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[37689] | 64 | #include "qemu-timer.h"
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[2422] | 65 | #if defined(CONFIG_USER_ONLY)
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| 66 | #include <qemu.h>
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[37689] | 67 | #include <signal.h>
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| 68 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
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| 69 | #include <sys/param.h>
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| 70 | #if __FreeBSD_version >= 700104
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| 71 | #define HAVE_KINFO_GETVMMAP
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| 72 | #define sigqueue sigqueue_freebsd /* avoid redefinition */
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| 73 | #include <sys/time.h>
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| 74 | #include <sys/proc.h>
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| 75 | #include <machine/profile.h>
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| 76 | #define _KERNEL
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| 77 | #include <sys/user.h>
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| 78 | #undef _KERNEL
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| 79 | #undef sigqueue
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| 80 | #include <libutil.h>
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[1] | 81 | #endif
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[37689] | 82 | #endif
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| 83 | #endif
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[1] | 84 |
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| 85 | //#define DEBUG_TB_INVALIDATE
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| 86 | //#define DEBUG_FLUSH
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| 87 | //#define DEBUG_TLB
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[2422] | 88 | //#define DEBUG_UNASSIGNED
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[1] | 89 |
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| 90 | /* make various TB consistency checks */
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[6532] | 91 | //#define DEBUG_TB_CHECK
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| 92 | //#define DEBUG_TLB_CHECK
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[1] | 93 |
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[36140] | 94 | //#define DEBUG_IOPORT
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| 95 | //#define DEBUG_SUBPAGE
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| 96 |
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[2422] | 97 | #if !defined(CONFIG_USER_ONLY)
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| 98 | /* TB consistency checks only implemented for usermode emulation. */
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| 99 | #undef DEBUG_TB_CHECK
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| 100 | #endif
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| 101 |
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[1] | 102 | #define SMC_BITMAP_USE_THRESHOLD 10
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| 103 |
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[13301] | 104 | static TranslationBlock *tbs;
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[37689] | 105 | static int code_gen_max_blocks;
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[1] | 106 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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[13301] | 107 | static int nb_tbs;
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[1] | 108 | /* any access to the tbs or the page table must use this lock */
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| 109 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
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| 110 |
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[13382] | 111 | #ifndef VBOX
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[13301] | 112 | #if defined(__arm__) || defined(__sparc_v9__)
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| 113 | /* The prologue must be reachable with a direct jump. ARM and Sparc64
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| 114 | have limited branch ranges (possibly also PPC) so place it in a
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| 115 | section close to code segment. */
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| 116 | #define code_gen_section \
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| 117 | __attribute__((__section__(".gen_code"))) \
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| 118 | __attribute__((aligned (32)))
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[36175] | 119 | #elif defined(_WIN32)
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| 120 | /* Maximum alignment for Win32 is 16. */
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| 121 | #define code_gen_section \
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| 122 | __attribute__((aligned (16)))
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[2422] | 123 | #else
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[13301] | 124 | #define code_gen_section \
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| 125 | __attribute__((aligned (32)))
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[6532] | 126 | #endif
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[36140] | 127 |
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[13382] | 128 | uint8_t code_gen_prologue[1024] code_gen_section;
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| 129 | #else /* VBOX */
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[37689] | 130 | extern uint8_t *code_gen_prologue;
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[13382] | 131 | #endif /* VBOX */
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[13301] | 132 | static uint8_t *code_gen_buffer;
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[42601] | 133 | static size_t code_gen_buffer_size;
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[13301] | 134 | /* threshold to flush the translated code buffer */
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[42601] | 135 | static size_t code_gen_buffer_max_size;
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[37689] | 136 | static uint8_t *code_gen_ptr;
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[1] | 137 |
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[13301] | 138 | #if !defined(CONFIG_USER_ONLY)
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[37689] | 139 | # ifndef VBOX
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[1] | 140 | int phys_ram_fd;
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[13301] | 141 | static int in_migration;
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[37689] | 142 | # endif /* !VBOX */
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[36175] | 143 |
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[37689] | 144 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) };
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[13301] | 145 | #endif
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[1] | 146 |
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[2422] | 147 | CPUState *first_cpu;
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| 148 | /* current CPU in the current thread. It is only valid inside
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| 149 | cpu_exec() */
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[6532] | 150 | CPUState *cpu_single_env;
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[13301] | 151 | /* 0 = Do not count executed instructions.
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| 152 | 1 = Precise instruction counting.
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| 153 | 2 = Adaptive rate instruction counting. */
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| 154 | int use_icount = 0;
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| 155 | /* Current instruction counter. While executing translated code this may
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| 156 | include some instructions that have not yet been executed. */
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| 157 | int64_t qemu_icount;
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[2422] | 158 |
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[1] | 159 | typedef struct PageDesc {
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| 160 | /* list of TBs intersecting this ram page */
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| 161 | TranslationBlock *first_tb;
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| 162 | /* in order to optimize self modifying code, we count the number
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| 163 | of lookups we do to a given page to use a bitmap */
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| 164 | unsigned int code_write_count;
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| 165 | uint8_t *code_bitmap;
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| 166 | #if defined(CONFIG_USER_ONLY)
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| 167 | unsigned long flags;
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| 168 | #endif
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| 169 | } PageDesc;
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| 170 |
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[37689] | 171 | /* In system mode we want L1_MAP to be based on ram offsets,
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| 172 | while in user mode we want it to be based on virtual addresses. */
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| 173 | #if !defined(CONFIG_USER_ONLY)
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| 174 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
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| 175 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS
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| 176 | #else
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| 177 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS
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| 178 | #endif
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| 179 | #else
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| 180 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS
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| 181 | #endif
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[1] | 182 |
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[37689] | 183 | /* Size of the L2 (and L3, etc) page tables. */
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[1] | 184 | #define L2_BITS 10
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[37689] | 185 | #define L2_SIZE (1 << L2_BITS)
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| 186 |
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| 187 | /* The bits remaining after N lower levels of page tables. */
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| 188 | #define P_L1_BITS_REM \
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| 189 | ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS)
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| 190 | #define V_L1_BITS_REM \
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| 191 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS)
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| 192 |
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| 193 | /* Size of the L1 page table. Avoid silly small sizes. */
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| 194 | #if P_L1_BITS_REM < 4
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| 195 | #define P_L1_BITS (P_L1_BITS_REM + L2_BITS)
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[13301] | 196 | #else
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[37689] | 197 | #define P_L1_BITS P_L1_BITS_REM
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[13301] | 198 | #endif
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[1] | 199 |
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[37689] | 200 | #if V_L1_BITS_REM < 4
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| 201 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS)
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| 202 | #else
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| 203 | #define V_L1_BITS V_L1_BITS_REM
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[18597] | 204 | #endif
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[1] | 205 |
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[37689] | 206 | #define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS)
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| 207 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS)
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| 208 |
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| 209 | #define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS)
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| 210 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS)
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| 211 |
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[42601] | 212 | size_t qemu_real_host_page_size;
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| 213 | size_t qemu_host_page_bits;
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| 214 | size_t qemu_host_page_size;
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| 215 | uintptr_t qemu_host_page_mask;
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[1] | 216 |
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[37689] | 217 | /* This is a multi-level map on the virtual address space.
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| 218 | The bottom level has pointers to PageDesc. */
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| 219 | static void *l1_map[V_L1_SIZE];
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[1] | 220 |
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[13301] | 221 | #if !defined(CONFIG_USER_ONLY)
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[37689] | 222 | typedef struct PhysPageDesc {
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| 223 | /* offset in host memory of the page + io_index in the low bits */
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| 224 | ram_addr_t phys_offset;
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| 225 | ram_addr_t region_offset;
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| 226 | } PhysPageDesc;
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| 227 |
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| 228 | /* This is a multi-level map on the physical address space.
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| 229 | The bottom level has pointers to PhysPageDesc. */
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| 230 | static void *l1_phys_map[P_L1_SIZE];
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| 231 |
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[13301] | 232 | static void io_mem_init(void);
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| 233 |
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[1] | 234 | /* io memory support */
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| 235 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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| 236 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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| 237 | void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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[36175] | 238 | static char io_mem_used[IO_MEM_NB_ENTRIES];
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[13301] | 239 | static int io_mem_watch;
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| 240 | #endif
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[1] | 241 |
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| 242 | #ifndef VBOX
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| 243 | /* log support */
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[37689] | 244 | #ifdef WIN32
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| 245 | static const char *logfilename = "qemu.log";
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| 246 | #else
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[13301] | 247 | static const char *logfilename = "/tmp/qemu.log";
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[37689] | 248 | #endif
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[2422] | 249 | #endif /* !VBOX */
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[1] | 250 | FILE *logfile;
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| 251 | int loglevel;
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[13337] | 252 | #ifndef VBOX
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[13301] | 253 | static int log_append = 0;
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[37689] | 254 | #endif /* !VBOX */
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[1] | 255 |
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| 256 | /* statistics */
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[18595] | 257 | #ifndef VBOX
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[37689] | 258 | #if !defined(CONFIG_USER_ONLY)
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[1] | 259 | static int tlb_flush_count;
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[37689] | 260 | #endif
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[1] | 261 | static int tb_flush_count;
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| 262 | static int tb_phys_invalidate_count;
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[18595] | 263 | #else /* VBOX - Resettable U32 stats, see VBoxRecompiler.c. */
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| 264 | uint32_t tlb_flush_count;
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| 265 | uint32_t tb_flush_count;
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| 266 | uint32_t tb_phys_invalidate_count;
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| 267 | #endif /* VBOX */
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[1] | 268 |
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[13301] | 269 | #ifndef VBOX
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| 270 | #ifdef _WIN32
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[42601] | 271 | static void map_exec(void *addr, size_t size)
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[13301] | 272 | {
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| 273 | DWORD old_protect;
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| 274 | VirtualProtect(addr, size,
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| 275 | PAGE_EXECUTE_READWRITE, &old_protect);
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[15284] | 276 |
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[13301] | 277 | }
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| 278 | #else
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[42601] | 279 | static void map_exec(void *addr, size_t size)
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[13301] | 280 | {
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[42601] | 281 | uintptr_t start, end, page_size;
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[15284] | 282 |
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[13301] | 283 | page_size = getpagesize();
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[42601] | 284 | start = (uintptr_t)addr;
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[13301] | 285 | start &= ~(page_size - 1);
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[15284] | 286 |
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[42601] | 287 | end = (uintptr_t)addr + size;
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[13301] | 288 | end += page_size - 1;
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| 289 | end &= ~(page_size - 1);
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[15284] | 290 |
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[13301] | 291 | mprotect((void *)start, end - start,
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| 292 | PROT_READ | PROT_WRITE | PROT_EXEC);
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| 293 | }
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| 294 | #endif
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[36140] | 295 | #else /* VBOX */
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[42601] | 296 | static void map_exec(void *addr, size_t size)
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[13301] | 297 | {
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| 298 | RTMemProtect(addr, size,
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| 299 | RTMEM_PROT_EXEC | RTMEM_PROT_READ | RTMEM_PROT_WRITE);
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| 300 | }
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[36140] | 301 | #endif /* VBOX */
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[13301] | 302 |
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[1] | 303 | static void page_init(void)
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| 304 | {
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| 305 | /* NOTE: we can always suppose that qemu_host_page_size >=
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| 306 | TARGET_PAGE_SIZE */
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[2422] | 307 | #ifdef VBOX
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[60049] | 308 | RTMemProtect(code_gen_buffer, code_gen_buffer_size,
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[2422] | 309 | RTMEM_PROT_EXEC | RTMEM_PROT_READ | RTMEM_PROT_WRITE);
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| 310 | qemu_real_host_page_size = PAGE_SIZE;
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| 311 | #else /* !VBOX */
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[1] | 312 | #ifdef _WIN32
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| 313 | {
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| 314 | SYSTEM_INFO system_info;
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[6532] | 315 |
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[1] | 316 | GetSystemInfo(&system_info);
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| 317 | qemu_real_host_page_size = system_info.dwPageSize;
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| 318 | }
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| 319 | #else
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| 320 | qemu_real_host_page_size = getpagesize();
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| 321 | #endif
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[2422] | 322 | #endif /* !VBOX */
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[1] | 323 | if (qemu_host_page_size == 0)
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| 324 | qemu_host_page_size = qemu_real_host_page_size;
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| 325 | if (qemu_host_page_size < TARGET_PAGE_SIZE)
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| 326 | qemu_host_page_size = TARGET_PAGE_SIZE;
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| 327 | qemu_host_page_bits = 0;
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[37689] | 328 | while ((1 << qemu_host_page_bits) < VBOX_ONLY((int))qemu_host_page_size)
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[1] | 329 | qemu_host_page_bits++;
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| 330 | qemu_host_page_mask = ~(qemu_host_page_size - 1);
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[36140] | 331 |
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[37689] | 332 | #ifndef VBOX /* We use other means to set reserved bit on our pages */
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| 333 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
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[13301] | 334 | {
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[37689] | 335 | #ifdef HAVE_KINFO_GETVMMAP
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| 336 | struct kinfo_vmentry *freep;
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| 337 | int i, cnt;
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| 338 |
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| 339 | freep = kinfo_getvmmap(getpid(), &cnt);
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| 340 | if (freep) {
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| 341 | mmap_lock();
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| 342 | for (i = 0; i < cnt; i++) {
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[42601] | 343 | uintptr_t startaddr, endaddr;
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[37689] | 344 |
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| 345 | startaddr = freep[i].kve_start;
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| 346 | endaddr = freep[i].kve_end;
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| 347 | if (h2g_valid(startaddr)) {
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| 348 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK;
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| 349 |
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| 350 | if (h2g_valid(endaddr)) {
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| 351 | endaddr = h2g(endaddr);
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| 352 | page_set_flags(startaddr, endaddr, PAGE_RESERVED);
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| 353 | } else {
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| 354 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS
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| 355 | endaddr = ~0ul;
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| 356 | page_set_flags(startaddr, endaddr, PAGE_RESERVED);
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| 357 | #endif
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| 358 | }
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| 359 | }
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| 360 | }
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| 361 | free(freep);
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| 362 | mmap_unlock();
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| 363 | }
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| 364 | #else
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[13301] | 365 | FILE *f;
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| 366 |
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[42601] | 367 | last_brk = (uintptr_t)sbrk(0);
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[37689] | 368 |
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| 369 | f = fopen("/compat/linux/proc/self/maps", "r");
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[13301] | 370 | if (f) {
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[37689] | 371 | mmap_lock();
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| 372 |
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[13301] | 373 | do {
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[42601] | 374 | uintptr_t startaddr, endaddr;
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[37689] | 375 | int n;
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| 376 |
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| 377 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr);
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| 378 |
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| 379 | if (n == 2 && h2g_valid(startaddr)) {
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| 380 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK;
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| 381 |
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| 382 | if (h2g_valid(endaddr)) {
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| 383 | endaddr = h2g(endaddr);
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| 384 | } else {
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| 385 | endaddr = ~0ul;
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---|
| 386 | }
|
---|
| 387 | page_set_flags(startaddr, endaddr, PAGE_RESERVED);
|
---|
[13301] | 388 | }
|
---|
| 389 | } while (!feof(f));
|
---|
[37689] | 390 |
|
---|
[13301] | 391 | fclose(f);
|
---|
[37689] | 392 | mmap_unlock();
|
---|
[13301] | 393 | }
|
---|
[37689] | 394 | #endif
|
---|
[13301] | 395 | }
|
---|
| 396 | #endif
|
---|
[36140] | 397 | #endif /* !VBOX */
|
---|
[1] | 398 | }
|
---|
| 399 |
|
---|
[37689] | 400 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
|
---|
[1] | 401 | {
|
---|
[37689] | 402 | PageDesc *pd;
|
---|
| 403 | void **lp;
|
---|
| 404 | int i;
|
---|
| 405 |
|
---|
| 406 | #if defined(CONFIG_USER_ONLY)
|
---|
| 407 | /* We can't use qemu_malloc because it may recurse into a locked mutex. */
|
---|
| 408 | # define ALLOC(P, SIZE) \
|
---|
| 409 | do { \
|
---|
| 410 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \
|
---|
| 411 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \
|
---|
| 412 | } while (0)
|
---|
| 413 | #else
|
---|
| 414 | # define ALLOC(P, SIZE) \
|
---|
| 415 | do { P = qemu_mallocz(SIZE); } while (0)
|
---|
[13301] | 416 | #endif
|
---|
[37689] | 417 |
|
---|
| 418 | /* Level 1. Always allocated. */
|
---|
| 419 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1));
|
---|
| 420 |
|
---|
| 421 | /* Level 2..N-1. */
|
---|
| 422 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) {
|
---|
| 423 | void **p = *lp;
|
---|
| 424 |
|
---|
| 425 | if (p == NULL) {
|
---|
| 426 | if (!alloc) {
|
---|
| 427 | return NULL;
|
---|
| 428 | }
|
---|
| 429 | ALLOC(p, sizeof(void *) * L2_SIZE);
|
---|
| 430 | *lp = p;
|
---|
| 431 | }
|
---|
| 432 |
|
---|
| 433 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
|
---|
| 434 | }
|
---|
| 435 |
|
---|
| 436 | pd = *lp;
|
---|
| 437 | if (pd == NULL) {
|
---|
| 438 | if (!alloc) {
|
---|
[18597] | 439 | return NULL;
|
---|
[37689] | 440 | }
|
---|
| 441 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE);
|
---|
| 442 | *lp = pd;
|
---|
[18597] | 443 | }
|
---|
[13301] | 444 |
|
---|
[37689] | 445 | #undef ALLOC
|
---|
[1] | 446 |
|
---|
[37689] | 447 | return pd + (index & (L2_SIZE - 1));
|
---|
[1] | 448 | }
|
---|
| 449 |
|
---|
[37689] | 450 | static inline PageDesc *page_find(tb_page_addr_t index)
|
---|
[1] | 451 | {
|
---|
[37689] | 452 | return page_find_alloc(index, 0);
|
---|
[1] | 453 | }
|
---|
| 454 |
|
---|
[37689] | 455 | #if !defined(CONFIG_USER_ONLY)
|
---|
[2422] | 456 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
|
---|
[1] | 457 | {
|
---|
[2422] | 458 | PhysPageDesc *pd;
|
---|
[37689] | 459 | void **lp;
|
---|
| 460 | int i;
|
---|
[1] | 461 |
|
---|
[37689] | 462 | /* Level 1. Always allocated. */
|
---|
| 463 | lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1));
|
---|
[2422] | 464 |
|
---|
[37689] | 465 | /* Level 2..N-1. */
|
---|
| 466 | for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) {
|
---|
| 467 | void **p = *lp;
|
---|
| 468 | if (p == NULL) {
|
---|
| 469 | if (!alloc) {
|
---|
| 470 | return NULL;
|
---|
| 471 | }
|
---|
| 472 | *lp = p = qemu_mallocz(sizeof(void *) * L2_SIZE);
|
---|
| 473 | }
|
---|
| 474 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
|
---|
[1] | 475 | }
|
---|
[18598] | 476 |
|
---|
[2422] | 477 | pd = *lp;
|
---|
[37689] | 478 | if (pd == NULL) {
|
---|
[2422] | 479 | int i;
|
---|
[37689] | 480 |
|
---|
| 481 | if (!alloc) {
|
---|
[2422] | 482 | return NULL;
|
---|
[37689] | 483 | }
|
---|
| 484 |
|
---|
| 485 | *lp = pd = qemu_malloc(sizeof(PhysPageDesc) * L2_SIZE);
|
---|
| 486 |
|
---|
[36170] | 487 | for (i = 0; i < L2_SIZE; i++) {
|
---|
[37689] | 488 | pd[i].phys_offset = IO_MEM_UNASSIGNED;
|
---|
| 489 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS;
|
---|
[36170] | 490 | }
|
---|
[1] | 491 | }
|
---|
[37689] | 492 |
|
---|
| 493 | return pd + (index & (L2_SIZE - 1));
|
---|
[1] | 494 | }
|
---|
| 495 |
|
---|
[2422] | 496 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
|
---|
[1] | 497 | {
|
---|
[2422] | 498 | return phys_page_find_alloc(index, 0);
|
---|
[1] | 499 | }
|
---|
| 500 |
|
---|
[2422] | 501 | static void tlb_protect_code(ram_addr_t ram_addr);
|
---|
[6532] | 502 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
|
---|
[2422] | 503 | target_ulong vaddr);
|
---|
[13301] | 504 | #define mmap_lock() do { } while(0)
|
---|
| 505 | #define mmap_unlock() do { } while(0)
|
---|
[2422] | 506 | #endif
|
---|
[1] | 507 |
|
---|
[36140] | 508 | #ifdef VBOX /* We don't need such huge codegen buffer size, as execute
|
---|
[43387] | 509 | most of the code in raw or hm mode. */
|
---|
[17420] | 510 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024)
|
---|
[36140] | 511 | #else /* !VBOX */
|
---|
[17420] | 512 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
|
---|
[36140] | 513 | #endif /* !VBOX */
|
---|
[13301] | 514 |
|
---|
| 515 | #if defined(CONFIG_USER_ONLY)
|
---|
[36175] | 516 | /* Currently it is not recommended to allocate big chunks of data in
|
---|
[13301] | 517 | user mode. It will change when a dedicated libc will be used */
|
---|
| 518 | #define USE_STATIC_CODE_GEN_BUFFER
|
---|
| 519 | #endif
|
---|
| 520 |
|
---|
[36175] | 521 | #if defined(VBOX) && defined(USE_STATIC_CODE_GEN_BUFFER)
|
---|
| 522 | # error "VBox allocates codegen buffer dynamically"
|
---|
| 523 | #endif
|
---|
| 524 |
|
---|
[13301] | 525 | #ifdef USE_STATIC_CODE_GEN_BUFFER
|
---|
[37689] | 526 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]
|
---|
| 527 | __attribute__((aligned (CODE_GEN_ALIGN)));
|
---|
[13301] | 528 | #endif
|
---|
| 529 |
|
---|
[42601] | 530 | static void code_gen_alloc(uintptr_t tb_size)
|
---|
[13301] | 531 | {
|
---|
| 532 | #ifdef USE_STATIC_CODE_GEN_BUFFER
|
---|
| 533 | code_gen_buffer = static_code_gen_buffer;
|
---|
| 534 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
|
---|
| 535 | map_exec(code_gen_buffer, code_gen_buffer_size);
|
---|
| 536 | #else
|
---|
[36175] | 537 | # ifdef VBOX
|
---|
[17420] | 538 | /* We cannot use phys_ram_size here, as it's 0 now,
|
---|
| 539 | * it only gets initialized once RAM registration callback
|
---|
| 540 | * (REMR3NotifyPhysRamRegister()) called.
|
---|
| 541 | */
|
---|
| 542 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
|
---|
[36175] | 543 | # else /* !VBOX */
|
---|
[13301] | 544 | code_gen_buffer_size = tb_size;
|
---|
| 545 | if (code_gen_buffer_size == 0) {
|
---|
| 546 | #if defined(CONFIG_USER_ONLY)
|
---|
| 547 | /* in user mode, phys_ram_size is not meaningful */
|
---|
| 548 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
|
---|
| 549 | #else
|
---|
[37675] | 550 | /* XXX: needs adjustments */
|
---|
[42601] | 551 | code_gen_buffer_size = (uintptr_t)(ram_size / 4);
|
---|
[13301] | 552 | #endif
|
---|
| 553 | }
|
---|
| 554 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
|
---|
| 555 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
|
---|
[36175] | 556 | # endif /* !VBOX */
|
---|
[13301] | 557 | /* The code gen buffer location may have constraints depending on
|
---|
| 558 | the host cpu and OS */
|
---|
[36175] | 559 | # ifdef VBOX
|
---|
[13301] | 560 | code_gen_buffer = RTMemExecAlloc(code_gen_buffer_size);
|
---|
[15284] | 561 |
|
---|
[13301] | 562 | if (!code_gen_buffer) {
|
---|
[15284] | 563 | LogRel(("REM: failed allocate codegen buffer %lld\n",
|
---|
[13301] | 564 | code_gen_buffer_size));
|
---|
| 565 | return;
|
---|
| 566 | }
|
---|
[36175] | 567 | # else /* !VBOX */
|
---|
[15284] | 568 | #if defined(__linux__)
|
---|
[13301] | 569 | {
|
---|
| 570 | int flags;
|
---|
| 571 | void *start = NULL;
|
---|
| 572 |
|
---|
| 573 | flags = MAP_PRIVATE | MAP_ANONYMOUS;
|
---|
| 574 | #if defined(__x86_64__)
|
---|
| 575 | flags |= MAP_32BIT;
|
---|
| 576 | /* Cannot map more than that */
|
---|
| 577 | if (code_gen_buffer_size > (800 * 1024 * 1024))
|
---|
| 578 | code_gen_buffer_size = (800 * 1024 * 1024);
|
---|
| 579 | #elif defined(__sparc_v9__)
|
---|
| 580 | // Map the buffer below 2G, so we can use direct calls and branches
|
---|
| 581 | flags |= MAP_FIXED;
|
---|
| 582 | start = (void *) 0x60000000UL;
|
---|
| 583 | if (code_gen_buffer_size > (512 * 1024 * 1024))
|
---|
| 584 | code_gen_buffer_size = (512 * 1024 * 1024);
|
---|
[36170] | 585 | #elif defined(__arm__)
|
---|
| 586 | /* Map the buffer below 32M, so we can use direct calls and branches */
|
---|
| 587 | flags |= MAP_FIXED;
|
---|
| 588 | start = (void *) 0x01000000UL;
|
---|
| 589 | if (code_gen_buffer_size > 16 * 1024 * 1024)
|
---|
| 590 | code_gen_buffer_size = 16 * 1024 * 1024;
|
---|
[37689] | 591 | #elif defined(__s390x__)
|
---|
| 592 | /* Map the buffer so that we can use direct calls and branches. */
|
---|
| 593 | /* We have a +- 4GB range on the branches; leave some slop. */
|
---|
| 594 | if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) {
|
---|
| 595 | code_gen_buffer_size = 3ul * 1024 * 1024 * 1024;
|
---|
| 596 | }
|
---|
| 597 | start = (void *)0x90000000UL;
|
---|
[13301] | 598 | #endif
|
---|
| 599 | code_gen_buffer = mmap(start, code_gen_buffer_size,
|
---|
| 600 | PROT_WRITE | PROT_READ | PROT_EXEC,
|
---|
| 601 | flags, -1, 0);
|
---|
| 602 | if (code_gen_buffer == MAP_FAILED) {
|
---|
| 603 | fprintf(stderr, "Could not allocate dynamic translator buffer\n");
|
---|
| 604 | exit(1);
|
---|
| 605 | }
|
---|
| 606 | }
|
---|
[37675] | 607 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
|
---|
[13301] | 608 | {
|
---|
| 609 | int flags;
|
---|
| 610 | void *addr = NULL;
|
---|
| 611 | flags = MAP_PRIVATE | MAP_ANONYMOUS;
|
---|
| 612 | #if defined(__x86_64__)
|
---|
| 613 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
|
---|
| 614 | * 0x40000000 is free */
|
---|
| 615 | flags |= MAP_FIXED;
|
---|
| 616 | addr = (void *)0x40000000;
|
---|
| 617 | /* Cannot map more than that */
|
---|
| 618 | if (code_gen_buffer_size > (800 * 1024 * 1024))
|
---|
| 619 | code_gen_buffer_size = (800 * 1024 * 1024);
|
---|
| 620 | #endif
|
---|
| 621 | code_gen_buffer = mmap(addr, code_gen_buffer_size,
|
---|
[15284] | 622 | PROT_WRITE | PROT_READ | PROT_EXEC,
|
---|
[13301] | 623 | flags, -1, 0);
|
---|
| 624 | if (code_gen_buffer == MAP_FAILED) {
|
---|
| 625 | fprintf(stderr, "Could not allocate dynamic translator buffer\n");
|
---|
| 626 | exit(1);
|
---|
| 627 | }
|
---|
| 628 | }
|
---|
| 629 | #else
|
---|
| 630 | code_gen_buffer = qemu_malloc(code_gen_buffer_size);
|
---|
| 631 | map_exec(code_gen_buffer, code_gen_buffer_size);
|
---|
| 632 | #endif
|
---|
[36175] | 633 | # endif /* !VBOX */
|
---|
[13301] | 634 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */
|
---|
[37675] | 635 | #ifndef VBOX /** @todo r=bird: why are we different? */
|
---|
[13301] | 636 | map_exec(code_gen_prologue, sizeof(code_gen_prologue));
|
---|
[13504] | 637 | #else
|
---|
| 638 | map_exec(code_gen_prologue, _1K);
|
---|
| 639 | #endif
|
---|
[15284] | 640 | code_gen_buffer_max_size = code_gen_buffer_size -
|
---|
[37689] | 641 | (TCG_MAX_OP_SIZE * OPC_MAX_SIZE);
|
---|
[13301] | 642 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
|
---|
| 643 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
|
---|
| 644 | }
|
---|
| 645 |
|
---|
| 646 | /* Must be called before using the QEMU cpus. 'tb_size' is the size
|
---|
| 647 | (in bytes) allocated to the translation buffer. Zero means default
|
---|
| 648 | size. */
|
---|
[42601] | 649 | void cpu_exec_init_all(uintptr_t tb_size)
|
---|
[13301] | 650 | {
|
---|
| 651 | cpu_gen_init();
|
---|
| 652 | code_gen_alloc(tb_size);
|
---|
| 653 | code_gen_ptr = code_gen_buffer;
|
---|
| 654 | page_init();
|
---|
| 655 | #if !defined(CONFIG_USER_ONLY)
|
---|
| 656 | io_mem_init();
|
---|
| 657 | #endif
|
---|
[37689] | 658 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE)
|
---|
| 659 | /* There's no guest base to take into account, so go ahead and
|
---|
| 660 | initialize the prologue now. */
|
---|
| 661 | tcg_prologue_init(&tcg_ctx);
|
---|
| 662 | #endif
|
---|
[13301] | 663 | }
|
---|
| 664 |
|
---|
| 665 | #ifndef VBOX
|
---|
| 666 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
|
---|
| 667 |
|
---|
[37675] | 668 | static int cpu_common_post_load(void *opaque, int version_id)
|
---|
[13301] | 669 | {
|
---|
| 670 | CPUState *env = opaque;
|
---|
| 671 |
|
---|
[36175] | 672 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
|
---|
| 673 | version_id is increased. */
|
---|
| 674 | env->interrupt_request &= ~0x01;
|
---|
[13301] | 675 | tlb_flush(env, 1);
|
---|
| 676 |
|
---|
| 677 | return 0;
|
---|
| 678 | }
|
---|
[37675] | 679 |
|
---|
| 680 | static const VMStateDescription vmstate_cpu_common = {
|
---|
| 681 | .name = "cpu_common",
|
---|
| 682 | .version_id = 1,
|
---|
| 683 | .minimum_version_id = 1,
|
---|
| 684 | .minimum_version_id_old = 1,
|
---|
| 685 | .post_load = cpu_common_post_load,
|
---|
| 686 | .fields = (VMStateField []) {
|
---|
| 687 | VMSTATE_UINT32(halted, CPUState),
|
---|
| 688 | VMSTATE_UINT32(interrupt_request, CPUState),
|
---|
| 689 | VMSTATE_END_OF_LIST()
|
---|
| 690 | }
|
---|
| 691 | };
|
---|
[13301] | 692 | #endif
|
---|
[36175] | 693 |
|
---|
| 694 | CPUState *qemu_get_cpu(int cpu)
|
---|
| 695 | {
|
---|
| 696 | CPUState *env = first_cpu;
|
---|
| 697 |
|
---|
| 698 | while (env) {
|
---|
| 699 | if (env->cpu_index == cpu)
|
---|
| 700 | break;
|
---|
| 701 | env = env->next_cpu;
|
---|
| 702 | }
|
---|
| 703 |
|
---|
| 704 | return env;
|
---|
| 705 | }
|
---|
| 706 |
|
---|
[36170] | 707 | #endif /* !VBOX */
|
---|
[13301] | 708 |
|
---|
[2422] | 709 | void cpu_exec_init(CPUState *env)
|
---|
[1] | 710 | {
|
---|
[2422] | 711 | CPUState **penv;
|
---|
| 712 | int cpu_index;
|
---|
[1] | 713 |
|
---|
[36175] | 714 | #if defined(CONFIG_USER_ONLY)
|
---|
| 715 | cpu_list_lock();
|
---|
| 716 | #endif
|
---|
[2422] | 717 | env->next_cpu = NULL;
|
---|
| 718 | penv = &first_cpu;
|
---|
| 719 | cpu_index = 0;
|
---|
| 720 | while (*penv != NULL) {
|
---|
[36175] | 721 | penv = &(*penv)->next_cpu;
|
---|
[2422] | 722 | cpu_index++;
|
---|
| 723 | }
|
---|
| 724 | env->cpu_index = cpu_index;
|
---|
[36175] | 725 | env->numa_node = 0;
|
---|
[37675] | 726 | QTAILQ_INIT(&env->breakpoints);
|
---|
| 727 | QTAILQ_INIT(&env->watchpoints);
|
---|
[2422] | 728 | *penv = env;
|
---|
[13301] | 729 | #ifndef VBOX
|
---|
[36175] | 730 | #if defined(CONFIG_USER_ONLY)
|
---|
| 731 | cpu_list_unlock();
|
---|
| 732 | #endif
|
---|
[13301] | 733 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
|
---|
[37689] | 734 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
|
---|
| 735 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
|
---|
[13301] | 736 | cpu_save, cpu_load, env);
|
---|
| 737 | #endif
|
---|
[36170] | 738 | #endif /* !VBOX */
|
---|
[1] | 739 | }
|
---|
| 740 |
|
---|
| 741 | static inline void invalidate_page_bitmap(PageDesc *p)
|
---|
| 742 | {
|
---|
| 743 | if (p->code_bitmap) {
|
---|
| 744 | qemu_free(p->code_bitmap);
|
---|
| 745 | p->code_bitmap = NULL;
|
---|
| 746 | }
|
---|
| 747 | p->code_write_count = 0;
|
---|
| 748 | }
|
---|
| 749 |
|
---|
[37689] | 750 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */
|
---|
| 751 |
|
---|
| 752 | static void page_flush_tb_1 (int level, void **lp)
|
---|
[1] | 753 | {
|
---|
[37689] | 754 | int i;
|
---|
[1] | 755 |
|
---|
[37689] | 756 | if (*lp == NULL) {
|
---|
| 757 | return;
|
---|
| 758 | }
|
---|
| 759 | if (level == 0) {
|
---|
| 760 | PageDesc *pd = *lp;
|
---|
| 761 | for (i = 0; i < L2_SIZE; ++i) {
|
---|
| 762 | pd[i].first_tb = NULL;
|
---|
| 763 | invalidate_page_bitmap(pd + i);
|
---|
[1] | 764 | }
|
---|
[37689] | 765 | } else {
|
---|
| 766 | void **pp = *lp;
|
---|
| 767 | for (i = 0; i < L2_SIZE; ++i) {
|
---|
| 768 | page_flush_tb_1 (level - 1, pp + i);
|
---|
| 769 | }
|
---|
[1] | 770 | }
|
---|
| 771 | }
|
---|
| 772 |
|
---|
[37689] | 773 | static void page_flush_tb(void)
|
---|
| 774 | {
|
---|
| 775 | int i;
|
---|
| 776 | for (i = 0; i < V_L1_SIZE; i++) {
|
---|
| 777 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i);
|
---|
| 778 | }
|
---|
| 779 | }
|
---|
| 780 |
|
---|
[1] | 781 | /* flush all the translation blocks */
|
---|
| 782 | /* XXX: tb_flush is currently not thread safe */
|
---|
[2422] | 783 | void tb_flush(CPUState *env1)
|
---|
[1] | 784 | {
|
---|
[2422] | 785 | CPUState *env;
|
---|
[18597] | 786 | #ifdef VBOX
|
---|
| 787 | STAM_PROFILE_START(&env1->StatTbFlush, a);
|
---|
| 788 | #endif
|
---|
[1] | 789 | #if defined(DEBUG_FLUSH)
|
---|
[13301] | 790 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
|
---|
| 791 | (unsigned long)(code_gen_ptr - code_gen_buffer),
|
---|
| 792 | nb_tbs, nb_tbs > 0 ?
|
---|
| 793 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
|
---|
[1] | 794 | #endif
|
---|
[42601] | 795 | if ((uintptr_t)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
|
---|
[13301] | 796 | cpu_abort(env1, "Internal error: code buffer overflow\n");
|
---|
| 797 |
|
---|
[1] | 798 | nb_tbs = 0;
|
---|
[6532] | 799 |
|
---|
[2422] | 800 | for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
---|
| 801 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
|
---|
| 802 | }
|
---|
[1] | 803 |
|
---|
| 804 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
|
---|
| 805 | page_flush_tb();
|
---|
| 806 |
|
---|
| 807 | code_gen_ptr = code_gen_buffer;
|
---|
| 808 | /* XXX: flush processor icache at this point if cache flush is
|
---|
| 809 | expensive */
|
---|
| 810 | tb_flush_count++;
|
---|
[18597] | 811 | #ifdef VBOX
|
---|
| 812 | STAM_PROFILE_STOP(&env1->StatTbFlush, a);
|
---|
| 813 | #endif
|
---|
[1] | 814 | }
|
---|
| 815 |
|
---|
| 816 | #ifdef DEBUG_TB_CHECK
|
---|
[36170] | 817 |
|
---|
[13301] | 818 | static void tb_invalidate_check(target_ulong address)
|
---|
[1] | 819 | {
|
---|
| 820 | TranslationBlock *tb;
|
---|
| 821 | int i;
|
---|
| 822 | address &= TARGET_PAGE_MASK;
|
---|
[2422] | 823 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
|
---|
| 824 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
|
---|
[1] | 825 | if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
|
---|
| 826 | address >= tb->pc + tb->size)) {
|
---|
[36175] | 827 | printf("ERROR invalidate: address=" TARGET_FMT_lx
|
---|
| 828 | " PC=%08lx size=%04x\n",
|
---|
[2422] | 829 | address, (long)tb->pc, tb->size);
|
---|
[1] | 830 | }
|
---|
| 831 | }
|
---|
| 832 | }
|
---|
| 833 | }
|
---|
| 834 |
|
---|
| 835 | /* verify that all the pages have correct rights for code */
|
---|
| 836 | static void tb_page_check(void)
|
---|
| 837 | {
|
---|
| 838 | TranslationBlock *tb;
|
---|
| 839 | int i, flags1, flags2;
|
---|
[6532] | 840 |
|
---|
[2422] | 841 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
|
---|
| 842 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
|
---|
[1] | 843 | flags1 = page_get_flags(tb->pc);
|
---|
| 844 | flags2 = page_get_flags(tb->pc + tb->size - 1);
|
---|
| 845 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
|
---|
| 846 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
|
---|
[2422] | 847 | (long)tb->pc, tb->size, flags1, flags2);
|
---|
[1] | 848 | }
|
---|
| 849 | }
|
---|
| 850 | }
|
---|
| 851 | }
|
---|
| 852 |
|
---|
[36140] | 853 | #endif
|
---|
| 854 |
|
---|
[1] | 855 | /* invalidate one TB */
|
---|
| 856 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
|
---|
| 857 | int next_offset)
|
---|
| 858 | {
|
---|
| 859 | TranslationBlock *tb1;
|
---|
| 860 | for(;;) {
|
---|
| 861 | tb1 = *ptb;
|
---|
| 862 | if (tb1 == tb) {
|
---|
| 863 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
|
---|
| 864 | break;
|
---|
| 865 | }
|
---|
| 866 | ptb = (TranslationBlock **)((char *)tb1 + next_offset);
|
---|
| 867 | }
|
---|
| 868 | }
|
---|
| 869 |
|
---|
| 870 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
|
---|
| 871 | {
|
---|
| 872 | TranslationBlock *tb1;
|
---|
| 873 | unsigned int n1;
|
---|
| 874 |
|
---|
| 875 | for(;;) {
|
---|
| 876 | tb1 = *ptb;
|
---|
[42601] | 877 | n1 = (intptr_t)tb1 & 3;
|
---|
| 878 | tb1 = (TranslationBlock *)((intptr_t)tb1 & ~3);
|
---|
[1] | 879 | if (tb1 == tb) {
|
---|
| 880 | *ptb = tb1->page_next[n1];
|
---|
| 881 | break;
|
---|
| 882 | }
|
---|
| 883 | ptb = &tb1->page_next[n1];
|
---|
| 884 | }
|
---|
| 885 | }
|
---|
| 886 |
|
---|
| 887 | static inline void tb_jmp_remove(TranslationBlock *tb, int n)
|
---|
| 888 | {
|
---|
| 889 | TranslationBlock *tb1, **ptb;
|
---|
| 890 | unsigned int n1;
|
---|
| 891 |
|
---|
| 892 | ptb = &tb->jmp_next[n];
|
---|
| 893 | tb1 = *ptb;
|
---|
| 894 | if (tb1) {
|
---|
| 895 | /* find tb(n) in circular list */
|
---|
| 896 | for(;;) {
|
---|
| 897 | tb1 = *ptb;
|
---|
[42601] | 898 | n1 = (intptr_t)tb1 & 3;
|
---|
| 899 | tb1 = (TranslationBlock *)((intptr_t)tb1 & ~3);
|
---|
[1] | 900 | if (n1 == n && tb1 == tb)
|
---|
| 901 | break;
|
---|
| 902 | if (n1 == 2) {
|
---|
| 903 | ptb = &tb1->jmp_first;
|
---|
| 904 | } else {
|
---|
| 905 | ptb = &tb1->jmp_next[n1];
|
---|
| 906 | }
|
---|
| 907 | }
|
---|
| 908 | /* now we can suppress tb(n) from the list */
|
---|
| 909 | *ptb = tb->jmp_next[n];
|
---|
| 910 |
|
---|
| 911 | tb->jmp_next[n] = NULL;
|
---|
| 912 | }
|
---|
| 913 | }
|
---|
| 914 |
|
---|
| 915 | /* reset the jump entry 'n' of a TB so that it is not chained to
|
---|
| 916 | another TB */
|
---|
| 917 | static inline void tb_reset_jump(TranslationBlock *tb, int n)
|
---|
| 918 | {
|
---|
[42601] | 919 | tb_set_jmp_target(tb, n, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[n]));
|
---|
[1] | 920 | }
|
---|
| 921 |
|
---|
[37689] | 922 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
|
---|
[1] | 923 | {
|
---|
[2422] | 924 | CPUState *env;
|
---|
| 925 | PageDesc *p;
|
---|
[1] | 926 | unsigned int h, n1;
|
---|
[37689] | 927 | tb_page_addr_t phys_pc;
|
---|
[2422] | 928 | TranslationBlock *tb1, *tb2;
|
---|
[6532] | 929 |
|
---|
[2422] | 930 | /* remove the TB from the hash list */
|
---|
| 931 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
|
---|
| 932 | h = tb_phys_hash_func(phys_pc);
|
---|
[6532] | 933 | tb_remove(&tb_phys_hash[h], tb,
|
---|
[2422] | 934 | offsetof(TranslationBlock, phys_hash_next));
|
---|
| 935 |
|
---|
| 936 | /* remove the TB from the page list */
|
---|
| 937 | if (tb->page_addr[0] != page_addr) {
|
---|
| 938 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
|
---|
| 939 | tb_page_remove(&p->first_tb, tb);
|
---|
| 940 | invalidate_page_bitmap(p);
|
---|
| 941 | }
|
---|
| 942 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
|
---|
| 943 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
|
---|
| 944 | tb_page_remove(&p->first_tb, tb);
|
---|
| 945 | invalidate_page_bitmap(p);
|
---|
| 946 | }
|
---|
| 947 |
|
---|
[1] | 948 | tb_invalidated_flag = 1;
|
---|
| 949 |
|
---|
| 950 | /* remove the TB from the hash list */
|
---|
[2422] | 951 | h = tb_jmp_cache_hash_func(tb->pc);
|
---|
| 952 | for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
---|
| 953 | if (env->tb_jmp_cache[h] == tb)
|
---|
| 954 | env->tb_jmp_cache[h] = NULL;
|
---|
[1] | 955 | }
|
---|
| 956 |
|
---|
| 957 | /* suppress this TB from the two jump lists */
|
---|
| 958 | tb_jmp_remove(tb, 0);
|
---|
| 959 | tb_jmp_remove(tb, 1);
|
---|
| 960 |
|
---|
| 961 | /* suppress any remaining jumps to this TB */
|
---|
| 962 | tb1 = tb->jmp_first;
|
---|
| 963 | for(;;) {
|
---|
[42601] | 964 | n1 = (intptr_t)tb1 & 3;
|
---|
[1] | 965 | if (n1 == 2)
|
---|
| 966 | break;
|
---|
[42601] | 967 | tb1 = (TranslationBlock *)((intptr_t)tb1 & ~3);
|
---|
[1] | 968 | tb2 = tb1->jmp_next[n1];
|
---|
| 969 | tb_reset_jump(tb1, n1);
|
---|
| 970 | tb1->jmp_next[n1] = NULL;
|
---|
| 971 | tb1 = tb2;
|
---|
| 972 | }
|
---|
[42601] | 973 | tb->jmp_first = (TranslationBlock *)((intptr_t)tb | 2); /* fail safe */
|
---|
[2422] | 974 |
|
---|
| 975 | tb_phys_invalidate_count++;
|
---|
[1] | 976 | }
|
---|
| 977 |
|
---|
| 978 | #ifdef VBOX
|
---|
[36140] | 979 |
|
---|
[1] | 980 | void tb_invalidate_virt(CPUState *env, uint32_t eip)
|
---|
| 981 | {
|
---|
[2422] | 982 | # if 1
|
---|
[1] | 983 | tb_flush(env);
|
---|
[2422] | 984 | # else
|
---|
[1] | 985 | uint8_t *cs_base, *pc;
|
---|
| 986 | unsigned int flags, h, phys_pc;
|
---|
| 987 | TranslationBlock *tb, **ptb;
|
---|
| 988 |
|
---|
| 989 | flags = env->hflags;
|
---|
| 990 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
|
---|
| 991 | cs_base = env->segs[R_CS].base;
|
---|
| 992 | pc = cs_base + eip;
|
---|
| 993 |
|
---|
[42601] | 994 | tb = tb_find(&ptb, (uintptr_t)pc, (uintptr_t)cs_base,
|
---|
[1] | 995 | flags);
|
---|
| 996 |
|
---|
[6532] | 997 | if(tb)
|
---|
[1] | 998 | {
|
---|
[2422] | 999 | # ifdef DEBUG
|
---|
[1] | 1000 | printf("invalidating TB (%08X) at %08X\n", tb, eip);
|
---|
[2422] | 1001 | # endif
|
---|
[1] | 1002 | tb_invalidate(tb);
|
---|
| 1003 | //Note: this will leak TBs, but the whole cache will be flushed
|
---|
| 1004 | // when it happens too often
|
---|
| 1005 | tb->pc = 0;
|
---|
| 1006 | tb->cs_base = 0;
|
---|
| 1007 | tb->flags = 0;
|
---|
| 1008 | }
|
---|
[2422] | 1009 | # endif
|
---|
[1] | 1010 | }
|
---|
| 1011 |
|
---|
| 1012 | # ifdef VBOX_STRICT
|
---|
| 1013 | /**
|
---|
| 1014 | * Gets the page offset.
|
---|
| 1015 | */
|
---|
[42601] | 1016 | ram_addr_t get_phys_page_offset(target_ulong addr)
|
---|
[1] | 1017 | {
|
---|
| 1018 | PhysPageDesc *p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 1019 | return p ? p->phys_offset : 0;
|
---|
| 1020 | }
|
---|
| 1021 | # endif /* VBOX_STRICT */
|
---|
[36140] | 1022 |
|
---|
[1] | 1023 | #endif /* VBOX */
|
---|
| 1024 |
|
---|
| 1025 | static inline void set_bits(uint8_t *tab, int start, int len)
|
---|
| 1026 | {
|
---|
| 1027 | int end, mask, end1;
|
---|
| 1028 |
|
---|
| 1029 | end = start + len;
|
---|
| 1030 | tab += start >> 3;
|
---|
| 1031 | mask = 0xff << (start & 7);
|
---|
| 1032 | if ((start & ~7) == (end & ~7)) {
|
---|
| 1033 | if (start < end) {
|
---|
| 1034 | mask &= ~(0xff << (end & 7));
|
---|
| 1035 | *tab |= mask;
|
---|
| 1036 | }
|
---|
| 1037 | } else {
|
---|
| 1038 | *tab++ |= mask;
|
---|
| 1039 | start = (start + 8) & ~7;
|
---|
| 1040 | end1 = end & ~7;
|
---|
| 1041 | while (start < end1) {
|
---|
| 1042 | *tab++ = 0xff;
|
---|
| 1043 | start += 8;
|
---|
| 1044 | }
|
---|
| 1045 | if (start < end) {
|
---|
| 1046 | mask = ~(0xff << (end & 7));
|
---|
| 1047 | *tab |= mask;
|
---|
| 1048 | }
|
---|
| 1049 | }
|
---|
| 1050 | }
|
---|
| 1051 |
|
---|
| 1052 | static void build_page_bitmap(PageDesc *p)
|
---|
| 1053 | {
|
---|
| 1054 | int n, tb_start, tb_end;
|
---|
| 1055 | TranslationBlock *tb;
|
---|
[6532] | 1056 |
|
---|
[36140] | 1057 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8);
|
---|
[1] | 1058 |
|
---|
| 1059 | tb = p->first_tb;
|
---|
| 1060 | while (tb != NULL) {
|
---|
[42601] | 1061 | n = (intptr_t)tb & 3;
|
---|
| 1062 | tb = (TranslationBlock *)((intptr_t)tb & ~3);
|
---|
[1] | 1063 | /* NOTE: this is subtle as a TB may span two physical pages */
|
---|
| 1064 | if (n == 0) {
|
---|
| 1065 | /* NOTE: tb_end may be after the end of the page, but
|
---|
| 1066 | it is not a problem */
|
---|
| 1067 | tb_start = tb->pc & ~TARGET_PAGE_MASK;
|
---|
| 1068 | tb_end = tb_start + tb->size;
|
---|
| 1069 | if (tb_end > TARGET_PAGE_SIZE)
|
---|
| 1070 | tb_end = TARGET_PAGE_SIZE;
|
---|
| 1071 | } else {
|
---|
| 1072 | tb_start = 0;
|
---|
| 1073 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
|
---|
| 1074 | }
|
---|
| 1075 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
|
---|
| 1076 | tb = tb->page_next[n];
|
---|
| 1077 | }
|
---|
| 1078 | }
|
---|
| 1079 |
|
---|
[13301] | 1080 | TranslationBlock *tb_gen_code(CPUState *env,
|
---|
| 1081 | target_ulong pc, target_ulong cs_base,
|
---|
| 1082 | int flags, int cflags)
|
---|
[1] | 1083 | {
|
---|
| 1084 | TranslationBlock *tb;
|
---|
| 1085 | uint8_t *tc_ptr;
|
---|
[37689] | 1086 | tb_page_addr_t phys_pc, phys_page2;
|
---|
| 1087 | target_ulong virt_page2;
|
---|
[1] | 1088 | int code_gen_size;
|
---|
| 1089 |
|
---|
[37689] | 1090 | phys_pc = get_page_addr_code(env, pc);
|
---|
[1] | 1091 | tb = tb_alloc(pc);
|
---|
| 1092 | if (!tb) {
|
---|
| 1093 | /* flush must be done */
|
---|
| 1094 | tb_flush(env);
|
---|
| 1095 | /* cannot fail at this point */
|
---|
| 1096 | tb = tb_alloc(pc);
|
---|
[13301] | 1097 | /* Don't forget to invalidate previous TB info. */
|
---|
| 1098 | tb_invalidated_flag = 1;
|
---|
[1] | 1099 | }
|
---|
| 1100 | tc_ptr = code_gen_ptr;
|
---|
| 1101 | tb->tc_ptr = tc_ptr;
|
---|
| 1102 | tb->cs_base = cs_base;
|
---|
| 1103 | tb->flags = flags;
|
---|
| 1104 | tb->cflags = cflags;
|
---|
[13301] | 1105 | cpu_gen_code(env, tb, &code_gen_size);
|
---|
[42601] | 1106 | code_gen_ptr = (void *)(((uintptr_t)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
|
---|
[6532] | 1107 |
|
---|
[1] | 1108 | /* check next page if needed */
|
---|
| 1109 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
|
---|
| 1110 | phys_page2 = -1;
|
---|
| 1111 | if ((pc & TARGET_PAGE_MASK) != virt_page2) {
|
---|
[37689] | 1112 | phys_page2 = get_page_addr_code(env, virt_page2);
|
---|
[1] | 1113 | }
|
---|
[37689] | 1114 | tb_link_page(tb, phys_pc, phys_page2);
|
---|
[13301] | 1115 | return tb;
|
---|
[1] | 1116 | }
|
---|
[6532] | 1117 |
|
---|
[1] | 1118 | /* invalidate all TBs which intersect with the target physical page
|
---|
| 1119 | starting in range [start;end[. NOTE: start and end must refer to
|
---|
| 1120 | the same physical page. 'is_cpu_write_access' should be true if called
|
---|
| 1121 | from a real cpu write access: the virtual CPU will exit the current
|
---|
| 1122 | TB if code is modified inside this TB. */
|
---|
[37689] | 1123 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
|
---|
[1] | 1124 | int is_cpu_write_access)
|
---|
| 1125 | {
|
---|
[36170] | 1126 | TranslationBlock *tb, *tb_next, *saved_tb;
|
---|
[1] | 1127 | CPUState *env = cpu_single_env;
|
---|
[37689] | 1128 | tb_page_addr_t tb_start, tb_end;
|
---|
[1] | 1129 | PageDesc *p;
|
---|
[36170] | 1130 | int n;
|
---|
| 1131 | #ifdef TARGET_HAS_PRECISE_SMC
|
---|
| 1132 | int current_tb_not_found = is_cpu_write_access;
|
---|
| 1133 | TranslationBlock *current_tb = NULL;
|
---|
| 1134 | int current_tb_modified = 0;
|
---|
| 1135 | target_ulong current_pc = 0;
|
---|
| 1136 | target_ulong current_cs_base = 0;
|
---|
| 1137 | int current_flags = 0;
|
---|
| 1138 | #endif /* TARGET_HAS_PRECISE_SMC */
|
---|
[1] | 1139 |
|
---|
| 1140 | p = page_find(start >> TARGET_PAGE_BITS);
|
---|
[6532] | 1141 | if (!p)
|
---|
[1] | 1142 | return;
|
---|
[6532] | 1143 | if (!p->code_bitmap &&
|
---|
[1] | 1144 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
|
---|
| 1145 | is_cpu_write_access) {
|
---|
| 1146 | /* build code bitmap */
|
---|
| 1147 | build_page_bitmap(p);
|
---|
| 1148 | }
|
---|
| 1149 |
|
---|
| 1150 | /* we remove all the TBs in the range [start, end[ */
|
---|
| 1151 | /* XXX: see if in some cases it could be faster to invalidate all the code */
|
---|
| 1152 | tb = p->first_tb;
|
---|
| 1153 | while (tb != NULL) {
|
---|
[42601] | 1154 | n = (intptr_t)tb & 3;
|
---|
| 1155 | tb = (TranslationBlock *)((intptr_t)tb & ~3);
|
---|
[1] | 1156 | tb_next = tb->page_next[n];
|
---|
| 1157 | /* NOTE: this is subtle as a TB may span two physical pages */
|
---|
| 1158 | if (n == 0) {
|
---|
| 1159 | /* NOTE: tb_end may be after the end of the page, but
|
---|
| 1160 | it is not a problem */
|
---|
| 1161 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
|
---|
| 1162 | tb_end = tb_start + tb->size;
|
---|
| 1163 | } else {
|
---|
| 1164 | tb_start = tb->page_addr[1];
|
---|
| 1165 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
|
---|
| 1166 | }
|
---|
| 1167 | if (!(tb_end <= start || tb_start >= end)) {
|
---|
| 1168 | #ifdef TARGET_HAS_PRECISE_SMC
|
---|
| 1169 | if (current_tb_not_found) {
|
---|
| 1170 | current_tb_not_found = 0;
|
---|
| 1171 | current_tb = NULL;
|
---|
[13301] | 1172 | if (env->mem_io_pc) {
|
---|
[1] | 1173 | /* now we have a real cpu fault */
|
---|
[13301] | 1174 | current_tb = tb_find_pc(env->mem_io_pc);
|
---|
[1] | 1175 | }
|
---|
| 1176 | }
|
---|
| 1177 | if (current_tb == tb &&
|
---|
[13301] | 1178 | (current_tb->cflags & CF_COUNT_MASK) != 1) {
|
---|
[1] | 1179 | /* If we are modifying the current TB, we must stop
|
---|
| 1180 | its execution. We could be more precise by checking
|
---|
| 1181 | that the modification is after the current PC, but it
|
---|
| 1182 | would require a specialized function to partially
|
---|
| 1183 | restore the CPU state */
|
---|
[6532] | 1184 |
|
---|
[1] | 1185 | current_tb_modified = 1;
|
---|
[6532] | 1186 | cpu_restore_state(current_tb, env,
|
---|
[13301] | 1187 | env->mem_io_pc, NULL);
|
---|
[36170] | 1188 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
|
---|
| 1189 | ¤t_flags);
|
---|
[1] | 1190 | }
|
---|
| 1191 | #endif /* TARGET_HAS_PRECISE_SMC */
|
---|
[2422] | 1192 | /* we need to do that to handle the case where a signal
|
---|
| 1193 | occurs while doing tb_phys_invalidate() */
|
---|
| 1194 | saved_tb = NULL;
|
---|
| 1195 | if (env) {
|
---|
| 1196 | saved_tb = env->current_tb;
|
---|
| 1197 | env->current_tb = NULL;
|
---|
| 1198 | }
|
---|
[1] | 1199 | tb_phys_invalidate(tb, -1);
|
---|
[2422] | 1200 | if (env) {
|
---|
| 1201 | env->current_tb = saved_tb;
|
---|
| 1202 | if (env->interrupt_request && env->current_tb)
|
---|
| 1203 | cpu_interrupt(env, env->interrupt_request);
|
---|
| 1204 | }
|
---|
[1] | 1205 | }
|
---|
| 1206 | tb = tb_next;
|
---|
| 1207 | }
|
---|
| 1208 | #if !defined(CONFIG_USER_ONLY)
|
---|
| 1209 | /* if no code remaining, no need to continue to use slow writes */
|
---|
| 1210 | if (!p->first_tb) {
|
---|
| 1211 | invalidate_page_bitmap(p);
|
---|
| 1212 | if (is_cpu_write_access) {
|
---|
[13301] | 1213 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
|
---|
[1] | 1214 | }
|
---|
| 1215 | }
|
---|
| 1216 | #endif
|
---|
| 1217 | #ifdef TARGET_HAS_PRECISE_SMC
|
---|
| 1218 | if (current_tb_modified) {
|
---|
| 1219 | /* we generate a block containing just the instruction
|
---|
| 1220 | modifying the memory. It will ensure that it cannot modify
|
---|
| 1221 | itself */
|
---|
| 1222 | env->current_tb = NULL;
|
---|
[13301] | 1223 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
|
---|
[1] | 1224 | cpu_resume_from_signal(env, NULL);
|
---|
| 1225 | }
|
---|
| 1226 | #endif
|
---|
| 1227 | }
|
---|
| 1228 |
|
---|
| 1229 | /* len must be <= 8 and start must be a multiple of len */
|
---|
[37689] | 1230 | static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len)
|
---|
[1] | 1231 | {
|
---|
| 1232 | PageDesc *p;
|
---|
| 1233 | int offset, b;
|
---|
| 1234 | #if 0
|
---|
| 1235 | if (1) {
|
---|
[36170] | 1236 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
|
---|
| 1237 | cpu_single_env->mem_io_vaddr, len,
|
---|
| 1238 | cpu_single_env->eip,
|
---|
[42601] | 1239 | cpu_single_env->eip + (intptr_t)cpu_single_env->segs[R_CS].base);
|
---|
[1] | 1240 | }
|
---|
| 1241 | #endif
|
---|
| 1242 | p = page_find(start >> TARGET_PAGE_BITS);
|
---|
[6532] | 1243 | if (!p)
|
---|
[1] | 1244 | return;
|
---|
| 1245 | if (p->code_bitmap) {
|
---|
| 1246 | offset = start & ~TARGET_PAGE_MASK;
|
---|
| 1247 | b = p->code_bitmap[offset >> 3] >> (offset & 7);
|
---|
| 1248 | if (b & ((1 << len) - 1))
|
---|
| 1249 | goto do_invalidate;
|
---|
| 1250 | } else {
|
---|
| 1251 | do_invalidate:
|
---|
| 1252 | tb_invalidate_phys_page_range(start, start + len, 1);
|
---|
| 1253 | }
|
---|
| 1254 | }
|
---|
| 1255 |
|
---|
| 1256 | #if !defined(CONFIG_SOFTMMU)
|
---|
[37689] | 1257 | static void tb_invalidate_phys_page(tb_page_addr_t addr,
|
---|
[42601] | 1258 | uintptr_t pc, void *puc)
|
---|
[1] | 1259 | {
|
---|
[36170] | 1260 | TranslationBlock *tb;
|
---|
[1] | 1261 | PageDesc *p;
|
---|
[36170] | 1262 | int n;
|
---|
[1] | 1263 | #ifdef TARGET_HAS_PRECISE_SMC
|
---|
[36170] | 1264 | TranslationBlock *current_tb = NULL;
|
---|
[1] | 1265 | CPUState *env = cpu_single_env;
|
---|
[36170] | 1266 | int current_tb_modified = 0;
|
---|
| 1267 | target_ulong current_pc = 0;
|
---|
| 1268 | target_ulong current_cs_base = 0;
|
---|
| 1269 | int current_flags = 0;
|
---|
[1] | 1270 | #endif
|
---|
| 1271 |
|
---|
| 1272 | addr &= TARGET_PAGE_MASK;
|
---|
| 1273 | p = page_find(addr >> TARGET_PAGE_BITS);
|
---|
[6532] | 1274 | if (!p)
|
---|
[1] | 1275 | return;
|
---|
| 1276 | tb = p->first_tb;
|
---|
| 1277 | #ifdef TARGET_HAS_PRECISE_SMC
|
---|
| 1278 | if (tb && pc != 0) {
|
---|
| 1279 | current_tb = tb_find_pc(pc);
|
---|
| 1280 | }
|
---|
| 1281 | #endif
|
---|
| 1282 | while (tb != NULL) {
|
---|
[42601] | 1283 | n = (intptr_t)tb & 3;
|
---|
| 1284 | tb = (TranslationBlock *)((intptr_t)tb & ~3);
|
---|
[1] | 1285 | #ifdef TARGET_HAS_PRECISE_SMC
|
---|
| 1286 | if (current_tb == tb &&
|
---|
[13301] | 1287 | (current_tb->cflags & CF_COUNT_MASK) != 1) {
|
---|
[1] | 1288 | /* If we are modifying the current TB, we must stop
|
---|
| 1289 | its execution. We could be more precise by checking
|
---|
| 1290 | that the modification is after the current PC, but it
|
---|
| 1291 | would require a specialized function to partially
|
---|
| 1292 | restore the CPU state */
|
---|
[6532] | 1293 |
|
---|
[1] | 1294 | current_tb_modified = 1;
|
---|
| 1295 | cpu_restore_state(current_tb, env, pc, puc);
|
---|
[36170] | 1296 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
|
---|
| 1297 | ¤t_flags);
|
---|
[1] | 1298 | }
|
---|
| 1299 | #endif /* TARGET_HAS_PRECISE_SMC */
|
---|
| 1300 | tb_phys_invalidate(tb, addr);
|
---|
| 1301 | tb = tb->page_next[n];
|
---|
| 1302 | }
|
---|
| 1303 | p->first_tb = NULL;
|
---|
| 1304 | #ifdef TARGET_HAS_PRECISE_SMC
|
---|
| 1305 | if (current_tb_modified) {
|
---|
| 1306 | /* we generate a block containing just the instruction
|
---|
| 1307 | modifying the memory. It will ensure that it cannot modify
|
---|
| 1308 | itself */
|
---|
| 1309 | env->current_tb = NULL;
|
---|
[13301] | 1310 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
|
---|
[1] | 1311 | cpu_resume_from_signal(env, puc);
|
---|
| 1312 | }
|
---|
| 1313 | #endif
|
---|
| 1314 | }
|
---|
| 1315 | #endif
|
---|
| 1316 |
|
---|
| 1317 | /* add the tb in the target page and protect it if necessary */
|
---|
[6532] | 1318 | static inline void tb_alloc_page(TranslationBlock *tb,
|
---|
[37689] | 1319 | unsigned int n, tb_page_addr_t page_addr)
|
---|
[1] | 1320 | {
|
---|
| 1321 | PageDesc *p;
|
---|
| 1322 | TranslationBlock *last_first_tb;
|
---|
| 1323 |
|
---|
| 1324 | tb->page_addr[n] = page_addr;
|
---|
[37689] | 1325 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1);
|
---|
[1] | 1326 | tb->page_next[n] = p->first_tb;
|
---|
| 1327 | last_first_tb = p->first_tb;
|
---|
[42601] | 1328 | p->first_tb = (TranslationBlock *)((intptr_t)tb | n);
|
---|
[1] | 1329 | invalidate_page_bitmap(p);
|
---|
| 1330 |
|
---|
| 1331 | #if defined(TARGET_HAS_SMC) || 1
|
---|
| 1332 |
|
---|
| 1333 | #if defined(CONFIG_USER_ONLY)
|
---|
| 1334 | if (p->flags & PAGE_WRITE) {
|
---|
[2422] | 1335 | target_ulong addr;
|
---|
| 1336 | PageDesc *p2;
|
---|
[1] | 1337 | int prot;
|
---|
| 1338 |
|
---|
| 1339 | /* force the host page as non writable (writes will have a
|
---|
| 1340 | page fault + mprotect overhead) */
|
---|
[2422] | 1341 | page_addr &= qemu_host_page_mask;
|
---|
[1] | 1342 | prot = 0;
|
---|
[2422] | 1343 | for(addr = page_addr; addr < page_addr + qemu_host_page_size;
|
---|
| 1344 | addr += TARGET_PAGE_SIZE) {
|
---|
| 1345 |
|
---|
| 1346 | p2 = page_find (addr >> TARGET_PAGE_BITS);
|
---|
| 1347 | if (!p2)
|
---|
| 1348 | continue;
|
---|
| 1349 | prot |= p2->flags;
|
---|
| 1350 | p2->flags &= ~PAGE_WRITE;
|
---|
| 1351 | }
|
---|
[6532] | 1352 | mprotect(g2h(page_addr), qemu_host_page_size,
|
---|
[1] | 1353 | (prot & PAGE_BITS) & ~PAGE_WRITE);
|
---|
| 1354 | #ifdef DEBUG_TB_INVALIDATE
|
---|
[13301] | 1355 | printf("protecting code page: 0x" TARGET_FMT_lx "\n",
|
---|
[2422] | 1356 | page_addr);
|
---|
[1] | 1357 | #endif
|
---|
| 1358 | }
|
---|
| 1359 | #else
|
---|
| 1360 | /* if some code is already present, then the pages are already
|
---|
| 1361 | protected. So we handle the case where only the first TB is
|
---|
| 1362 | allocated in a physical page */
|
---|
| 1363 | if (!last_first_tb) {
|
---|
[2422] | 1364 | tlb_protect_code(page_addr);
|
---|
[1] | 1365 | }
|
---|
| 1366 | #endif
|
---|
| 1367 |
|
---|
| 1368 | #endif /* TARGET_HAS_SMC */
|
---|
| 1369 | }
|
---|
| 1370 |
|
---|
| 1371 | /* Allocate a new translation block. Flush the translation buffer if
|
---|
| 1372 | too many translation blocks or too much generated code. */
|
---|
| 1373 | TranslationBlock *tb_alloc(target_ulong pc)
|
---|
| 1374 | {
|
---|
| 1375 | TranslationBlock *tb;
|
---|
| 1376 |
|
---|
[13301] | 1377 | if (nb_tbs >= code_gen_max_blocks ||
|
---|
[42601] | 1378 | (code_gen_ptr - code_gen_buffer) >= VBOX_ONLY((uintptr_t))code_gen_buffer_max_size)
|
---|
[1] | 1379 | return NULL;
|
---|
| 1380 | tb = &tbs[nb_tbs++];
|
---|
| 1381 | tb->pc = pc;
|
---|
| 1382 | tb->cflags = 0;
|
---|
| 1383 | return tb;
|
---|
| 1384 | }
|
---|
| 1385 |
|
---|
[13301] | 1386 | void tb_free(TranslationBlock *tb)
|
---|
| 1387 | {
|
---|
| 1388 | /* In practice this is mostly used for single use temporary TB
|
---|
| 1389 | Ignore the hard cases and just back up if this TB happens to
|
---|
| 1390 | be the last one generated. */
|
---|
| 1391 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
|
---|
| 1392 | code_gen_ptr = tb->tc_ptr;
|
---|
| 1393 | nb_tbs--;
|
---|
| 1394 | }
|
---|
| 1395 | }
|
---|
| 1396 |
|
---|
[1] | 1397 | /* add a new TB and link it to the physical page tables. phys_page2 is
|
---|
| 1398 | (-1) to indicate that only one page contains the TB. */
|
---|
[37689] | 1399 | void tb_link_page(TranslationBlock *tb,
|
---|
| 1400 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2)
|
---|
[1] | 1401 | {
|
---|
| 1402 | unsigned int h;
|
---|
| 1403 | TranslationBlock **ptb;
|
---|
| 1404 |
|
---|
[13301] | 1405 | /* Grab the mmap lock to stop another thread invalidating this TB
|
---|
| 1406 | before we are done. */
|
---|
| 1407 | mmap_lock();
|
---|
[1] | 1408 | /* add in the physical hash table */
|
---|
| 1409 | h = tb_phys_hash_func(phys_pc);
|
---|
| 1410 | ptb = &tb_phys_hash[h];
|
---|
| 1411 | tb->phys_hash_next = *ptb;
|
---|
| 1412 | *ptb = tb;
|
---|
| 1413 |
|
---|
| 1414 | /* add in the page list */
|
---|
| 1415 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
|
---|
| 1416 | if (phys_page2 != -1)
|
---|
| 1417 | tb_alloc_page(tb, 1, phys_page2);
|
---|
| 1418 | else
|
---|
| 1419 | tb->page_addr[1] = -1;
|
---|
| 1420 |
|
---|
[42601] | 1421 | tb->jmp_first = (TranslationBlock *)((intptr_t)tb | 2);
|
---|
[1] | 1422 | tb->jmp_next[0] = NULL;
|
---|
| 1423 | tb->jmp_next[1] = NULL;
|
---|
| 1424 |
|
---|
| 1425 | /* init original jump addresses */
|
---|
| 1426 | if (tb->tb_next_offset[0] != 0xffff)
|
---|
| 1427 | tb_reset_jump(tb, 0);
|
---|
| 1428 | if (tb->tb_next_offset[1] != 0xffff)
|
---|
| 1429 | tb_reset_jump(tb, 1);
|
---|
[2422] | 1430 |
|
---|
| 1431 | #ifdef DEBUG_TB_CHECK
|
---|
| 1432 | tb_page_check();
|
---|
| 1433 | #endif
|
---|
[13301] | 1434 | mmap_unlock();
|
---|
[1] | 1435 | }
|
---|
| 1436 |
|
---|
| 1437 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
|
---|
| 1438 | tb[1].tc_ptr. Return NULL if not found */
|
---|
[42601] | 1439 | TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
|
---|
[1] | 1440 | {
|
---|
| 1441 | int m_min, m_max, m;
|
---|
[42601] | 1442 | uintptr_t v;
|
---|
[1] | 1443 | TranslationBlock *tb;
|
---|
| 1444 |
|
---|
| 1445 | if (nb_tbs <= 0)
|
---|
| 1446 | return NULL;
|
---|
[42601] | 1447 | if (tc_ptr < (uintptr_t)code_gen_buffer ||
|
---|
| 1448 | tc_ptr >= (uintptr_t)code_gen_ptr)
|
---|
[1] | 1449 | return NULL;
|
---|
| 1450 | /* binary search (cf Knuth) */
|
---|
| 1451 | m_min = 0;
|
---|
| 1452 | m_max = nb_tbs - 1;
|
---|
| 1453 | while (m_min <= m_max) {
|
---|
| 1454 | m = (m_min + m_max) >> 1;
|
---|
| 1455 | tb = &tbs[m];
|
---|
[42601] | 1456 | v = (uintptr_t)tb->tc_ptr;
|
---|
[1] | 1457 | if (v == tc_ptr)
|
---|
| 1458 | return tb;
|
---|
| 1459 | else if (tc_ptr < v) {
|
---|
| 1460 | m_max = m - 1;
|
---|
| 1461 | } else {
|
---|
| 1462 | m_min = m + 1;
|
---|
| 1463 | }
|
---|
[6532] | 1464 | }
|
---|
[1] | 1465 | return &tbs[m_max];
|
---|
| 1466 | }
|
---|
| 1467 |
|
---|
| 1468 | static void tb_reset_jump_recursive(TranslationBlock *tb);
|
---|
| 1469 |
|
---|
| 1470 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
|
---|
| 1471 | {
|
---|
| 1472 | TranslationBlock *tb1, *tb_next, **ptb;
|
---|
| 1473 | unsigned int n1;
|
---|
| 1474 |
|
---|
| 1475 | tb1 = tb->jmp_next[n];
|
---|
| 1476 | if (tb1 != NULL) {
|
---|
| 1477 | /* find head of list */
|
---|
| 1478 | for(;;) {
|
---|
[42601] | 1479 | n1 = (intptr_t)tb1 & 3;
|
---|
| 1480 | tb1 = (TranslationBlock *)((intptr_t)tb1 & ~3);
|
---|
[1] | 1481 | if (n1 == 2)
|
---|
| 1482 | break;
|
---|
| 1483 | tb1 = tb1->jmp_next[n1];
|
---|
| 1484 | }
|
---|
| 1485 | /* we are now sure now that tb jumps to tb1 */
|
---|
| 1486 | tb_next = tb1;
|
---|
| 1487 |
|
---|
| 1488 | /* remove tb from the jmp_first list */
|
---|
| 1489 | ptb = &tb_next->jmp_first;
|
---|
| 1490 | for(;;) {
|
---|
| 1491 | tb1 = *ptb;
|
---|
[42601] | 1492 | n1 = (intptr_t)tb1 & 3;
|
---|
| 1493 | tb1 = (TranslationBlock *)((intptr_t)tb1 & ~3);
|
---|
[1] | 1494 | if (n1 == n && tb1 == tb)
|
---|
| 1495 | break;
|
---|
| 1496 | ptb = &tb1->jmp_next[n1];
|
---|
| 1497 | }
|
---|
| 1498 | *ptb = tb->jmp_next[n];
|
---|
| 1499 | tb->jmp_next[n] = NULL;
|
---|
[6532] | 1500 |
|
---|
[1] | 1501 | /* suppress the jump to next tb in generated code */
|
---|
| 1502 | tb_reset_jump(tb, n);
|
---|
| 1503 |
|
---|
| 1504 | /* suppress jumps in the tb on which we could have jumped */
|
---|
| 1505 | tb_reset_jump_recursive(tb_next);
|
---|
| 1506 | }
|
---|
| 1507 | }
|
---|
| 1508 |
|
---|
| 1509 | static void tb_reset_jump_recursive(TranslationBlock *tb)
|
---|
| 1510 | {
|
---|
| 1511 | tb_reset_jump_recursive2(tb, 0);
|
---|
| 1512 | tb_reset_jump_recursive2(tb, 1);
|
---|
| 1513 | }
|
---|
| 1514 |
|
---|
[2422] | 1515 | #if defined(TARGET_HAS_ICE)
|
---|
[37689] | 1516 | #if defined(CONFIG_USER_ONLY)
|
---|
[1] | 1517 | static void breakpoint_invalidate(CPUState *env, target_ulong pc)
|
---|
| 1518 | {
|
---|
[37689] | 1519 | tb_invalidate_phys_page_range(pc, pc + 1, 0);
|
---|
| 1520 | }
|
---|
| 1521 | #else
|
---|
| 1522 | static void breakpoint_invalidate(CPUState *env, target_ulong pc)
|
---|
| 1523 | {
|
---|
[36140] | 1524 | target_phys_addr_t addr;
|
---|
| 1525 | target_ulong pd;
|
---|
[2422] | 1526 | ram_addr_t ram_addr;
|
---|
| 1527 | PhysPageDesc *p;
|
---|
[1] | 1528 |
|
---|
[2422] | 1529 | addr = cpu_get_phys_page_debug(env, pc);
|
---|
| 1530 | p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 1531 | if (!p) {
|
---|
| 1532 | pd = IO_MEM_UNASSIGNED;
|
---|
| 1533 | } else {
|
---|
| 1534 | pd = p->phys_offset;
|
---|
| 1535 | }
|
---|
| 1536 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
|
---|
| 1537 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
|
---|
[1] | 1538 | }
|
---|
| 1539 | #endif
|
---|
[37689] | 1540 | #endif /* TARGET_HAS_ICE */
|
---|
[1] | 1541 |
|
---|
[37689] | 1542 | #if defined(CONFIG_USER_ONLY)
|
---|
| 1543 | void cpu_watchpoint_remove_all(CPUState *env, int mask)
|
---|
| 1544 |
|
---|
| 1545 | {
|
---|
| 1546 | }
|
---|
| 1547 |
|
---|
| 1548 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
|
---|
| 1549 | int flags, CPUWatchpoint **watchpoint)
|
---|
| 1550 | {
|
---|
| 1551 | return -ENOSYS;
|
---|
| 1552 | }
|
---|
| 1553 | #else
|
---|
[13301] | 1554 | /* Add a watchpoint. */
|
---|
[36170] | 1555 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
|
---|
| 1556 | int flags, CPUWatchpoint **watchpoint)
|
---|
[13301] | 1557 | {
|
---|
[36170] | 1558 | target_ulong len_mask = ~(len - 1);
|
---|
| 1559 | CPUWatchpoint *wp;
|
---|
[13301] | 1560 |
|
---|
[36170] | 1561 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
|
---|
| 1562 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
|
---|
| 1563 | fprintf(stderr, "qemu: tried to set invalid watchpoint at "
|
---|
| 1564 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
|
---|
| 1565 | #ifndef VBOX
|
---|
| 1566 | return -EINVAL;
|
---|
| 1567 | #else
|
---|
| 1568 | return VERR_INVALID_PARAMETER;
|
---|
| 1569 | #endif
|
---|
[13301] | 1570 | }
|
---|
[36170] | 1571 | wp = qemu_malloc(sizeof(*wp));
|
---|
[13301] | 1572 |
|
---|
[36170] | 1573 | wp->vaddr = addr;
|
---|
| 1574 | wp->len_mask = len_mask;
|
---|
| 1575 | wp->flags = flags;
|
---|
| 1576 |
|
---|
| 1577 | /* keep all GDB-injected watchpoints in front */
|
---|
| 1578 | if (flags & BP_GDB)
|
---|
[37675] | 1579 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry);
|
---|
[36170] | 1580 | else
|
---|
[37675] | 1581 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry);
|
---|
[36170] | 1582 |
|
---|
[13301] | 1583 | tlb_flush_page(env, addr);
|
---|
[36170] | 1584 |
|
---|
| 1585 | if (watchpoint)
|
---|
| 1586 | *watchpoint = wp;
|
---|
| 1587 | return 0;
|
---|
[13301] | 1588 | }
|
---|
| 1589 |
|
---|
[36170] | 1590 | /* Remove a specific watchpoint. */
|
---|
| 1591 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
|
---|
| 1592 | int flags)
|
---|
[13301] | 1593 | {
|
---|
[36170] | 1594 | target_ulong len_mask = ~(len - 1);
|
---|
| 1595 | CPUWatchpoint *wp;
|
---|
[13301] | 1596 |
|
---|
[37675] | 1597 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
|
---|
[36170] | 1598 | if (addr == wp->vaddr && len_mask == wp->len_mask
|
---|
| 1599 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
|
---|
| 1600 | cpu_watchpoint_remove_by_ref(env, wp);
|
---|
[13301] | 1601 | return 0;
|
---|
| 1602 | }
|
---|
| 1603 | }
|
---|
[36170] | 1604 | #ifndef VBOX
|
---|
| 1605 | return -ENOENT;
|
---|
| 1606 | #else
|
---|
| 1607 | return VERR_NOT_FOUND;
|
---|
| 1608 | #endif
|
---|
[13301] | 1609 | }
|
---|
| 1610 |
|
---|
[36170] | 1611 | /* Remove a specific watchpoint by reference. */
|
---|
| 1612 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
|
---|
| 1613 | {
|
---|
[37675] | 1614 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
|
---|
[13301] | 1615 |
|
---|
[36170] | 1616 | tlb_flush_page(env, watchpoint->vaddr);
|
---|
| 1617 |
|
---|
| 1618 | qemu_free(watchpoint);
|
---|
| 1619 | }
|
---|
| 1620 |
|
---|
| 1621 | /* Remove all matching watchpoints. */
|
---|
| 1622 | void cpu_watchpoint_remove_all(CPUState *env, int mask)
|
---|
| 1623 | {
|
---|
| 1624 | CPUWatchpoint *wp, *next;
|
---|
| 1625 |
|
---|
[37675] | 1626 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
|
---|
[36170] | 1627 | if (wp->flags & mask)
|
---|
| 1628 | cpu_watchpoint_remove_by_ref(env, wp);
|
---|
[13301] | 1629 | }
|
---|
| 1630 | }
|
---|
[37689] | 1631 | #endif
|
---|
[13301] | 1632 |
|
---|
[36170] | 1633 | /* Add a breakpoint. */
|
---|
| 1634 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
|
---|
| 1635 | CPUBreakpoint **breakpoint)
|
---|
[1] | 1636 | {
|
---|
[2422] | 1637 | #if defined(TARGET_HAS_ICE)
|
---|
[36170] | 1638 | CPUBreakpoint *bp;
|
---|
[6532] | 1639 |
|
---|
[36170] | 1640 | bp = qemu_malloc(sizeof(*bp));
|
---|
[1] | 1641 |
|
---|
[36170] | 1642 | bp->pc = pc;
|
---|
| 1643 | bp->flags = flags;
|
---|
[6532] | 1644 |
|
---|
[36170] | 1645 | /* keep all GDB-injected breakpoints in front */
|
---|
| 1646 | if (flags & BP_GDB)
|
---|
[37675] | 1647 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
|
---|
[36170] | 1648 | else
|
---|
[37675] | 1649 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
|
---|
[36170] | 1650 |
|
---|
[1] | 1651 | breakpoint_invalidate(env, pc);
|
---|
[36170] | 1652 |
|
---|
| 1653 | if (breakpoint)
|
---|
| 1654 | *breakpoint = bp;
|
---|
[1] | 1655 | return 0;
|
---|
| 1656 | #else
|
---|
[36170] | 1657 | return -ENOSYS;
|
---|
[1] | 1658 | #endif
|
---|
| 1659 | }
|
---|
| 1660 |
|
---|
[36170] | 1661 | /* Remove a specific breakpoint. */
|
---|
| 1662 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
|
---|
| 1663 | {
|
---|
[13301] | 1664 | #if defined(TARGET_HAS_ICE)
|
---|
[36170] | 1665 | CPUBreakpoint *bp;
|
---|
| 1666 |
|
---|
[37675] | 1667 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
---|
[36170] | 1668 | if (bp->pc == pc && bp->flags == flags) {
|
---|
| 1669 | cpu_breakpoint_remove_by_ref(env, bp);
|
---|
| 1670 | return 0;
|
---|
| 1671 | }
|
---|
[13301] | 1672 | }
|
---|
[36170] | 1673 | # ifndef VBOX
|
---|
| 1674 | return -ENOENT;
|
---|
| 1675 | # else
|
---|
| 1676 | return VERR_NOT_FOUND;
|
---|
| 1677 | # endif
|
---|
| 1678 | #else
|
---|
| 1679 | return -ENOSYS;
|
---|
[13301] | 1680 | #endif
|
---|
| 1681 | }
|
---|
| 1682 |
|
---|
[36170] | 1683 | /* Remove a specific breakpoint by reference. */
|
---|
| 1684 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
|
---|
[1] | 1685 | {
|
---|
[2422] | 1686 | #if defined(TARGET_HAS_ICE)
|
---|
[37675] | 1687 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
|
---|
[1] | 1688 |
|
---|
[36170] | 1689 | breakpoint_invalidate(env, breakpoint->pc);
|
---|
| 1690 |
|
---|
| 1691 | qemu_free(breakpoint);
|
---|
[1] | 1692 | #endif
|
---|
| 1693 | }
|
---|
| 1694 |
|
---|
[36170] | 1695 | /* Remove all matching breakpoints. */
|
---|
| 1696 | void cpu_breakpoint_remove_all(CPUState *env, int mask)
|
---|
| 1697 | {
|
---|
| 1698 | #if defined(TARGET_HAS_ICE)
|
---|
| 1699 | CPUBreakpoint *bp, *next;
|
---|
| 1700 |
|
---|
[37675] | 1701 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
|
---|
[36170] | 1702 | if (bp->flags & mask)
|
---|
| 1703 | cpu_breakpoint_remove_by_ref(env, bp);
|
---|
| 1704 | }
|
---|
| 1705 | #endif
|
---|
| 1706 | }
|
---|
| 1707 |
|
---|
[1] | 1708 | /* enable or disable single step mode. EXCP_DEBUG is returned by the
|
---|
| 1709 | CPU loop after each instruction */
|
---|
| 1710 | void cpu_single_step(CPUState *env, int enabled)
|
---|
| 1711 | {
|
---|
[2422] | 1712 | #if defined(TARGET_HAS_ICE)
|
---|
[1] | 1713 | if (env->singlestep_enabled != enabled) {
|
---|
| 1714 | env->singlestep_enabled = enabled;
|
---|
[36175] | 1715 | if (kvm_enabled())
|
---|
| 1716 | kvm_update_guest_debug(env, 0);
|
---|
| 1717 | else {
|
---|
| 1718 | /* must flush all the translated code to avoid inconsistencies */
|
---|
| 1719 | /* XXX: only flush what is necessary */
|
---|
| 1720 | tb_flush(env);
|
---|
| 1721 | }
|
---|
[1] | 1722 | }
|
---|
| 1723 | #endif
|
---|
| 1724 | }
|
---|
| 1725 |
|
---|
| 1726 | #ifndef VBOX
|
---|
[36175] | 1727 |
|
---|
[1] | 1728 | /* enable or disable low levels log */
|
---|
| 1729 | void cpu_set_log(int log_flags)
|
---|
| 1730 | {
|
---|
| 1731 | loglevel = log_flags;
|
---|
| 1732 | if (loglevel && !logfile) {
|
---|
[36140] | 1733 | logfile = fopen(logfilename, log_append ? "a" : "w");
|
---|
[1] | 1734 | if (!logfile) {
|
---|
| 1735 | perror(logfilename);
|
---|
| 1736 | _exit(1);
|
---|
| 1737 | }
|
---|
| 1738 | #if !defined(CONFIG_SOFTMMU)
|
---|
| 1739 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
|
---|
| 1740 | {
|
---|
[36140] | 1741 | static char logfile_buf[4096];
|
---|
[1] | 1742 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
|
---|
| 1743 | }
|
---|
[37675] | 1744 | #elif !defined(_WIN32)
|
---|
| 1745 | /* Win32 doesn't support line-buffering and requires size >= 2 */
|
---|
[1] | 1746 | setvbuf(logfile, NULL, _IOLBF, 0);
|
---|
| 1747 | #endif
|
---|
[36140] | 1748 | log_append = 1;
|
---|
[1] | 1749 | }
|
---|
[36140] | 1750 | if (!loglevel && logfile) {
|
---|
| 1751 | fclose(logfile);
|
---|
| 1752 | logfile = NULL;
|
---|
| 1753 | }
|
---|
[1] | 1754 | }
|
---|
| 1755 |
|
---|
| 1756 | void cpu_set_log_filename(const char *filename)
|
---|
| 1757 | {
|
---|
| 1758 | logfilename = strdup(filename);
|
---|
[36140] | 1759 | if (logfile) {
|
---|
| 1760 | fclose(logfile);
|
---|
| 1761 | logfile = NULL;
|
---|
| 1762 | }
|
---|
| 1763 | cpu_set_log(loglevel);
|
---|
[1] | 1764 | }
|
---|
[36175] | 1765 |
|
---|
[2422] | 1766 | #endif /* !VBOX */
|
---|
[1] | 1767 |
|
---|
[36175] | 1768 | static void cpu_unlink_tb(CPUState *env)
|
---|
[1] | 1769 | {
|
---|
[36175] | 1770 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the
|
---|
| 1771 | problem and hope the cpu will stop of its own accord. For userspace
|
---|
| 1772 | emulation this often isn't actually as bad as it sounds. Often
|
---|
| 1773 | signals are used primarily to interrupt blocking syscalls. */
|
---|
[1] | 1774 | TranslationBlock *tb;
|
---|
[13301] | 1775 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
|
---|
[36175] | 1776 |
|
---|
[37689] | 1777 | spin_lock(&interrupt_lock);
|
---|
[36175] | 1778 | tb = env->current_tb;
|
---|
| 1779 | /* if the cpu is currently executing code, we must unlink it and
|
---|
| 1780 | all the potentially executing TB */
|
---|
[37689] | 1781 | if (tb) {
|
---|
[36175] | 1782 | env->current_tb = NULL;
|
---|
| 1783 | tb_reset_jump_recursive(tb);
|
---|
| 1784 | }
|
---|
[37689] | 1785 | spin_unlock(&interrupt_lock);
|
---|
[36175] | 1786 | }
|
---|
| 1787 |
|
---|
| 1788 | /* mask must never be zero, except for A20 change call */
|
---|
| 1789 | void cpu_interrupt(CPUState *env, int mask)
|
---|
| 1790 | {
|
---|
[13301] | 1791 | int old_mask;
|
---|
[1] | 1792 |
|
---|
[13301] | 1793 | old_mask = env->interrupt_request;
|
---|
[36175] | 1794 | #ifndef VBOX
|
---|
| 1795 | env->interrupt_request |= mask;
|
---|
| 1796 | #else /* VBOX */
|
---|
[1] | 1797 | VM_ASSERT_EMT(env->pVM);
|
---|
[13301] | 1798 | ASMAtomicOrS32((int32_t volatile *)&env->interrupt_request, mask);
|
---|
[36175] | 1799 | #endif /* VBOX */
|
---|
| 1800 |
|
---|
| 1801 | #ifndef VBOX
|
---|
| 1802 | #ifndef CONFIG_USER_ONLY
|
---|
| 1803 | /*
|
---|
| 1804 | * If called from iothread context, wake the target cpu in
|
---|
| 1805 | * case its halted.
|
---|
| 1806 | */
|
---|
| 1807 | if (!qemu_cpu_self(env)) {
|
---|
| 1808 | qemu_cpu_kick(env);
|
---|
| 1809 | return;
|
---|
| 1810 | }
|
---|
| 1811 | #endif
|
---|
[2422] | 1812 | #endif /* !VBOX */
|
---|
[36175] | 1813 |
|
---|
[13301] | 1814 | if (use_icount) {
|
---|
| 1815 | env->icount_decr.u16.high = 0xffff;
|
---|
| 1816 | #ifndef CONFIG_USER_ONLY
|
---|
| 1817 | if (!can_do_io(env)
|
---|
[36171] | 1818 | && (mask & ~old_mask) != 0) {
|
---|
[13301] | 1819 | cpu_abort(env, "Raised interrupt while not in I/O function");
|
---|
| 1820 | }
|
---|
| 1821 | #endif
|
---|
| 1822 | } else {
|
---|
[36175] | 1823 | cpu_unlink_tb(env);
|
---|
[1] | 1824 | }
|
---|
| 1825 | }
|
---|
| 1826 |
|
---|
| 1827 | void cpu_reset_interrupt(CPUState *env, int mask)
|
---|
| 1828 | {
|
---|
[2422] | 1829 | #ifdef VBOX
|
---|
[1] | 1830 | /*
|
---|
| 1831 | * Note: the current implementation can be executed by another thread without problems; make sure this remains true
|
---|
| 1832 | * for future changes!
|
---|
| 1833 | */
|
---|
[13301] | 1834 | ASMAtomicAndS32((int32_t volatile *)&env->interrupt_request, ~mask);
|
---|
[1] | 1835 | #else /* !VBOX */
|
---|
| 1836 | env->interrupt_request &= ~mask;
|
---|
| 1837 | #endif /* !VBOX */
|
---|
| 1838 | }
|
---|
| 1839 |
|
---|
[36175] | 1840 | void cpu_exit(CPUState *env)
|
---|
| 1841 | {
|
---|
| 1842 | env->exit_request = 1;
|
---|
| 1843 | cpu_unlink_tb(env);
|
---|
| 1844 | }
|
---|
| 1845 |
|
---|
[1] | 1846 | #ifndef VBOX
|
---|
[36170] | 1847 | const CPULogItem cpu_log_items[] = {
|
---|
[6532] | 1848 | { CPU_LOG_TB_OUT_ASM, "out_asm",
|
---|
[1] | 1849 | "show generated host assembly code for each compiled TB" },
|
---|
| 1850 | { CPU_LOG_TB_IN_ASM, "in_asm",
|
---|
| 1851 | "show target assembly code for each compiled TB" },
|
---|
[6532] | 1852 | { CPU_LOG_TB_OP, "op",
|
---|
[36140] | 1853 | "show micro ops for each compiled TB" },
|
---|
| 1854 | { CPU_LOG_TB_OP_OPT, "op_opt",
|
---|
| 1855 | "show micro ops "
|
---|
[1] | 1856 | #ifdef TARGET_I386
|
---|
[36140] | 1857 | "before eflags optimization and "
|
---|
[1] | 1858 | #endif
|
---|
[36140] | 1859 | "after liveness analysis" },
|
---|
[1] | 1860 | { CPU_LOG_INT, "int",
|
---|
| 1861 | "show interrupts/exceptions in short format" },
|
---|
| 1862 | { CPU_LOG_EXEC, "exec",
|
---|
| 1863 | "show trace before each executed TB (lots of logs)" },
|
---|
| 1864 | { CPU_LOG_TB_CPU, "cpu",
|
---|
[36140] | 1865 | "show CPU state before block translation" },
|
---|
[1] | 1866 | #ifdef TARGET_I386
|
---|
| 1867 | { CPU_LOG_PCALL, "pcall",
|
---|
| 1868 | "show protected mode far calls/returns/exceptions" },
|
---|
[36170] | 1869 | { CPU_LOG_RESET, "cpu_reset",
|
---|
| 1870 | "show CPU state before CPU resets" },
|
---|
[1] | 1871 | #endif
|
---|
| 1872 | #ifdef DEBUG_IOPORT
|
---|
| 1873 | { CPU_LOG_IOPORT, "ioport",
|
---|
| 1874 | "show all i/o ports accesses" },
|
---|
| 1875 | #endif
|
---|
| 1876 | { 0, NULL, NULL },
|
---|
| 1877 | };
|
---|
| 1878 |
|
---|
[37689] | 1879 | #ifndef CONFIG_USER_ONLY
|
---|
| 1880 | static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list
|
---|
| 1881 | = QLIST_HEAD_INITIALIZER(memory_client_list);
|
---|
| 1882 |
|
---|
| 1883 | static void cpu_notify_set_memory(target_phys_addr_t start_addr,
|
---|
| 1884 | ram_addr_t size,
|
---|
| 1885 | ram_addr_t phys_offset)
|
---|
| 1886 | {
|
---|
| 1887 | CPUPhysMemoryClient *client;
|
---|
| 1888 | QLIST_FOREACH(client, &memory_client_list, list) {
|
---|
| 1889 | client->set_memory(client, start_addr, size, phys_offset);
|
---|
| 1890 | }
|
---|
| 1891 | }
|
---|
| 1892 |
|
---|
| 1893 | static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start,
|
---|
| 1894 | target_phys_addr_t end)
|
---|
| 1895 | {
|
---|
| 1896 | CPUPhysMemoryClient *client;
|
---|
| 1897 | QLIST_FOREACH(client, &memory_client_list, list) {
|
---|
| 1898 | int r = client->sync_dirty_bitmap(client, start, end);
|
---|
| 1899 | if (r < 0)
|
---|
| 1900 | return r;
|
---|
| 1901 | }
|
---|
| 1902 | return 0;
|
---|
| 1903 | }
|
---|
| 1904 |
|
---|
| 1905 | static int cpu_notify_migration_log(int enable)
|
---|
| 1906 | {
|
---|
| 1907 | CPUPhysMemoryClient *client;
|
---|
| 1908 | QLIST_FOREACH(client, &memory_client_list, list) {
|
---|
| 1909 | int r = client->migration_log(client, enable);
|
---|
| 1910 | if (r < 0)
|
---|
| 1911 | return r;
|
---|
| 1912 | }
|
---|
| 1913 | return 0;
|
---|
| 1914 | }
|
---|
| 1915 |
|
---|
| 1916 | static void phys_page_for_each_1(CPUPhysMemoryClient *client,
|
---|
| 1917 | int level, void **lp)
|
---|
| 1918 | {
|
---|
| 1919 | int i;
|
---|
| 1920 |
|
---|
| 1921 | if (*lp == NULL) {
|
---|
| 1922 | return;
|
---|
| 1923 | }
|
---|
| 1924 | if (level == 0) {
|
---|
| 1925 | PhysPageDesc *pd = *lp;
|
---|
| 1926 | for (i = 0; i < L2_SIZE; ++i) {
|
---|
| 1927 | if (pd[i].phys_offset != IO_MEM_UNASSIGNED) {
|
---|
| 1928 | client->set_memory(client, pd[i].region_offset,
|
---|
| 1929 | TARGET_PAGE_SIZE, pd[i].phys_offset);
|
---|
| 1930 | }
|
---|
| 1931 | }
|
---|
| 1932 | } else {
|
---|
| 1933 | void **pp = *lp;
|
---|
| 1934 | for (i = 0; i < L2_SIZE; ++i) {
|
---|
| 1935 | phys_page_for_each_1(client, level - 1, pp + i);
|
---|
| 1936 | }
|
---|
| 1937 | }
|
---|
| 1938 | }
|
---|
| 1939 |
|
---|
| 1940 | static void phys_page_for_each(CPUPhysMemoryClient *client)
|
---|
| 1941 | {
|
---|
| 1942 | int i;
|
---|
| 1943 | for (i = 0; i < P_L1_SIZE; ++i) {
|
---|
| 1944 | phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1,
|
---|
| 1945 | l1_phys_map + 1);
|
---|
| 1946 | }
|
---|
| 1947 | }
|
---|
| 1948 |
|
---|
| 1949 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *client)
|
---|
| 1950 | {
|
---|
| 1951 | QLIST_INSERT_HEAD(&memory_client_list, client, list);
|
---|
| 1952 | phys_page_for_each(client);
|
---|
| 1953 | }
|
---|
| 1954 |
|
---|
| 1955 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client)
|
---|
| 1956 | {
|
---|
| 1957 | QLIST_REMOVE(client, list);
|
---|
| 1958 | }
|
---|
| 1959 | #endif
|
---|
| 1960 |
|
---|
[1] | 1961 | static int cmp1(const char *s1, int n, const char *s2)
|
---|
| 1962 | {
|
---|
| 1963 | if (strlen(s2) != n)
|
---|
| 1964 | return 0;
|
---|
| 1965 | return memcmp(s1, s2, n) == 0;
|
---|
| 1966 | }
|
---|
[6532] | 1967 |
|
---|
[1] | 1968 | /* takes a comma separated list of log masks. Return 0 if error. */
|
---|
| 1969 | int cpu_str_to_log_mask(const char *str)
|
---|
| 1970 | {
|
---|
[36140] | 1971 | const CPULogItem *item;
|
---|
[1] | 1972 | int mask;
|
---|
| 1973 | const char *p, *p1;
|
---|
| 1974 |
|
---|
| 1975 | p = str;
|
---|
| 1976 | mask = 0;
|
---|
| 1977 | for(;;) {
|
---|
| 1978 | p1 = strchr(p, ',');
|
---|
| 1979 | if (!p1)
|
---|
| 1980 | p1 = p + strlen(p);
|
---|
| 1981 | if(cmp1(p,p1-p,"all")) {
|
---|
| 1982 | for(item = cpu_log_items; item->mask != 0; item++) {
|
---|
| 1983 | mask |= item->mask;
|
---|
| 1984 | }
|
---|
| 1985 | } else {
|
---|
| 1986 | for(item = cpu_log_items; item->mask != 0; item++) {
|
---|
| 1987 | if (cmp1(p, p1 - p, item->name))
|
---|
| 1988 | goto found;
|
---|
| 1989 | }
|
---|
| 1990 | return 0;
|
---|
| 1991 | }
|
---|
| 1992 | found:
|
---|
| 1993 | mask |= item->mask;
|
---|
| 1994 | if (*p1 != ',')
|
---|
| 1995 | break;
|
---|
| 1996 | p = p1 + 1;
|
---|
| 1997 | }
|
---|
| 1998 | return mask;
|
---|
| 1999 | }
|
---|
| 2000 |
|
---|
| 2001 | void cpu_abort(CPUState *env, const char *fmt, ...)
|
---|
| 2002 | {
|
---|
| 2003 | va_list ap;
|
---|
[36140] | 2004 | va_list ap2;
|
---|
[1] | 2005 |
|
---|
| 2006 | va_start(ap, fmt);
|
---|
[36140] | 2007 | va_copy(ap2, ap);
|
---|
[1] | 2008 | fprintf(stderr, "qemu: fatal: ");
|
---|
| 2009 | vfprintf(stderr, fmt, ap);
|
---|
| 2010 | fprintf(stderr, "\n");
|
---|
| 2011 | #ifdef TARGET_I386
|
---|
| 2012 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
|
---|
| 2013 | #else
|
---|
| 2014 | cpu_dump_state(env, stderr, fprintf, 0);
|
---|
| 2015 | #endif
|
---|
[36170] | 2016 | if (qemu_log_enabled()) {
|
---|
| 2017 | qemu_log("qemu: fatal: ");
|
---|
| 2018 | qemu_log_vprintf(fmt, ap2);
|
---|
| 2019 | qemu_log("\n");
|
---|
[36140] | 2020 | #ifdef TARGET_I386
|
---|
[36170] | 2021 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
|
---|
[36140] | 2022 | #else
|
---|
[36170] | 2023 | log_cpu_state(env, 0);
|
---|
[36140] | 2024 | #endif
|
---|
[36170] | 2025 | qemu_log_flush();
|
---|
| 2026 | qemu_log_close();
|
---|
[36140] | 2027 | }
|
---|
| 2028 | va_end(ap2);
|
---|
[1] | 2029 | va_end(ap);
|
---|
[37689] | 2030 | #if defined(CONFIG_USER_ONLY)
|
---|
| 2031 | {
|
---|
| 2032 | struct sigaction act;
|
---|
| 2033 | sigfillset(&act.sa_mask);
|
---|
| 2034 | act.sa_handler = SIG_DFL;
|
---|
| 2035 | sigaction(SIGABRT, &act, NULL);
|
---|
| 2036 | }
|
---|
| 2037 | #endif
|
---|
[1] | 2038 | abort();
|
---|
| 2039 | }
|
---|
| 2040 |
|
---|
[13301] | 2041 | CPUState *cpu_copy(CPUState *env)
|
---|
| 2042 | {
|
---|
| 2043 | CPUState *new_env = cpu_init(env->cpu_model_str);
|
---|
| 2044 | CPUState *next_cpu = new_env->next_cpu;
|
---|
| 2045 | int cpu_index = new_env->cpu_index;
|
---|
[36170] | 2046 | #if defined(TARGET_HAS_ICE)
|
---|
| 2047 | CPUBreakpoint *bp;
|
---|
| 2048 | CPUWatchpoint *wp;
|
---|
| 2049 | #endif
|
---|
| 2050 |
|
---|
[13301] | 2051 | memcpy(new_env, env, sizeof(CPUState));
|
---|
[36170] | 2052 |
|
---|
| 2053 | /* Preserve chaining and index. */
|
---|
[13301] | 2054 | new_env->next_cpu = next_cpu;
|
---|
| 2055 | new_env->cpu_index = cpu_index;
|
---|
[36170] | 2056 |
|
---|
| 2057 | /* Clone all break/watchpoints.
|
---|
| 2058 | Note: Once we support ptrace with hw-debug register access, make sure
|
---|
| 2059 | BP_CPU break/watchpoints are handled correctly on clone. */
|
---|
[37675] | 2060 | QTAILQ_INIT(&env->breakpoints);
|
---|
| 2061 | QTAILQ_INIT(&env->watchpoints);
|
---|
[36170] | 2062 | #if defined(TARGET_HAS_ICE)
|
---|
[37675] | 2063 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
---|
[36170] | 2064 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
|
---|
| 2065 | }
|
---|
[37675] | 2066 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
|
---|
[36170] | 2067 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
|
---|
| 2068 | wp->flags, NULL);
|
---|
| 2069 | }
|
---|
| 2070 | #endif
|
---|
| 2071 |
|
---|
[13301] | 2072 | return new_env;
|
---|
| 2073 | }
|
---|
[37689] | 2074 |
|
---|
[36140] | 2075 | #endif /* !VBOX */
|
---|
[1] | 2076 | #if !defined(CONFIG_USER_ONLY)
|
---|
| 2077 |
|
---|
[13301] | 2078 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
|
---|
| 2079 | {
|
---|
| 2080 | unsigned int i;
|
---|
| 2081 |
|
---|
| 2082 | /* Discard jump cache entries for any tb which might potentially
|
---|
| 2083 | overlap the flushed page. */
|
---|
| 2084 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
|
---|
[15284] | 2085 | memset (&env->tb_jmp_cache[i], 0,
|
---|
[13301] | 2086 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
|
---|
| 2087 |
|
---|
| 2088 | i = tb_jmp_cache_hash_page(addr);
|
---|
[15284] | 2089 | memset (&env->tb_jmp_cache[i], 0,
|
---|
[13301] | 2090 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
|
---|
[37689] | 2091 | #ifdef VBOX
|
---|
[13301] | 2092 |
|
---|
| 2093 | /* inform raw mode about TLB page flush */
|
---|
| 2094 | remR3FlushPage(env, addr);
|
---|
| 2095 | #endif /* VBOX */
|
---|
| 2096 | }
|
---|
| 2097 |
|
---|
[35996] | 2098 | static CPUTLBEntry s_cputlb_empty_entry = {
|
---|
| 2099 | .addr_read = -1,
|
---|
| 2100 | .addr_write = -1,
|
---|
| 2101 | .addr_code = -1,
|
---|
| 2102 | .addend = -1,
|
---|
| 2103 | };
|
---|
| 2104 |
|
---|
[1] | 2105 | /* NOTE: if flush_global is true, also flush global entries (not
|
---|
| 2106 | implemented yet) */
|
---|
| 2107 | void tlb_flush(CPUState *env, int flush_global)
|
---|
| 2108 | {
|
---|
| 2109 | int i;
|
---|
[35996] | 2110 |
|
---|
[37702] | 2111 | #ifdef VBOX
|
---|
| 2112 | Assert(EMRemIsLockOwner(env->pVM));
|
---|
| 2113 | ASMAtomicAndS32((int32_t volatile *)&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_FLUSH_TLB);
|
---|
| 2114 | #endif
|
---|
| 2115 |
|
---|
[1] | 2116 | #if defined(DEBUG_TLB)
|
---|
| 2117 | printf("tlb_flush:\n");
|
---|
| 2118 | #endif
|
---|
| 2119 | /* must reset current TB so that interrupts cannot modify the
|
---|
| 2120 | links while we are modifying them */
|
---|
| 2121 | env->current_tb = NULL;
|
---|
| 2122 |
|
---|
| 2123 | for(i = 0; i < CPU_TLB_SIZE; i++) {
|
---|
[35996] | 2124 | int mmu_idx;
|
---|
| 2125 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
|
---|
| 2126 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry;
|
---|
| 2127 | }
|
---|
[1] | 2128 | }
|
---|
| 2129 |
|
---|
[2422] | 2130 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
|
---|
[1] | 2131 |
|
---|
[37689] | 2132 | env->tlb_flush_addr = -1;
|
---|
| 2133 | env->tlb_flush_mask = 0;
|
---|
| 2134 | tlb_flush_count++;
|
---|
[2422] | 2135 | #ifdef VBOX
|
---|
[37689] | 2136 |
|
---|
[1] | 2137 | /* inform raw mode about TLB flush */
|
---|
| 2138 | remR3FlushTLB(env, flush_global);
|
---|
[37689] | 2139 | #endif /* VBOX */
|
---|
[1] | 2140 | }
|
---|
| 2141 |
|
---|
| 2142 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
|
---|
| 2143 | {
|
---|
[6532] | 2144 | if (addr == (tlb_entry->addr_read &
|
---|
[2422] | 2145 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
|
---|
[6532] | 2146 | addr == (tlb_entry->addr_write &
|
---|
[2422] | 2147 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
|
---|
[6532] | 2148 | addr == (tlb_entry->addr_code &
|
---|
[2422] | 2149 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
|
---|
[36175] | 2150 | *tlb_entry = s_cputlb_empty_entry;
|
---|
[2422] | 2151 | }
|
---|
[1] | 2152 | }
|
---|
| 2153 |
|
---|
| 2154 | void tlb_flush_page(CPUState *env, target_ulong addr)
|
---|
| 2155 | {
|
---|
[2422] | 2156 | int i;
|
---|
[36175] | 2157 | int mmu_idx;
|
---|
[1] | 2158 |
|
---|
[37702] | 2159 | Assert(EMRemIsLockOwner(env->pVM));
|
---|
[1] | 2160 | #if defined(DEBUG_TLB)
|
---|
[2422] | 2161 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
|
---|
[1] | 2162 | #endif
|
---|
[37689] | 2163 | /* Check if we need to flush due to large pages. */
|
---|
| 2164 | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
|
---|
| 2165 | #if defined(DEBUG_TLB)
|
---|
| 2166 | printf("tlb_flush_page: forced full flush ("
|
---|
| 2167 | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
|
---|
| 2168 | env->tlb_flush_addr, env->tlb_flush_mask);
|
---|
| 2169 | #endif
|
---|
| 2170 | tlb_flush(env, 1);
|
---|
| 2171 | return;
|
---|
| 2172 | }
|
---|
[1] | 2173 | /* must reset current TB so that interrupts cannot modify the
|
---|
| 2174 | links while we are modifying them */
|
---|
| 2175 | env->current_tb = NULL;
|
---|
| 2176 |
|
---|
| 2177 | addr &= TARGET_PAGE_MASK;
|
---|
| 2178 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
---|
[36175] | 2179 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++)
|
---|
| 2180 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
|
---|
[15284] | 2181 |
|
---|
[13301] | 2182 | tlb_flush_jmp_cache(env, addr);
|
---|
[1] | 2183 | }
|
---|
| 2184 |
|
---|
| 2185 | /* update the TLBs so that writes to code in the virtual page 'addr'
|
---|
| 2186 | can be detected */
|
---|
[2422] | 2187 | static void tlb_protect_code(ram_addr_t ram_addr)
|
---|
[1] | 2188 | {
|
---|
[6532] | 2189 | cpu_physical_memory_reset_dirty(ram_addr,
|
---|
[2422] | 2190 | ram_addr + TARGET_PAGE_SIZE,
|
---|
| 2191 | CODE_DIRTY_FLAG);
|
---|
[1] | 2192 | #if defined(VBOX) && defined(REM_MONITOR_CODE_PAGES)
|
---|
[2422] | 2193 | /** @todo Retest this? This function has changed... */
|
---|
| 2194 | remR3ProtectCode(cpu_single_env, ram_addr);
|
---|
[37689] | 2195 | #endif /* VBOX */
|
---|
[1] | 2196 | }
|
---|
| 2197 |
|
---|
| 2198 | /* update the TLB so that writes in physical page 'phys_addr' are no longer
|
---|
[2422] | 2199 | tested for self modifying code */
|
---|
[6532] | 2200 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
|
---|
[2422] | 2201 | target_ulong vaddr)
|
---|
[1] | 2202 | {
|
---|
[37689] | 2203 | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG);
|
---|
[1] | 2204 | }
|
---|
| 2205 |
|
---|
[6532] | 2206 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
|
---|
[42601] | 2207 | uintptr_t start, uintptr_t length)
|
---|
[1] | 2208 | {
|
---|
[42601] | 2209 | uintptr_t addr;
|
---|
[37689] | 2210 | #ifdef VBOX
|
---|
[14974] | 2211 |
|
---|
[15284] | 2212 | if (start & 3)
|
---|
[14974] | 2213 | return;
|
---|
[37689] | 2214 | #endif /* VBOX */
|
---|
[2422] | 2215 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
|
---|
| 2216 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
|
---|
[1] | 2217 | if ((addr - start) < length) {
|
---|
[36140] | 2218 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
|
---|
[1] | 2219 | }
|
---|
| 2220 | }
|
---|
| 2221 | }
|
---|
| 2222 |
|
---|
[36175] | 2223 | /* Note: start and end must be within the same ram block. */
|
---|
[2422] | 2224 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
|
---|
| 2225 | int dirty_flags)
|
---|
[1] | 2226 | {
|
---|
| 2227 | CPUState *env;
|
---|
[42601] | 2228 | uintptr_t length, start1;
|
---|
[37689] | 2229 | int i;
|
---|
[1] | 2230 |
|
---|
| 2231 | start &= TARGET_PAGE_MASK;
|
---|
| 2232 | end = TARGET_PAGE_ALIGN(end);
|
---|
| 2233 |
|
---|
| 2234 | length = end - start;
|
---|
| 2235 | if (length == 0)
|
---|
| 2236 | return;
|
---|
[37689] | 2237 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags);
|
---|
[1] | 2238 |
|
---|
| 2239 | /* we modify the TLB cache so that the dirty bit will be set again
|
---|
| 2240 | when accessing the range */
|
---|
[2422] | 2241 | #if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
|
---|
| 2242 | start1 = start;
|
---|
[6532] | 2243 | #elif !defined(VBOX)
|
---|
[42601] | 2244 | start1 = (uintptr_t)qemu_get_ram_ptr(start);
|
---|
[36175] | 2245 | /* Chek that we don't span multiple blocks - this breaks the
|
---|
| 2246 | address comparisons below. */
|
---|
[42601] | 2247 | if ((uintptr_t)qemu_get_ram_ptr(end - 1) - start1
|
---|
[36175] | 2248 | != (end - 1) - start) {
|
---|
| 2249 | abort();
|
---|
| 2250 | }
|
---|
[1] | 2251 | #else
|
---|
[42601] | 2252 | start1 = (uintptr_t)remR3TlbGCPhys2Ptr(first_cpu, start, 1 /*fWritable*/); /** @todo page replacing (sharing or read only) may cause trouble, fix interface/whatever. */
|
---|
[1] | 2253 | #endif
|
---|
[36175] | 2254 |
|
---|
[2422] | 2255 | for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
---|
[36175] | 2256 | int mmu_idx;
|
---|
| 2257 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
|
---|
| 2258 | for(i = 0; i < CPU_TLB_SIZE; i++)
|
---|
| 2259 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
|
---|
| 2260 | start1, length);
|
---|
| 2261 | }
|
---|
[2422] | 2262 | }
|
---|
[13301] | 2263 | }
|
---|
[1] | 2264 |
|
---|
[13337] | 2265 | #ifndef VBOX
|
---|
[37689] | 2266 |
|
---|
[13301] | 2267 | int cpu_physical_memory_set_dirty_tracking(int enable)
|
---|
| 2268 | {
|
---|
[37689] | 2269 | int ret = 0;
|
---|
[13301] | 2270 | in_migration = enable;
|
---|
[37689] | 2271 | ret = cpu_notify_migration_log(!!enable);
|
---|
| 2272 | return ret;
|
---|
[13301] | 2273 | }
|
---|
[1] | 2274 |
|
---|
[13301] | 2275 | int cpu_physical_memory_get_dirty_tracking(void)
|
---|
| 2276 | {
|
---|
| 2277 | return in_migration;
|
---|
[1] | 2278 | }
|
---|
[37689] | 2279 |
|
---|
[36170] | 2280 | #endif /* !VBOX */
|
---|
[1] | 2281 |
|
---|
[36175] | 2282 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
|
---|
| 2283 | target_phys_addr_t end_addr)
|
---|
[36170] | 2284 | {
|
---|
[36211] | 2285 | #ifndef VBOX
|
---|
[37689] | 2286 | int ret;
|
---|
[36175] | 2287 |
|
---|
[37689] | 2288 | ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr);
|
---|
[36175] | 2289 | return ret;
|
---|
[37689] | 2290 | #else /* VBOX */
|
---|
[36211] | 2291 | return 0;
|
---|
[37689] | 2292 | #endif /* VBOX */
|
---|
[36170] | 2293 | }
|
---|
| 2294 |
|
---|
[17274] | 2295 | #if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
| 2296 | DECLINLINE(void) tlb_update_dirty(CPUTLBEntry *tlb_entry, target_phys_addr_t phys_addend)
|
---|
| 2297 | #else
|
---|
[2422] | 2298 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
|
---|
[13382] | 2299 | #endif
|
---|
[2422] | 2300 | {
|
---|
| 2301 | ram_addr_t ram_addr;
|
---|
[42601] | 2302 | #ifndef VBOX
|
---|
[36175] | 2303 | void *p;
|
---|
[42601] | 2304 | #endif
|
---|
[2422] | 2305 |
|
---|
| 2306 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
|
---|
| 2307 | #if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
|
---|
| 2308 | ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
|
---|
[6532] | 2309 | #elif !defined(VBOX)
|
---|
[42601] | 2310 | p = (void *)(uintptr_t)((tlb_entry->addr_write & TARGET_PAGE_MASK)
|
---|
[36175] | 2311 | + tlb_entry->addend);
|
---|
| 2312 | ram_addr = qemu_ram_addr_from_host(p);
|
---|
[2422] | 2313 | #else
|
---|
[17274] | 2314 | Assert(phys_addend != -1);
|
---|
| 2315 | ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + phys_addend;
|
---|
[2422] | 2316 | #endif
|
---|
| 2317 | if (!cpu_physical_memory_is_dirty(ram_addr)) {
|
---|
[13559] | 2318 | tlb_entry->addr_write |= TLB_NOTDIRTY;
|
---|
[2422] | 2319 | }
|
---|
| 2320 | }
|
---|
| 2321 | }
|
---|
| 2322 |
|
---|
| 2323 | /* update the TLB according to the current state of the dirty bits */
|
---|
| 2324 | void cpu_tlb_update_dirty(CPUState *env)
|
---|
| 2325 | {
|
---|
| 2326 | int i;
|
---|
[36175] | 2327 | int mmu_idx;
|
---|
| 2328 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
|
---|
| 2329 | for(i = 0; i < CPU_TLB_SIZE; i++)
|
---|
[17274] | 2330 | #if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[36175] | 2331 | tlb_update_dirty(&env->tlb_table[mmu_idx][i], env->phys_addends[mmu_idx][i]);
|
---|
| 2332 | #else
|
---|
| 2333 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]);
|
---|
[13301] | 2334 | #endif
|
---|
[36175] | 2335 | }
|
---|
[2422] | 2336 | }
|
---|
| 2337 |
|
---|
[13301] | 2338 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
|
---|
[1] | 2339 | {
|
---|
[13301] | 2340 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
|
---|
| 2341 | tlb_entry->addr_write = vaddr;
|
---|
[1] | 2342 | }
|
---|
| 2343 |
|
---|
[36140] | 2344 | /* update the TLB corresponding to virtual page vaddr
|
---|
| 2345 | so that it is no longer dirty */
|
---|
| 2346 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
|
---|
[1] | 2347 | {
|
---|
| 2348 | int i;
|
---|
[36175] | 2349 | int mmu_idx;
|
---|
[1] | 2350 |
|
---|
[36140] | 2351 | vaddr &= TARGET_PAGE_MASK;
|
---|
[1] | 2352 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
---|
[36175] | 2353 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++)
|
---|
| 2354 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
|
---|
[1] | 2355 | }
|
---|
| 2356 |
|
---|
[37689] | 2357 | /* Our TLB does not support large pages, so remember the area covered by
|
---|
| 2358 | large pages and trigger a full TLB flush if these are invalidated. */
|
---|
| 2359 | static void tlb_add_large_page(CPUState *env, target_ulong vaddr,
|
---|
| 2360 | target_ulong size)
|
---|
[1] | 2361 | {
|
---|
[37689] | 2362 | target_ulong mask = ~(size - 1);
|
---|
| 2363 |
|
---|
| 2364 | if (env->tlb_flush_addr == (target_ulong)-1) {
|
---|
| 2365 | env->tlb_flush_addr = vaddr & mask;
|
---|
| 2366 | env->tlb_flush_mask = mask;
|
---|
| 2367 | return;
|
---|
| 2368 | }
|
---|
| 2369 | /* Extend the existing region to include the new page.
|
---|
| 2370 | This is a compromise between unnecessary flushes and the cost
|
---|
| 2371 | of maintaining a full variable size TLB. */
|
---|
| 2372 | mask &= env->tlb_flush_mask;
|
---|
| 2373 | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
|
---|
| 2374 | mask <<= 1;
|
---|
| 2375 | }
|
---|
| 2376 | env->tlb_flush_addr &= mask;
|
---|
| 2377 | env->tlb_flush_mask = mask;
|
---|
| 2378 | }
|
---|
| 2379 |
|
---|
| 2380 | /* Add a new TLB entry. At most one entry for a given virtual address
|
---|
| 2381 | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
|
---|
| 2382 | supplied size is only used by tlb_flush_page. */
|
---|
| 2383 | void tlb_set_page(CPUState *env, target_ulong vaddr,
|
---|
| 2384 | target_phys_addr_t paddr, int prot,
|
---|
| 2385 | int mmu_idx, target_ulong size)
|
---|
| 2386 | {
|
---|
[1] | 2387 | PhysPageDesc *p;
|
---|
[42601] | 2388 | ram_addr_t pd;
|
---|
[1] | 2389 | unsigned int index;
|
---|
| 2390 | target_ulong address;
|
---|
[13337] | 2391 | target_ulong code_address;
|
---|
[42601] | 2392 | uintptr_t addend;
|
---|
[2422] | 2393 | CPUTLBEntry *te;
|
---|
[36170] | 2394 | CPUWatchpoint *wp;
|
---|
[13337] | 2395 | target_phys_addr_t iotlb;
|
---|
[15761] | 2396 | #if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
| 2397 | int read_mods = 0, write_mods = 0, code_mods = 0;
|
---|
| 2398 | #endif
|
---|
[1] | 2399 |
|
---|
[37689] | 2400 | assert(size >= TARGET_PAGE_SIZE);
|
---|
| 2401 | if (size != TARGET_PAGE_SIZE) {
|
---|
| 2402 | tlb_add_large_page(env, vaddr, size);
|
---|
| 2403 | }
|
---|
[1] | 2404 | p = phys_page_find(paddr >> TARGET_PAGE_BITS);
|
---|
| 2405 | if (!p) {
|
---|
| 2406 | pd = IO_MEM_UNASSIGNED;
|
---|
| 2407 | } else {
|
---|
| 2408 | pd = p->phys_offset;
|
---|
| 2409 | }
|
---|
| 2410 | #if defined(DEBUG_TLB)
|
---|
[37696] | 2411 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d size=" TARGET_FMT_lx " pd=0x%08lx\n",
|
---|
[42601] | 2412 | vaddr, (int)paddr, prot, mmu_idx, size, (long)pd);
|
---|
[1] | 2413 | #endif
|
---|
| 2414 |
|
---|
[13337] | 2415 | address = vaddr;
|
---|
| 2416 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
---|
| 2417 | /* IO memory case (romd handled later) */
|
---|
| 2418 | address |= TLB_MMIO;
|
---|
| 2419 | }
|
---|
[2422] | 2420 | #if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[13337] | 2421 | addend = pd & TARGET_PAGE_MASK;
|
---|
[6532] | 2422 | #elif !defined(VBOX)
|
---|
[42601] | 2423 | addend = (uintptr_t)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK);
|
---|
[2422] | 2424 | #else
|
---|
[15284] | 2425 | /** @todo this is racing the phys_page_find call above since it may register
|
---|
| 2426 | * a new chunk of memory... */
|
---|
[42601] | 2427 | addend = (uintptr_t)remR3TlbGCPhys2Ptr(env, pd & TARGET_PAGE_MASK, !!(prot & PAGE_WRITE));
|
---|
[6532] | 2428 | #endif
|
---|
[15761] | 2429 |
|
---|
[13337] | 2430 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
|
---|
| 2431 | /* Normal RAM. */
|
---|
| 2432 | iotlb = pd & TARGET_PAGE_MASK;
|
---|
| 2433 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
|
---|
| 2434 | iotlb |= IO_MEM_NOTDIRTY;
|
---|
| 2435 | else
|
---|
| 2436 | iotlb |= IO_MEM_ROM;
|
---|
| 2437 | } else {
|
---|
[36175] | 2438 | /* IO handlers are currently passed a physical address.
|
---|
[13337] | 2439 | It would be nice to pass an offset from the base address
|
---|
| 2440 | of that region. This would avoid having to special case RAM,
|
---|
| 2441 | and avoid full address decoding in every device.
|
---|
| 2442 | We can't use the high bits of pd for this because
|
---|
| 2443 | IO_MEM_ROMD uses these as a ram address. */
|
---|
[36170] | 2444 | iotlb = (pd & ~TARGET_PAGE_MASK);
|
---|
| 2445 | if (p) {
|
---|
| 2446 | iotlb += p->region_offset;
|
---|
| 2447 | } else {
|
---|
| 2448 | iotlb += paddr;
|
---|
| 2449 | }
|
---|
[13337] | 2450 | }
|
---|
[6532] | 2451 |
|
---|
[13337] | 2452 | code_address = address;
|
---|
[36175] | 2453 | #if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[14974] | 2454 |
|
---|
[15761] | 2455 | if (addend & 0x3)
|
---|
[14974] | 2456 | {
|
---|
[15761] | 2457 | if (addend & 0x2)
|
---|
[14974] | 2458 | {
|
---|
[15761] | 2459 | /* catch write */
|
---|
| 2460 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM)
|
---|
| 2461 | write_mods |= TLB_MMIO;
|
---|
[14974] | 2462 | }
|
---|
[15761] | 2463 | else if (addend & 0x1)
|
---|
[15284] | 2464 | {
|
---|
[15761] | 2465 | /* catch all */
|
---|
| 2466 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM)
|
---|
| 2467 | {
|
---|
| 2468 | read_mods |= TLB_MMIO;
|
---|
| 2469 | write_mods |= TLB_MMIO;
|
---|
| 2470 | code_mods |= TLB_MMIO;
|
---|
| 2471 | }
|
---|
[15284] | 2472 | }
|
---|
[15761] | 2473 | if ((iotlb & ~TARGET_PAGE_MASK) == 0)
|
---|
| 2474 | iotlb = env->pVM->rem.s.iHandlerMemType + paddr;
|
---|
| 2475 | addend &= ~(target_ulong)0x3;
|
---|
[15284] | 2476 | }
|
---|
[36175] | 2477 |
|
---|
[14974] | 2478 | #endif
|
---|
[13337] | 2479 | /* Make accesses to pages with watchpoints go via the
|
---|
| 2480 | watchpoint trap routines. */
|
---|
[37675] | 2481 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
|
---|
[36170] | 2482 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
|
---|
[37689] | 2483 | /* Avoid trapping reads of pages with a write breakpoint. */
|
---|
| 2484 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
|
---|
| 2485 | iotlb = io_mem_watch + paddr;
|
---|
| 2486 | address |= TLB_MMIO;
|
---|
| 2487 | break;
|
---|
| 2488 | }
|
---|
[1] | 2489 | }
|
---|
| 2490 | }
|
---|
| 2491 |
|
---|
[13337] | 2492 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
---|
| 2493 | env->iotlb[mmu_idx][index] = iotlb - vaddr;
|
---|
| 2494 | te = &env->tlb_table[mmu_idx][index];
|
---|
| 2495 | te->addend = addend - vaddr;
|
---|
| 2496 | if (prot & PAGE_READ) {
|
---|
| 2497 | te->addr_read = address;
|
---|
| 2498 | } else {
|
---|
| 2499 | te->addr_read = -1;
|
---|
| 2500 | }
|
---|
[6532] | 2501 |
|
---|
[13337] | 2502 | if (prot & PAGE_EXEC) {
|
---|
| 2503 | te->addr_code = code_address;
|
---|
| 2504 | } else {
|
---|
| 2505 | te->addr_code = -1;
|
---|
| 2506 | }
|
---|
| 2507 | if (prot & PAGE_WRITE) {
|
---|
| 2508 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
|
---|
| 2509 | (pd & IO_MEM_ROMD)) {
|
---|
| 2510 | /* Write access calls the I/O callback. */
|
---|
| 2511 | te->addr_write = address | TLB_MMIO;
|
---|
| 2512 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
|
---|
| 2513 | !cpu_physical_memory_is_dirty(pd)) {
|
---|
| 2514 | te->addr_write = address | TLB_NOTDIRTY;
|
---|
| 2515 | } else {
|
---|
| 2516 | te->addr_write = address;
|
---|
[1] | 2517 | }
|
---|
[13337] | 2518 | } else {
|
---|
| 2519 | te->addr_write = -1;
|
---|
[1] | 2520 | }
|
---|
[15761] | 2521 |
|
---|
| 2522 | #if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
| 2523 | if (prot & PAGE_READ)
|
---|
| 2524 | te->addr_read |= read_mods;
|
---|
| 2525 | if (prot & PAGE_EXEC)
|
---|
| 2526 | te->addr_code |= code_mods;
|
---|
| 2527 | if (prot & PAGE_WRITE)
|
---|
| 2528 | te->addr_write |= write_mods;
|
---|
[17274] | 2529 |
|
---|
| 2530 | env->phys_addends[mmu_idx][index] = (pd & TARGET_PAGE_MASK)- vaddr;
|
---|
[15761] | 2531 | #endif
|
---|
| 2532 |
|
---|
[13337] | 2533 | #ifdef VBOX
|
---|
| 2534 | /* inform raw mode about TLB page change */
|
---|
| 2535 | remR3FlushPage(env, vaddr);
|
---|
[1] | 2536 | #endif
|
---|
| 2537 | }
|
---|
| 2538 |
|
---|
| 2539 | #else
|
---|
| 2540 |
|
---|
| 2541 | void tlb_flush(CPUState *env, int flush_global)
|
---|
| 2542 | {
|
---|
| 2543 | }
|
---|
| 2544 |
|
---|
| 2545 | void tlb_flush_page(CPUState *env, target_ulong addr)
|
---|
| 2546 | {
|
---|
| 2547 | }
|
---|
| 2548 |
|
---|
[36175] | 2549 | /*
|
---|
| 2550 | * Walks guest process memory "regions" one by one
|
---|
| 2551 | * and calls callback function 'fn' for each region.
|
---|
| 2552 | */
|
---|
[37689] | 2553 |
|
---|
| 2554 | struct walk_memory_regions_data
|
---|
[1] | 2555 | {
|
---|
[37689] | 2556 | walk_memory_regions_fn fn;
|
---|
| 2557 | void *priv;
|
---|
[42601] | 2558 | uintptr_t start;
|
---|
[37689] | 2559 | int prot;
|
---|
| 2560 | };
|
---|
[1] | 2561 |
|
---|
[37689] | 2562 | static int walk_memory_regions_end(struct walk_memory_regions_data *data,
|
---|
| 2563 | abi_ulong end, int new_prot)
|
---|
| 2564 | {
|
---|
| 2565 | if (data->start != -1ul) {
|
---|
| 2566 | int rc = data->fn(data->priv, data->start, end, data->prot);
|
---|
| 2567 | if (rc != 0) {
|
---|
| 2568 | return rc;
|
---|
| 2569 | }
|
---|
| 2570 | }
|
---|
[36175] | 2571 |
|
---|
[37689] | 2572 | data->start = (new_prot ? end : -1ul);
|
---|
| 2573 | data->prot = new_prot;
|
---|
| 2574 |
|
---|
| 2575 | return 0;
|
---|
| 2576 | }
|
---|
| 2577 |
|
---|
| 2578 | static int walk_memory_regions_1(struct walk_memory_regions_data *data,
|
---|
| 2579 | abi_ulong base, int level, void **lp)
|
---|
| 2580 | {
|
---|
| 2581 | abi_ulong pa;
|
---|
| 2582 | int i, rc;
|
---|
| 2583 |
|
---|
| 2584 | if (*lp == NULL) {
|
---|
| 2585 | return walk_memory_regions_end(data, base, 0);
|
---|
| 2586 | }
|
---|
| 2587 |
|
---|
| 2588 | if (level == 0) {
|
---|
| 2589 | PageDesc *pd = *lp;
|
---|
| 2590 | for (i = 0; i < L2_SIZE; ++i) {
|
---|
| 2591 | int prot = pd[i].flags;
|
---|
| 2592 |
|
---|
| 2593 | pa = base | (i << TARGET_PAGE_BITS);
|
---|
| 2594 | if (prot != data->prot) {
|
---|
| 2595 | rc = walk_memory_regions_end(data, pa, prot);
|
---|
| 2596 | if (rc != 0) {
|
---|
| 2597 | return rc;
|
---|
[1] | 2598 | }
|
---|
| 2599 | }
|
---|
| 2600 | }
|
---|
[37689] | 2601 | } else {
|
---|
| 2602 | void **pp = *lp;
|
---|
| 2603 | for (i = 0; i < L2_SIZE; ++i) {
|
---|
| 2604 | pa = base | ((abi_ulong)i <<
|
---|
| 2605 | (TARGET_PAGE_BITS + L2_BITS * level));
|
---|
| 2606 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i);
|
---|
| 2607 | if (rc != 0) {
|
---|
| 2608 | return rc;
|
---|
| 2609 | }
|
---|
| 2610 | }
|
---|
[1] | 2611 | }
|
---|
[37689] | 2612 |
|
---|
| 2613 | return 0;
|
---|
[1] | 2614 | }
|
---|
[36175] | 2615 |
|
---|
[37689] | 2616 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn)
|
---|
[36175] | 2617 | {
|
---|
[37689] | 2618 | struct walk_memory_regions_data data;
|
---|
[42601] | 2619 | target_ulong i;
|
---|
[37689] | 2620 |
|
---|
| 2621 | data.fn = fn;
|
---|
| 2622 | data.priv = priv;
|
---|
| 2623 | data.start = -1ul;
|
---|
| 2624 | data.prot = 0;
|
---|
| 2625 |
|
---|
| 2626 | for (i = 0; i < V_L1_SIZE; i++) {
|
---|
| 2627 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT,
|
---|
| 2628 | V_L1_SHIFT / L2_BITS - 1, l1_map + i);
|
---|
| 2629 | if (rc != 0) {
|
---|
| 2630 | return rc;
|
---|
| 2631 | }
|
---|
| 2632 | }
|
---|
| 2633 |
|
---|
| 2634 | return walk_memory_regions_end(&data, 0, 0);
|
---|
| 2635 | }
|
---|
| 2636 |
|
---|
| 2637 | static int dump_region(void *priv, abi_ulong start,
|
---|
| 2638 | abi_ulong end, unsigned long prot)
|
---|
| 2639 | {
|
---|
[36175] | 2640 | FILE *f = (FILE *)priv;
|
---|
| 2641 |
|
---|
[37689] | 2642 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx
|
---|
| 2643 | " "TARGET_ABI_FMT_lx" %c%c%c\n",
|
---|
[36175] | 2644 | start, end, end - start,
|
---|
| 2645 | ((prot & PAGE_READ) ? 'r' : '-'),
|
---|
| 2646 | ((prot & PAGE_WRITE) ? 'w' : '-'),
|
---|
| 2647 | ((prot & PAGE_EXEC) ? 'x' : '-'));
|
---|
| 2648 |
|
---|
| 2649 | return (0);
|
---|
| 2650 | }
|
---|
| 2651 |
|
---|
| 2652 | /* dump memory mappings */
|
---|
| 2653 | void page_dump(FILE *f)
|
---|
| 2654 | {
|
---|
| 2655 | (void) fprintf(f, "%-8s %-8s %-8s %s\n",
|
---|
| 2656 | "start", "end", "size", "prot");
|
---|
| 2657 | walk_memory_regions(f, dump_region);
|
---|
| 2658 | }
|
---|
| 2659 |
|
---|
[2422] | 2660 | int page_get_flags(target_ulong address)
|
---|
[1] | 2661 | {
|
---|
| 2662 | PageDesc *p;
|
---|
| 2663 |
|
---|
| 2664 | p = page_find(address >> TARGET_PAGE_BITS);
|
---|
| 2665 | if (!p)
|
---|
| 2666 | return 0;
|
---|
| 2667 | return p->flags;
|
---|
| 2668 | }
|
---|
| 2669 |
|
---|
[37689] | 2670 | /* Modify the flags of a page and invalidate the code if necessary.
|
---|
| 2671 | The flag PAGE_WRITE_ORG is positioned automatically depending
|
---|
| 2672 | on PAGE_WRITE. The mmap_lock should already be held. */
|
---|
[2422] | 2673 | void page_set_flags(target_ulong start, target_ulong end, int flags)
|
---|
[1] | 2674 | {
|
---|
[37689] | 2675 | target_ulong addr, len;
|
---|
[1] | 2676 |
|
---|
[37689] | 2677 | /* This function should never be called with addresses outside the
|
---|
| 2678 | guest address space. If this assert fires, it probably indicates
|
---|
| 2679 | a missing call to h2g_valid. */
|
---|
| 2680 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
|
---|
| 2681 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS));
|
---|
| 2682 | #endif
|
---|
| 2683 | assert(start < end);
|
---|
| 2684 |
|
---|
[1] | 2685 | start = start & TARGET_PAGE_MASK;
|
---|
| 2686 | end = TARGET_PAGE_ALIGN(end);
|
---|
[37689] | 2687 |
|
---|
| 2688 | if (flags & PAGE_WRITE) {
|
---|
[1] | 2689 | flags |= PAGE_WRITE_ORG;
|
---|
[37689] | 2690 | }
|
---|
| 2691 |
|
---|
[2422] | 2692 | #ifdef VBOX
|
---|
[1] | 2693 | AssertMsgFailed(("We shouldn't be here, and if we should, we must have an env to do the proper locking!\n"));
|
---|
| 2694 | #endif
|
---|
[37689] | 2695 | for (addr = start, len = end - start;
|
---|
| 2696 | len != 0;
|
---|
| 2697 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
|
---|
| 2698 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
|
---|
| 2699 |
|
---|
| 2700 | /* If the write protection bit is set, then we invalidate
|
---|
| 2701 | the code inside. */
|
---|
[6532] | 2702 | if (!(p->flags & PAGE_WRITE) &&
|
---|
[1] | 2703 | (flags & PAGE_WRITE) &&
|
---|
| 2704 | p->first_tb) {
|
---|
| 2705 | tb_invalidate_phys_page(addr, 0, NULL);
|
---|
| 2706 | }
|
---|
| 2707 | p->flags = flags;
|
---|
| 2708 | }
|
---|
| 2709 | }
|
---|
| 2710 |
|
---|
[13559] | 2711 | int page_check_range(target_ulong start, target_ulong len, int flags)
|
---|
| 2712 | {
|
---|
| 2713 | PageDesc *p;
|
---|
| 2714 | target_ulong end;
|
---|
| 2715 | target_ulong addr;
|
---|
| 2716 |
|
---|
[37689] | 2717 | /* This function should never be called with addresses outside the
|
---|
| 2718 | guest address space. If this assert fires, it probably indicates
|
---|
| 2719 | a missing call to h2g_valid. */
|
---|
| 2720 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
|
---|
| 2721 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS));
|
---|
| 2722 | #endif
|
---|
| 2723 |
|
---|
| 2724 | if (len == 0) {
|
---|
| 2725 | return 0;
|
---|
| 2726 | }
|
---|
| 2727 | if (start + len - 1 < start) {
|
---|
| 2728 | /* We've wrapped around. */
|
---|
[36170] | 2729 | return -1;
|
---|
[37689] | 2730 | }
|
---|
[36170] | 2731 |
|
---|
[13559] | 2732 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
|
---|
| 2733 | start = start & TARGET_PAGE_MASK;
|
---|
| 2734 |
|
---|
[37689] | 2735 | for (addr = start, len = end - start;
|
---|
| 2736 | len != 0;
|
---|
| 2737 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
|
---|
[13559] | 2738 | p = page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 2739 | if( !p )
|
---|
| 2740 | return -1;
|
---|
| 2741 | if( !(p->flags & PAGE_VALID) )
|
---|
| 2742 | return -1;
|
---|
| 2743 |
|
---|
| 2744 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
|
---|
| 2745 | return -1;
|
---|
| 2746 | if (flags & PAGE_WRITE) {
|
---|
| 2747 | if (!(p->flags & PAGE_WRITE_ORG))
|
---|
| 2748 | return -1;
|
---|
| 2749 | /* unprotect the page if it was put read-only because it
|
---|
| 2750 | contains translated code */
|
---|
| 2751 | if (!(p->flags & PAGE_WRITE)) {
|
---|
| 2752 | if (!page_unprotect(addr, 0, NULL))
|
---|
| 2753 | return -1;
|
---|
| 2754 | }
|
---|
| 2755 | return 0;
|
---|
| 2756 | }
|
---|
| 2757 | }
|
---|
| 2758 | return 0;
|
---|
| 2759 | }
|
---|
| 2760 |
|
---|
[1] | 2761 | /* called from signal handler: invalidate the code and unprotect the
|
---|
[36175] | 2762 | page. Return TRUE if the fault was successfully handled. */
|
---|
[42601] | 2763 | int page_unprotect(target_ulong address, uintptr_t pc, void *puc)
|
---|
[1] | 2764 | {
|
---|
[37689] | 2765 | unsigned int prot;
|
---|
| 2766 | PageDesc *p;
|
---|
[2422] | 2767 | target_ulong host_start, host_end, addr;
|
---|
[1] | 2768 |
|
---|
[13559] | 2769 | /* Technically this isn't safe inside a signal handler. However we
|
---|
| 2770 | know this only ever happens in a synchronous SEGV handler, so in
|
---|
| 2771 | practice it seems to be ok. */
|
---|
| 2772 | mmap_lock();
|
---|
| 2773 |
|
---|
[37689] | 2774 | p = page_find(address >> TARGET_PAGE_BITS);
|
---|
| 2775 | if (!p) {
|
---|
[13559] | 2776 | mmap_unlock();
|
---|
[1] | 2777 | return 0;
|
---|
[13559] | 2778 | }
|
---|
[37689] | 2779 |
|
---|
[1] | 2780 | /* if the page was really writable, then we change its
|
---|
| 2781 | protection back to writable */
|
---|
[37689] | 2782 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) {
|
---|
| 2783 | host_start = address & qemu_host_page_mask;
|
---|
| 2784 | host_end = host_start + qemu_host_page_size;
|
---|
| 2785 |
|
---|
| 2786 | prot = 0;
|
---|
| 2787 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) {
|
---|
| 2788 | p = page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 2789 | p->flags |= PAGE_WRITE;
|
---|
| 2790 | prot |= p->flags;
|
---|
| 2791 |
|
---|
[1] | 2792 | /* and since the content will be modified, we must invalidate
|
---|
| 2793 | the corresponding translated code. */
|
---|
[37689] | 2794 | tb_invalidate_phys_page(addr, pc, puc);
|
---|
[1] | 2795 | #ifdef DEBUG_TB_CHECK
|
---|
[37689] | 2796 | tb_invalidate_check(addr);
|
---|
[1] | 2797 | #endif
|
---|
| 2798 | }
|
---|
[37689] | 2799 | mprotect((void *)g2h(host_start), qemu_host_page_size,
|
---|
| 2800 | prot & PAGE_BITS);
|
---|
| 2801 |
|
---|
| 2802 | mmap_unlock();
|
---|
| 2803 | return 1;
|
---|
[1] | 2804 | }
|
---|
[13559] | 2805 | mmap_unlock();
|
---|
[1] | 2806 | return 0;
|
---|
| 2807 | }
|
---|
| 2808 |
|
---|
[2422] | 2809 | static inline void tlb_set_dirty(CPUState *env,
|
---|
[42601] | 2810 | uintptr_t addr, target_ulong vaddr)
|
---|
[1] | 2811 | {
|
---|
| 2812 | }
|
---|
| 2813 | #endif /* defined(CONFIG_USER_ONLY) */
|
---|
| 2814 |
|
---|
[13559] | 2815 | #if !defined(CONFIG_USER_ONLY)
|
---|
[36170] | 2816 |
|
---|
[37689] | 2817 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
|
---|
| 2818 | typedef struct subpage_t {
|
---|
| 2819 | target_phys_addr_t base;
|
---|
| 2820 | ram_addr_t sub_io_index[TARGET_PAGE_SIZE];
|
---|
| 2821 | ram_addr_t region_offset[TARGET_PAGE_SIZE];
|
---|
| 2822 | } subpage_t;
|
---|
| 2823 |
|
---|
[13559] | 2824 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
|
---|
[36170] | 2825 | ram_addr_t memory, ram_addr_t region_offset);
|
---|
[37689] | 2826 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
|
---|
| 2827 | ram_addr_t orig_memory,
|
---|
| 2828 | ram_addr_t region_offset);
|
---|
[13559] | 2829 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
|
---|
| 2830 | need_subpage) \
|
---|
| 2831 | do { \
|
---|
| 2832 | if (addr > start_addr) \
|
---|
| 2833 | start_addr2 = 0; \
|
---|
| 2834 | else { \
|
---|
| 2835 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
|
---|
| 2836 | if (start_addr2 > 0) \
|
---|
| 2837 | need_subpage = 1; \
|
---|
| 2838 | } \
|
---|
| 2839 | \
|
---|
| 2840 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
|
---|
| 2841 | end_addr2 = TARGET_PAGE_SIZE - 1; \
|
---|
| 2842 | else { \
|
---|
| 2843 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
|
---|
| 2844 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \
|
---|
| 2845 | need_subpage = 1; \
|
---|
| 2846 | } \
|
---|
| 2847 | } while (0)
|
---|
| 2848 |
|
---|
[37675] | 2849 | /* register physical memory.
|
---|
| 2850 | For RAM, 'size' must be a multiple of the target page size.
|
---|
| 2851 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
|
---|
[36170] | 2852 | io memory page. The address used when calling the IO function is
|
---|
| 2853 | the offset from the start of the region, plus region_offset. Both
|
---|
[36175] | 2854 | start_addr and region_offset are rounded down to a page boundary
|
---|
[36170] | 2855 | before calculating this offset. This should not be a problem unless
|
---|
| 2856 | the low bits of start_addr and region_offset differ. */
|
---|
| 2857 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
|
---|
| 2858 | ram_addr_t size,
|
---|
| 2859 | ram_addr_t phys_offset,
|
---|
| 2860 | ram_addr_t region_offset)
|
---|
[1] | 2861 | {
|
---|
[2422] | 2862 | target_phys_addr_t addr, end_addr;
|
---|
[1] | 2863 | PhysPageDesc *p;
|
---|
[2422] | 2864 | CPUState *env;
|
---|
[13559] | 2865 | ram_addr_t orig_size = size;
|
---|
[37689] | 2866 | subpage_t *subpage;
|
---|
[1] | 2867 |
|
---|
[37689] | 2868 | #ifndef VBOX
|
---|
| 2869 | cpu_notify_set_memory(start_addr, size, phys_offset);
|
---|
| 2870 | #endif /* !VBOX */
|
---|
[36170] | 2871 |
|
---|
| 2872 | if (phys_offset == IO_MEM_UNASSIGNED) {
|
---|
| 2873 | region_offset = start_addr;
|
---|
| 2874 | }
|
---|
| 2875 | region_offset &= TARGET_PAGE_MASK;
|
---|
[1] | 2876 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
---|
[13559] | 2877 | end_addr = start_addr + (target_phys_addr_t)size;
|
---|
[1] | 2878 | for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
|
---|
[13559] | 2879 | p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 2880 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
|
---|
| 2881 | ram_addr_t orig_memory = p->phys_offset;
|
---|
| 2882 | target_phys_addr_t start_addr2, end_addr2;
|
---|
| 2883 | int need_subpage = 0;
|
---|
| 2884 |
|
---|
| 2885 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
|
---|
| 2886 | need_subpage);
|
---|
[37689] | 2887 | if (need_subpage) {
|
---|
[13559] | 2888 | if (!(orig_memory & IO_MEM_SUBPAGE)) {
|
---|
| 2889 | subpage = subpage_init((addr & TARGET_PAGE_MASK),
|
---|
[36170] | 2890 | &p->phys_offset, orig_memory,
|
---|
| 2891 | p->region_offset);
|
---|
[13559] | 2892 | } else {
|
---|
| 2893 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
|
---|
| 2894 | >> IO_MEM_SHIFT];
|
---|
| 2895 | }
|
---|
[36170] | 2896 | subpage_register(subpage, start_addr2, end_addr2, phys_offset,
|
---|
| 2897 | region_offset);
|
---|
| 2898 | p->region_offset = 0;
|
---|
[13559] | 2899 | } else {
|
---|
| 2900 | p->phys_offset = phys_offset;
|
---|
[36140] | 2901 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
|
---|
| 2902 | (phys_offset & IO_MEM_ROMD))
|
---|
[13559] | 2903 | phys_offset += TARGET_PAGE_SIZE;
|
---|
| 2904 | }
|
---|
| 2905 | } else {
|
---|
| 2906 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
|
---|
| 2907 | p->phys_offset = phys_offset;
|
---|
[36170] | 2908 | p->region_offset = region_offset;
|
---|
[36140] | 2909 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
|
---|
[36170] | 2910 | (phys_offset & IO_MEM_ROMD)) {
|
---|
[13559] | 2911 | phys_offset += TARGET_PAGE_SIZE;
|
---|
[36170] | 2912 | } else {
|
---|
[13559] | 2913 | target_phys_addr_t start_addr2, end_addr2;
|
---|
| 2914 | int need_subpage = 0;
|
---|
[2422] | 2915 |
|
---|
[13559] | 2916 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
|
---|
| 2917 | end_addr2, need_subpage);
|
---|
| 2918 |
|
---|
[37689] | 2919 | if (need_subpage) {
|
---|
[13559] | 2920 | subpage = subpage_init((addr & TARGET_PAGE_MASK),
|
---|
[36170] | 2921 | &p->phys_offset, IO_MEM_UNASSIGNED,
|
---|
| 2922 | addr & TARGET_PAGE_MASK);
|
---|
[13559] | 2923 | subpage_register(subpage, start_addr2, end_addr2,
|
---|
[36170] | 2924 | phys_offset, region_offset);
|
---|
| 2925 | p->region_offset = 0;
|
---|
[13559] | 2926 | }
|
---|
| 2927 | }
|
---|
| 2928 | }
|
---|
[36170] | 2929 | region_offset += TARGET_PAGE_SIZE;
|
---|
[1] | 2930 | }
|
---|
[36140] | 2931 |
|
---|
[2422] | 2932 | /* since each CPU stores ram addresses in its TLB cache, we must
|
---|
| 2933 | reset the modified entries */
|
---|
[37702] | 2934 | #ifndef VBOX
|
---|
[2422] | 2935 | /* XXX: slow ! */
|
---|
| 2936 | for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
---|
| 2937 | tlb_flush(env, 1);
|
---|
| 2938 | }
|
---|
[37702] | 2939 | #else
|
---|
| 2940 | /* We have one thread per CPU, so, one of the other EMTs might be executing
|
---|
| 2941 | code right now and flushing the TLB may crash it. */
|
---|
| 2942 | env = first_cpu;
|
---|
| 2943 | if (EMRemIsLockOwner(env->pVM))
|
---|
| 2944 | tlb_flush(env, 1);
|
---|
| 2945 | else
|
---|
| 2946 | ASMAtomicOrS32((int32_t volatile *)&env->interrupt_request,
|
---|
| 2947 | CPU_INTERRUPT_EXTERNAL_FLUSH_TLB);
|
---|
| 2948 | #endif
|
---|
[1] | 2949 | }
|
---|
| 2950 |
|
---|
[2422] | 2951 | /* XXX: temporary until new memory mapping API */
|
---|
[36140] | 2952 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
|
---|
[2422] | 2953 | {
|
---|
| 2954 | PhysPageDesc *p;
|
---|
| 2955 |
|
---|
| 2956 | p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 2957 | if (!p)
|
---|
| 2958 | return IO_MEM_UNASSIGNED;
|
---|
| 2959 | return p->phys_offset;
|
---|
| 2960 | }
|
---|
| 2961 |
|
---|
[13559] | 2962 | #ifndef VBOX
|
---|
[37689] | 2963 |
|
---|
[36170] | 2964 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
|
---|
| 2965 | {
|
---|
| 2966 | if (kvm_enabled())
|
---|
| 2967 | kvm_coalesce_mmio_region(addr, size);
|
---|
| 2968 | }
|
---|
| 2969 |
|
---|
| 2970 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
|
---|
| 2971 | {
|
---|
| 2972 | if (kvm_enabled())
|
---|
| 2973 | kvm_uncoalesce_mmio_region(addr, size);
|
---|
| 2974 | }
|
---|
| 2975 |
|
---|
[37689] | 2976 | void qemu_flush_coalesced_mmio_buffer(void)
|
---|
[36175] | 2977 | {
|
---|
[37689] | 2978 | if (kvm_enabled())
|
---|
| 2979 | kvm_flush_coalesced_mmio_buffer();
|
---|
| 2980 | }
|
---|
[36175] | 2981 |
|
---|
[37689] | 2982 | #if defined(__linux__) && !defined(TARGET_S390X)
|
---|
| 2983 |
|
---|
| 2984 | #include <sys/vfs.h>
|
---|
| 2985 |
|
---|
| 2986 | #define HUGETLBFS_MAGIC 0x958458f6
|
---|
| 2987 |
|
---|
[42601] | 2988 | static size_t gethugepagesize(const char *path)
|
---|
[37689] | 2989 | {
|
---|
| 2990 | struct statfs fs;
|
---|
| 2991 | int ret;
|
---|
| 2992 |
|
---|
| 2993 | do {
|
---|
| 2994 | ret = statfs(path, &fs);
|
---|
| 2995 | } while (ret != 0 && errno == EINTR);
|
---|
| 2996 |
|
---|
| 2997 | if (ret != 0) {
|
---|
| 2998 | perror(path);
|
---|
| 2999 | return 0;
|
---|
| 3000 | }
|
---|
| 3001 |
|
---|
| 3002 | if (fs.f_type != HUGETLBFS_MAGIC)
|
---|
| 3003 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path);
|
---|
| 3004 |
|
---|
[42601] | 3005 | return (size_t)fs.f_bsize;
|
---|
[37689] | 3006 | }
|
---|
| 3007 |
|
---|
| 3008 | static void *file_ram_alloc(RAMBlock *block,
|
---|
| 3009 | ram_addr_t memory,
|
---|
| 3010 | const char *path)
|
---|
| 3011 | {
|
---|
| 3012 | char *filename;
|
---|
| 3013 | void *area;
|
---|
| 3014 | int fd;
|
---|
| 3015 | #ifdef MAP_POPULATE
|
---|
| 3016 | int flags;
|
---|
| 3017 | #endif
|
---|
[42601] | 3018 | size_t hpagesize;
|
---|
[37689] | 3019 |
|
---|
| 3020 | hpagesize = gethugepagesize(path);
|
---|
| 3021 | if (!hpagesize) {
|
---|
| 3022 | return NULL;
|
---|
| 3023 | }
|
---|
| 3024 |
|
---|
| 3025 | if (memory < hpagesize) {
|
---|
| 3026 | return NULL;
|
---|
| 3027 | }
|
---|
| 3028 |
|
---|
| 3029 | if (kvm_enabled() && !kvm_has_sync_mmu()) {
|
---|
| 3030 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n");
|
---|
| 3031 | return NULL;
|
---|
| 3032 | }
|
---|
| 3033 |
|
---|
| 3034 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) {
|
---|
| 3035 | return NULL;
|
---|
| 3036 | }
|
---|
| 3037 |
|
---|
| 3038 | fd = mkstemp(filename);
|
---|
| 3039 | if (fd < 0) {
|
---|
| 3040 | perror("unable to create backing store for hugepages");
|
---|
| 3041 | free(filename);
|
---|
| 3042 | return NULL;
|
---|
| 3043 | }
|
---|
| 3044 | unlink(filename);
|
---|
| 3045 | free(filename);
|
---|
| 3046 |
|
---|
| 3047 | memory = (memory+hpagesize-1) & ~(hpagesize-1);
|
---|
| 3048 |
|
---|
| 3049 | /*
|
---|
| 3050 | * ftruncate is not supported by hugetlbfs in older
|
---|
| 3051 | * hosts, so don't bother bailing out on errors.
|
---|
| 3052 | * If anything goes wrong with it under other filesystems,
|
---|
| 3053 | * mmap will fail.
|
---|
| 3054 | */
|
---|
| 3055 | if (ftruncate(fd, memory))
|
---|
| 3056 | perror("ftruncate");
|
---|
| 3057 |
|
---|
| 3058 | #ifdef MAP_POPULATE
|
---|
| 3059 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case
|
---|
| 3060 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED
|
---|
| 3061 | * to sidestep this quirk.
|
---|
| 3062 | */
|
---|
| 3063 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE;
|
---|
| 3064 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0);
|
---|
| 3065 | #else
|
---|
| 3066 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
|
---|
| 3067 | #endif
|
---|
| 3068 | if (area == MAP_FAILED) {
|
---|
| 3069 | perror("file_ram_alloc: can't mmap RAM pages");
|
---|
| 3070 | close(fd);
|
---|
| 3071 | return (NULL);
|
---|
| 3072 | }
|
---|
| 3073 | block->fd = fd;
|
---|
| 3074 | return area;
|
---|
| 3075 | }
|
---|
| 3076 | #endif
|
---|
| 3077 |
|
---|
| 3078 | static ram_addr_t find_ram_offset(ram_addr_t size)
|
---|
| 3079 | {
|
---|
| 3080 | RAMBlock *block, *next_block;
|
---|
| 3081 | ram_addr_t offset = 0, mingap = ULONG_MAX;
|
---|
| 3082 |
|
---|
| 3083 | if (QLIST_EMPTY(&ram_list.blocks))
|
---|
| 3084 | return 0;
|
---|
| 3085 |
|
---|
| 3086 | QLIST_FOREACH(block, &ram_list.blocks, next) {
|
---|
| 3087 | ram_addr_t end, next = ULONG_MAX;
|
---|
| 3088 |
|
---|
| 3089 | end = block->offset + block->length;
|
---|
| 3090 |
|
---|
| 3091 | QLIST_FOREACH(next_block, &ram_list.blocks, next) {
|
---|
| 3092 | if (next_block->offset >= end) {
|
---|
| 3093 | next = MIN(next, next_block->offset);
|
---|
| 3094 | }
|
---|
| 3095 | }
|
---|
| 3096 | if (next - end >= size && next - end < mingap) {
|
---|
| 3097 | offset = end;
|
---|
| 3098 | mingap = next - end;
|
---|
| 3099 | }
|
---|
| 3100 | }
|
---|
| 3101 | return offset;
|
---|
| 3102 | }
|
---|
| 3103 |
|
---|
| 3104 | static ram_addr_t last_ram_offset(void)
|
---|
| 3105 | {
|
---|
| 3106 | RAMBlock *block;
|
---|
| 3107 | ram_addr_t last = 0;
|
---|
| 3108 |
|
---|
| 3109 | QLIST_FOREACH(block, &ram_list.blocks, next)
|
---|
| 3110 | last = MAX(last, block->offset + block->length);
|
---|
| 3111 |
|
---|
| 3112 | return last;
|
---|
| 3113 | }
|
---|
| 3114 |
|
---|
| 3115 | ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
|
---|
| 3116 | ram_addr_t size, void *host)
|
---|
| 3117 | {
|
---|
| 3118 | RAMBlock *new_block, *block;
|
---|
| 3119 |
|
---|
[36175] | 3120 | size = TARGET_PAGE_ALIGN(size);
|
---|
[37689] | 3121 | new_block = qemu_mallocz(sizeof(*new_block));
|
---|
[36175] | 3122 |
|
---|
[37689] | 3123 | if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) {
|
---|
| 3124 | char *id = dev->parent_bus->info->get_dev_path(dev);
|
---|
| 3125 | if (id) {
|
---|
| 3126 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
|
---|
| 3127 | qemu_free(id);
|
---|
| 3128 | }
|
---|
| 3129 | }
|
---|
| 3130 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
|
---|
| 3131 |
|
---|
| 3132 | QLIST_FOREACH(block, &ram_list.blocks, next) {
|
---|
| 3133 | if (!strcmp(block->idstr, new_block->idstr)) {
|
---|
| 3134 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
|
---|
| 3135 | new_block->idstr);
|
---|
| 3136 | abort();
|
---|
| 3137 | }
|
---|
| 3138 | }
|
---|
| 3139 |
|
---|
| 3140 | new_block->host = host;
|
---|
| 3141 |
|
---|
| 3142 | new_block->offset = find_ram_offset(size);
|
---|
| 3143 | new_block->length = size;
|
---|
| 3144 |
|
---|
| 3145 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next);
|
---|
| 3146 |
|
---|
| 3147 | ram_list.phys_dirty = qemu_realloc(ram_list.phys_dirty,
|
---|
| 3148 | last_ram_offset() >> TARGET_PAGE_BITS);
|
---|
| 3149 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS),
|
---|
| 3150 | 0xff, size >> TARGET_PAGE_BITS);
|
---|
| 3151 |
|
---|
| 3152 | if (kvm_enabled())
|
---|
| 3153 | kvm_setup_guest_memory(new_block->host, size);
|
---|
| 3154 |
|
---|
| 3155 | return new_block->offset;
|
---|
| 3156 | }
|
---|
| 3157 |
|
---|
| 3158 | ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size)
|
---|
| 3159 | {
|
---|
| 3160 | RAMBlock *new_block, *block;
|
---|
| 3161 |
|
---|
| 3162 | size = TARGET_PAGE_ALIGN(size);
|
---|
| 3163 | new_block = qemu_mallocz(sizeof(*new_block));
|
---|
| 3164 |
|
---|
| 3165 | if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) {
|
---|
| 3166 | char *id = dev->parent_bus->info->get_dev_path(dev);
|
---|
| 3167 | if (id) {
|
---|
| 3168 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
|
---|
| 3169 | qemu_free(id);
|
---|
| 3170 | }
|
---|
| 3171 | }
|
---|
| 3172 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
|
---|
| 3173 |
|
---|
| 3174 | QLIST_FOREACH(block, &ram_list.blocks, next) {
|
---|
| 3175 | if (!strcmp(block->idstr, new_block->idstr)) {
|
---|
| 3176 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
|
---|
| 3177 | new_block->idstr);
|
---|
| 3178 | abort();
|
---|
| 3179 | }
|
---|
| 3180 | }
|
---|
| 3181 |
|
---|
| 3182 | if (mem_path) {
|
---|
| 3183 | #if defined (__linux__) && !defined(TARGET_S390X)
|
---|
| 3184 | new_block->host = file_ram_alloc(new_block, size, mem_path);
|
---|
| 3185 | if (!new_block->host) {
|
---|
| 3186 | new_block->host = qemu_vmalloc(size);
|
---|
| 3187 | #ifdef MADV_MERGEABLE
|
---|
| 3188 | madvise(new_block->host, size, MADV_MERGEABLE);
|
---|
| 3189 | #endif
|
---|
| 3190 | }
|
---|
| 3191 | #else
|
---|
| 3192 | fprintf(stderr, "-mem-path option unsupported\n");
|
---|
| 3193 | exit(1);
|
---|
| 3194 | #endif
|
---|
| 3195 | } else {
|
---|
[37675] | 3196 | #if defined(TARGET_S390X) && defined(CONFIG_KVM)
|
---|
[37689] | 3197 | /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */
|
---|
| 3198 | new_block->host = mmap((void*)0x1000000, size,
|
---|
| 3199 | PROT_EXEC|PROT_READ|PROT_WRITE,
|
---|
| 3200 | MAP_SHARED | MAP_ANONYMOUS, -1, 0);
|
---|
[37675] | 3201 | #else
|
---|
[37689] | 3202 | new_block->host = qemu_vmalloc(size);
|
---|
[37675] | 3203 | #endif
|
---|
| 3204 | #ifdef MADV_MERGEABLE
|
---|
[37689] | 3205 | madvise(new_block->host, size, MADV_MERGEABLE);
|
---|
[37675] | 3206 | #endif
|
---|
[37689] | 3207 | }
|
---|
| 3208 | new_block->offset = find_ram_offset(size);
|
---|
[36175] | 3209 | new_block->length = size;
|
---|
| 3210 |
|
---|
[37689] | 3211 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next);
|
---|
[36175] | 3212 |
|
---|
[37689] | 3213 | ram_list.phys_dirty = qemu_realloc(ram_list.phys_dirty,
|
---|
| 3214 | last_ram_offset() >> TARGET_PAGE_BITS);
|
---|
| 3215 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS),
|
---|
[36175] | 3216 | 0xff, size >> TARGET_PAGE_BITS);
|
---|
| 3217 |
|
---|
| 3218 | if (kvm_enabled())
|
---|
| 3219 | kvm_setup_guest_memory(new_block->host, size);
|
---|
| 3220 |
|
---|
| 3221 | return new_block->offset;
|
---|
| 3222 | }
|
---|
| 3223 |
|
---|
[13559] | 3224 | void qemu_ram_free(ram_addr_t addr)
|
---|
| 3225 | {
|
---|
[37689] | 3226 | RAMBlock *block;
|
---|
| 3227 |
|
---|
| 3228 | QLIST_FOREACH(block, &ram_list.blocks, next) {
|
---|
| 3229 | if (addr == block->offset) {
|
---|
| 3230 | QLIST_REMOVE(block, next);
|
---|
| 3231 | if (mem_path) {
|
---|
| 3232 | #if defined (__linux__) && !defined(TARGET_S390X)
|
---|
| 3233 | if (block->fd) {
|
---|
| 3234 | munmap(block->host, block->length);
|
---|
| 3235 | close(block->fd);
|
---|
| 3236 | } else {
|
---|
| 3237 | qemu_vfree(block->host);
|
---|
| 3238 | }
|
---|
| 3239 | #endif
|
---|
| 3240 | } else {
|
---|
| 3241 | #if defined(TARGET_S390X) && defined(CONFIG_KVM)
|
---|
| 3242 | munmap(block->host, block->length);
|
---|
| 3243 | #else
|
---|
| 3244 | qemu_vfree(block->host);
|
---|
| 3245 | #endif
|
---|
| 3246 | }
|
---|
| 3247 | qemu_free(block);
|
---|
| 3248 | return;
|
---|
| 3249 | }
|
---|
| 3250 | }
|
---|
| 3251 |
|
---|
[13559] | 3252 | }
|
---|
[36175] | 3253 |
|
---|
| 3254 | /* Return a host pointer to ram allocated with qemu_ram_alloc.
|
---|
| 3255 | With the exception of the softmmu code in this file, this should
|
---|
| 3256 | only be used for local memory (e.g. video ram) that the device owns,
|
---|
| 3257 | and knows it isn't going to access beyond the end of the block.
|
---|
| 3258 |
|
---|
| 3259 | It should not be used for general purpose DMA.
|
---|
| 3260 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
|
---|
| 3261 | */
|
---|
| 3262 | void *qemu_get_ram_ptr(ram_addr_t addr)
|
---|
| 3263 | {
|
---|
| 3264 | RAMBlock *block;
|
---|
| 3265 |
|
---|
[37689] | 3266 | QLIST_FOREACH(block, &ram_list.blocks, next) {
|
---|
| 3267 | if (addr - block->offset < block->length) {
|
---|
| 3268 | QLIST_REMOVE(block, next);
|
---|
| 3269 | QLIST_INSERT_HEAD(&ram_list.blocks, block, next);
|
---|
| 3270 | return block->host + (addr - block->offset);
|
---|
| 3271 | }
|
---|
[36175] | 3272 | }
|
---|
[37689] | 3273 |
|
---|
| 3274 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
|
---|
| 3275 | abort();
|
---|
| 3276 |
|
---|
| 3277 | return NULL;
|
---|
[36175] | 3278 | }
|
---|
| 3279 |
|
---|
| 3280 | /* Some of the softmmu routines need to translate from a host pointer
|
---|
| 3281 | (typically a TLB entry) back to a ram offset. */
|
---|
| 3282 | ram_addr_t qemu_ram_addr_from_host(void *ptr)
|
---|
| 3283 | {
|
---|
| 3284 | RAMBlock *block;
|
---|
| 3285 | uint8_t *host = ptr;
|
---|
| 3286 |
|
---|
[37689] | 3287 | QLIST_FOREACH(block, &ram_list.blocks, next) {
|
---|
| 3288 | if (host - block->host < block->length) {
|
---|
| 3289 | return block->offset + (host - block->host);
|
---|
| 3290 | }
|
---|
[36175] | 3291 | }
|
---|
[37689] | 3292 |
|
---|
| 3293 | fprintf(stderr, "Bad ram pointer %p\n", ptr);
|
---|
| 3294 | abort();
|
---|
| 3295 |
|
---|
| 3296 | return 0;
|
---|
[36175] | 3297 | }
|
---|
| 3298 |
|
---|
[36140] | 3299 | #endif /* !VBOX */
|
---|
[13559] | 3300 |
|
---|
[1] | 3301 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
|
---|
| 3302 | {
|
---|
[2422] | 3303 | #ifdef DEBUG_UNASSIGNED
|
---|
[36140] | 3304 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
|
---|
[2422] | 3305 | #endif
|
---|
[37675] | 3306 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
|
---|
[13559] | 3307 | do_unassigned_access(addr, 0, 0, 0, 1);
|
---|
| 3308 | #endif
|
---|
[1] | 3309 | return 0;
|
---|
| 3310 | }
|
---|
| 3311 |
|
---|
[13559] | 3312 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
|
---|
| 3313 | {
|
---|
| 3314 | #ifdef DEBUG_UNASSIGNED
|
---|
| 3315 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
|
---|
| 3316 | #endif
|
---|
[37675] | 3317 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
|
---|
[13559] | 3318 | do_unassigned_access(addr, 0, 0, 0, 2);
|
---|
| 3319 | #endif
|
---|
| 3320 | return 0;
|
---|
| 3321 | }
|
---|
| 3322 |
|
---|
| 3323 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
|
---|
| 3324 | {
|
---|
| 3325 | #ifdef DEBUG_UNASSIGNED
|
---|
| 3326 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
|
---|
| 3327 | #endif
|
---|
[37675] | 3328 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
|
---|
[13559] | 3329 | do_unassigned_access(addr, 0, 0, 0, 4);
|
---|
| 3330 | #endif
|
---|
| 3331 | return 0;
|
---|
| 3332 | }
|
---|
| 3333 |
|
---|
[1] | 3334 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
---|
| 3335 | {
|
---|
[2422] | 3336 | #ifdef DEBUG_UNASSIGNED
|
---|
[36140] | 3337 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
|
---|
[2422] | 3338 | #endif
|
---|
[37675] | 3339 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
|
---|
[36140] | 3340 | do_unassigned_access(addr, 1, 0, 0, 1);
|
---|
| 3341 | #endif
|
---|
[1] | 3342 | }
|
---|
| 3343 |
|
---|
[13559] | 3344 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
---|
| 3345 | {
|
---|
| 3346 | #ifdef DEBUG_UNASSIGNED
|
---|
| 3347 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
|
---|
| 3348 | #endif
|
---|
[37675] | 3349 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
|
---|
[13559] | 3350 | do_unassigned_access(addr, 1, 0, 0, 2);
|
---|
| 3351 | #endif
|
---|
| 3352 | }
|
---|
| 3353 |
|
---|
| 3354 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
---|
| 3355 | {
|
---|
| 3356 | #ifdef DEBUG_UNASSIGNED
|
---|
| 3357 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
|
---|
| 3358 | #endif
|
---|
[37675] | 3359 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
|
---|
[13559] | 3360 | do_unassigned_access(addr, 1, 0, 0, 4);
|
---|
| 3361 | #endif
|
---|
| 3362 | }
|
---|
[36140] | 3363 |
|
---|
[37675] | 3364 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = {
|
---|
[1] | 3365 | unassigned_mem_readb,
|
---|
[13559] | 3366 | unassigned_mem_readw,
|
---|
| 3367 | unassigned_mem_readl,
|
---|
[1] | 3368 | };
|
---|
| 3369 |
|
---|
[37675] | 3370 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = {
|
---|
[1] | 3371 | unassigned_mem_writeb,
|
---|
[13559] | 3372 | unassigned_mem_writew,
|
---|
| 3373 | unassigned_mem_writel,
|
---|
[1] | 3374 | };
|
---|
| 3375 |
|
---|
[36140] | 3376 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
|
---|
| 3377 | uint32_t val)
|
---|
[1] | 3378 | {
|
---|
[2422] | 3379 | int dirty_flags;
|
---|
[37689] | 3380 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
|
---|
[2422] | 3381 | if (!(dirty_flags & CODE_DIRTY_FLAG)) {
|
---|
[1] | 3382 | #if !defined(CONFIG_USER_ONLY)
|
---|
[2422] | 3383 | tb_invalidate_phys_page_fast(ram_addr, 1);
|
---|
[37689] | 3384 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
|
---|
[1] | 3385 | #endif
|
---|
[2422] | 3386 | }
|
---|
[14277] | 3387 | #if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[36140] | 3388 | remR3PhysWriteU8(ram_addr, val);
|
---|
[14277] | 3389 | #else
|
---|
[36175] | 3390 | stb_p(qemu_get_ram_ptr(ram_addr), val);
|
---|
[14277] | 3391 | #endif
|
---|
[2422] | 3392 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
|
---|
[37689] | 3393 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
|
---|
[2422] | 3394 | /* we remove the notdirty callback only if the code has been
|
---|
| 3395 | flushed */
|
---|
| 3396 | if (dirty_flags == 0xff)
|
---|
[36140] | 3397 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
|
---|
[1] | 3398 | }
|
---|
| 3399 |
|
---|
[36140] | 3400 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
|
---|
| 3401 | uint32_t val)
|
---|
[1] | 3402 | {
|
---|
[2422] | 3403 | int dirty_flags;
|
---|
[37689] | 3404 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
|
---|
[2422] | 3405 | if (!(dirty_flags & CODE_DIRTY_FLAG)) {
|
---|
[1] | 3406 | #if !defined(CONFIG_USER_ONLY)
|
---|
[2422] | 3407 | tb_invalidate_phys_page_fast(ram_addr, 2);
|
---|
[37689] | 3408 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
|
---|
[1] | 3409 | #endif
|
---|
[2422] | 3410 | }
|
---|
[14277] | 3411 | #if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[36140] | 3412 | remR3PhysWriteU16(ram_addr, val);
|
---|
[14277] | 3413 | #else
|
---|
[36175] | 3414 | stw_p(qemu_get_ram_ptr(ram_addr), val);
|
---|
[14277] | 3415 | #endif
|
---|
[2422] | 3416 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
|
---|
[37689] | 3417 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
|
---|
[2422] | 3418 | /* we remove the notdirty callback only if the code has been
|
---|
| 3419 | flushed */
|
---|
| 3420 | if (dirty_flags == 0xff)
|
---|
[36140] | 3421 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
|
---|
[1] | 3422 | }
|
---|
| 3423 |
|
---|
[36140] | 3424 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
|
---|
| 3425 | uint32_t val)
|
---|
[1] | 3426 | {
|
---|
[2422] | 3427 | int dirty_flags;
|
---|
[37689] | 3428 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
|
---|
[2422] | 3429 | if (!(dirty_flags & CODE_DIRTY_FLAG)) {
|
---|
[1] | 3430 | #if !defined(CONFIG_USER_ONLY)
|
---|
[2422] | 3431 | tb_invalidate_phys_page_fast(ram_addr, 4);
|
---|
[37689] | 3432 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
|
---|
[1] | 3433 | #endif
|
---|
[2422] | 3434 | }
|
---|
[14277] | 3435 | #if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[36140] | 3436 | remR3PhysWriteU32(ram_addr, val);
|
---|
[14277] | 3437 | #else
|
---|
[36175] | 3438 | stl_p(qemu_get_ram_ptr(ram_addr), val);
|
---|
[14277] | 3439 | #endif
|
---|
[2422] | 3440 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
|
---|
[37689] | 3441 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
|
---|
[2422] | 3442 | /* we remove the notdirty callback only if the code has been
|
---|
| 3443 | flushed */
|
---|
| 3444 | if (dirty_flags == 0xff)
|
---|
[36140] | 3445 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
|
---|
[1] | 3446 | }
|
---|
| 3447 |
|
---|
[37675] | 3448 | static CPUReadMemoryFunc * const error_mem_read[3] = {
|
---|
[1] | 3449 | NULL, /* never used */
|
---|
| 3450 | NULL, /* never used */
|
---|
| 3451 | NULL, /* never used */
|
---|
| 3452 | };
|
---|
| 3453 |
|
---|
[37675] | 3454 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = {
|
---|
[1] | 3455 | notdirty_mem_writeb,
|
---|
| 3456 | notdirty_mem_writew,
|
---|
| 3457 | notdirty_mem_writel,
|
---|
| 3458 | };
|
---|
| 3459 |
|
---|
[13559] | 3460 | /* Generate a debug exception if a watchpoint has been hit. */
|
---|
[36170] | 3461 | static void check_watchpoint(int offset, int len_mask, int flags)
|
---|
[13559] | 3462 | {
|
---|
| 3463 | CPUState *env = cpu_single_env;
|
---|
[36170] | 3464 | target_ulong pc, cs_base;
|
---|
| 3465 | TranslationBlock *tb;
|
---|
[13559] | 3466 | target_ulong vaddr;
|
---|
[36170] | 3467 | CPUWatchpoint *wp;
|
---|
| 3468 | int cpu_flags;
|
---|
[13559] | 3469 |
|
---|
[36170] | 3470 | if (env->watchpoint_hit) {
|
---|
| 3471 | /* We re-entered the check after replacing the TB. Now raise
|
---|
| 3472 | * the debug interrupt so that is will trigger after the
|
---|
| 3473 | * current instruction. */
|
---|
| 3474 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
|
---|
| 3475 | return;
|
---|
| 3476 | }
|
---|
[13559] | 3477 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
|
---|
[37675] | 3478 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
|
---|
[36170] | 3479 | if ((vaddr == (wp->vaddr & len_mask) ||
|
---|
| 3480 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
|
---|
| 3481 | wp->flags |= BP_WATCHPOINT_HIT;
|
---|
| 3482 | if (!env->watchpoint_hit) {
|
---|
| 3483 | env->watchpoint_hit = wp;
|
---|
| 3484 | tb = tb_find_pc(env->mem_io_pc);
|
---|
| 3485 | if (!tb) {
|
---|
| 3486 | cpu_abort(env, "check_watchpoint: could not find TB for "
|
---|
| 3487 | "pc=%p", (void *)env->mem_io_pc);
|
---|
| 3488 | }
|
---|
| 3489 | cpu_restore_state(tb, env, env->mem_io_pc, NULL);
|
---|
| 3490 | tb_phys_invalidate(tb, -1);
|
---|
| 3491 | if (wp->flags & BP_STOP_BEFORE_ACCESS) {
|
---|
| 3492 | env->exception_index = EXCP_DEBUG;
|
---|
| 3493 | } else {
|
---|
| 3494 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
|
---|
| 3495 | tb_gen_code(env, pc, cs_base, cpu_flags, 1);
|
---|
| 3496 | }
|
---|
| 3497 | cpu_resume_from_signal(env, NULL);
|
---|
| 3498 | }
|
---|
| 3499 | } else {
|
---|
| 3500 | wp->flags &= ~BP_WATCHPOINT_HIT;
|
---|
[13559] | 3501 | }
|
---|
| 3502 | }
|
---|
| 3503 | }
|
---|
| 3504 |
|
---|
| 3505 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
|
---|
| 3506 | so these check for a hit then pass through to the normal out-of-line
|
---|
| 3507 | phys routines. */
|
---|
| 3508 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
|
---|
| 3509 | {
|
---|
[36170] | 3510 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
|
---|
[13559] | 3511 | return ldub_phys(addr);
|
---|
| 3512 | }
|
---|
| 3513 |
|
---|
| 3514 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
|
---|
| 3515 | {
|
---|
[36170] | 3516 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
|
---|
[13559] | 3517 | return lduw_phys(addr);
|
---|
| 3518 | }
|
---|
| 3519 |
|
---|
| 3520 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
|
---|
| 3521 | {
|
---|
[36170] | 3522 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
|
---|
[13559] | 3523 | return ldl_phys(addr);
|
---|
| 3524 | }
|
---|
| 3525 |
|
---|
| 3526 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
|
---|
| 3527 | uint32_t val)
|
---|
| 3528 | {
|
---|
[36170] | 3529 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
|
---|
[13559] | 3530 | stb_phys(addr, val);
|
---|
| 3531 | }
|
---|
| 3532 |
|
---|
| 3533 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
|
---|
| 3534 | uint32_t val)
|
---|
| 3535 | {
|
---|
[36170] | 3536 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
|
---|
[13559] | 3537 | stw_phys(addr, val);
|
---|
| 3538 | }
|
---|
| 3539 |
|
---|
| 3540 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
|
---|
| 3541 | uint32_t val)
|
---|
| 3542 | {
|
---|
[36170] | 3543 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
|
---|
[13559] | 3544 | stl_phys(addr, val);
|
---|
| 3545 | }
|
---|
| 3546 |
|
---|
[37675] | 3547 | static CPUReadMemoryFunc * const watch_mem_read[3] = {
|
---|
[13559] | 3548 | watch_mem_readb,
|
---|
| 3549 | watch_mem_readw,
|
---|
| 3550 | watch_mem_readl,
|
---|
| 3551 | };
|
---|
| 3552 |
|
---|
[37675] | 3553 | static CPUWriteMemoryFunc * const watch_mem_write[3] = {
|
---|
[13559] | 3554 | watch_mem_writeb,
|
---|
| 3555 | watch_mem_writew,
|
---|
| 3556 | watch_mem_writel,
|
---|
| 3557 | };
|
---|
| 3558 |
|
---|
[37689] | 3559 | static inline uint32_t subpage_readlen (subpage_t *mmio,
|
---|
| 3560 | target_phys_addr_t addr,
|
---|
| 3561 | unsigned int len)
|
---|
[13559] | 3562 | {
|
---|
[37689] | 3563 | unsigned int idx = SUBPAGE_IDX(addr);
|
---|
[13559] | 3564 | #if defined(DEBUG_SUBPAGE)
|
---|
| 3565 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
|
---|
| 3566 | mmio, len, addr, idx);
|
---|
| 3567 | #endif
|
---|
| 3568 |
|
---|
[37689] | 3569 | addr += mmio->region_offset[idx];
|
---|
| 3570 | idx = mmio->sub_io_index[idx];
|
---|
| 3571 | return io_mem_read[idx][len](io_mem_opaque[idx], addr);
|
---|
[13559] | 3572 | }
|
---|
| 3573 |
|
---|
| 3574 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
|
---|
[37689] | 3575 | uint32_t value, unsigned int len)
|
---|
[13559] | 3576 | {
|
---|
[37689] | 3577 | unsigned int idx = SUBPAGE_IDX(addr);
|
---|
[13559] | 3578 | #if defined(DEBUG_SUBPAGE)
|
---|
[37689] | 3579 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n",
|
---|
| 3580 | __func__, mmio, len, addr, idx, value);
|
---|
[13559] | 3581 | #endif
|
---|
[37689] | 3582 |
|
---|
| 3583 | addr += mmio->region_offset[idx];
|
---|
| 3584 | idx = mmio->sub_io_index[idx];
|
---|
| 3585 | io_mem_write[idx][len](io_mem_opaque[idx], addr, value);
|
---|
[13559] | 3586 | }
|
---|
| 3587 |
|
---|
| 3588 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
|
---|
| 3589 | {
|
---|
| 3590 | return subpage_readlen(opaque, addr, 0);
|
---|
| 3591 | }
|
---|
| 3592 |
|
---|
| 3593 | static void subpage_writeb (void *opaque, target_phys_addr_t addr,
|
---|
| 3594 | uint32_t value)
|
---|
| 3595 | {
|
---|
| 3596 | subpage_writelen(opaque, addr, value, 0);
|
---|
| 3597 | }
|
---|
| 3598 |
|
---|
| 3599 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
|
---|
| 3600 | {
|
---|
| 3601 | return subpage_readlen(opaque, addr, 1);
|
---|
| 3602 | }
|
---|
| 3603 |
|
---|
| 3604 | static void subpage_writew (void *opaque, target_phys_addr_t addr,
|
---|
| 3605 | uint32_t value)
|
---|
| 3606 | {
|
---|
| 3607 | subpage_writelen(opaque, addr, value, 1);
|
---|
| 3608 | }
|
---|
| 3609 |
|
---|
| 3610 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
|
---|
| 3611 | {
|
---|
| 3612 | return subpage_readlen(opaque, addr, 2);
|
---|
| 3613 | }
|
---|
| 3614 |
|
---|
[37689] | 3615 | static void subpage_writel (void *opaque, target_phys_addr_t addr,
|
---|
| 3616 | uint32_t value)
|
---|
[13559] | 3617 | {
|
---|
| 3618 | subpage_writelen(opaque, addr, value, 2);
|
---|
| 3619 | }
|
---|
| 3620 |
|
---|
[37675] | 3621 | static CPUReadMemoryFunc * const subpage_read[] = {
|
---|
[13559] | 3622 | &subpage_readb,
|
---|
| 3623 | &subpage_readw,
|
---|
| 3624 | &subpage_readl,
|
---|
| 3625 | };
|
---|
| 3626 |
|
---|
[37675] | 3627 | static CPUWriteMemoryFunc * const subpage_write[] = {
|
---|
[13559] | 3628 | &subpage_writeb,
|
---|
| 3629 | &subpage_writew,
|
---|
| 3630 | &subpage_writel,
|
---|
| 3631 | };
|
---|
| 3632 |
|
---|
| 3633 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
|
---|
[36170] | 3634 | ram_addr_t memory, ram_addr_t region_offset)
|
---|
[13559] | 3635 | {
|
---|
| 3636 | int idx, eidx;
|
---|
| 3637 |
|
---|
| 3638 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
|
---|
| 3639 | return -1;
|
---|
| 3640 | idx = SUBPAGE_IDX(start);
|
---|
| 3641 | eidx = SUBPAGE_IDX(end);
|
---|
| 3642 | #if defined(DEBUG_SUBPAGE)
|
---|
[36175] | 3643 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__,
|
---|
[13559] | 3644 | mmio, start, end, idx, eidx, memory);
|
---|
| 3645 | #endif
|
---|
[37689] | 3646 | memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
---|
[13559] | 3647 | for (; idx <= eidx; idx++) {
|
---|
[37689] | 3648 | mmio->sub_io_index[idx] = memory;
|
---|
| 3649 | mmio->region_offset[idx] = region_offset;
|
---|
[13559] | 3650 | }
|
---|
| 3651 |
|
---|
| 3652 | return 0;
|
---|
| 3653 | }
|
---|
| 3654 |
|
---|
[37689] | 3655 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
|
---|
| 3656 | ram_addr_t orig_memory,
|
---|
| 3657 | ram_addr_t region_offset)
|
---|
[13559] | 3658 | {
|
---|
| 3659 | subpage_t *mmio;
|
---|
| 3660 | int subpage_memory;
|
---|
| 3661 |
|
---|
| 3662 | mmio = qemu_mallocz(sizeof(subpage_t));
|
---|
[36170] | 3663 |
|
---|
| 3664 | mmio->base = base;
|
---|
[36175] | 3665 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio);
|
---|
[13559] | 3666 | #if defined(DEBUG_SUBPAGE)
|
---|
[36170] | 3667 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
|
---|
| 3668 | mmio, base, TARGET_PAGE_SIZE, subpage_memory);
|
---|
[13559] | 3669 | #endif
|
---|
[36170] | 3670 | *phys = subpage_memory | IO_MEM_SUBPAGE;
|
---|
[37689] | 3671 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset);
|
---|
[13559] | 3672 |
|
---|
| 3673 | return mmio;
|
---|
| 3674 | }
|
---|
| 3675 |
|
---|
[36170] | 3676 | static int get_free_io_mem_idx(void)
|
---|
| 3677 | {
|
---|
| 3678 | int i;
|
---|
| 3679 |
|
---|
| 3680 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++)
|
---|
| 3681 | if (!io_mem_used[i]) {
|
---|
| 3682 | io_mem_used[i] = 1;
|
---|
| 3683 | return i;
|
---|
| 3684 | }
|
---|
[37689] | 3685 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES);
|
---|
[36170] | 3686 | return -1;
|
---|
| 3687 | }
|
---|
| 3688 |
|
---|
[1] | 3689 | /* mem_read and mem_write are arrays of functions containing the
|
---|
| 3690 | function to access byte (index 0), word (index 1) and dword (index
|
---|
[36175] | 3691 | 2). Functions can be omitted with a NULL function pointer.
|
---|
[13559] | 3692 | If io_index is non zero, the corresponding io zone is
|
---|
| 3693 | modified. If it is zero, a new io zone is allocated. The return
|
---|
| 3694 | value can be used with cpu_register_physical_memory(). (-1) is
|
---|
| 3695 | returned if error. */
|
---|
[36175] | 3696 | static int cpu_register_io_memory_fixed(int io_index,
|
---|
[37675] | 3697 | CPUReadMemoryFunc * const *mem_read,
|
---|
| 3698 | CPUWriteMemoryFunc * const *mem_write,
|
---|
[36175] | 3699 | void *opaque)
|
---|
[1] | 3700 | {
|
---|
[37689] | 3701 | int i;
|
---|
[1] | 3702 |
|
---|
| 3703 | if (io_index <= 0) {
|
---|
[36170] | 3704 | io_index = get_free_io_mem_idx();
|
---|
| 3705 | if (io_index == -1)
|
---|
| 3706 | return io_index;
|
---|
[1] | 3707 | } else {
|
---|
[36175] | 3708 | io_index >>= IO_MEM_SHIFT;
|
---|
[1] | 3709 | if (io_index >= IO_MEM_NB_ENTRIES)
|
---|
| 3710 | return -1;
|
---|
| 3711 | }
|
---|
[2422] | 3712 |
|
---|
[37689] | 3713 | for (i = 0; i < 3; ++i) {
|
---|
| 3714 | io_mem_read[io_index][i]
|
---|
| 3715 | = (mem_read[i] ? mem_read[i] : unassigned_mem_read[i]);
|
---|
[1] | 3716 | }
|
---|
[37689] | 3717 | for (i = 0; i < 3; ++i) {
|
---|
| 3718 | io_mem_write[io_index][i]
|
---|
| 3719 | = (mem_write[i] ? mem_write[i] : unassigned_mem_write[i]);
|
---|
| 3720 | }
|
---|
[1] | 3721 | io_mem_opaque[io_index] = opaque;
|
---|
[37689] | 3722 |
|
---|
| 3723 | return (io_index << IO_MEM_SHIFT);
|
---|
[1] | 3724 | }
|
---|
| 3725 |
|
---|
[37675] | 3726 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
|
---|
| 3727 | CPUWriteMemoryFunc * const *mem_write,
|
---|
[36175] | 3728 | void *opaque)
|
---|
| 3729 | {
|
---|
| 3730 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque);
|
---|
| 3731 | }
|
---|
| 3732 |
|
---|
[36170] | 3733 | void cpu_unregister_io_memory(int io_table_address)
|
---|
| 3734 | {
|
---|
| 3735 | int i;
|
---|
| 3736 | int io_index = io_table_address >> IO_MEM_SHIFT;
|
---|
| 3737 |
|
---|
| 3738 | for (i=0;i < 3; i++) {
|
---|
| 3739 | io_mem_read[io_index][i] = unassigned_mem_read[i];
|
---|
| 3740 | io_mem_write[io_index][i] = unassigned_mem_write[i];
|
---|
| 3741 | }
|
---|
| 3742 | io_mem_opaque[io_index] = NULL;
|
---|
| 3743 | io_mem_used[io_index] = 0;
|
---|
| 3744 | }
|
---|
| 3745 |
|
---|
[36175] | 3746 | static void io_mem_init(void)
|
---|
[1] | 3747 | {
|
---|
[36175] | 3748 | int i;
|
---|
[1] | 3749 |
|
---|
[36175] | 3750 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL);
|
---|
| 3751 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL);
|
---|
| 3752 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL);
|
---|
| 3753 | for (i=0; i<5; i++)
|
---|
| 3754 | io_mem_used[i] = 1;
|
---|
| 3755 |
|
---|
| 3756 | io_mem_watch = cpu_register_io_memory(watch_mem_read,
|
---|
| 3757 | watch_mem_write, NULL);
|
---|
[1] | 3758 | }
|
---|
[36140] | 3759 |
|
---|
[13559] | 3760 | #endif /* !defined(CONFIG_USER_ONLY) */
|
---|
[1] | 3761 |
|
---|
| 3762 | /* physical memory access (slow version, mainly for debug) */
|
---|
| 3763 | #if defined(CONFIG_USER_ONLY)
|
---|
[37689] | 3764 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
---|
| 3765 | uint8_t *buf, int len, int is_write)
|
---|
[1] | 3766 | {
|
---|
| 3767 | int l, flags;
|
---|
| 3768 | target_ulong page;
|
---|
[2422] | 3769 | void * p;
|
---|
[1] | 3770 |
|
---|
| 3771 | while (len > 0) {
|
---|
| 3772 | page = addr & TARGET_PAGE_MASK;
|
---|
| 3773 | l = (page + TARGET_PAGE_SIZE) - addr;
|
---|
| 3774 | if (l > len)
|
---|
| 3775 | l = len;
|
---|
| 3776 | flags = page_get_flags(page);
|
---|
| 3777 | if (!(flags & PAGE_VALID))
|
---|
[37689] | 3778 | return -1;
|
---|
[1] | 3779 | if (is_write) {
|
---|
| 3780 | if (!(flags & PAGE_WRITE))
|
---|
[37689] | 3781 | return -1;
|
---|
[13559] | 3782 | /* XXX: this code should not depend on lock_user */
|
---|
| 3783 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
|
---|
[37689] | 3784 | return -1;
|
---|
[36140] | 3785 | memcpy(p, buf, l);
|
---|
| 3786 | unlock_user(p, addr, l);
|
---|
[1] | 3787 | } else {
|
---|
| 3788 | if (!(flags & PAGE_READ))
|
---|
[37689] | 3789 | return -1;
|
---|
[36140] | 3790 | /* XXX: this code should not depend on lock_user */
|
---|
[13559] | 3791 | if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
|
---|
[37689] | 3792 | return -1;
|
---|
[36140] | 3793 | memcpy(buf, p, l);
|
---|
[2422] | 3794 | unlock_user(p, addr, 0);
|
---|
[1] | 3795 | }
|
---|
| 3796 | len -= l;
|
---|
| 3797 | buf += l;
|
---|
| 3798 | addr += l;
|
---|
| 3799 | }
|
---|
[37689] | 3800 | return 0;
|
---|
[1] | 3801 | }
|
---|
| 3802 |
|
---|
| 3803 | #else
|
---|
[6532] | 3804 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
|
---|
[1] | 3805 | int len, int is_write)
|
---|
| 3806 | {
|
---|
| 3807 | int l, io_index;
|
---|
| 3808 | uint8_t *ptr;
|
---|
| 3809 | uint32_t val;
|
---|
| 3810 | target_phys_addr_t page;
|
---|
[42601] | 3811 | ram_addr_t pd;
|
---|
[1] | 3812 | PhysPageDesc *p;
|
---|
[6532] | 3813 |
|
---|
[1] | 3814 | while (len > 0) {
|
---|
| 3815 | page = addr & TARGET_PAGE_MASK;
|
---|
| 3816 | l = (page + TARGET_PAGE_SIZE) - addr;
|
---|
| 3817 | if (l > len)
|
---|
| 3818 | l = len;
|
---|
| 3819 | p = phys_page_find(page >> TARGET_PAGE_BITS);
|
---|
| 3820 | if (!p) {
|
---|
| 3821 | pd = IO_MEM_UNASSIGNED;
|
---|
| 3822 | } else {
|
---|
| 3823 | pd = p->phys_offset;
|
---|
| 3824 | }
|
---|
[6532] | 3825 |
|
---|
[1] | 3826 | if (is_write) {
|
---|
[2422] | 3827 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
---|
[36170] | 3828 | target_phys_addr_t addr1 = addr;
|
---|
[1] | 3829 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
---|
[36170] | 3830 | if (p)
|
---|
| 3831 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
|
---|
[2422] | 3832 | /* XXX: could force cpu_single_env to NULL to avoid
|
---|
| 3833 | potential bugs */
|
---|
[36170] | 3834 | if (l >= 4 && ((addr1 & 3) == 0)) {
|
---|
[2422] | 3835 | /* 32 bit write access */
|
---|
| 3836 | #if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[1] | 3837 | val = ldl_p(buf);
|
---|
[2422] | 3838 | #else
|
---|
| 3839 | val = *(const uint32_t *)buf;
|
---|
[6532] | 3840 | #endif
|
---|
[36170] | 3841 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val);
|
---|
[1] | 3842 | l = 4;
|
---|
[36170] | 3843 | } else if (l >= 2 && ((addr1 & 1) == 0)) {
|
---|
[2422] | 3844 | /* 16 bit write access */
|
---|
| 3845 | #if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[1] | 3846 | val = lduw_p(buf);
|
---|
[2422] | 3847 | #else
|
---|
| 3848 | val = *(const uint16_t *)buf;
|
---|
[6532] | 3849 | #endif
|
---|
[36170] | 3850 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val);
|
---|
[1] | 3851 | l = 2;
|
---|
| 3852 | } else {
|
---|
[2422] | 3853 | /* 8 bit write access */
|
---|
| 3854 | #if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[1] | 3855 | val = ldub_p(buf);
|
---|
[2422] | 3856 | #else
|
---|
| 3857 | val = *(const uint8_t *)buf;
|
---|
[6532] | 3858 | #endif
|
---|
[36170] | 3859 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val);
|
---|
[1] | 3860 | l = 1;
|
---|
| 3861 | }
|
---|
| 3862 | } else {
|
---|
[42601] | 3863 | ram_addr_t addr1;
|
---|
[1] | 3864 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
---|
| 3865 | /* RAM case */
|
---|
| 3866 | #ifdef VBOX
|
---|
[2422] | 3867 | remR3PhysWrite(addr1, buf, l); NOREF(ptr);
|
---|
[1] | 3868 | #else
|
---|
[36175] | 3869 | ptr = qemu_get_ram_ptr(addr1);
|
---|
[1] | 3870 | memcpy(ptr, buf, l);
|
---|
| 3871 | #endif
|
---|
[2422] | 3872 | if (!cpu_physical_memory_is_dirty(addr1)) {
|
---|
| 3873 | /* invalidate code */
|
---|
| 3874 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
|
---|
| 3875 | /* set dirty bit */
|
---|
[37689] | 3876 | cpu_physical_memory_set_dirty_flags(
|
---|
| 3877 | addr1, (0xff & ~CODE_DIRTY_FLAG));
|
---|
[2422] | 3878 | }
|
---|
[1] | 3879 | }
|
---|
| 3880 | } else {
|
---|
[6532] | 3881 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
|
---|
[2422] | 3882 | !(pd & IO_MEM_ROMD)) {
|
---|
[36170] | 3883 | target_phys_addr_t addr1 = addr;
|
---|
[1] | 3884 | /* I/O case */
|
---|
| 3885 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
---|
[36170] | 3886 | if (p)
|
---|
| 3887 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
|
---|
| 3888 | if (l >= 4 && ((addr1 & 3) == 0)) {
|
---|
[1] | 3889 | /* 32 bit read access */
|
---|
[36170] | 3890 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1);
|
---|
[2422] | 3891 | #if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[1] | 3892 | stl_p(buf, val);
|
---|
[2422] | 3893 | #else
|
---|
| 3894 | *(uint32_t *)buf = val;
|
---|
[6532] | 3895 | #endif
|
---|
[1] | 3896 | l = 4;
|
---|
[36170] | 3897 | } else if (l >= 2 && ((addr1 & 1) == 0)) {
|
---|
[1] | 3898 | /* 16 bit read access */
|
---|
[36170] | 3899 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1);
|
---|
[2422] | 3900 | #if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[1] | 3901 | stw_p(buf, val);
|
---|
[2422] | 3902 | #else
|
---|
| 3903 | *(uint16_t *)buf = val;
|
---|
[6532] | 3904 | #endif
|
---|
[1] | 3905 | l = 2;
|
---|
| 3906 | } else {
|
---|
[2422] | 3907 | /* 8 bit read access */
|
---|
[36170] | 3908 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1);
|
---|
[2422] | 3909 | #if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
[1] | 3910 | stb_p(buf, val);
|
---|
[2422] | 3911 | #else
|
---|
| 3912 | *(uint8_t *)buf = val;
|
---|
[6532] | 3913 | #endif
|
---|
[1] | 3914 | l = 1;
|
---|
| 3915 | }
|
---|
| 3916 | } else {
|
---|
| 3917 | /* RAM case */
|
---|
| 3918 | #ifdef VBOX
|
---|
[2422] | 3919 | remR3PhysRead((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), buf, l); NOREF(ptr);
|
---|
[1] | 3920 | #else
|
---|
[36175] | 3921 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
|
---|
[1] | 3922 | (addr & ~TARGET_PAGE_MASK);
|
---|
| 3923 | memcpy(buf, ptr, l);
|
---|
| 3924 | #endif
|
---|
| 3925 | }
|
---|
| 3926 | }
|
---|
| 3927 | len -= l;
|
---|
| 3928 | buf += l;
|
---|
| 3929 | addr += l;
|
---|
| 3930 | }
|
---|
| 3931 | }
|
---|
| 3932 |
|
---|
[2422] | 3933 | #ifndef VBOX
|
---|
[36170] | 3934 |
|
---|
[2422] | 3935 | /* used for ROM loading : can write in RAM and ROM */
|
---|
[6532] | 3936 | void cpu_physical_memory_write_rom(target_phys_addr_t addr,
|
---|
[2422] | 3937 | const uint8_t *buf, int len)
|
---|
| 3938 | {
|
---|
| 3939 | int l;
|
---|
| 3940 | uint8_t *ptr;
|
---|
| 3941 | target_phys_addr_t page;
|
---|
[42601] | 3942 | ram_addr_t pd;
|
---|
[2422] | 3943 | PhysPageDesc *p;
|
---|
[6532] | 3944 |
|
---|
[2422] | 3945 | while (len > 0) {
|
---|
| 3946 | page = addr & TARGET_PAGE_MASK;
|
---|
| 3947 | l = (page + TARGET_PAGE_SIZE) - addr;
|
---|
| 3948 | if (l > len)
|
---|
| 3949 | l = len;
|
---|
| 3950 | p = phys_page_find(page >> TARGET_PAGE_BITS);
|
---|
| 3951 | if (!p) {
|
---|
| 3952 | pd = IO_MEM_UNASSIGNED;
|
---|
| 3953 | } else {
|
---|
| 3954 | pd = p->phys_offset;
|
---|
| 3955 | }
|
---|
[6532] | 3956 |
|
---|
[2422] | 3957 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
|
---|
| 3958 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
|
---|
| 3959 | !(pd & IO_MEM_ROMD)) {
|
---|
| 3960 | /* do nothing */
|
---|
| 3961 | } else {
|
---|
[42601] | 3962 | ram_addr_t addr1;
|
---|
[2422] | 3963 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
---|
| 3964 | /* ROM/RAM case */
|
---|
[36175] | 3965 | ptr = qemu_get_ram_ptr(addr1);
|
---|
[2422] | 3966 | memcpy(ptr, buf, l);
|
---|
| 3967 | }
|
---|
| 3968 | len -= l;
|
---|
| 3969 | buf += l;
|
---|
| 3970 | addr += l;
|
---|
| 3971 | }
|
---|
| 3972 | }
|
---|
[36170] | 3973 |
|
---|
| 3974 | typedef struct {
|
---|
| 3975 | void *buffer;
|
---|
| 3976 | target_phys_addr_t addr;
|
---|
| 3977 | target_phys_addr_t len;
|
---|
| 3978 | } BounceBuffer;
|
---|
| 3979 |
|
---|
| 3980 | static BounceBuffer bounce;
|
---|
| 3981 |
|
---|
| 3982 | typedef struct MapClient {
|
---|
| 3983 | void *opaque;
|
---|
| 3984 | void (*callback)(void *opaque);
|
---|
[37675] | 3985 | QLIST_ENTRY(MapClient) link;
|
---|
[36170] | 3986 | } MapClient;
|
---|
| 3987 |
|
---|
[37675] | 3988 | static QLIST_HEAD(map_client_list, MapClient) map_client_list
|
---|
| 3989 | = QLIST_HEAD_INITIALIZER(map_client_list);
|
---|
[36170] | 3990 |
|
---|
| 3991 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque))
|
---|
| 3992 | {
|
---|
| 3993 | MapClient *client = qemu_malloc(sizeof(*client));
|
---|
| 3994 |
|
---|
| 3995 | client->opaque = opaque;
|
---|
| 3996 | client->callback = callback;
|
---|
[37675] | 3997 | QLIST_INSERT_HEAD(&map_client_list, client, link);
|
---|
[36170] | 3998 | return client;
|
---|
| 3999 | }
|
---|
| 4000 |
|
---|
| 4001 | void cpu_unregister_map_client(void *_client)
|
---|
| 4002 | {
|
---|
| 4003 | MapClient *client = (MapClient *)_client;
|
---|
| 4004 |
|
---|
[37675] | 4005 | QLIST_REMOVE(client, link);
|
---|
[36175] | 4006 | qemu_free(client);
|
---|
[36170] | 4007 | }
|
---|
| 4008 |
|
---|
| 4009 | static void cpu_notify_map_clients(void)
|
---|
| 4010 | {
|
---|
| 4011 | MapClient *client;
|
---|
| 4012 |
|
---|
[37675] | 4013 | while (!QLIST_EMPTY(&map_client_list)) {
|
---|
| 4014 | client = QLIST_FIRST(&map_client_list);
|
---|
[36170] | 4015 | client->callback(client->opaque);
|
---|
[36175] | 4016 | cpu_unregister_map_client(client);
|
---|
[36170] | 4017 | }
|
---|
| 4018 | }
|
---|
| 4019 |
|
---|
| 4020 | /* Map a physical memory region into a host virtual address.
|
---|
| 4021 | * May map a subset of the requested range, given by and returned in *plen.
|
---|
| 4022 | * May return NULL if resources needed to perform the mapping are exhausted.
|
---|
| 4023 | * Use only for reads OR writes - not for read-modify-write operations.
|
---|
| 4024 | * Use cpu_register_map_client() to know when retrying the map operation is
|
---|
| 4025 | * likely to succeed.
|
---|
| 4026 | */
|
---|
| 4027 | void *cpu_physical_memory_map(target_phys_addr_t addr,
|
---|
| 4028 | target_phys_addr_t *plen,
|
---|
| 4029 | int is_write)
|
---|
| 4030 | {
|
---|
| 4031 | target_phys_addr_t len = *plen;
|
---|
| 4032 | target_phys_addr_t done = 0;
|
---|
| 4033 | int l;
|
---|
| 4034 | uint8_t *ret = NULL;
|
---|
| 4035 | uint8_t *ptr;
|
---|
| 4036 | target_phys_addr_t page;
|
---|
[42601] | 4037 | ram_addr_t pd;
|
---|
[36170] | 4038 | PhysPageDesc *p;
|
---|
[42601] | 4039 | ram_addr_t addr1;
|
---|
[36170] | 4040 |
|
---|
| 4041 | while (len > 0) {
|
---|
| 4042 | page = addr & TARGET_PAGE_MASK;
|
---|
| 4043 | l = (page + TARGET_PAGE_SIZE) - addr;
|
---|
| 4044 | if (l > len)
|
---|
| 4045 | l = len;
|
---|
| 4046 | p = phys_page_find(page >> TARGET_PAGE_BITS);
|
---|
| 4047 | if (!p) {
|
---|
| 4048 | pd = IO_MEM_UNASSIGNED;
|
---|
| 4049 | } else {
|
---|
| 4050 | pd = p->phys_offset;
|
---|
| 4051 | }
|
---|
| 4052 |
|
---|
| 4053 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
---|
| 4054 | if (done || bounce.buffer) {
|
---|
| 4055 | break;
|
---|
| 4056 | }
|
---|
| 4057 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
|
---|
| 4058 | bounce.addr = addr;
|
---|
| 4059 | bounce.len = l;
|
---|
| 4060 | if (!is_write) {
|
---|
| 4061 | cpu_physical_memory_rw(addr, bounce.buffer, l, 0);
|
---|
| 4062 | }
|
---|
| 4063 | ptr = bounce.buffer;
|
---|
| 4064 | } else {
|
---|
| 4065 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
---|
[36175] | 4066 | ptr = qemu_get_ram_ptr(addr1);
|
---|
[36170] | 4067 | }
|
---|
| 4068 | if (!done) {
|
---|
| 4069 | ret = ptr;
|
---|
| 4070 | } else if (ret + done != ptr) {
|
---|
| 4071 | break;
|
---|
| 4072 | }
|
---|
| 4073 |
|
---|
| 4074 | len -= l;
|
---|
| 4075 | addr += l;
|
---|
| 4076 | done += l;
|
---|
| 4077 | }
|
---|
| 4078 | *plen = done;
|
---|
| 4079 | return ret;
|
---|
| 4080 | }
|
---|
| 4081 |
|
---|
| 4082 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map().
|
---|
| 4083 | * Will also mark the memory as dirty if is_write == 1. access_len gives
|
---|
| 4084 | * the amount of memory that was actually read or written by the caller.
|
---|
| 4085 | */
|
---|
| 4086 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
|
---|
| 4087 | int is_write, target_phys_addr_t access_len)
|
---|
| 4088 | {
|
---|
| 4089 | if (buffer != bounce.buffer) {
|
---|
| 4090 | if (is_write) {
|
---|
[36175] | 4091 | ram_addr_t addr1 = qemu_ram_addr_from_host(buffer);
|
---|
[36170] | 4092 | while (access_len) {
|
---|
| 4093 | unsigned l;
|
---|
| 4094 | l = TARGET_PAGE_SIZE;
|
---|
| 4095 | if (l > access_len)
|
---|
| 4096 | l = access_len;
|
---|
| 4097 | if (!cpu_physical_memory_is_dirty(addr1)) {
|
---|
| 4098 | /* invalidate code */
|
---|
| 4099 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
|
---|
| 4100 | /* set dirty bit */
|
---|
[37689] | 4101 | cpu_physical_memory_set_dirty_flags(
|
---|
| 4102 | addr1, (0xff & ~CODE_DIRTY_FLAG));
|
---|
[36170] | 4103 | }
|
---|
| 4104 | addr1 += l;
|
---|
| 4105 | access_len -= l;
|
---|
| 4106 | }
|
---|
| 4107 | }
|
---|
| 4108 | return;
|
---|
| 4109 | }
|
---|
| 4110 | if (is_write) {
|
---|
| 4111 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len);
|
---|
| 4112 | }
|
---|
[37675] | 4113 | qemu_vfree(bounce.buffer);
|
---|
[36170] | 4114 | bounce.buffer = NULL;
|
---|
| 4115 | cpu_notify_map_clients();
|
---|
| 4116 | }
|
---|
| 4117 |
|
---|
[2422] | 4118 | #endif /* !VBOX */
|
---|
| 4119 |
|
---|
[1] | 4120 | /* warning: addr must be aligned */
|
---|
| 4121 | uint32_t ldl_phys(target_phys_addr_t addr)
|
---|
| 4122 | {
|
---|
| 4123 | int io_index;
|
---|
| 4124 | uint8_t *ptr;
|
---|
| 4125 | uint32_t val;
|
---|
[42601] | 4126 | ram_addr_t pd;
|
---|
[1] | 4127 | PhysPageDesc *p;
|
---|
| 4128 |
|
---|
| 4129 | p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 4130 | if (!p) {
|
---|
| 4131 | pd = IO_MEM_UNASSIGNED;
|
---|
| 4132 | } else {
|
---|
| 4133 | pd = p->phys_offset;
|
---|
| 4134 | }
|
---|
[6532] | 4135 |
|
---|
| 4136 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
|
---|
[2422] | 4137 | !(pd & IO_MEM_ROMD)) {
|
---|
| 4138 | /* I/O case */
|
---|
| 4139 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
---|
[36170] | 4140 | if (p)
|
---|
| 4141 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
|
---|
[2422] | 4142 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
|
---|
| 4143 | } else {
|
---|
| 4144 | /* RAM case */
|
---|
| 4145 | #ifndef VBOX
|
---|
[36175] | 4146 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
|
---|
[2422] | 4147 | (addr & ~TARGET_PAGE_MASK);
|
---|
| 4148 | val = ldl_p(ptr);
|
---|
| 4149 | #else
|
---|
| 4150 | val = remR3PhysReadU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK)); NOREF(ptr);
|
---|
| 4151 | #endif
|
---|
| 4152 | }
|
---|
| 4153 | return val;
|
---|
| 4154 | }
|
---|
| 4155 |
|
---|
| 4156 | /* warning: addr must be aligned */
|
---|
| 4157 | uint64_t ldq_phys(target_phys_addr_t addr)
|
---|
| 4158 | {
|
---|
| 4159 | int io_index;
|
---|
| 4160 | uint8_t *ptr;
|
---|
| 4161 | uint64_t val;
|
---|
[42601] | 4162 | ram_addr_t pd;
|
---|
[2422] | 4163 | PhysPageDesc *p;
|
---|
| 4164 |
|
---|
| 4165 | p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 4166 | if (!p) {
|
---|
| 4167 | pd = IO_MEM_UNASSIGNED;
|
---|
| 4168 | } else {
|
---|
| 4169 | pd = p->phys_offset;
|
---|
| 4170 | }
|
---|
[6532] | 4171 |
|
---|
[1] | 4172 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
|
---|
[2422] | 4173 | !(pd & IO_MEM_ROMD)) {
|
---|
[1] | 4174 | /* I/O case */
|
---|
| 4175 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
---|
[36170] | 4176 | if (p)
|
---|
| 4177 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
|
---|
[2422] | 4178 | #ifdef TARGET_WORDS_BIGENDIAN
|
---|
| 4179 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
|
---|
| 4180 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
|
---|
| 4181 | #else
|
---|
[1] | 4182 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
|
---|
[2422] | 4183 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
|
---|
| 4184 | #endif
|
---|
[1] | 4185 | } else {
|
---|
| 4186 | /* RAM case */
|
---|
[2422] | 4187 | #ifndef VBOX
|
---|
[36175] | 4188 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
|
---|
[1] | 4189 | (addr & ~TARGET_PAGE_MASK);
|
---|
[2422] | 4190 | val = ldq_p(ptr);
|
---|
| 4191 | #else
|
---|
| 4192 | val = remR3PhysReadU64((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK)); NOREF(ptr);
|
---|
[1] | 4193 | #endif
|
---|
| 4194 | }
|
---|
| 4195 | return val;
|
---|
| 4196 | }
|
---|
| 4197 |
|
---|
[2422] | 4198 | /* XXX: optimize */
|
---|
| 4199 | uint32_t ldub_phys(target_phys_addr_t addr)
|
---|
| 4200 | {
|
---|
| 4201 | uint8_t val;
|
---|
| 4202 | cpu_physical_memory_read(addr, &val, 1);
|
---|
| 4203 | return val;
|
---|
| 4204 | }
|
---|
| 4205 |
|
---|
[37689] | 4206 | /* warning: addr must be aligned */
|
---|
[2422] | 4207 | uint32_t lduw_phys(target_phys_addr_t addr)
|
---|
| 4208 | {
|
---|
[37689] | 4209 | int io_index;
|
---|
[42601] | 4210 | #ifndef VBOX
|
---|
[37689] | 4211 | uint8_t *ptr;
|
---|
[42601] | 4212 | #endif
|
---|
[37689] | 4213 | uint64_t val;
|
---|
[42601] | 4214 | ram_addr_t pd;
|
---|
[37689] | 4215 | PhysPageDesc *p;
|
---|
| 4216 |
|
---|
| 4217 | p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 4218 | if (!p) {
|
---|
| 4219 | pd = IO_MEM_UNASSIGNED;
|
---|
| 4220 | } else {
|
---|
| 4221 | pd = p->phys_offset;
|
---|
| 4222 | }
|
---|
| 4223 |
|
---|
| 4224 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
|
---|
| 4225 | !(pd & IO_MEM_ROMD)) {
|
---|
| 4226 | /* I/O case */
|
---|
| 4227 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
---|
| 4228 | if (p)
|
---|
| 4229 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
|
---|
| 4230 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
|
---|
| 4231 | } else {
|
---|
| 4232 | /* RAM case */
|
---|
| 4233 | #ifndef VBOX
|
---|
| 4234 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
|
---|
| 4235 | (addr & ~TARGET_PAGE_MASK);
|
---|
| 4236 | val = lduw_p(ptr);
|
---|
| 4237 | #else
|
---|
| 4238 | val = remR3PhysReadU16((pd & TARGET_PAGE_MASK) | (addr & ~TARGET_PAGE_MASK));
|
---|
| 4239 | #endif
|
---|
| 4240 | }
|
---|
| 4241 | return val;
|
---|
[2422] | 4242 | }
|
---|
| 4243 |
|
---|
[1] | 4244 | /* warning: addr must be aligned. The ram page is not masked as dirty
|
---|
| 4245 | and the code inside is not invalidated. It is useful if the dirty
|
---|
| 4246 | bits are used to track modified PTEs */
|
---|
| 4247 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
|
---|
| 4248 | {
|
---|
| 4249 | int io_index;
|
---|
| 4250 | uint8_t *ptr;
|
---|
[42601] | 4251 | ram_addr_t pd;
|
---|
[1] | 4252 | PhysPageDesc *p;
|
---|
| 4253 |
|
---|
| 4254 | p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 4255 | if (!p) {
|
---|
| 4256 | pd = IO_MEM_UNASSIGNED;
|
---|
| 4257 | } else {
|
---|
| 4258 | pd = p->phys_offset;
|
---|
| 4259 | }
|
---|
[6532] | 4260 |
|
---|
[2422] | 4261 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
---|
[1] | 4262 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
---|
[36170] | 4263 | if (p)
|
---|
| 4264 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
|
---|
[1] | 4265 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
|
---|
| 4266 | } else {
|
---|
[2422] | 4267 | #ifndef VBOX
|
---|
[42601] | 4268 | ram_addr_t addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
---|
[36175] | 4269 | ptr = qemu_get_ram_ptr(addr1);
|
---|
[2422] | 4270 | stl_p(ptr, val);
|
---|
| 4271 | #else
|
---|
| 4272 | remR3PhysWriteU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
|
---|
[1] | 4273 | #endif
|
---|
[36170] | 4274 |
|
---|
[13559] | 4275 | #ifndef VBOX
|
---|
| 4276 | if (unlikely(in_migration)) {
|
---|
| 4277 | if (!cpu_physical_memory_is_dirty(addr1)) {
|
---|
| 4278 | /* invalidate code */
|
---|
| 4279 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
|
---|
| 4280 | /* set dirty bit */
|
---|
[37689] | 4281 | cpu_physical_memory_set_dirty_flags(
|
---|
| 4282 | addr1, (0xff & ~CODE_DIRTY_FLAG));
|
---|
[13559] | 4283 | }
|
---|
| 4284 | }
|
---|
[36140] | 4285 | #endif /* !VBOX */
|
---|
[1] | 4286 | }
|
---|
| 4287 | }
|
---|
| 4288 |
|
---|
[13559] | 4289 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
|
---|
| 4290 | {
|
---|
| 4291 | int io_index;
|
---|
| 4292 | uint8_t *ptr;
|
---|
[42601] | 4293 | ram_addr_t pd;
|
---|
[13559] | 4294 | PhysPageDesc *p;
|
---|
| 4295 |
|
---|
| 4296 | p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 4297 | if (!p) {
|
---|
| 4298 | pd = IO_MEM_UNASSIGNED;
|
---|
| 4299 | } else {
|
---|
| 4300 | pd = p->phys_offset;
|
---|
| 4301 | }
|
---|
| 4302 |
|
---|
| 4303 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
---|
| 4304 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
---|
[36170] | 4305 | if (p)
|
---|
| 4306 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
|
---|
[13559] | 4307 | #ifdef TARGET_WORDS_BIGENDIAN
|
---|
| 4308 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
|
---|
| 4309 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
|
---|
| 4310 | #else
|
---|
| 4311 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
|
---|
| 4312 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
|
---|
| 4313 | #endif
|
---|
| 4314 | } else {
|
---|
| 4315 | #ifndef VBOX
|
---|
[36175] | 4316 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
|
---|
[13559] | 4317 | (addr & ~TARGET_PAGE_MASK);
|
---|
| 4318 | stq_p(ptr, val);
|
---|
| 4319 | #else
|
---|
| 4320 | remR3PhysWriteU64((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
|
---|
| 4321 | #endif
|
---|
| 4322 | }
|
---|
| 4323 | }
|
---|
| 4324 |
|
---|
[1] | 4325 | /* warning: addr must be aligned */
|
---|
| 4326 | void stl_phys(target_phys_addr_t addr, uint32_t val)
|
---|
| 4327 | {
|
---|
| 4328 | int io_index;
|
---|
| 4329 | uint8_t *ptr;
|
---|
[42601] | 4330 | ram_addr_t pd;
|
---|
[1] | 4331 | PhysPageDesc *p;
|
---|
| 4332 |
|
---|
| 4333 | p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 4334 | if (!p) {
|
---|
| 4335 | pd = IO_MEM_UNASSIGNED;
|
---|
| 4336 | } else {
|
---|
| 4337 | pd = p->phys_offset;
|
---|
| 4338 | }
|
---|
[6532] | 4339 |
|
---|
[2422] | 4340 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
---|
[1] | 4341 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
---|
[36170] | 4342 | if (p)
|
---|
| 4343 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
|
---|
[1] | 4344 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
|
---|
| 4345 | } else {
|
---|
[42601] | 4346 | ram_addr_t addr1;
|
---|
[1] | 4347 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
---|
| 4348 | /* RAM case */
|
---|
[2422] | 4349 | #ifndef VBOX
|
---|
[36175] | 4350 | ptr = qemu_get_ram_ptr(addr1);
|
---|
[2422] | 4351 | stl_p(ptr, val);
|
---|
[1] | 4352 | #else
|
---|
[2422] | 4353 | remR3PhysWriteU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
|
---|
[1] | 4354 | #endif
|
---|
[2422] | 4355 | if (!cpu_physical_memory_is_dirty(addr1)) {
|
---|
| 4356 | /* invalidate code */
|
---|
| 4357 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
|
---|
| 4358 | /* set dirty bit */
|
---|
[37689] | 4359 | cpu_physical_memory_set_dirty_flags(addr1,
|
---|
| 4360 | (0xff & ~CODE_DIRTY_FLAG));
|
---|
[2422] | 4361 | }
|
---|
[1] | 4362 | }
|
---|
| 4363 | }
|
---|
| 4364 |
|
---|
[2422] | 4365 | /* XXX: optimize */
|
---|
| 4366 | void stb_phys(target_phys_addr_t addr, uint32_t val)
|
---|
| 4367 | {
|
---|
| 4368 | uint8_t v = val;
|
---|
| 4369 | cpu_physical_memory_write(addr, &v, 1);
|
---|
| 4370 | }
|
---|
| 4371 |
|
---|
[37689] | 4372 | /* warning: addr must be aligned */
|
---|
[2422] | 4373 | void stw_phys(target_phys_addr_t addr, uint32_t val)
|
---|
| 4374 | {
|
---|
[37689] | 4375 | int io_index;
|
---|
| 4376 | uint8_t *ptr;
|
---|
[42601] | 4377 | ram_addr_t pd;
|
---|
[37689] | 4378 | PhysPageDesc *p;
|
---|
| 4379 |
|
---|
| 4380 | p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
---|
| 4381 | if (!p) {
|
---|
| 4382 | pd = IO_MEM_UNASSIGNED;
|
---|
| 4383 | } else {
|
---|
| 4384 | pd = p->phys_offset;
|
---|
| 4385 | }
|
---|
| 4386 |
|
---|
| 4387 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
---|
| 4388 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
---|
| 4389 | if (p)
|
---|
| 4390 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
|
---|
| 4391 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
|
---|
| 4392 | } else {
|
---|
[42601] | 4393 | ram_addr_t addr1;
|
---|
[37689] | 4394 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
---|
| 4395 | /* RAM case */
|
---|
| 4396 | #ifndef VBOX
|
---|
| 4397 | ptr = qemu_get_ram_ptr(addr1);
|
---|
| 4398 | stw_p(ptr, val);
|
---|
| 4399 | #else
|
---|
| 4400 | remR3PhysWriteU16(addr1, val); NOREF(ptr);
|
---|
| 4401 | #endif
|
---|
| 4402 | if (!cpu_physical_memory_is_dirty(addr1)) {
|
---|
| 4403 | /* invalidate code */
|
---|
| 4404 | tb_invalidate_phys_page_range(addr1, addr1 + 2, 0);
|
---|
| 4405 | /* set dirty bit */
|
---|
| 4406 | cpu_physical_memory_set_dirty_flags(addr1,
|
---|
| 4407 | (0xff & ~CODE_DIRTY_FLAG));
|
---|
| 4408 | }
|
---|
| 4409 | }
|
---|
[2422] | 4410 | }
|
---|
| 4411 |
|
---|
| 4412 | /* XXX: optimize */
|
---|
| 4413 | void stq_phys(target_phys_addr_t addr, uint64_t val)
|
---|
| 4414 | {
|
---|
| 4415 | val = tswap64(val);
|
---|
| 4416 | cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
|
---|
| 4417 | }
|
---|
| 4418 |
|
---|
[36175] | 4419 | #ifndef VBOX
|
---|
| 4420 | /* virtual memory access for debug (includes writing to ROM) */
|
---|
[6532] | 4421 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
---|
[1] | 4422 | uint8_t *buf, int len, int is_write)
|
---|
| 4423 | {
|
---|
| 4424 | int l;
|
---|
[36140] | 4425 | target_phys_addr_t phys_addr;
|
---|
| 4426 | target_ulong page;
|
---|
[1] | 4427 |
|
---|
| 4428 | while (len > 0) {
|
---|
| 4429 | page = addr & TARGET_PAGE_MASK;
|
---|
| 4430 | phys_addr = cpu_get_phys_page_debug(env, page);
|
---|
| 4431 | /* if no physical page mapped, return an error */
|
---|
| 4432 | if (phys_addr == -1)
|
---|
| 4433 | return -1;
|
---|
| 4434 | l = (page + TARGET_PAGE_SIZE) - addr;
|
---|
| 4435 | if (l > len)
|
---|
| 4436 | l = len;
|
---|
[36175] | 4437 | phys_addr += (addr & ~TARGET_PAGE_MASK);
|
---|
| 4438 | if (is_write)
|
---|
| 4439 | cpu_physical_memory_write_rom(phys_addr, buf, l);
|
---|
| 4440 | else
|
---|
| 4441 | cpu_physical_memory_rw(phys_addr, buf, l, is_write);
|
---|
[1] | 4442 | len -= l;
|
---|
| 4443 | buf += l;
|
---|
| 4444 | addr += l;
|
---|
| 4445 | }
|
---|
| 4446 | return 0;
|
---|
| 4447 | }
|
---|
[36175] | 4448 | #endif /* !VBOX */
|
---|
[37689] | 4449 | #endif
|
---|
[1] | 4450 |
|
---|
[13559] | 4451 | /* in deterministic execution mode, instructions doing device I/Os
|
---|
| 4452 | must be at the end of the TB */
|
---|
| 4453 | void cpu_io_recompile(CPUState *env, void *retaddr)
|
---|
| 4454 | {
|
---|
| 4455 | TranslationBlock *tb;
|
---|
| 4456 | uint32_t n, cflags;
|
---|
| 4457 | target_ulong pc, cs_base;
|
---|
| 4458 | uint64_t flags;
|
---|
| 4459 |
|
---|
[42601] | 4460 | tb = tb_find_pc((uintptr_t)retaddr);
|
---|
[13559] | 4461 | if (!tb) {
|
---|
[15284] | 4462 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
|
---|
[13559] | 4463 | retaddr);
|
---|
| 4464 | }
|
---|
| 4465 | n = env->icount_decr.u16.low + tb->icount;
|
---|
[42601] | 4466 | cpu_restore_state(tb, env, (uintptr_t)retaddr, NULL);
|
---|
[13559] | 4467 | /* Calculate how many instructions had been executed before the fault
|
---|
| 4468 | occurred. */
|
---|
| 4469 | n = n - env->icount_decr.u16.low;
|
---|
| 4470 | /* Generate a new TB ending on the I/O insn. */
|
---|
| 4471 | n++;
|
---|
| 4472 | /* On MIPS and SH, delay slot instructions can only be restarted if
|
---|
| 4473 | they were already the first instruction in the TB. If this is not
|
---|
| 4474 | the first instruction in a TB then re-execute the preceding
|
---|
| 4475 | branch. */
|
---|
| 4476 | #if defined(TARGET_MIPS)
|
---|
| 4477 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
|
---|
| 4478 | env->active_tc.PC -= 4;
|
---|
| 4479 | env->icount_decr.u16.low++;
|
---|
| 4480 | env->hflags &= ~MIPS_HFLAG_BMASK;
|
---|
| 4481 | }
|
---|
| 4482 | #elif defined(TARGET_SH4)
|
---|
| 4483 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
|
---|
| 4484 | && n > 1) {
|
---|
| 4485 | env->pc -= 2;
|
---|
| 4486 | env->icount_decr.u16.low++;
|
---|
| 4487 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
|
---|
| 4488 | }
|
---|
| 4489 | #endif
|
---|
| 4490 | /* This should never happen. */
|
---|
| 4491 | if (n > CF_COUNT_MASK)
|
---|
| 4492 | cpu_abort(env, "TB too big during recompile");
|
---|
| 4493 |
|
---|
| 4494 | cflags = n | CF_LAST_IO;
|
---|
| 4495 | pc = tb->pc;
|
---|
| 4496 | cs_base = tb->cs_base;
|
---|
| 4497 | flags = tb->flags;
|
---|
| 4498 | tb_phys_invalidate(tb, -1);
|
---|
| 4499 | /* FIXME: In theory this could raise an exception. In practice
|
---|
| 4500 | we have already translated the block once so it's probably ok. */
|
---|
| 4501 | tb_gen_code(env, pc, cs_base, flags, cflags);
|
---|
[63568] | 4502 | /** @todo If env->pc != tb->pc (i.e. the faulting instruction was not
|
---|
[13559] | 4503 | the first in the TB) then we end up generating a whole new TB and
|
---|
| 4504 | repeating the fault, which is horribly inefficient.
|
---|
| 4505 | Better would be to execute just this insn uncached, or generate a
|
---|
| 4506 | second new TB. */
|
---|
| 4507 | cpu_resume_from_signal(env, NULL);
|
---|
| 4508 | }
|
---|
| 4509 |
|
---|
[37689] | 4510 | #if !defined(CONFIG_USER_ONLY)
|
---|
| 4511 |
|
---|
[13652] | 4512 | #ifndef VBOX
|
---|
[1] | 4513 | void dump_exec_info(FILE *f,
|
---|
| 4514 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
|
---|
| 4515 | {
|
---|
| 4516 | int i, target_code_size, max_target_code_size;
|
---|
| 4517 | int direct_jmp_count, direct_jmp2_count, cross_page;
|
---|
| 4518 | TranslationBlock *tb;
|
---|
[6532] | 4519 |
|
---|
[1] | 4520 | target_code_size = 0;
|
---|
| 4521 | max_target_code_size = 0;
|
---|
| 4522 | cross_page = 0;
|
---|
| 4523 | direct_jmp_count = 0;
|
---|
| 4524 | direct_jmp2_count = 0;
|
---|
| 4525 | for(i = 0; i < nb_tbs; i++) {
|
---|
| 4526 | tb = &tbs[i];
|
---|
| 4527 | target_code_size += tb->size;
|
---|
| 4528 | if (tb->size > max_target_code_size)
|
---|
| 4529 | max_target_code_size = tb->size;
|
---|
| 4530 | if (tb->page_addr[1] != -1)
|
---|
| 4531 | cross_page++;
|
---|
| 4532 | if (tb->tb_next_offset[0] != 0xffff) {
|
---|
| 4533 | direct_jmp_count++;
|
---|
| 4534 | if (tb->tb_next_offset[1] != 0xffff) {
|
---|
| 4535 | direct_jmp2_count++;
|
---|
| 4536 | }
|
---|
| 4537 | }
|
---|
| 4538 | }
|
---|
| 4539 | /* XXX: avoid using doubles ? */
|
---|
[13559] | 4540 | cpu_fprintf(f, "Translation buffer state:\n");
|
---|
| 4541 | cpu_fprintf(f, "gen code size %ld/%ld\n",
|
---|
| 4542 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
|
---|
[15284] | 4543 | cpu_fprintf(f, "TB count %d/%d\n",
|
---|
[13559] | 4544 | nb_tbs, code_gen_max_blocks);
|
---|
[6532] | 4545 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
|
---|
[1] | 4546 | nb_tbs ? target_code_size / nb_tbs : 0,
|
---|
| 4547 | max_target_code_size);
|
---|
[6532] | 4548 | cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
|
---|
[1] | 4549 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
|
---|
| 4550 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
|
---|
[6532] | 4551 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
|
---|
| 4552 | cross_page,
|
---|
[1] | 4553 | nb_tbs ? (cross_page * 100) / nb_tbs : 0);
|
---|
| 4554 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
|
---|
[6532] | 4555 | direct_jmp_count,
|
---|
[1] | 4556 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
|
---|
| 4557 | direct_jmp2_count,
|
---|
| 4558 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
|
---|
[13559] | 4559 | cpu_fprintf(f, "\nStatistics:\n");
|
---|
[1] | 4560 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
|
---|
| 4561 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
|
---|
| 4562 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
|
---|
[13559] | 4563 | tcg_dump_info(f, cpu_fprintf);
|
---|
[1] | 4564 | }
|
---|
| 4565 | #endif /* !VBOX */
|
---|
| 4566 |
|
---|
| 4567 | #define MMUSUFFIX _cmmu
|
---|
| 4568 | #define GETPC() NULL
|
---|
| 4569 | #define env cpu_single_env
|
---|
| 4570 | #define SOFTMMU_CODE_ACCESS
|
---|
| 4571 |
|
---|
| 4572 | #define SHIFT 0
|
---|
| 4573 | #include "softmmu_template.h"
|
---|
| 4574 |
|
---|
| 4575 | #define SHIFT 1
|
---|
| 4576 | #include "softmmu_template.h"
|
---|
| 4577 |
|
---|
| 4578 | #define SHIFT 2
|
---|
| 4579 | #include "softmmu_template.h"
|
---|
| 4580 |
|
---|
| 4581 | #define SHIFT 3
|
---|
| 4582 | #include "softmmu_template.h"
|
---|
| 4583 |
|
---|
| 4584 | #undef env
|
---|
| 4585 |
|
---|
| 4586 | #endif
|
---|