1 | ; $Id: bs3-cpu-weird-1-template.mac 102789 2024-01-08 21:48:55Z vboxsync $
|
---|
2 | ;; @file
|
---|
3 | ; BS3Kit - bs3-cpu-weird-1 assembly template.
|
---|
4 | ;
|
---|
5 |
|
---|
6 | ;
|
---|
7 | ; Copyright (C) 2007-2023 Oracle and/or its affiliates.
|
---|
8 | ;
|
---|
9 | ; This file is part of VirtualBox base platform packages, as
|
---|
10 | ; available from https://www.virtualbox.org.
|
---|
11 | ;
|
---|
12 | ; This program is free software; you can redistribute it and/or
|
---|
13 | ; modify it under the terms of the GNU General Public License
|
---|
14 | ; as published by the Free Software Foundation, in version 3 of the
|
---|
15 | ; License.
|
---|
16 | ;
|
---|
17 | ; This program is distributed in the hope that it will be useful, but
|
---|
18 | ; WITHOUT ANY WARRANTY; without even the implied warranty of
|
---|
19 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
---|
20 | ; General Public License for more details.
|
---|
21 | ;
|
---|
22 | ; You should have received a copy of the GNU General Public License
|
---|
23 | ; along with this program; if not, see <https://www.gnu.org/licenses>.
|
---|
24 | ;
|
---|
25 | ; The contents of this file may alternatively be used under the terms
|
---|
26 | ; of the Common Development and Distribution License Version 1.0
|
---|
27 | ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
|
---|
28 | ; in the VirtualBox distribution, in which case the provisions of the
|
---|
29 | ; CDDL are applicable instead of those of the GPL.
|
---|
30 | ;
|
---|
31 | ; You may elect to license modified versions of this file under the
|
---|
32 | ; terms and conditions of either the GPL or the CDDL or both.
|
---|
33 | ;
|
---|
34 | ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
|
---|
35 | ;
|
---|
36 |
|
---|
37 |
|
---|
38 | ;*********************************************************************************************************************************
|
---|
39 | ;* Header Files *
|
---|
40 | ;*********************************************************************************************************************************
|
---|
41 | %include "bs3kit-template-header.mac" ; setup environment
|
---|
42 |
|
---|
43 |
|
---|
44 | ;*********************************************************************************************************************************
|
---|
45 | ;* External Symbols *
|
---|
46 | ;*********************************************************************************************************************************
|
---|
47 | TMPL_BEGIN_TEXT
|
---|
48 |
|
---|
49 |
|
---|
50 | ;
|
---|
51 | ; Test code snippets containing code which differs between 16-bit, 32-bit
|
---|
52 | ; and 64-bit CPUs modes.
|
---|
53 | ;
|
---|
54 | %ifdef BS3_INSTANTIATING_CMN
|
---|
55 |
|
---|
56 |
|
---|
57 | ;
|
---|
58 | ; Inhibited int 80h.
|
---|
59 | ;
|
---|
60 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedInt80, BS3_PBC_NEAR
|
---|
61 | ; Load SS from stack. This instruction causes fusing.
|
---|
62 | %if TMPL_BITS != 64
|
---|
63 | pop ss
|
---|
64 | %else
|
---|
65 | mov ss, [rsp]
|
---|
66 | %endif
|
---|
67 | ; The ring transition instruction.
|
---|
68 | BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedInt80_int80), , 0
|
---|
69 | int 80h
|
---|
70 | ; We shouldn't get here!
|
---|
71 | .ud2_again:
|
---|
72 | ud2
|
---|
73 | jmp .ud2_again
|
---|
74 | BS3_PROC_END_CMN bs3CpuWeird1_InhibitedInt80
|
---|
75 |
|
---|
76 | ;
|
---|
77 | ; Inhibited int 3.
|
---|
78 | ;
|
---|
79 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedInt3, BS3_PBC_NEAR
|
---|
80 | ; Load SS from stack. This instruction causes fusing.
|
---|
81 | %if TMPL_BITS != 64
|
---|
82 | pop ss
|
---|
83 | %else
|
---|
84 | mov ss, [rsp]
|
---|
85 | %endif
|
---|
86 | ; The ring transition instruction.
|
---|
87 | BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedInt3_int3), , 0
|
---|
88 | int 3
|
---|
89 | ; We shouldn't get here!
|
---|
90 | .ud2_again:
|
---|
91 | ud2
|
---|
92 | jmp .ud2_again
|
---|
93 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_InhibitedInt3_int3) == 2)
|
---|
94 | BS3_PROC_END_CMN bs3CpuWeird1_InhibitedInt3
|
---|
95 |
|
---|
96 |
|
---|
97 | ;
|
---|
98 | ; Inhibited int3.
|
---|
99 | ;
|
---|
100 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedBp, BS3_PBC_NEAR
|
---|
101 | ; Load SS from stack. This instruction causes fusing.
|
---|
102 | %if TMPL_BITS != 64
|
---|
103 | pop ss
|
---|
104 | %else
|
---|
105 | mov ss, [rsp]
|
---|
106 | %endif
|
---|
107 | ; The ring transition instruction.
|
---|
108 | BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedBp_int3), , 0
|
---|
109 | int3
|
---|
110 | ; We shouldn't get here!
|
---|
111 | .ud2_again:
|
---|
112 | ud2
|
---|
113 | jmp .ud2_again
|
---|
114 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_InhibitedBp_int3) == 1)
|
---|
115 | BS3_PROC_END_CMN bs3CpuWeird1_InhibitedBp
|
---|
116 |
|
---|
117 |
|
---|
118 | ;
|
---|
119 | ; PC (IP/EIP) wrapper templates.
|
---|
120 | ; These will potentially trigger VM exits, except for the benign one.
|
---|
121 | ;
|
---|
122 | ; Note! Single instructions as the testcase will shift multibyte variations
|
---|
123 | ; across the wrap-around boundary and that would cause unpredictable
|
---|
124 | ; results for the 16-bit if there is more than one instruction.
|
---|
125 | ;
|
---|
126 |
|
---|
127 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapBenign1, BS3_PBC_NEAR
|
---|
128 | nop
|
---|
129 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapBenign1
|
---|
130 |
|
---|
131 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapBenign2, BS3_PBC_NEAR
|
---|
132 | xor xDX, xAX
|
---|
133 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapBenign2
|
---|
134 |
|
---|
135 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapCpuId, BS3_PBC_NEAR
|
---|
136 | cpuid
|
---|
137 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapCpuId
|
---|
138 |
|
---|
139 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapIn80, BS3_PBC_NEAR
|
---|
140 | in al, 80h
|
---|
141 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapIn80
|
---|
142 |
|
---|
143 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapOut80, BS3_PBC_NEAR
|
---|
144 | out 80h, al
|
---|
145 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapOut80
|
---|
146 |
|
---|
147 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapSmsw, BS3_PBC_NEAR
|
---|
148 | smsw si
|
---|
149 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapSmsw
|
---|
150 |
|
---|
151 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapRdCr0, BS3_PBC_NEAR
|
---|
152 | mov sAX, cr0
|
---|
153 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapRdCr0
|
---|
154 |
|
---|
155 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapRdDr0, BS3_PBC_NEAR
|
---|
156 | mov sAX, dr0
|
---|
157 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapRdDr0
|
---|
158 |
|
---|
159 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapWrDr0, BS3_PBC_NEAR
|
---|
160 | mov dr0, sAX
|
---|
161 | BS3_PROC_END_CMN bs3CpuWeird1_PcWrapWrDr0
|
---|
162 |
|
---|
163 |
|
---|
164 | ;
|
---|
165 | ; PUSH / POP.
|
---|
166 | ;
|
---|
167 |
|
---|
168 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_xSP_Ud2, BS3_PBC_NEAR
|
---|
169 | push xSP
|
---|
170 | .ud2_again:
|
---|
171 | ud2
|
---|
172 | jmp .ud2_again
|
---|
173 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_xSP_Ud2) == 1)
|
---|
174 | BS3_PROC_END_CMN bs3CpuWeird1_Push_xSP_Ud2
|
---|
175 |
|
---|
176 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_xSP_Ud2, BS3_PBC_NEAR
|
---|
177 | pop xSP
|
---|
178 | .ud2_again:
|
---|
179 | ud2
|
---|
180 | jmp .ud2_again
|
---|
181 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_xSP_Ud2) == 1)
|
---|
182 | BS3_PROC_END_CMN bs3CpuWeird1_Pop_xSP_Ud2
|
---|
183 |
|
---|
184 |
|
---|
185 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_opsize_xSP_Ud2, BS3_PBC_NEAR
|
---|
186 | db 066h
|
---|
187 | push xSP
|
---|
188 | .ud2_again:
|
---|
189 | ud2
|
---|
190 | jmp .ud2_again
|
---|
191 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_opsize_xSP_Ud2) == 2)
|
---|
192 | BS3_PROC_END_CMN bs3CpuWeird1_Push_opsize_xSP_Ud2
|
---|
193 |
|
---|
194 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_opsize_xSP_Ud2, BS3_PBC_NEAR
|
---|
195 | db 066h
|
---|
196 | pop xSP
|
---|
197 | .ud2_again:
|
---|
198 | ud2
|
---|
199 | jmp .ud2_again
|
---|
200 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_opsize_xSP_Ud2) == 2)
|
---|
201 | BS3_PROC_END_CMN bs3CpuWeird1_Pop_opsize_xSP_Ud2
|
---|
202 |
|
---|
203 |
|
---|
204 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_opsize_xBX_Ud2, BS3_PBC_NEAR
|
---|
205 | db 066h
|
---|
206 | push xBX
|
---|
207 | .ud2_again:
|
---|
208 | ud2
|
---|
209 | jmp .ud2_again
|
---|
210 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_opsize_xBX_Ud2) == 2)
|
---|
211 | BS3_PROC_END_CMN bs3CpuWeird1_Push_opsize_xBX_Ud2
|
---|
212 |
|
---|
213 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_opsize_xBX_Ud2, BS3_PBC_NEAR
|
---|
214 | db 066h
|
---|
215 | pop xBX
|
---|
216 | .ud2_again:
|
---|
217 | ud2
|
---|
218 | jmp .ud2_again
|
---|
219 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_opsize_xBX_Ud2) == 2)
|
---|
220 | BS3_PROC_END_CMN bs3CpuWeird1_Pop_opsize_xBX_Ud2
|
---|
221 |
|
---|
222 |
|
---|
223 | ;
|
---|
224 | ; PUSH / POP SREG.
|
---|
225 | ;
|
---|
226 |
|
---|
227 | %ifndef DEFINED_DO_PUSH_POP_MACROS
|
---|
228 | %define DEFINED_DO_PUSH_POP_MACROS
|
---|
229 | %macro DoPushSeg 2
|
---|
230 |
|
---|
231 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
|
---|
232 | push %1
|
---|
233 | .ud2_again:
|
---|
234 | ud2
|
---|
235 | jmp .ud2_again
|
---|
236 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_ %+ %1 %+ _Ud2) == %2)
|
---|
237 | BS3_PROC_END_CMN bs3CpuWeird1_Push_ %+ %1 %+ _Ud2
|
---|
238 |
|
---|
239 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
|
---|
240 | db 066h
|
---|
241 | push %1
|
---|
242 | .ud2_again:
|
---|
243 | ud2
|
---|
244 | jmp .ud2_again
|
---|
245 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2) == (%2 + 1))
|
---|
246 | BS3_PROC_END_CMN bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2
|
---|
247 |
|
---|
248 | %endmacro ; DoPushSeg
|
---|
249 |
|
---|
250 | %macro DoPopSeg 2
|
---|
251 |
|
---|
252 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
|
---|
253 | pop %1
|
---|
254 | .ud2_again:
|
---|
255 | ud2
|
---|
256 | jmp .ud2_again
|
---|
257 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2) == %2)
|
---|
258 | BS3_PROC_END_CMN bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2
|
---|
259 |
|
---|
260 | BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
|
---|
261 | db 066h
|
---|
262 | pop %1
|
---|
263 | .ud2_again:
|
---|
264 | ud2
|
---|
265 | jmp .ud2_again
|
---|
266 | AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2) == (%2 + 1))
|
---|
267 | BS3_PROC_END_CMN bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2
|
---|
268 |
|
---|
269 | %endmacro ; DoPopSeg
|
---|
270 | %endif ; !DEFINED_DO_PUSH_POP_MACROS
|
---|
271 |
|
---|
272 | DoPushSeg fs, 2
|
---|
273 | DoPopSeg fs, 2
|
---|
274 | DoPushSeg gs, 2
|
---|
275 | DoPopSeg gs, 2
|
---|
276 | %if TMPL_BITS == 32 || TMPL_BITS == 16
|
---|
277 | DoPushSeg es, 1
|
---|
278 | DoPopSeg es, 1
|
---|
279 | DoPushSeg ds, 1
|
---|
280 | DoPopSeg ds, 1
|
---|
281 | DoPushSeg ss, 1
|
---|
282 | DoPopSeg ss, 1
|
---|
283 | DoPushSeg cs, 1
|
---|
284 | %endif
|
---|
285 |
|
---|
286 | %endif ; BS3_INSTANTIATING_CMN
|
---|
287 |
|
---|
288 | %include "bs3kit-template-footer.mac" ; reset environment
|
---|
289 |
|
---|