1  ; $Id: bs3cpuinstr2template.mac 98828 20230303 12:03:11Z vboxsync $


2  ;; @file


3  ; BS3Kit  bs3cpuinstr2 assembly template.


4  ;


5 


6  ;


7  ; Copyright (C) 20072023 Oracle and/or its affiliates.


8  ;


9  ; This file is part of VirtualBox base platform packages, as


10  ; available from https://www.virtualbox.org.


11  ;


12  ; This program is free software; you can redistribute it and/or


13  ; modify it under the terms of the GNU General Public License


14  ; as published by the Free Software Foundation, in version 3 of the


15  ; License.


16  ;


17  ; This program is distributed in the hope that it will be useful, but


18  ; WITHOUT ANY WARRANTY; without even the implied warranty of


19  ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU


20  ; General Public License for more details.


21  ;


22  ; You should have received a copy of the GNU General Public License


23  ; along with this program; if not, see <https://www.gnu.org/licenses>.


24  ;


25  ; The contents of this file may alternatively be used under the terms


26  ; of the Common Development and Distribution License Version 1.0


27  ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included


28  ; in the VirtualBox distribution, in which case the provisions of the


29  ; CDDL are applicable instead of those of the GPL.


30  ;


31  ; You may elect to license modified versions of this file under the


32  ; terms and conditions of either the GPL or the CDDL or both.


33  ;


34  ; SPDXLicenseIdentifier: GPL3.0only OR CDDL1.0


35  ;


36 


37 


38  ;*********************************************************************************************************************************


39  ;* Header Files *


40  ;*********************************************************************************************************************************


41  %include "bs3kittemplateheader.mac" ; setup environment


42 


43 


44  ;*********************************************************************************************************************************


45  ;* Defined Constants And Macros *


46  ;*********************************************************************************************************************************


47  ;;


48  ; Variant on BS3_PROC_BEGIN_CMN w/ BS3_PBC_NEAR that prefixes the function


49  ; with an instruction length byte.


50  ;


51  ; ASSUMES the length is between the start of the function and the .again label.


52  ;


53  %ifndef BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED


54  %define BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED


55  %macro BS3CPUINSTR2_PROC_BEGIN_CMN 1


56  align 8, db 0cch


57  db BS3_CMN_NM(%1).again  BS3_CMN_NM(%1)


58  BS3_PROC_BEGIN_CMN %1, BS3_PBC_NEAR


59  %endmacro


60  %endif


61 


62 


63  ;*********************************************************************************************************************************


64  ;* External Symbols *


65  ;*********************************************************************************************************************************


66  TMPL_BEGIN_TEXT


67 


68 


69  ;


70  ; Test code snippets containing code which differs between 16bit, 32bit


71  ; and 64bit CPUs modes.


72  ;


73  %ifdef BS3_INSTANTIATING_CMN


74 


75  BS3_PROC_BEGIN_CMN bs3CpuInstr2_mul_xBX_ud2, BS3_PBC_NEAR


76  mul xBX


77  .again:


78  ud2


79  jmp .again


80  BS3_PROC_END_CMN bs3CpuInstr2_mul_xBX_ud2


81 


82 


83  BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xBX_ud2, BS3_PBC_NEAR


84  imul xBX


85  .again:


86  ud2


87  jmp .again


88  BS3_PROC_END_CMN bs3CpuInstr2_imul_xBX_ud2


89 


90 


91  BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xCX_xBX_ud2, BS3_PBC_NEAR


92  imul xCX, xBX


93  .again:


94  ud2


95  jmp .again


96  BS3_PROC_END_CMN bs3CpuInstr2_imul_xCX_xBX_ud2


97 


98 


99  BS3_PROC_BEGIN_CMN bs3CpuInstr2_div_xBX_ud2, BS3_PBC_NEAR


100  div xBX


101  .again:


102  ud2


103  jmp .again


104  BS3_PROC_END_CMN bs3CpuInstr2_div_xBX_ud2


105 


106 


107  BS3_PROC_BEGIN_CMN bs3CpuInstr2_idiv_xBX_ud2, BS3_PBC_NEAR


108  idiv xBX


109  .again:


110  ud2


111  jmp .again


112  BS3_PROC_END_CMN bs3CpuInstr2_idiv_xBX_ud2


113 


114 


115  ;


116  ; BSF / BSR / TZCNT / LZCNT


117  ;


118  %ifndef EMIT_BITSCAN_DEFINED


119  %define EMIT_BITSCAN_DEFINED


120  %macro EMIT_BITSCAN 3


121  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2, BS3_PBC_NEAR


122  %2


123  %1 ax, bx


124  .again:


125  ud2


126  jmp .again


127  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2


128 


129  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2, BS3_PBC_NEAR


130  %2


131  %1 ax, [fs:xBX]


132  .again:


133  ud2


134  jmp .again


135  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2


136 


137  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2, BS3_PBC_NEAR


138  %2


139  %1 eax, ebx


140  .again:


141  ud2


142  jmp .again


143  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2


144 


145  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2, BS3_PBC_NEAR


146  %2


147  %1 eax, [fs:xBX]


148  .again:


149  ud2


150  jmp .again


151  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2


152 


153  %if TMPL_BITS == 64


154  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2, BS3_PBC_NEAR


155  %2


156  %1 rax, rbx


157  .again:


158  ud2


159  jmp .again


160  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2


161 


162  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2, BS3_PBC_NEAR


163  %2


164  %1 rax, [fs:xBX]


165  .again:


166  ud2


167  jmp .again


168  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2


169  %endif


170  %endmacro


171  %endif


172 


173  EMIT_BITSCAN bsf, .ignored:, bsf


174  EMIT_BITSCAN bsr, .ignored:, bsr


175  EMIT_BITSCAN tzcnt, .ignored:, tzcnt


176  EMIT_BITSCAN lzcnt, .ignored:, lzcnt


177  EMIT_BITSCAN bsf, db 0f2h, f2_bsf


178  EMIT_BITSCAN bsr, db 0f2h, f2_bsr


179  EMIT_BITSCAN tzcnt, db 0f2h, f2_tzcnt


180  EMIT_BITSCAN lzcnt, db 0f2h, f2_lzcnt


181 


182 


183  ;


184  ; RORX  VEX instruction with a couple of questions about nonstandard encodings.


185  ;


186  ;;%define icebp ud2


187  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp, BS3_PBC_NEAR


188  rorx ebx, edx, 2


189  .again:


190  icebp


191  jmp .again


192  BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp


193 


194  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp, BS3_PBC_NEAR


195  %if TMPL_BITS == 64


196  rorx rbx, rdx, 2


197  %else


198  db 0C4h,0E3h,0FBh,0F0h,0DAh,002h ; 32bit ignores VEX.W=1 (10980xe)


199  %endif


200  .again:


201  icebp


202  jmp .again


203  BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp


204 


205  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1, BS3_PBC_NEAR


206  db 0C4h, 0E3h, 07Bh  4h, 0F0h, 0DAh, 002h ; VEX.L=1 should #UD according to the docs


207  .again:


208  icebp


209  jmp .again


210  BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1


211 


212  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1, BS3_PBC_NEAR


213  db 0C4h, 0E3h, 003h  ~(1 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=1  behaviour is undocumented  10980xe #UD


214  .again:


215  icebp


216  jmp .again


217  BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1


218 


219  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15, BS3_PBC_NEAR


220  db 0C4h, 0E3h, 003h  ~(15 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=15  behaviour is not documented  10980xe #UD


221  .again:


222  icebp


223  jmp .again


224  BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15


225 


226  %if TMPL_BITS == 64


227  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1, BS3_PBC_NEAR


228  db 0C4h, 0E3h & ~40h, 07Bh, 0F0h, 0DAh, 002h ; VEX.X=0  behaviour is not documented  ignored by 10980xe


229  .again:


230  icebp


231  jmp .again


232  BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1


233  %endif


234 


235  ; A couple of memory variants


236  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp, BS3_PBC_NEAR


237  rorx ebx, [xDI], 36


238  .again:


239  icebp


240  jmp .again


241  BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp


242 


243  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp, BS3_PBC_NEAR


244  %if TMPL_BITS == 64


245  rorx rbx, [xDI], 68


246  %elif TMPL_BITS == 32


247  db 0C4h,0E3h,07Bh,0F0h,01Fh,044h ; 16bit ignores VEX.W=1 (10980xe)


248  %else


249  db 0C4h,0E3h,0FBh,0F0h,01Dh,044h ; 16bit ignores VEX.W=1 (10980xe)


250  %endif


251  .again:


252  icebp


253  jmp .again


254  BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp


255 


256  ;


257  ; ANDN (BMI1)


258  ;


259  BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp, BS3_PBC_NEAR


260  %if TMPL_BITS == 64


261  andn rax, rcx, rbx


262  %else


263  db 0C4h,0E2h,0F0h,0F2h,0C3h ; 32bit & 16bit ignores VEX.W=1 (10980xe)


264  %endif


265  .again:


266  icebp


267  jmp .again


268  BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp


269 


270  BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp, BS3_PBC_NEAR


271  andn eax, ecx, ebx


272  .again:


273  icebp


274  jmp .again


275  BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp


276 


277 


278  BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR


279  %if TMPL_BITS == 64


280  andn rax, rcx, [fs:rbx]


281  %elif TMPL_BITS == 32


282  db 064h,0C4h,0E2h,0F0h,0F2h,003h ; andn rax, rcx, [fs:ebx]


283  %else


284  db 064h,0C4h,0E2h,0F0h,0F2h,007h ; andn rax, rcx, [fs:bx]


285  %endif


286  .again:


287  icebp


288  jmp .again


289  BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp


290 


291  BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR


292  andn eax, ecx, [fs:xBX]


293  .again:


294  icebp


295  jmp .again


296  BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp


297 


298 


299  ;


300  ; BEXTR / SHLX / SARX / SHRX  BMI1 (opcode f7h)


301  ; BZHI  BMI2 (opcode f5h)


302  ;


303  ; @param %1 instruction


304  ; @param %2 opcode


305  ; @param %3 prefix


306  ;


307  %ifndef SHLX_SARX_SHRX_DEFINED


308  %define SHLX_SARX_SHRX_DEFINED


309  %macro SHLX_SARX_SHRX 3


310 


311  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp, BS3_PBC_NEAR


312  %if TMPL_BITS == 64


313  %1 rax, rbx, rcx ; SHLX=C4E2F1F7C3


314  %else


315  db 0C4h,0E2h,0F0h%3,%2,0C3h ; 32bit & 16bit ignores VEX.W=1 (10980xe)


316  %endif


317  .again:


318  icebp


319  jmp .again


320  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp


321 


322  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp, BS3_PBC_NEAR


323  %1 eax, ebx, ecx


324  .again:


325  icebp


326  jmp .again


327  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp


328 


329  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp, BS3_PBC_NEAR


330  %if TMPL_BITS == 64


331  %1 rax, [fs:rbx], rcx ; SHLX=64C4E2F1F703


332  %elif TMPL_BITS == 32


333  db 064h,0C4h,0E2h,0F0h%3,%2,003h


334  %else


335  db 064h,0C4h,0E2h,0F0h%3,%2,007h


336  %endif


337  .again:


338  icebp


339  jmp .again


340  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp


341 


342  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp, BS3_PBC_NEAR


343  %1 eax, [fs:xBX], ecx


344  .again:


345  icebp


346  jmp .again


347  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp


348 


349  %endmacro


350  %endif


351 


352  SHLX_SARX_SHRX bextr, 0f7h, 0 ; none


353  SHLX_SARX_SHRX shlx, 0f7h, 1 ; 66h


354  SHLX_SARX_SHRX sarx, 0f7h, 2 ; f3h


355  SHLX_SARX_SHRX shrx, 0f7h, 3 ; f2h


356  SHLX_SARX_SHRX bzhi, 0f5h, 0 ; none


357 


358  ;


359  ; PPEP / PEXT  BMI2 (opcode f5h)


360  ;


361  ; @param %1 instruction


362  ; @param %2 opcode


363  ; @param %3 prefix


364  ;


365  %ifndef PDEP_PEXT_DEFINED


366  %define PDEP_PEXT_DEFINED


367  %macro PDEP_PEXT_ 3


368 


369  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp, BS3_PBC_NEAR


370  %if TMPL_BITS == 64


371  %1 rax, rcx, rbx


372  %else


373  db 0C4h,0E2h,0F0h%3,%2,0C3h ; 32bit & 16bit ignores VEX.W=1 (10980xe)


374  %endif


375  .again:


376  icebp


377  jmp .again


378  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp


379 


380  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp, BS3_PBC_NEAR


381  %1 eax, ecx, ebx


382  .again:


383  icebp


384  jmp .again


385  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp


386 


387  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR


388  %if TMPL_BITS == 64


389  %1 rax, rcx, [fs:rbx]


390  %elif TMPL_BITS == 32


391  db 064h,0C4h,0E2h,0F0h%3,%2,003h


392  %else


393  db 064h,0C4h,0E2h,0F0h%3,%2,007h


394  %endif


395  .again:


396  icebp


397  jmp .again


398  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp


399 


400  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR


401  %1 eax, ecx, [fs:xBX]


402  .again:


403  icebp


404  jmp .again


405  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp


406 


407  %endmacro


408  %endif


409 


410  PDEP_PEXT_ pext, 0f5h, 2 ; f3h


411  PDEP_PEXT_ pdep, 0f5h, 3 ; f2h


412 


413  ;


414  ; BLSR / BLSMSK / BLSI


415  ; These are encoded in the exact same way, only the /r differs (%2).


416  ;


417  %ifndef BLSR_BLSMSK_BLSI_DEFINED


418  %define BLSR_BLSMSK_BLSI_DEFINED


419  %macro BLSR_BLSMSK_BLSI 2


420 


421  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp, BS3_PBC_NEAR


422  %if TMPL_BITS == 64


423  %1 rax, rbx ; BLSR=C4E2F8F3CB


424  %else


425  db 0C4h,0E2h,0F8h,0F3h,0C3h  (%2 << 3) ; 32bit & 16bit ignores VEX.W=1 (10980xe)


426  %endif


427  .again:


428  icebp


429  jmp .again


430  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp


431 


432  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp, BS3_PBC_NEAR


433  %1 eax, ebx


434  .again:


435  icebp


436  jmp .again


437  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp


438 


439  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp, BS3_PBC_NEAR


440  %if TMPL_BITS == 64


441  %1 rax, [fs:rbx] ; BSLR=64C4E2F8F30B


442  %elif TMPL_BITS == 32


443  db 064h,0C4h,0E2h,0F8h,0F3h,003h  (%2 << 3)


444  %else


445  db 064h,0C4h,0E2h,0F8h,0F3h,007h  (%2 << 3)


446  %endif


447  .again:


448  icebp


449  jmp .again


450  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp


451 


452  BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp, BS3_PBC_NEAR


453  %1 eax, [fs:xBX]


454  .again:


455  icebp


456  jmp .again


457  BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp


458 


459  %endmacro


460  %endif


461 


462  BLSR_BLSMSK_BLSI blsr, 1


463  BLSR_BLSMSK_BLSI blsmsk, 2


464  BLSR_BLSMSK_BLSI blsi, 3


465 


466  ;


467  ; MULX


468  ;


469  BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR


470  %if TMPL_BITS == 64


471  mulx rax, rcx, rbx ; C4E2F3F6C3


472  %else


473  db 0C4h,0E2h,0F3h,0F6h,0C3h ; 32bit & 16bit ignores VEX.W=1 (10980xe)


474  %endif


475  .again:


476  icebp


477  jmp .again


478  BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp


479 


480  BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR


481  %if TMPL_BITS == 64


482  mulx rcx, rcx, rbx ; C4E2F3F6CB


483  %else


484  db 0C4h,0E2h,0F3h,0F6h,0CBh ; 32bit & 16bit ignores VEX.W=1 (10980xe)


485  %endif


486  .again:


487  icebp


488  jmp .again


489  BS3_PROC_END_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp


490 


491  BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp, BS3_PBC_NEAR


492  %if TMPL_BITS == 64


493  mulx rax, rcx, [fs:rbx] ; 64C4E2F3F603


494  %elif TMPL_BITS == 32


495  db 064h,0C4h,0E2h,0F3h,0F6h,003h ; 32bit & 16bit ignores VEX.W=1 (10980xe)


496  %else


497  db 064h,0C4h,0E2h,0F3h,0F6h,007h ; 32bit & 16bit ignores VEX.W=1 (10980xe)


498  %endif


499  .again:


500  icebp


501  jmp .again


502  BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp


503 


504  BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR


505  mulx eax, ecx, ebx


506  .again:


507  icebp


508  jmp .again


509  BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp


510 


511  BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR


512  mulx ecx, ecx, ebx


513  .again:


514  icebp


515  jmp .again


516  BS3_PROC_END_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp


517 


518  BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp, BS3_PBC_NEAR


519  mulx eax, ecx, [fs:xBX]


520  .again:


521  icebp


522  jmp .again


523  BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp


524 


525 


526  ;


527  ; POPCNT


528  ;


529  BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_BX_icebp, BS3_PBC_NEAR


530  popcnt ax, bx


531  .again:


532  icebp


533  jmp .again


534  BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_BX_icebp


535 


536  BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp, BS3_PBC_NEAR


537  popcnt eax, ebx


538  .again:


539  icebp


540  jmp .again


541  BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp


542 


543  %if TMPL_BITS == 64


544  BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp, BS3_PBC_NEAR


545  popcnt rax, rbx


546  .again:


547  icebp


548  jmp .again


549  BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp


550  %endif


551 


552 


553  BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp, BS3_PBC_NEAR


554  popcnt ax, [fs:xBX]


555  .again:


556  icebp


557  jmp .again


558  BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp


559 


560  BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp, BS3_PBC_NEAR


561  popcnt eax, [fs:xBX]


562  .again:


563  icebp


564  jmp .again


565  BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp


566 


567  %if TMPL_BITS == 64


568  BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp, BS3_PBC_NEAR


569  popcnt rax, [fs:xBX]


570  .again:


571  icebp


572  jmp .again


573  BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp


574  %endif


575 


576 


577  ;


578  ; CRC32


579  ;


580  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BL_icebp


581  crc32 eax, bl


582  .again:


583  icebp


584  jmp .again


585  BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BL_icebp


586 


587  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BX_icebp


588  crc32 eax, bx


589  .again:


590  icebp


591  jmp .again


592  BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BX_icebp


593 


594  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp


595  crc32 eax, ebx


596  .again:


597  icebp


598  jmp .again


599  BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp


600 


601  %if TMPL_BITS == 64


602  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp


603  crc32 rax, rbx


604  .again:


605  icebp


606  jmp .again


607  BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp


608  %endif


609 


610 


611  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp


612  crc32 eax, byte [fs:xBX]


613  .again:


614  icebp


615  jmp .again


616  BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp


617 


618  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp


619  crc32 eax, word [fs:xBX]


620  .again:


621  icebp


622  jmp .again


623  BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp


624 


625  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp


626  crc32 eax, dword [fs:xBX]


627  .again:


628  icebp


629  jmp .again


630  BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp


631 


632  %if TMPL_BITS == 64


633  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp


634  crc32 rax, qword [fs:xBX]


635  .again:


636  icebp


637  jmp .again


638  BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp


639  %endif


640 


641 


642  ;


643  ; ADCX


644  ;


645  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_EAX_EBX_icebp


646  adcx eax, ebx


647  .again:


648  icebp


649  jmp .again


650  BS3_PROC_END_CMN bs3CpuInstr2_adcx_EAX_EBX_icebp


651 


652  %if TMPL_BITS == 64


653  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_RAX_RBX_icebp


654  adcx rax, rbx


655  .again:


656  icebp


657  jmp .again


658  BS3_PROC_END_CMN bs3CpuInstr2_adcx_RAX_RBX_icebp


659  %endif


660 


661  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_EAX_dword_FSxBX_icebp


662  adcx eax, dword [fs:xBX]


663  .again:


664  icebp


665  jmp .again


666  BS3_PROC_END_CMN bs3CpuInstr2_adcx_EAX_dword_FSxBX_icebp


667 


668  %if TMPL_BITS == 64


669  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_RAX_qword_FSxBX_icebp


670  adcx rax, qword [fs:xBX]


671  .again:


672  icebp


673  jmp .again


674  BS3_PROC_END_CMN bs3CpuInstr2_adcx_RAX_qword_FSxBX_icebp


675  %endif


676 


677 


678  ;


679  ; ADOX


680  ;


681  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_EAX_EBX_icebp


682  adox eax, ebx


683  .again:


684  icebp


685  jmp .again


686  BS3_PROC_END_CMN bs3CpuInstr2_adox_EAX_EBX_icebp


687 


688  %if TMPL_BITS == 64


689  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_RAX_RBX_icebp


690  adox rax, rbx


691  .again:


692  icebp


693  jmp .again


694  BS3_PROC_END_CMN bs3CpuInstr2_adox_RAX_RBX_icebp


695  %endif


696 


697  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_EAX_dword_FSxBX_icebp


698  adox eax, dword [fs:xBX]


699  .again:


700  icebp


701  jmp .again


702  BS3_PROC_END_CMN bs3CpuInstr2_adox_EAX_dword_FSxBX_icebp


703 


704  %if TMPL_BITS == 64


705  BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_RAX_qword_FSxBX_icebp


706  adox rax, qword [fs:xBX]


707  .again:


708  icebp


709  jmp .again


710  BS3_PROC_END_CMN bs3CpuInstr2_adox_RAX_qword_FSxBX_icebp


711  %endif


712 


713 


714  ;


715  ; CMPXCHG16B


716  ;


717  %if TMPL_BITS == 64


718  BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR


719  cmpxchg16b [rdi]


720  .again:


721  ud2


722  jmp .again


723  AssertCompile(.again  BS3_LAST_LABEL == 4)


724  BS3_PROC_END_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2


725 


726 


727  BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR


728  lock cmpxchg16b [rdi]


729  .again:


730  ud2


731  jmp .again


732  AssertCompile(.again  BS3_LAST_LABEL == 5)


733  BS3_PROC_END_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2


734 


735 


736  BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR


737  o16 cmpxchg16b [rdi]


738  .again:


739  ud2


740  jmp .again


741  AssertCompile(.again  BS3_LAST_LABEL == 5)


742  BS3_PROC_END_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2


743 


744 


745  BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR


746  db 0f0h, 066h


747  cmpxchg16b [rdi]


748  .again:


749  ud2


750  jmp .again


751  AssertCompile(.again  BS3_LAST_LABEL == 6)


752  BS3_PROC_END_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2


753 


754 


755  BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR


756  repz cmpxchg16b [rdi]


757  .again:


758  ud2


759  jmp .again


760  AssertCompile(.again  BS3_LAST_LABEL == 5)


761  BS3_PROC_END_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2


762 


763 


764  BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR


765  db 0f0h, 0f3h


766  cmpxchg16b [rdi]


767  .again:


768  ud2


769  jmp .again


770  AssertCompile(.again  BS3_LAST_LABEL == 6)


771  BS3_PROC_END_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2


772 


773  BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR


774  repnz cmpxchg16b [rdi]


775  .again:


776  ud2


777  jmp .again


778  AssertCompile(.again  BS3_LAST_LABEL == 5)


779  BS3_PROC_END_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2


780 


781 


782  BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR


783  db 0f0h, 0f2h


784  cmpxchg16b [rdi]


785  .again:


786  ud2


787  jmp .again


788  AssertCompile(.again  BS3_LAST_LABEL == 6)


789  BS3_PROC_END_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2


790 


791 


792  BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_ud2, BS3_PBC_NEAR


793  wrfsbase rbx


794  .again:


795  ud2


796  jmp .again


797  AssertCompile(.again  BS3_LAST_LABEL == 5)


798  BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_ud2


799 


800 


801  BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_ud2, BS3_PBC_NEAR


802  wrfsbase ebx


803  .again:


804  ud2


805  jmp .again


806  AssertCompile(.again  BS3_LAST_LABEL == 4)


807  BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_ud2


808 


809 


810  BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_ud2, BS3_PBC_NEAR


811  wrgsbase rbx


812  .again:


813  ud2


814  jmp .again


815  AssertCompile(.again  BS3_LAST_LABEL == 5)


816  BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_ud2


817 


818 


819  BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_ud2, BS3_PBC_NEAR


820  wrgsbase ebx


821  .again:


822  ud2


823  jmp .again


824  AssertCompile(.again  BS3_LAST_LABEL == 4)


825  BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_ebx_ud2


826 


827 


828  BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2, BS3_PBC_NEAR


829  wrfsbase rbx


830  mov ebx, 0


831  rdfsbase rcx


832  .again:


833  ud2


834  jmp .again


835  AssertCompile(.again  BS3_LAST_LABEL == 15)


836  BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2


837 


838 


839  BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2, BS3_PBC_NEAR


840  wrfsbase ebx


841  mov ebx, 0


842  rdfsbase ecx


843  .again:


844  ud2


845  jmp .again


846  AssertCompile(.again  BS3_LAST_LABEL == 13)


847  BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2


848 


849 


850  BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2, BS3_PBC_NEAR


851  wrgsbase rbx


852  mov ebx, 0


853  rdgsbase rcx


854  .again:


855  ud2


856  jmp .again


857  AssertCompile(.again  BS3_LAST_LABEL == 15)


858  BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2


859 


860 


861  BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_rdgsbase_ecx_ud2, BS3_PBC_NEAR


862  wrgsbase ebx


863  mov ebx, 0


864  rdgsbase ecx


865  .again:


866  ud2


867  jmp .again


868  AssertCompile(.again  BS3_LAST_LABEL == 13)


869  BS3_PROC_END_CMN bs3CpuInstr2_wrfgbase_ebx_rdgsbase_ecx_ud2


870 


871 


872  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_rbx_ud2, BS3_PBC_NEAR


873  rdfsbase rbx


874  .again:


875  ud2


876  jmp .again


877  AssertCompile(.again  BS3_LAST_LABEL == 5)


878  BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_rbx_ud2


879 


880 


881  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_ebx_ud2, BS3_PBC_NEAR


882  rdfsbase ebx


883  .again:


884  ud2


885  jmp .again


886  AssertCompile(.again  BS3_LAST_LABEL == 4)


887  BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_ebx_ud2


888 


889 


890  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_rbx_ud2, BS3_PBC_NEAR


891  rdgsbase rbx


892  .again:


893  ud2


894  jmp .again


895  AssertCompile(.again  BS3_LAST_LABEL == 5)


896  BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_rbx_ud2


897 


898 


899  BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_ebx_ud2, BS3_PBC_NEAR


900  rdgsbase ebx


901  .again:


902  ud2


903  jmp .again


904  AssertCompile(.again  BS3_LAST_LABEL == 4)


905  BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_ebx_ud2


906 


907 


908  ;; @todo figure out this fudge. sigh.


909  times (348) db 0cch ; fudge to avoid 'rderr' during boot.


910 


911  %endif ; TMPL_BITS == 64


912 


913 


914  %endif ; BS3_INSTANTIATING_CMN


915 


916  %include "bs3kittemplatefooter.mac" ; reset environment


917 

