1 | /* $Id: bs3-cpu-instr-2-template.c 66342 2017-03-29 16:22:31Z vboxsync $ */
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2 | /** @file
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3 | * BS3Kit - bs3-cpu-instr-2, C code template.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2007-2016 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * The contents of this file may alternatively be used under the terms
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18 | * of the Common Development and Distribution License Version 1.0
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19 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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20 | * VirtualBox OSE distribution, in which case the provisions of the
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21 | * CDDL are applicable instead of those of the GPL.
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22 | *
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23 | * You may elect to license modified versions of this file under the
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24 | * terms and conditions of either the GPL or the CDDL or both.
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25 | */
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26 |
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27 |
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28 | /*********************************************************************************************************************************
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29 | * Header Files *
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30 | *********************************************************************************************************************************/
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31 | #include <iprt/asm.h>
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32 | #include <iprt/asm-amd64-x86.h>
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33 |
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34 |
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35 |
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36 |
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37 | /*********************************************************************************************************************************
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38 | * Structures and Typedefs *
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39 | *********************************************************************************************************************************/
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40 | #ifdef BS3_INSTANTIATING_CMN
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41 | #endif
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42 |
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43 |
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44 | /*********************************************************************************************************************************
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45 | * External Symbols *
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46 | *********************************************************************************************************************************/
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47 | #ifdef BS3_INSTANTIATING_CMN
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48 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_mul_xBX_ud2);
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49 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_imul_xBX_ud2);
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50 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_imul_xCX_xBX_ud2);
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51 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_div_xBX_ud2);
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52 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_idiv_xBX_ud2);
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53 | # if ARCH_BITS == 64
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54 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b_rdi_ud2);
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55 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2);
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56 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2);
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57 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2);
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58 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2);
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59 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2);
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60 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2);
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61 | extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2);
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62 | # endif
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63 | #endif
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64 |
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65 |
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66 | /*********************************************************************************************************************************
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67 | * Global Variables *
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68 | *********************************************************************************************************************************/
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69 | #ifdef BS3_INSTANTIATING_CMN
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70 |
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71 | #endif /* BS3_INSTANTIATING_CMN - global */
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72 |
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73 |
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74 | /*
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75 | * Common code.
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76 | * Common code.
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77 | * Common code.
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78 | */
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79 | #ifdef BS3_INSTANTIATING_CMN
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80 |
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81 | BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_mul)(uint8_t bMode)
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82 | {
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83 | #define MUL_CHECK_EFLAGS_ZERO (uint16_t)(X86_EFL_AF | X86_EFL_ZF)
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84 | #define MUL_CHECK_EFLAGS (uint16_t)(X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_PF)
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85 |
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86 | static const struct
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87 | {
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88 | RTCCUINTREG uInAX;
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89 | RTCCUINTREG uInBX;
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90 | RTCCUINTREG uOutDX;
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91 | RTCCUINTREG uOutAX;
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92 | uint16_t fFlags;
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93 | } s_aTests[] =
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94 | {
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95 | { 1, 1,
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96 | 0, 1, 0 },
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97 | { 2, 2,
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98 | 0, 4, 0 },
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99 | { RTCCUINTREG_MAX, RTCCUINTREG_MAX,
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100 | RTCCUINTREG_MAX-1, 1, X86_EFL_CF | X86_EFL_OF },
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101 | { RTCCINTREG_MAX, RTCCINTREG_MAX,
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102 | RTCCINTREG_MAX / 2, 1, X86_EFL_CF | X86_EFL_OF },
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103 | { 1, RTCCUINTREG_MAX,
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104 | 0, RTCCUINTREG_MAX, X86_EFL_PF | X86_EFL_SF },
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105 | { 1, RTCCINTREG_MAX,
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106 | 0, RTCCINTREG_MAX, X86_EFL_PF },
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107 | { 2, RTCCINTREG_MAX,
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108 | 0, RTCCUINTREG_MAX - 1, X86_EFL_SF },
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109 | { (RTCCUINTREG)RTCCINTREG_MAX + 1, 2,
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110 | 1, 0, X86_EFL_PF | X86_EFL_CF | X86_EFL_OF },
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111 | { (RTCCUINTREG)RTCCINTREG_MAX / 2 + 1, 3,
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112 | 0, ((RTCCUINTREG)RTCCINTREG_MAX / 2 + 1) * 3, X86_EFL_PF | X86_EFL_SF },
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113 | };
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114 |
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115 | BS3REGCTX Ctx;
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116 | BS3TRAPFRAME TrapFrame;
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117 | unsigned i, j, k;
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118 |
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119 | /* Ensure the structures are allocated before we sample the stack pointer. */
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120 | Bs3MemSet(&Ctx, 0, sizeof(Ctx));
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121 | Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
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122 |
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123 | /*
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124 | * Create test context.
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125 | */
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126 | Bs3RegCtxSaveEx(&Ctx, bMode, 512);
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127 | Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_mul_xBX_ud2));
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128 | for (k = 0; k < 2; k++)
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129 | {
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130 | Ctx.rflags.u16 |= MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO;
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131 | for (j = 0; j < 2; j++)
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132 | {
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133 | for (i = 0; i < RT_ELEMENTS(s_aTests); i++)
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134 | {
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135 | if (k == 0)
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136 | {
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137 | Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX;
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138 | Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX;
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139 | }
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140 | else
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141 | {
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142 | Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX;
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143 | Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX;
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144 | }
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145 | Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame);
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146 | if (TrapFrame.bXcpt != X86_XCPT_UD)
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147 | Bs3TestFailedF("Expected #UD got %#x", TrapFrame.bXcpt);
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148 | else if ( TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX
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149 | || TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX
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150 | || (TrapFrame.Ctx.rflags.u16 & (MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO))
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151 | != (s_aTests[i].fFlags & MUL_CHECK_EFLAGS) )
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152 | {
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153 | Bs3TestFailedF("test #%i failed: input %#" RTCCUINTREG_XFMT " * %#" RTCCUINTREG_XFMT,
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154 | i, s_aTests[i].uInAX, s_aTests[i].uInBX);
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155 |
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156 | if (TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX)
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157 | Bs3TestFailedF("Expected xAX = %#RX" RT_XSTR(ARCH_BITS) " got %#RX" RT_XSTR(ARCH_BITS),
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158 | s_aTests[i].uOutAX, TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS));
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159 | if (TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX)
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160 | Bs3TestFailedF("Expected xDX = %#RX" RT_XSTR(ARCH_BITS) " got %#RX" RT_XSTR(ARCH_BITS),
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161 | s_aTests[i].uOutDX, TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS));
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162 | if ( (TrapFrame.Ctx.rflags.u16 & (MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO))
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163 | != (s_aTests[i].fFlags & MUL_CHECK_EFLAGS) )
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164 | Bs3TestFailedF("Expected EFLAGS = %#06RX16, got %#06RX16", s_aTests[i].fFlags & MUL_CHECK_EFLAGS,
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165 | TrapFrame.Ctx.rflags.u16 & (MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO));
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166 | }
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167 | }
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168 | Ctx.rflags.u16 &= ~(MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO);
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169 | }
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170 | }
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171 |
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172 | return 0;
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173 | }
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174 |
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175 |
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176 | BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_imul)(uint8_t bMode)
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177 | {
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178 | #define IMUL_CHECK_EFLAGS_ZERO (uint16_t)(X86_EFL_AF | X86_EFL_ZF)
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179 | #define IMUL_CHECK_EFLAGS (uint16_t)(X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_PF)
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180 | static const struct
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181 | {
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182 | RTCCUINTREG uInAX;
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183 | RTCCUINTREG uInBX;
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184 | RTCCUINTREG uOutDX;
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185 | RTCCUINTREG uOutAX;
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186 | uint16_t fFlags;
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187 | } s_aTests[] =
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188 | {
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189 | /* two positive values. */
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190 | { 1, 1,
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191 | 0, 1, 0 },
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192 | { 2, 2,
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193 | 0, 4, 0 },
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194 | { RTCCINTREG_MAX, RTCCINTREG_MAX,
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195 | RTCCINTREG_MAX/2, 1, X86_EFL_CF | X86_EFL_OF },
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196 | { 1, RTCCINTREG_MAX,
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197 | 0, RTCCINTREG_MAX, X86_EFL_PF },
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198 | { 2, RTCCINTREG_MAX,
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199 | 0, RTCCUINTREG_MAX - 1U, X86_EFL_CF | X86_EFL_OF | X86_EFL_SF },
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200 | { 2, RTCCINTREG_MAX / 2,
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201 | 0, RTCCINTREG_MAX - 1U, 0 },
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202 | { 2, (RTCCINTREG_MAX / 2 + 1),
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203 | 0, (RTCCUINTREG)RTCCINTREG_MAX + 1U, X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_PF },
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204 | { 4, (RTCCINTREG_MAX / 2 + 1),
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205 | 1, 0, X86_EFL_CF | X86_EFL_OF | X86_EFL_PF },
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206 |
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207 | /* negative and positive */
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208 | { -4, 3,
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209 | -1, -12, X86_EFL_SF },
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210 | { 32, -127,
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211 | -1, -4064, X86_EFL_SF },
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212 | { RTCCINTREG_MIN, 1,
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213 | -1, RTCCINTREG_MIN, X86_EFL_SF | X86_EFL_PF },
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214 | { RTCCINTREG_MIN, 2,
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215 | -1, 0, X86_EFL_CF | X86_EFL_OF | X86_EFL_PF },
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216 | { RTCCINTREG_MIN, 3,
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217 | -2, RTCCINTREG_MIN, X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_PF },
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218 | { RTCCINTREG_MIN, 4,
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219 | -2, 0, X86_EFL_CF | X86_EFL_OF | X86_EFL_PF },
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220 | { RTCCINTREG_MIN, RTCCINTREG_MAX,
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221 | RTCCINTREG_MIN / 2, RTCCINTREG_MIN, X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_PF },
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222 | { RTCCINTREG_MIN, RTCCINTREG_MAX - 1,
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223 | RTCCINTREG_MIN / 2 + 1, 0, X86_EFL_CF | X86_EFL_OF | X86_EFL_PF },
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224 |
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225 | /* two negative values. */
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226 | { -4, -63,
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227 | 0, 252, X86_EFL_PF },
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228 | { RTCCINTREG_MIN, RTCCINTREG_MIN,
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229 | RTCCUINTREG_MAX / 4 + 1, 0, X86_EFL_CF | X86_EFL_OF | X86_EFL_PF },
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230 | { RTCCINTREG_MIN, RTCCINTREG_MIN + 1,
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231 | RTCCUINTREG_MAX / 4, RTCCINTREG_MIN, X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_PF},
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232 | { RTCCINTREG_MIN + 1, RTCCINTREG_MIN + 1,
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233 | RTCCUINTREG_MAX / 4, 1, X86_EFL_CF | X86_EFL_OF },
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234 |
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235 | };
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236 |
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237 | BS3REGCTX Ctx;
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238 | BS3TRAPFRAME TrapFrame;
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239 | unsigned i, j, k;
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240 |
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241 | /* Ensure the structures are allocated before we sample the stack pointer. */
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242 | Bs3MemSet(&Ctx, 0, sizeof(Ctx));
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243 | Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
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244 |
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245 | /*
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246 | * Create test context.
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247 | */
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248 | Bs3RegCtxSaveEx(&Ctx, bMode, 512);
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249 | Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_imul_xBX_ud2));
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250 |
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251 | for (k = 0; k < 2; k++)
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252 | {
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253 | Ctx.rflags.u16 |= MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO;
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254 | for (j = 0; j < 2; j++)
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255 | {
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256 | for (i = 0; i < RT_ELEMENTS(s_aTests); i++)
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257 | {
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258 | if (k == 0)
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259 | {
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260 | Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX;
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261 | Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX;
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262 | }
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263 | else
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264 | {
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265 | Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX;
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266 | Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX;
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267 | }
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268 | Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame);
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269 | if (TrapFrame.bXcpt != X86_XCPT_UD)
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270 | Bs3TestFailedF("Expected #UD got %#x", TrapFrame.bXcpt);
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271 | else if ( TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX
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272 | || TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX
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273 | || (TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO))
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274 | != (s_aTests[i].fFlags & IMUL_CHECK_EFLAGS) )
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275 | {
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276 | Bs3TestFailedF("test #%i failed: input %#" RTCCUINTREG_XFMT " * %#" RTCCUINTREG_XFMT,
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277 | i, s_aTests[i].uInAX, s_aTests[i].uInBX);
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278 |
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279 | if (TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX)
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280 | Bs3TestFailedF("Expected xAX = %#RX" RT_XSTR(ARCH_BITS) " got %#RX" RT_XSTR(ARCH_BITS),
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281 | s_aTests[i].uOutAX, TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS));
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282 | if (TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX)
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283 | Bs3TestFailedF("Expected xDX = %#RX" RT_XSTR(ARCH_BITS) " got %#RX" RT_XSTR(ARCH_BITS),
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284 | s_aTests[i].uOutDX, TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS));
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285 | if ( (TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO))
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286 | != (s_aTests[i].fFlags & IMUL_CHECK_EFLAGS) )
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287 | Bs3TestFailedF("Expected EFLAGS = %#06RX16, got %#06RX16", s_aTests[i].fFlags & IMUL_CHECK_EFLAGS,
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288 | TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO));
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289 | }
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290 | }
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291 | }
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292 | }
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293 |
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294 | /*
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295 | * Repeat for the truncating two operand version.
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296 | */
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297 | Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_imul_xCX_xBX_ud2));
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298 |
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299 | for (k = 0; k < 2; k++)
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300 | {
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301 | Ctx.rflags.u16 |= MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO;
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302 | for (j = 0; j < 2; j++)
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303 | {
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304 | for (i = 0; i < RT_ELEMENTS(s_aTests); i++)
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305 | {
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306 | if (k == 0)
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307 | {
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308 | Ctx.rcx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX;
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309 | Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX;
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310 | }
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311 | else
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312 | {
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313 | Ctx.rcx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX;
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314 | Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX;
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315 | }
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316 | Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame);
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317 | if (TrapFrame.bXcpt != X86_XCPT_UD)
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318 | Bs3TestFailedF("Expected #UD got %#x", TrapFrame.bXcpt);
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319 | else if ( TrapFrame.Ctx.rcx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX
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320 | || TrapFrame.Ctx.rdx.u != Ctx.rdx.u
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321 | || TrapFrame.Ctx.rbx.u != Ctx.rbx.u
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322 | || (TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO))
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323 | != (s_aTests[i].fFlags & IMUL_CHECK_EFLAGS) )
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324 | {
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325 | Bs3TestFailedF("test #%i failed: input %#" RTCCUINTREG_XFMT " * %#" RTCCUINTREG_XFMT,
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326 | i, s_aTests[i].uInAX, s_aTests[i].uInBX);
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327 |
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328 | if (TrapFrame.Ctx.rcx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX)
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329 | Bs3TestFailedF("Expected xAX = %#RX" RT_XSTR(ARCH_BITS) " got %#RX" RT_XSTR(ARCH_BITS),
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330 | s_aTests[i].uOutAX, TrapFrame.Ctx.rcx.RT_CONCAT(u,ARCH_BITS));
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331 | if ( (TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO))
|
---|
332 | != (s_aTests[i].fFlags & IMUL_CHECK_EFLAGS) )
|
---|
333 | Bs3TestFailedF("Expected EFLAGS = %#06RX16, got %#06RX16", s_aTests[i].fFlags & IMUL_CHECK_EFLAGS,
|
---|
334 | TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO));
|
---|
335 | }
|
---|
336 | }
|
---|
337 | }
|
---|
338 | }
|
---|
339 |
|
---|
340 | return 0;
|
---|
341 | }
|
---|
342 |
|
---|
343 |
|
---|
344 | BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_div)(uint8_t bMode)
|
---|
345 | {
|
---|
346 | #define DIV_CHECK_EFLAGS (uint16_t)(X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
|
---|
347 | static const struct
|
---|
348 | {
|
---|
349 | RTCCUINTREG uInDX;
|
---|
350 | RTCCUINTREG uInAX;
|
---|
351 | RTCCUINTREG uInBX;
|
---|
352 | RTCCUINTREG uOutAX;
|
---|
353 | RTCCUINTREG uOutDX;
|
---|
354 | uint8_t bXcpt;
|
---|
355 | } s_aTests[] =
|
---|
356 | {
|
---|
357 | { 0, 1, 1,
|
---|
358 | 1, 0, X86_XCPT_UD },
|
---|
359 | { 0, 5, 2,
|
---|
360 | 2, 1, X86_XCPT_UD },
|
---|
361 | { 0, 0, 0,
|
---|
362 | 0, 0, X86_XCPT_DE },
|
---|
363 | { RTCCUINTREG_MAX, RTCCUINTREG_MAX, 0,
|
---|
364 | 0, 0, X86_XCPT_DE },
|
---|
365 | { RTCCUINTREG_MAX, RTCCUINTREG_MAX, 1,
|
---|
366 | 0, 0, X86_XCPT_DE },
|
---|
367 | { RTCCUINTREG_MAX, RTCCUINTREG_MAX, RTCCUINTREG_MAX,
|
---|
368 | 0, 0, X86_XCPT_DE },
|
---|
369 | { RTCCUINTREG_MAX - 1, RTCCUINTREG_MAX, RTCCUINTREG_MAX,
|
---|
370 | RTCCUINTREG_MAX, RTCCUINTREG_MAX - 1, X86_XCPT_UD },
|
---|
371 | };
|
---|
372 |
|
---|
373 | BS3REGCTX Ctx;
|
---|
374 | BS3TRAPFRAME TrapFrame;
|
---|
375 | unsigned i, j;
|
---|
376 |
|
---|
377 | /* Ensure the structures are allocated before we sample the stack pointer. */
|
---|
378 | Bs3MemSet(&Ctx, 0, sizeof(Ctx));
|
---|
379 | Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
|
---|
380 |
|
---|
381 | /*
|
---|
382 | * Create test context.
|
---|
383 | */
|
---|
384 | Bs3RegCtxSaveEx(&Ctx, bMode, 512);
|
---|
385 | Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_div_xBX_ud2));
|
---|
386 |
|
---|
387 | /*
|
---|
388 | * Do the tests twice, first with all flags set, then once again with
|
---|
389 | * flags cleared. The flags are not touched by my intel skylake CPU.
|
---|
390 | */
|
---|
391 | Ctx.rflags.u16 |= DIV_CHECK_EFLAGS;
|
---|
392 | for (j = 0; j < 2; j++)
|
---|
393 | {
|
---|
394 | for (i = 0; i < RT_ELEMENTS(s_aTests); i++)
|
---|
395 | {
|
---|
396 | Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX;
|
---|
397 | Ctx.rdx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInDX;
|
---|
398 | Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX;
|
---|
399 | Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame);
|
---|
400 |
|
---|
401 | if ( TrapFrame.bXcpt != s_aTests[i].bXcpt
|
---|
402 | || ( s_aTests[i].bXcpt == X86_XCPT_UD
|
---|
403 | ? TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX
|
---|
404 | || TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX
|
---|
405 | || (TrapFrame.Ctx.rflags.u16 & DIV_CHECK_EFLAGS) != (Ctx.rflags.u16 & DIV_CHECK_EFLAGS)
|
---|
406 | : TrapFrame.Ctx.rax.u != Ctx.rax.u
|
---|
407 | || TrapFrame.Ctx.rdx.u != Ctx.rdx.u
|
---|
408 | || (TrapFrame.Ctx.rflags.u16 & DIV_CHECK_EFLAGS) != (Ctx.rflags.u16 & DIV_CHECK_EFLAGS) ) )
|
---|
409 | {
|
---|
410 | Bs3TestFailedF("test #%i failed: input %#" RTCCUINTREG_XFMT ":%" RTCCUINTREG_XFMT " / %#" RTCCUINTREG_XFMT,
|
---|
411 | i, s_aTests[i].uInDX, s_aTests[i].uInAX, s_aTests[i].uInBX);
|
---|
412 | if (TrapFrame.bXcpt != s_aTests[i].bXcpt)
|
---|
413 | Bs3TestFailedF("Expected bXcpt = %#x, got %#x", s_aTests[i].bXcpt, TrapFrame.bXcpt);
|
---|
414 | if (s_aTests[i].bXcpt == X86_XCPT_UD)
|
---|
415 | {
|
---|
416 | if (TrapFrame.Ctx.rax.RT_CONCAT(u, ARCH_BITS) != s_aTests[i].uOutAX)
|
---|
417 | Bs3TestFailedF("Expected xAX = %#" RTCCUINTREG_XFMT ", got %#" RTCCUINTREG_XFMT,
|
---|
418 | s_aTests[i].uOutAX, TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS));
|
---|
419 | if (TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX)
|
---|
420 | Bs3TestFailedF("Expected xDX = %#" RTCCUINTREG_XFMT ", got %#" RTCCUINTREG_XFMT,
|
---|
421 | s_aTests[i].uOutDX, TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS));
|
---|
422 | if ((TrapFrame.Ctx.rflags.u16 & DIV_CHECK_EFLAGS) != (Ctx.rflags.u16 & DIV_CHECK_EFLAGS))
|
---|
423 | Bs3TestFailedF("Expected EFLAGS = %#06RX16, got %#06RX16",
|
---|
424 | Ctx.rflags.u16 & DIV_CHECK_EFLAGS, TrapFrame.Ctx.rflags.u16 & DIV_CHECK_EFLAGS);
|
---|
425 | }
|
---|
426 | }
|
---|
427 | }
|
---|
428 | Ctx.rflags.u16 &= ~DIV_CHECK_EFLAGS;
|
---|
429 | }
|
---|
430 |
|
---|
431 | return 0;
|
---|
432 | }
|
---|
433 |
|
---|
434 |
|
---|
435 |
|
---|
436 | BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_idiv)(uint8_t bMode)
|
---|
437 | {
|
---|
438 | #define IDIV_CHECK_EFLAGS (uint16_t)(X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
|
---|
439 | static const struct
|
---|
440 | {
|
---|
441 | RTCCUINTREG uInDX;
|
---|
442 | RTCCUINTREG uInAX;
|
---|
443 | RTCCUINTREG uInBX;
|
---|
444 | RTCCUINTREG uOutAX;
|
---|
445 | RTCCUINTREG uOutDX;
|
---|
446 | uint8_t bXcpt;
|
---|
447 | } s_aTests[] =
|
---|
448 | {
|
---|
449 | { 0, 0, 0,
|
---|
450 | 0, 0, X86_XCPT_DE },
|
---|
451 | { RTCCINTREG_MAX, RTCCINTREG_MAX, 0,
|
---|
452 | 0, 0, X86_XCPT_DE },
|
---|
453 | /* two positive values. */
|
---|
454 | { 0, 1, 1,
|
---|
455 | 1, 0, X86_XCPT_UD },
|
---|
456 | { 0, 5, 2,
|
---|
457 | 2, 1, X86_XCPT_UD },
|
---|
458 | { RTCCINTREG_MAX / 2, RTCCUINTREG_MAX / 2, RTCCINTREG_MAX,
|
---|
459 | RTCCINTREG_MAX, RTCCINTREG_MAX - 1, X86_XCPT_UD },
|
---|
460 | { RTCCINTREG_MAX / 2, RTCCUINTREG_MAX / 2 + 1, RTCCINTREG_MAX,
|
---|
461 | RTCCINTREG_MAX, RTCCINTREG_MAX - 1, X86_XCPT_DE },
|
---|
462 | /* negative dividend, positive divisor. */
|
---|
463 | { -1, -7, 2,
|
---|
464 | -3, -1, X86_XCPT_UD },
|
---|
465 | { RTCCINTREG_MIN / 2 + 1, 0, RTCCINTREG_MAX,
|
---|
466 | RTCCINTREG_MIN + 2, RTCCINTREG_MIN + 2, X86_XCPT_UD },
|
---|
467 | { RTCCINTREG_MIN / 2, 0, RTCCINTREG_MAX,
|
---|
468 | 0, 0, X86_XCPT_DE },
|
---|
469 | /* positive dividend, negative divisor. */
|
---|
470 | { 0, 7, -2,
|
---|
471 | -3, 1, X86_XCPT_UD },
|
---|
472 | { RTCCINTREG_MAX / 2 + 1, RTCCINTREG_MAX, RTCCINTREG_MIN,
|
---|
473 | RTCCINTREG_MIN, RTCCINTREG_MAX, X86_XCPT_UD },
|
---|
474 | { RTCCINTREG_MAX / 2 + 1, (RTCCUINTREG)RTCCINTREG_MAX+1, RTCCINTREG_MIN,
|
---|
475 | 0, 0, X86_XCPT_DE },
|
---|
476 | /* negative dividend, negative divisor. */
|
---|
477 | { -1, -7, -2,
|
---|
478 | 3, -1, X86_XCPT_UD },
|
---|
479 | { RTCCINTREG_MIN / 2, 1, RTCCINTREG_MIN,
|
---|
480 | RTCCINTREG_MAX, RTCCINTREG_MIN + 1, X86_XCPT_UD },
|
---|
481 | { RTCCINTREG_MIN / 2, 2, RTCCINTREG_MIN,
|
---|
482 | RTCCINTREG_MAX, RTCCINTREG_MIN + 2, X86_XCPT_UD },
|
---|
483 | { RTCCINTREG_MIN / 2, 0, RTCCINTREG_MIN,
|
---|
484 | 0, 0, X86_XCPT_DE },
|
---|
485 | };
|
---|
486 |
|
---|
487 | BS3REGCTX Ctx;
|
---|
488 | BS3TRAPFRAME TrapFrame;
|
---|
489 | unsigned i, j;
|
---|
490 |
|
---|
491 | /* Ensure the structures are allocated before we sample the stack pointer. */
|
---|
492 | Bs3MemSet(&Ctx, 0, sizeof(Ctx));
|
---|
493 | Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
|
---|
494 |
|
---|
495 | /*
|
---|
496 | * Create test context.
|
---|
497 | */
|
---|
498 | Bs3RegCtxSaveEx(&Ctx, bMode, 512);
|
---|
499 | Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_idiv_xBX_ud2));
|
---|
500 |
|
---|
501 | /*
|
---|
502 | * Do the tests twice, first with all flags set, then once again with
|
---|
503 | * flags cleared. The flags are not touched by my intel skylake CPU.
|
---|
504 | */
|
---|
505 | Ctx.rflags.u16 |= IDIV_CHECK_EFLAGS;
|
---|
506 | for (j = 0; j < 2; j++)
|
---|
507 | {
|
---|
508 | for (i = 0; i < RT_ELEMENTS(s_aTests); i++)
|
---|
509 | {
|
---|
510 | Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX;
|
---|
511 | Ctx.rdx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInDX;
|
---|
512 | Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX;
|
---|
513 | Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame);
|
---|
514 |
|
---|
515 | if ( TrapFrame.bXcpt != s_aTests[i].bXcpt
|
---|
516 | || ( s_aTests[i].bXcpt == X86_XCPT_UD
|
---|
517 | ? TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX
|
---|
518 | || TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX
|
---|
519 | || (TrapFrame.Ctx.rflags.u16 & IDIV_CHECK_EFLAGS) != (Ctx.rflags.u16 & IDIV_CHECK_EFLAGS)
|
---|
520 | : TrapFrame.Ctx.rax.u != Ctx.rax.u
|
---|
521 | || TrapFrame.Ctx.rdx.u != Ctx.rdx.u
|
---|
522 | || (TrapFrame.Ctx.rflags.u16 & IDIV_CHECK_EFLAGS) != (Ctx.rflags.u16 & IDIV_CHECK_EFLAGS) ) )
|
---|
523 | {
|
---|
524 | Bs3TestFailedF("test #%i failed: input %#" RTCCUINTREG_XFMT ":%" RTCCUINTREG_XFMT " / %#" RTCCUINTREG_XFMT,
|
---|
525 | i, s_aTests[i].uInDX, s_aTests[i].uInAX, s_aTests[i].uInBX);
|
---|
526 | if (TrapFrame.bXcpt != s_aTests[i].bXcpt)
|
---|
527 | Bs3TestFailedF("Expected bXcpt = %#x, got %#x", s_aTests[i].bXcpt, TrapFrame.bXcpt);
|
---|
528 | if (s_aTests[i].bXcpt == X86_XCPT_UD)
|
---|
529 | {
|
---|
530 | if (TrapFrame.Ctx.rax.RT_CONCAT(u, ARCH_BITS) != s_aTests[i].uOutAX)
|
---|
531 | Bs3TestFailedF("Expected xAX = %#" RTCCUINTREG_XFMT ", got %#" RTCCUINTREG_XFMT,
|
---|
532 | s_aTests[i].uOutAX, TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS));
|
---|
533 | if (TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX)
|
---|
534 | Bs3TestFailedF("Expected xDX = %#" RTCCUINTREG_XFMT ", got %#" RTCCUINTREG_XFMT,
|
---|
535 | s_aTests[i].uOutDX, TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS));
|
---|
536 | if ((TrapFrame.Ctx.rflags.u16 & IDIV_CHECK_EFLAGS) != (Ctx.rflags.u16 & IDIV_CHECK_EFLAGS))
|
---|
537 | Bs3TestFailedF("Expected EFLAGS = %#06RX16, got %#06RX16",
|
---|
538 | Ctx.rflags.u16 & IDIV_CHECK_EFLAGS, TrapFrame.Ctx.rflags.u16 & IDIV_CHECK_EFLAGS);
|
---|
539 | }
|
---|
540 | }
|
---|
541 | }
|
---|
542 | Ctx.rflags.u16 &= ~IDIV_CHECK_EFLAGS;
|
---|
543 | }
|
---|
544 |
|
---|
545 | return 0;
|
---|
546 | }
|
---|
547 |
|
---|
548 |
|
---|
549 | # if ARCH_BITS == 64
|
---|
550 | BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b)(uint8_t bMode)
|
---|
551 | {
|
---|
552 | BS3REGCTX Ctx;
|
---|
553 | BS3REGCTX ExpectCtx;
|
---|
554 | BS3TRAPFRAME TrapFrame;
|
---|
555 | RTUINT128U au128[3];
|
---|
556 | PRTUINT128U pau128 = RT_ALIGN_PT(&au128[0], sizeof(RTUINT128U), PRTUINT128U);
|
---|
557 | bool const fSupportCX16 = RT_BOOL(ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_CX16);
|
---|
558 | unsigned iFlags;
|
---|
559 | unsigned offBuf;
|
---|
560 | unsigned iMatch;
|
---|
561 | unsigned iWorker;
|
---|
562 | static struct
|
---|
563 | {
|
---|
564 | bool fLocked;
|
---|
565 | uint8_t offUd2;
|
---|
566 | FNBS3FAR *pfnWorker;
|
---|
567 | } const s_aWorkers[] =
|
---|
568 | {
|
---|
569 | { false, 4, BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b_rdi_ud2) },
|
---|
570 | { false, 5, BS3_CMN_NM(bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2) },
|
---|
571 | { false, 5, BS3_CMN_NM(bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2) },
|
---|
572 | { false, 5, BS3_CMN_NM(bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2) },
|
---|
573 | { true, 1+4, BS3_CMN_NM(bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2) },
|
---|
574 | { true, 1+5, BS3_CMN_NM(bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2) },
|
---|
575 | { true, 1+5, BS3_CMN_NM(bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2) },
|
---|
576 | { true, 1+5, BS3_CMN_NM(bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2) },
|
---|
577 | };
|
---|
578 |
|
---|
579 | /* Ensure the structures are allocated before we sample the stack pointer. */
|
---|
580 | Bs3MemSet(&Ctx, 0, sizeof(Ctx));
|
---|
581 | Bs3MemSet(&ExpectCtx, 0, sizeof(ExpectCtx));
|
---|
582 | Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
|
---|
583 | Bs3MemSet(pau128, 0, sizeof(pau128[0]) * 2);
|
---|
584 |
|
---|
585 | /*
|
---|
586 | * Create test context.
|
---|
587 | */
|
---|
588 | Bs3RegCtxSaveEx(&Ctx, bMode, 512);
|
---|
589 | if (!fSupportCX16)
|
---|
590 | Bs3TestPrintf("Note! CMPXCHG16B is not supported by the CPU!\n");
|
---|
591 |
|
---|
592 | /*
|
---|
593 | * One loop with the normal variant and one with the locked one
|
---|
594 | */
|
---|
595 | g_usBs3TestStep = 0;
|
---|
596 | for (iWorker = 0; iWorker < RT_ELEMENTS(s_aWorkers); iWorker++)
|
---|
597 | {
|
---|
598 | Bs3RegCtxSetRipCsFromCurPtr(&Ctx, s_aWorkers[iWorker].pfnWorker);
|
---|
599 |
|
---|
600 | /*
|
---|
601 | * One loop with all status flags set, and one with them clear.
|
---|
602 | */
|
---|
603 | Ctx.rflags.u16 |= X86_EFL_STATUS_BITS;
|
---|
604 | for (iFlags = 0; iFlags < 2; iFlags++)
|
---|
605 | {
|
---|
606 | Bs3MemCpy(&ExpectCtx, &Ctx, sizeof(ExpectCtx));
|
---|
607 |
|
---|
608 | for (offBuf = 0; offBuf < sizeof(RTUINT128U); offBuf++)
|
---|
609 | {
|
---|
610 | # define CX16_OLD_LO UINT64_C(0xabb6345dcc9c4bbd)
|
---|
611 | # define CX16_OLD_HI UINT64_C(0x7b06ea35749549ab)
|
---|
612 | # define CX16_MISMATCH_LO UINT64_C(0xbace3e3590f18981)
|
---|
613 | # define CX16_MISMATCH_HI UINT64_C(0x9b385e8bfd5b4000)
|
---|
614 | # define CX16_STORE_LO UINT64_C(0x5cbd27d251f6559b)
|
---|
615 | # define CX16_STORE_HI UINT64_C(0x17ff434ed1b54963)
|
---|
616 |
|
---|
617 | PRTUINT128U pBuf = (PRTUINT128U)&pau128->au8[offBuf];
|
---|
618 |
|
---|
619 | ExpectCtx.rax.u = Ctx.rax.u = CX16_MISMATCH_LO;
|
---|
620 | ExpectCtx.rdx.u = Ctx.rdx.u = CX16_MISMATCH_HI;
|
---|
621 | for (iMatch = 0; iMatch < 2; iMatch++)
|
---|
622 | {
|
---|
623 | uint8_t bExpectXcpt;
|
---|
624 | pBuf->s.Lo = CX16_OLD_LO;
|
---|
625 | pBuf->s.Hi = CX16_OLD_HI;
|
---|
626 | ExpectCtx.rdi.u = Ctx.rdi.u = (uintptr_t)pBuf;
|
---|
627 | Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame);
|
---|
628 | g_usBs3TestStep++;
|
---|
629 | //Bs3TestPrintf("Test: iFlags=%d offBuf=%d iMatch=%u iWorker=%u\n", iFlags, offBuf, iMatch, iWorker);
|
---|
630 | bExpectXcpt = X86_XCPT_UD;
|
---|
631 | if (fSupportCX16)
|
---|
632 | {
|
---|
633 | if (offBuf & 15)
|
---|
634 | {
|
---|
635 | bExpectXcpt = X86_XCPT_GP;
|
---|
636 | ExpectCtx.rip.u = Ctx.rip.u;
|
---|
637 | ExpectCtx.rflags.u32 = Ctx.rflags.u32;
|
---|
638 | }
|
---|
639 | else
|
---|
640 | {
|
---|
641 | ExpectCtx.rax.u = CX16_OLD_LO;
|
---|
642 | ExpectCtx.rdx.u = CX16_OLD_HI;
|
---|
643 | if (iMatch & 1)
|
---|
644 | ExpectCtx.rflags.u32 = Ctx.rflags.u32 | X86_EFL_ZF;
|
---|
645 | else
|
---|
646 | ExpectCtx.rflags.u32 = Ctx.rflags.u32 & ~X86_EFL_ZF;
|
---|
647 | ExpectCtx.rip.u = Ctx.rip.u + s_aWorkers[iWorker].offUd2;
|
---|
648 | }
|
---|
649 | ExpectCtx.rflags.u32 |= X86_EFL_RF;
|
---|
650 | }
|
---|
651 | if ( !Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &ExpectCtx, 0 /*cbPcAdjust*/, 0 /*cbSpAdjust*/,
|
---|
652 | 0 /*fExtraEfl*/, "lm64", 0 /*idTestStep*/)
|
---|
653 | || TrapFrame.bXcpt != bExpectXcpt)
|
---|
654 | {
|
---|
655 | if (TrapFrame.bXcpt != bExpectXcpt)
|
---|
656 | Bs3TestFailedF("Expected bXcpt=#%x, got %#x (%#x)", bExpectXcpt, TrapFrame.bXcpt, TrapFrame.uErrCd);
|
---|
657 | Bs3TestFailedF("^^^ iWorker=%d iFlags=%d offBuf=%d iMatch=%u\n", iWorker, iFlags, offBuf, iMatch);
|
---|
658 | ASMHalt();
|
---|
659 | }
|
---|
660 |
|
---|
661 | ExpectCtx.rax.u = Ctx.rax.u = CX16_OLD_LO;
|
---|
662 | ExpectCtx.rdx.u = Ctx.rdx.u = CX16_OLD_HI;
|
---|
663 | }
|
---|
664 | }
|
---|
665 | Ctx.rflags.u16 &= ~X86_EFL_STATUS_BITS;
|
---|
666 | }
|
---|
667 | }
|
---|
668 |
|
---|
669 | return 0;
|
---|
670 | }
|
---|
671 | # endif /* ARCH_BITS == 64 */
|
---|
672 |
|
---|
673 |
|
---|
674 | #endif /* BS3_INSTANTIATING_CMN */
|
---|
675 |
|
---|
676 |
|
---|
677 |
|
---|
678 | /*
|
---|
679 | * Mode specific code.
|
---|
680 | * Mode specific code.
|
---|
681 | * Mode specific code.
|
---|
682 | */
|
---|
683 | #ifdef BS3_INSTANTIATING_MODE
|
---|
684 |
|
---|
685 |
|
---|
686 | #endif /* BS3_INSTANTIATING_MODE */
|
---|
687 |
|
---|