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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c@ 67954

Last change on this file since 67954 was 67161, checked in by vboxsync, 7 years ago

bs3-cpu-generated-1-template.c: Redid r115830 by not using BS3_DECL_NEAR for FNBS3CG1ENCODER and by moving the PBS3CG1STATE typedef up.
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File size: 265.5 KB
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1/* $Id: bs3-cpu-generated-1-template.c 67161 2017-05-31 09:57:31Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-cpu-generated-1, C code template.
4 */
5
6/*
7 * Copyright (C) 2007-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27#ifndef BS3_INSTANTIATING_CMN
28# error "BS3_INSTANTIATING_CMN not defined"
29#endif
30
31
32/*********************************************************************************************************************************
33* Header Files *
34*********************************************************************************************************************************/
35#include <iprt/asm.h>
36#include <iprt/asm-amd64-x86.h>
37
38#include "bs3-cpu-generated-1.h"
39
40
41/*********************************************************************************************************************************
42* Defined Constants And Macros *
43*********************************************************************************************************************************/
44#define BS3CG1_WITH_VEX
45
46#define P_CS X86_OP_PRF_CS
47#define P_SS X86_OP_PRF_SS
48#define P_DS X86_OP_PRF_DS
49#define P_ES X86_OP_PRF_ES
50#define P_FS X86_OP_PRF_FS
51#define P_GS X86_OP_PRF_GS
52#define P_OZ X86_OP_PRF_SIZE_OP
53#define P_AZ X86_OP_PRF_SIZE_ADDR
54#define P_LK X86_OP_PRF_LOCK
55#define P_RN X86_OP_PRF_REPNZ
56#define P_RZ X86_OP_PRF_REPZ
57
58#define REX_WRBX (X86_OP_REX_W | X86_OP_REX_R | X86_OP_REX_B | X86_OP_REX_X)
59#define REX_W___ (X86_OP_REX_W)
60#define REX_WR__ (X86_OP_REX_W | X86_OP_REX_R)
61#define REX_W_B_ (X86_OP_REX_W | X86_OP_REX_B)
62#define REX_W__X (X86_OP_REX_W | X86_OP_REX_X)
63#define REX_WRB_ (X86_OP_REX_W | X86_OP_REX_R | X86_OP_REX_B)
64#define REX_WR_X (X86_OP_REX_W | X86_OP_REX_R | X86_OP_REX_X)
65#define REX_W_BX (X86_OP_REX_W | X86_OP_REX_B | X86_OP_REX_X)
66#define REX__R__ (X86_OP_REX_R)
67#define REX__RB_ (X86_OP_REX_R | X86_OP_REX_B)
68#define REX__R_X (X86_OP_REX_R | X86_OP_REX_X)
69#define REX__RBX (X86_OP_REX_R | X86_OP_REX_B | X86_OP_REX_X)
70#define REX___B_ (X86_OP_REX_B)
71#define REX___BX (X86_OP_REX_B | X86_OP_REX_X)
72#define REX____X (X86_OP_REX_X)
73#define REX_____ (0x40)
74
75
76/** @def BS3CG1_DPRINTF
77 * Debug print macro.
78 */
79#if 0
80# define BS3CG1_DPRINTF(a_ArgList) Bs3TestPrintf a_ArgList
81# define BS3CG1_DEBUG_CTX_MOD
82#else
83# define BS3CG1_DPRINTF(a_ArgList) do { } while (0)
84#endif
85
86/**
87 * Checks if this is a 64-bit test target or not.
88 * Helps avoid ifdefs or code bloat.
89 */
90#if ARCH_BITS == 64
91# define BS3CG1_IS_64BIT_TARGET(a_pThis) BS3_MODE_IS_64BIT_CODE((a_pThis)->bMode)
92#else
93# define BS3CG1_IS_64BIT_TARGET(a_pThis) (false)
94#endif
95
96
97/*********************************************************************************************************************************
98* Structures and Typedefs *
99*********************************************************************************************************************************/
100/** Operand value location. */
101typedef enum BS3CG1OPLOC
102{
103 BS3CG1OPLOC_INVALID = 0,
104 BS3CG1OPLOC_CTX,
105 BS3CG1OPLOC_CTX_ZX_VLMAX,
106 BS3CG1OPLOC_IMM,
107 BS3CG1OPLOC_MEM,
108 BS3CG1OPLOC_MEM_RW,
109 BS3CG1OPLOC_MEM_WO,
110 BS3CG1OPLOC_END
111} BS3CG1OPLOC;
112AssertCompile(BS3CG1OPLOC_END <= 16);
113
114
115/** Pointer to the generated test state. */
116typedef struct BS3CG1STATE *PBS3CG1STATE;
117
118/**
119 * Encoder callback.
120 * @returns Next encoding. If equal or less to @a iEncoding, no
121 * further encodings are available for testing.
122 * @param pThis The state.
123 * @param iEncoding The encoding.
124 */
125typedef unsigned BS3_NEAR_CODE FNBS3CG1ENCODER(PBS3CG1STATE pThis, unsigned iEncoding);
126/** Pointer to a encoder callback. */
127typedef FNBS3CG1ENCODER *PFNBS3CG1ENCODER;
128
129
130/**
131 * The state.
132 */
133typedef struct BS3CG1STATE
134{
135 /** @name Instruction details (expanded from BS3CG1INSTR).
136 * @{ */
137 /** Pointer to the mnemonic string (not terminated) (g_achBs3Cg1Mnemonics). */
138 const char BS3_FAR *pchMnemonic;
139 /** Pointer to the test header. */
140 PCBS3CG1TESTHDR pTestHdr;
141 /** Pointer to the per operand flags (g_abBs3Cg1Operands). */
142 const uint8_t BS3_FAR *pabOperands;
143 /** Opcode bytes (g_abBs3Cg1Opcodes). */
144 const uint8_t BS3_FAR *pabOpcodes;
145 /** The current instruction number in the input array (for error reporting). */
146 uint32_t iInstr;
147
148 /** The instruction flags. */
149 uint32_t fFlags;
150 /** The encoding. */
151 BS3CG1ENC enmEncoding;
152 /** The non-invalid encoding. This may differ from enmEncoding when
153 * Bs3Cg1CalcNoneIntelInvalidEncoding has been called. */
154 BS3CG1ENC enmEncodingNonInvalid;
155 /** The CPU test / CPU ID. */
156 BS3CG1CPU enmCpuTest;
157 /** Prefix sensitivity and requirements. */
158 BS3CG1PFXKIND enmPrefixKind;
159 /** Exception type (SSE, AVX). */
160 BS3CG1XCPTTYPE enmXcptType;
161 /** Per operand flags. */
162 BS3CG1OP aenmOperands[4];
163 /** Opcode bytes. */
164 uint8_t abOpcodes[4];
165 /** The instruction encoder. */
166 PFNBS3CG1ENCODER pfnEncoder;
167
168 /** The length of the mnemonic. */
169 uint8_t cchMnemonic;
170 /** Whether to advance the mnemonic pointer or not. */
171 uint8_t fAdvanceMnemonic;
172 /** The opcode map number. */
173 uint8_t uOpcodeMap;
174 /** The number of opcode bytes. */
175 uint8_t cbOpcodes;
176 /** Number of operands. */
177 uint8_t cOperands;
178 /** @} */
179
180 /** Default operand size. */
181 uint8_t cbOpDefault;
182 /** Operand size when overridden by 066h. */
183 uint8_t cbOpOvrd66;
184 /** Operand size when overridden by REX.W. */
185 uint8_t cbOpOvrdRexW;
186
187 /** Operand size in bytes (0 if not applicable). */
188 uint8_t cbOperand;
189 /** Current VEX.L value (UINT8_MAX if not applicable). */
190 uint8_t uVexL;
191 /** Current target ring (0..3). */
192 uint8_t uCpl;
193
194 /** The current test number. */
195 uint8_t iTest;
196
197 /** Target mode (g_bBs3CurrentMode). */
198 uint8_t bMode;
199 /** The CPU vendor (BS3CPUVENDOR). */
200 uint8_t bCpuVendor;
201 /** First ring being tested. */
202 uint8_t iFirstRing;
203 /** End of rings being tested. */
204 uint8_t iEndRing;
205
206 /** @name Current encoded instruction.
207 * @{ */
208 /** The size of the current instruction that we're testing. */
209 uint8_t cbCurInstr;
210 /** The size the prefixes. */
211 uint8_t cbCurPrefix;
212 /** The offset into abCurInstr of the immediate. */
213 uint8_t offCurImm;
214 /** Buffer for assembling the current instruction. */
215 uint8_t abCurInstr[23];
216
217 /** Set if the encoding can't be tested in the same ring as this test code.
218 * This is used to deal with encodings modifying SP/ESP/RSP. */
219 bool fSameRingNotOkay;
220 /** Whether to work the extended context too. */
221 bool fWorkExtCtx;
222 /** The aOperands index of the modrm.reg operand (if applicable). */
223 uint8_t iRegOp;
224 /** The aOperands index of the modrm.rm operand (if applicable). */
225 uint8_t iRmOp;
226
227 /** Operands details. */
228 struct
229 {
230 uint8_t cbOp;
231 /** BS3CG1OPLOC_XXX. */
232 uint8_t enmLocation;
233 /** BS3CG1OPLOC_XXX for memory encodings (MODRM.rm field). */
234 uint8_t enmLocationMem : 4;
235 /** BS3CG1OPLOC_XXX for register encodings (MODRM.rm field). */
236 uint8_t enmLocationReg : 4;
237 /** The BS3CG1DST value for this field.
238 * Set to BS3CG1DST_INVALID if memory or immediate. */
239 uint8_t idxField;
240 /** The base BS3CG1DST value for this field.
241 * Used only by some generalized encoders when dealing with registers. */
242 uint8_t idxFieldBase;
243 /** Depends on enmLocation.
244 * - BS3CG1OPLOC_IMM: offset relative to start of the instruction.
245 * - BS3CG1OPLOC_MEM: offset should be subtracted from &pbDataPg[_4K].
246 * - BS3CG1OPLOC_MEM_RW: offset should be subtracted from &pbDataPg[_4K].
247 * - BS3CG1OPLOC_MEM_RO: offset should be subtracted from &pbDataPg[_4K].
248 * - BS3CG1OPLOC_CTX: not used (use idxField instead).
249 */
250 uint8_t off;
251 } aOperands[4];
252 /** @} */
253
254 /** Page to put code in. When paging is enabled, the page before and after
255 * are marked not-present. */
256 uint8_t BS3_FAR *pbCodePg;
257 /** The flat address corresponding to pbCodePg. */
258 uintptr_t uCodePgFlat;
259 /** The 16-bit address corresponding to pbCodePg if relevant for bMode. */
260 RTFAR16 CodePgFar;
261 /** The IP/EIP/RIP value for pbCodePg[0] relative to CS (bMode). */
262 uintptr_t CodePgRip;
263
264 /** Page for placing data operands in. When paging is enabled, the page before
265 * and after are marked not-present. */
266 uint8_t BS3_FAR *pbDataPg;
267 /** The flat address corresponding to pbDataPg. */
268 uintptr_t uDataPgFlat;
269 /** The 16-bit address corresponding to pbDataPg. */
270 RTFAR16 DataPgFar;
271
272 /** The name corresponding to bMode. */
273 const char BS3_FAR *pszMode;
274 /** The short name corresponding to bMode. */
275 const char BS3_FAR *pszModeShort;
276
277 /** @name Expected result (modifiable by output program).
278 * @{ */
279 /** The expected exception based on operand values or result.
280 * UINT8_MAX if no special exception expected. */
281 uint8_t bValueXcpt;
282 /** @} */
283 /** Alignment exception expected by the encoder.
284 * UINT8_MAX if no special exception expected. */
285 uint8_t bAlignmentXcpt;
286 /** Set by the encoding method to indicating invalid encoding. */
287 bool fInvalidEncoding;
288 /** The result of Bs3Cg1CpuSetupFirst(). */
289 bool fCpuSetupFirstResult;
290
291 /** The context we're working on. */
292 BS3REGCTX Ctx;
293 /** The trap context and frame. */
294 BS3TRAPFRAME TrapFrame;
295 /** Initial contexts, one for each ring. */
296 BS3REGCTX aInitialCtxs[4];
297
298 /** The extended context we're working on (input, expected output). */
299 PBS3EXTCTX pExtCtx;
300 /** The extended result context (analoguous to TrapFrame). */
301 PBS3EXTCTX pResultExtCtx;
302 /** The initial extended context. */
303 PBS3EXTCTX pInitialExtCtx;
304
305 /** Memory operand scratch space. */
306 union
307 {
308 uint8_t ab[128];
309 uint16_t au16[128 / sizeof(uint16_t)];
310 uint32_t au32[128 / sizeof(uint32_t)];
311 uint64_t au64[128 / sizeof(uint64_t)];
312 } MemOp;
313
314 /** Array parallel to aInitialCtxs for saving segment registers. */
315 struct
316 {
317 RTSEL ds;
318 } aSavedSegRegs[4];
319
320} BS3CG1STATE;
321
322
323#define BS3CG1_PF_OZ UINT16_C(0x0001)
324#define BS3CG1_PF_AZ UINT16_C(0x0002)
325#define BS3CG1_PF_CS UINT16_C(0x0004)
326#define BS3CG1_PF_DS UINT16_C(0x0008)
327#define BS3CG1_PF_ES UINT16_C(0x0010)
328#define BS3CG1_PF_FS UINT16_C(0x0020)
329#define BS3CG1_PF_GS UINT16_C(0x0040)
330#define BS3CG1_PF_SS UINT16_C(0x0080)
331#define BS3CG1_PF_SEGS (BS3CG1_PF_CS | BS3CG1_PF_DS | BS3CG1_PF_ES | BS3CG1_PF_FS | BS3CG1_PF_GS | BS3CG1_PF_SS)
332#define BS3CG1_PF_MEM (BS3CG1_PF_SEGS | BS3CG1_PF_AZ)
333#define BS3CG1_PF_LK UINT16_C(0x0100)
334#define BS3CG1_PF_RN UINT16_C(0x0200)
335#define BS3CG1_PF_RZ UINT16_C(0x0400)
336#define BS3CG1_PF_W UINT16_C(0x0800) /**< REX.W */
337#define BS3CG1_PF_R UINT16_C(0x1000) /**< REX.R */
338#define BS3CG1_PF_B UINT16_C(0x2000) /**< REX.B */
339#define BS3CG1_PF_X UINT16_C(0x4000) /**< REX.X */
340
341
342/** Used in g_cbBs3Cg1DstFields to indicate that it's one of the 4 operands. */
343#define BS3CG1DSTSIZE_OPERAND UINT8_C(255)
344/** Used in g_cbBs3Cg1DstFields to indicate that the operand size determins
345 * the field size (2, 4, or 8). */
346#define BS3CG1DSTSIZE_OPERAND_SIZE_GRP UINT8_C(254)
347
348
349
350/*********************************************************************************************************************************
351* Global Variables *
352*********************************************************************************************************************************/
353/** Destination field sizes indexed by bBS3CG1DST.
354 * Zero means operand size sized. */
355static const uint8_t g_acbBs3Cg1DstFields[] =
356{
357 /* [BS3CG1DST_INVALID] = */ BS3CG1DSTSIZE_OPERAND,
358
359 /* [BS3CG1DST_OP1] = */ BS3CG1DSTSIZE_OPERAND,
360 /* [BS3CG1DST_OP2] = */ BS3CG1DSTSIZE_OPERAND,
361 /* [BS3CG1DST_OP3] = */ BS3CG1DSTSIZE_OPERAND,
362 /* [BS3CG1DST_OP4] = */ BS3CG1DSTSIZE_OPERAND,
363 /* [BS3CG1DST_EFL] = */ 4,
364 /* [BS3CG1DST_EFL_UNDEF]=*/ 4,
365
366 /* [BS3CG1DST_AL] = */ 1,
367 /* [BS3CG1DST_CL] = */ 1,
368 /* [BS3CG1DST_DL] = */ 1,
369 /* [BS3CG1DST_BL] = */ 1,
370 /* [BS3CG1DST_AH] = */ 1,
371 /* [BS3CG1DST_CH] = */ 1,
372 /* [BS3CG1DST_DH] = */ 1,
373 /* [BS3CG1DST_BH] = */ 1,
374 /* [BS3CG1DST_SPL] = */ 1,
375 /* [BS3CG1DST_BPL] = */ 1,
376 /* [BS3CG1DST_SIL] = */ 1,
377 /* [BS3CG1DST_DIL] = */ 1,
378 /* [BS3CG1DST_R8L] = */ 1,
379 /* [BS3CG1DST_R9L] = */ 1,
380 /* [BS3CG1DST_R10L] = */ 1,
381 /* [BS3CG1DST_R11L] = */ 1,
382 /* [BS3CG1DST_R12L] = */ 1,
383 /* [BS3CG1DST_R13L] = */ 1,
384 /* [BS3CG1DST_R14L] = */ 1,
385 /* [BS3CG1DST_R15L] = */ 1,
386
387 /* [BS3CG1DST_AX] = */ 2,
388 /* [BS3CG1DST_CX] = */ 2,
389 /* [BS3CG1DST_DX] = */ 2,
390 /* [BS3CG1DST_BX] = */ 2,
391 /* [BS3CG1DST_SP] = */ 2,
392 /* [BS3CG1DST_BP] = */ 2,
393 /* [BS3CG1DST_SI] = */ 2,
394 /* [BS3CG1DST_DI] = */ 2,
395 /* [BS3CG1DST_R8W] = */ 2,
396 /* [BS3CG1DST_R9W] = */ 2,
397 /* [BS3CG1DST_R10W] = */ 2,
398 /* [BS3CG1DST_R11W] = */ 2,
399 /* [BS3CG1DST_R12W] = */ 2,
400 /* [BS3CG1DST_R13W] = */ 2,
401 /* [BS3CG1DST_R14W] = */ 2,
402 /* [BS3CG1DST_R15W] = */ 2,
403
404 /* [BS3CG1DST_EAX] = */ 4,
405 /* [BS3CG1DST_ECX] = */ 4,
406 /* [BS3CG1DST_EDX] = */ 4,
407 /* [BS3CG1DST_EBX] = */ 4,
408 /* [BS3CG1DST_ESP] = */ 4,
409 /* [BS3CG1DST_EBP] = */ 4,
410 /* [BS3CG1DST_ESI] = */ 4,
411 /* [BS3CG1DST_EDI] = */ 4,
412 /* [BS3CG1DST_R8D] = */ 4,
413 /* [BS3CG1DST_R9D] = */ 4,
414 /* [BS3CG1DST_R10D] = */ 4,
415 /* [BS3CG1DST_R11D] = */ 4,
416 /* [BS3CG1DST_R12D] = */ 4,
417 /* [BS3CG1DST_R13D] = */ 4,
418 /* [BS3CG1DST_R14D] = */ 4,
419 /* [BS3CG1DST_R15D] = */ 4,
420
421 /* [BS3CG1DST_RAX] = */ 8,
422 /* [BS3CG1DST_RCX] = */ 8,
423 /* [BS3CG1DST_RDX] = */ 8,
424 /* [BS3CG1DST_RBX] = */ 8,
425 /* [BS3CG1DST_RSP] = */ 8,
426 /* [BS3CG1DST_RBP] = */ 8,
427 /* [BS3CG1DST_RSI] = */ 8,
428 /* [BS3CG1DST_RDI] = */ 8,
429 /* [BS3CG1DST_R8] = */ 8,
430 /* [BS3CG1DST_R9] = */ 8,
431 /* [BS3CG1DST_R10] = */ 8,
432 /* [BS3CG1DST_R11] = */ 8,
433 /* [BS3CG1DST_R12] = */ 8,
434 /* [BS3CG1DST_R13] = */ 8,
435 /* [BS3CG1DST_R14] = */ 8,
436 /* [BS3CG1DST_R15] = */ 8,
437
438 /* [BS3CG1DST_OZ_RAX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
439 /* [BS3CG1DST_OZ_RCX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
440 /* [BS3CG1DST_OZ_RDX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
441 /* [BS3CG1DST_OZ_RBX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
442 /* [BS3CG1DST_OZ_RSP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
443 /* [BS3CG1DST_OZ_RBP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
444 /* [BS3CG1DST_OZ_RSI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
445 /* [BS3CG1DST_OZ_RDI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
446 /* [BS3CG1DST_OZ_R8] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
447 /* [BS3CG1DST_OZ_R9] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
448 /* [BS3CG1DST_OZ_R10] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
449 /* [BS3CG1DST_OZ_R11] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
450 /* [BS3CG1DST_OZ_R12] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
451 /* [BS3CG1DST_OZ_R13] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
452 /* [BS3CG1DST_OZ_R14] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
453 /* [BS3CG1DST_OZ_R15] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
454
455 /* [BS3CG1DST_CR0] = */ 4,
456 /* [BS3CG1DST_CR4] = */ 4,
457 /* [BS3CG1DST_XCR0] = */ 8,
458
459 /* [BS3CG1DST_FCW] = */ 2,
460 /* [BS3CG1DST_FSW] = */ 2,
461 /* [BS3CG1DST_FTW] = */ 2,
462 /* [BS3CG1DST_FOP] = */ 2,
463 /* [BS3CG1DST_FPUIP] = */ 2,
464 /* [BS3CG1DST_FPUCS] = */ 2,
465 /* [BS3CG1DST_FPUDP] = */ 2,
466 /* [BS3CG1DST_FPUDS] = */ 2,
467 /* [BS3CG1DST_MXCSR] = */ 4,
468 /* [BS3CG1DST_ST0] = */ 12,
469 /* [BS3CG1DST_ST1] = */ 12,
470 /* [BS3CG1DST_ST2] = */ 12,
471 /* [BS3CG1DST_ST3] = */ 12,
472 /* [BS3CG1DST_ST4] = */ 12,
473 /* [BS3CG1DST_ST5] = */ 12,
474 /* [BS3CG1DST_ST6] = */ 12,
475 /* [BS3CG1DST_ST7] = */ 12,
476 /* [BS3CG1DST_MM0] = */ 8,
477 /* [BS3CG1DST_MM1] = */ 8,
478 /* [BS3CG1DST_MM2] = */ 8,
479 /* [BS3CG1DST_MM3] = */ 8,
480 /* [BS3CG1DST_MM4] = */ 8,
481 /* [BS3CG1DST_MM5] = */ 8,
482 /* [BS3CG1DST_MM6] = */ 8,
483 /* [BS3CG1DST_MM7] = */ 8,
484 /* [BS3CG1DST_MM0_LO_ZX] = */ 4,
485 /* [BS3CG1DST_MM1_LO_ZX] = */ 4,
486 /* [BS3CG1DST_MM2_LO_ZX] = */ 4,
487 /* [BS3CG1DST_MM3_LO_ZX] = */ 4,
488 /* [BS3CG1DST_MM4_LO_ZX] = */ 4,
489 /* [BS3CG1DST_MM5_LO_ZX] = */ 4,
490 /* [BS3CG1DST_MM6_LO_ZX] = */ 4,
491 /* [BS3CG1DST_MM7_LO_ZX] = */ 4,
492 /* [BS3CG1DST_XMM0] = */ 16,
493 /* [BS3CG1DST_XMM1] = */ 16,
494 /* [BS3CG1DST_XMM2] = */ 16,
495 /* [BS3CG1DST_XMM3] = */ 16,
496 /* [BS3CG1DST_XMM4] = */ 16,
497 /* [BS3CG1DST_XMM5] = */ 16,
498 /* [BS3CG1DST_XMM6] = */ 16,
499 /* [BS3CG1DST_XMM7] = */ 16,
500 /* [BS3CG1DST_XMM8] = */ 16,
501 /* [BS3CG1DST_XMM9] = */ 16,
502 /* [BS3CG1DST_XMM10] = */ 16,
503 /* [BS3CG1DST_XMM11] = */ 16,
504 /* [BS3CG1DST_XMM12] = */ 16,
505 /* [BS3CG1DST_XMM13] = */ 16,
506 /* [BS3CG1DST_XMM14] = */ 16,
507 /* [BS3CG1DST_XMM15] = */ 16,
508 /* [BS3CG1DST_XMM0_LO] = */ 8,
509 /* [BS3CG1DST_XMM1_LO] = */ 8,
510 /* [BS3CG1DST_XMM2_LO] = */ 8,
511 /* [BS3CG1DST_XMM3_LO] = */ 8,
512 /* [BS3CG1DST_XMM4_LO] = */ 8,
513 /* [BS3CG1DST_XMM5_LO] = */ 8,
514 /* [BS3CG1DST_XMM6_LO] = */ 8,
515 /* [BS3CG1DST_XMM7_LO] = */ 8,
516 /* [BS3CG1DST_XMM8_LO] = */ 8,
517 /* [BS3CG1DST_XMM9_LO] = */ 8,
518 /* [BS3CG1DST_XMM10_LO] = */ 8,
519 /* [BS3CG1DST_XMM11_LO] = */ 8,
520 /* [BS3CG1DST_XMM12_LO] = */ 8,
521 /* [BS3CG1DST_XMM13_LO] = */ 8,
522 /* [BS3CG1DST_XMM14_LO] = */ 8,
523 /* [BS3CG1DST_XMM15_LO] = */ 8,
524 /* [BS3CG1DST_XMM0_HI] = */ 8,
525 /* [BS3CG1DST_XMM1_HI] = */ 8,
526 /* [BS3CG1DST_XMM2_HI] = */ 8,
527 /* [BS3CG1DST_XMM3_HI] = */ 8,
528 /* [BS3CG1DST_XMM4_HI] = */ 8,
529 /* [BS3CG1DST_XMM5_HI] = */ 8,
530 /* [BS3CG1DST_XMM6_HI] = */ 8,
531 /* [BS3CG1DST_XMM7_HI] = */ 8,
532 /* [BS3CG1DST_XMM8_HI] = */ 8,
533 /* [BS3CG1DST_XMM9_HI] = */ 8,
534 /* [BS3CG1DST_XMM10_HI] = */ 8,
535 /* [BS3CG1DST_XMM11_HI] = */ 8,
536 /* [BS3CG1DST_XMM12_HI] = */ 8,
537 /* [BS3CG1DST_XMM13_HI] = */ 8,
538 /* [BS3CG1DST_XMM14_HI] = */ 8,
539 /* [BS3CG1DST_XMM15_HI] = */ 8,
540 /* [BS3CG1DST_XMM0_LO_ZX] = */ 8,
541 /* [BS3CG1DST_XMM1_LO_ZX] = */ 8,
542 /* [BS3CG1DST_XMM2_LO_ZX] = */ 8,
543 /* [BS3CG1DST_XMM3_LO_ZX] = */ 8,
544 /* [BS3CG1DST_XMM4_LO_ZX] = */ 8,
545 /* [BS3CG1DST_XMM5_LO_ZX] = */ 8,
546 /* [BS3CG1DST_XMM6_LO_ZX] = */ 8,
547 /* [BS3CG1DST_XMM7_LO_ZX] = */ 8,
548 /* [BS3CG1DST_XMM8_LO_ZX] = */ 8,
549 /* [BS3CG1DST_XMM9_LO_ZX] = */ 8,
550 /* [BS3CG1DST_XMM10_LO_ZX] = */ 8,
551 /* [BS3CG1DST_XMM11_LO_ZX] = */ 8,
552 /* [BS3CG1DST_XMM12_LO_ZX] = */ 8,
553 /* [BS3CG1DST_XMM13_LO_ZX] = */ 8,
554 /* [BS3CG1DST_XMM14_LO_ZX] = */ 8,
555 /* [BS3CG1DST_XMM15_LO_ZX] = */ 8,
556 /* [BS3CG1DST_XMM0_DW0] = */ 4,
557 /* [BS3CG1DST_XMM1_DW0] = */ 4,
558 /* [BS3CG1DST_XMM2_DW0] = */ 4,
559 /* [BS3CG1DST_XMM3_DW0] = */ 4,
560 /* [BS3CG1DST_XMM4_DW0] = */ 4,
561 /* [BS3CG1DST_XMM5_DW0] = */ 4,
562 /* [BS3CG1DST_XMM6_DW0] = */ 4,
563 /* [BS3CG1DST_XMM7_DW0] = */ 4,
564 /* [BS3CG1DST_XMM8_DW0] = */ 4,
565 /* [BS3CG1DST_XMM9_DW0] = */ 4,
566 /* [BS3CG1DST_XMM10_DW0] = */ 4,
567 /* [BS3CG1DST_XMM11_DW0] = */ 4,
568 /* [BS3CG1DST_XMM12_DW0] = */ 4,
569 /* [BS3CG1DST_XMM13_DW0] = */ 4,
570 /* [BS3CG1DST_XMM14_DW0] = */ 4,
571 /* [BS3CG1DST_XMM15_DW0] = */ 4,
572 /* [BS3CG1DST_XMM0_DW0_ZX] = */ 4,
573 /* [BS3CG1DST_XMM1_DW0_ZX] = */ 4,
574 /* [BS3CG1DST_XMM2_DW0_ZX] = */ 4,
575 /* [BS3CG1DST_XMM3_DW0_ZX] = */ 4,
576 /* [BS3CG1DST_XMM4_DW0_ZX] = */ 4,
577 /* [BS3CG1DST_XMM5_DW0_ZX] = */ 4,
578 /* [BS3CG1DST_XMM6_DW0_ZX] = */ 4,
579 /* [BS3CG1DST_XMM7_DW0_ZX] = */ 4,
580 /* [BS3CG1DST_XMM8_DW0_ZX] = */ 4,
581 /* [BS3CG1DST_XMM9_DW0_ZX] = */ 4,
582 /* [BS3CG1DST_XMM10_DW0_ZX] =*/ 4,
583 /* [BS3CG1DST_XMM11_DW0_ZX] =*/ 4,
584 /* [BS3CG1DST_XMM12_DW0_ZX] =*/ 4,
585 /* [BS3CG1DST_XMM13_DW0_ZX] =*/ 4,
586 /* [BS3CG1DST_XMM14_DW0_ZX] =*/ 4,
587 /* [BS3CG1DST_XMM15_DW0_ZX] =*/ 4,
588 /* [BS3CG1DST_XMM0_HI96] = */ 12,
589 /* [BS3CG1DST_XMM1_HI96] = */ 12,
590 /* [BS3CG1DST_XMM2_HI96] = */ 12,
591 /* [BS3CG1DST_XMM3_HI96] = */ 12,
592 /* [BS3CG1DST_XMM4_HI96] = */ 12,
593 /* [BS3CG1DST_XMM5_HI96] = */ 12,
594 /* [BS3CG1DST_XMM6_HI96] = */ 12,
595 /* [BS3CG1DST_XMM7_HI96] = */ 12,
596 /* [BS3CG1DST_XMM8_HI96] = */ 12,
597 /* [BS3CG1DST_XMM9_HI96] = */ 12,
598 /* [BS3CG1DST_XMM10_HI96] =*/ 12,
599 /* [BS3CG1DST_XMM11_HI96] =*/ 12,
600 /* [BS3CG1DST_XMM12_HI96] =*/ 12,
601 /* [BS3CG1DST_XMM13_HI96] =*/ 12,
602 /* [BS3CG1DST_XMM14_HI96] =*/ 12,
603 /* [BS3CG1DST_XMM15_HI96] =*/ 12,
604 /* [BS3CG1DST_YMM0] = */ 32,
605 /* [BS3CG1DST_YMM1] = */ 32,
606 /* [BS3CG1DST_YMM2] = */ 32,
607 /* [BS3CG1DST_YMM3] = */ 32,
608 /* [BS3CG1DST_YMM4] = */ 32,
609 /* [BS3CG1DST_YMM5] = */ 32,
610 /* [BS3CG1DST_YMM6] = */ 32,
611 /* [BS3CG1DST_YMM7] = */ 32,
612 /* [BS3CG1DST_YMM8] = */ 32,
613 /* [BS3CG1DST_YMM9] = */ 32,
614 /* [BS3CG1DST_YMM10] = */ 32,
615 /* [BS3CG1DST_YMM11] = */ 32,
616 /* [BS3CG1DST_YMM12] = */ 32,
617 /* [BS3CG1DST_YMM13] = */ 32,
618 /* [BS3CG1DST_YMM14] = */ 32,
619 /* [BS3CG1DST_YMM15] = */ 32,
620
621 /* [BS3CG1DST_VALUE_XCPT] = */ 1,
622};
623AssertCompile(RT_ELEMENTS(g_acbBs3Cg1DstFields) == BS3CG1DST_END);
624
625/** Destination field offset indexed by bBS3CG1DST.
626 * Zero means operand size sized. */
627static const unsigned g_aoffBs3Cg1DstFields[] =
628{
629 /* [BS3CG1DST_INVALID] = */ ~0U,
630 /* [BS3CG1DST_OP1] = */ ~0U,
631 /* [BS3CG1DST_OP2] = */ ~0U,
632 /* [BS3CG1DST_OP3] = */ ~0U,
633 /* [BS3CG1DST_OP4] = */ ~0U,
634 /* [BS3CG1DST_EFL] = */ RT_OFFSETOF(BS3REGCTX, rflags),
635 /* [BS3CG1DST_EFL_UNDEF]=*/ ~0, /* special field */
636
637 /* [BS3CG1DST_AL] = */ RT_OFFSETOF(BS3REGCTX, rax.u8),
638 /* [BS3CG1DST_CL] = */ RT_OFFSETOF(BS3REGCTX, rcx.u8),
639 /* [BS3CG1DST_DL] = */ RT_OFFSETOF(BS3REGCTX, rdx.u8),
640 /* [BS3CG1DST_BL] = */ RT_OFFSETOF(BS3REGCTX, rbx.u8),
641 /* [BS3CG1DST_AH] = */ RT_OFFSETOF(BS3REGCTX, rax.b.bHi),
642 /* [BS3CG1DST_CH] = */ RT_OFFSETOF(BS3REGCTX, rcx.b.bHi),
643 /* [BS3CG1DST_DH] = */ RT_OFFSETOF(BS3REGCTX, rdx.b.bHi),
644 /* [BS3CG1DST_BH] = */ RT_OFFSETOF(BS3REGCTX, rbx.b.bHi),
645 /* [BS3CG1DST_SPL] = */ RT_OFFSETOF(BS3REGCTX, rsp.u8),
646 /* [BS3CG1DST_BPL] = */ RT_OFFSETOF(BS3REGCTX, rbp.u8),
647 /* [BS3CG1DST_SIL] = */ RT_OFFSETOF(BS3REGCTX, rsi.u8),
648 /* [BS3CG1DST_DIL] = */ RT_OFFSETOF(BS3REGCTX, rdi.u8),
649 /* [BS3CG1DST_R8L] = */ RT_OFFSETOF(BS3REGCTX, r8.u8),
650 /* [BS3CG1DST_R9L] = */ RT_OFFSETOF(BS3REGCTX, r9.u8),
651 /* [BS3CG1DST_R10L] = */ RT_OFFSETOF(BS3REGCTX, r10.u8),
652 /* [BS3CG1DST_R11L] = */ RT_OFFSETOF(BS3REGCTX, r11.u8),
653 /* [BS3CG1DST_R12L] = */ RT_OFFSETOF(BS3REGCTX, r12.u8),
654 /* [BS3CG1DST_R13L] = */ RT_OFFSETOF(BS3REGCTX, r13.u8),
655 /* [BS3CG1DST_R14L] = */ RT_OFFSETOF(BS3REGCTX, r14.u8),
656 /* [BS3CG1DST_R15L] = */ RT_OFFSETOF(BS3REGCTX, r15.u8),
657
658 /* [BS3CG1DST_AX] = */ RT_OFFSETOF(BS3REGCTX, rax.u16),
659 /* [BS3CG1DST_CX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u16),
660 /* [BS3CG1DST_DX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u16),
661 /* [BS3CG1DST_BX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u16),
662 /* [BS3CG1DST_SP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u16),
663 /* [BS3CG1DST_BP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u16),
664 /* [BS3CG1DST_SI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u16),
665 /* [BS3CG1DST_DI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u16),
666 /* [BS3CG1DST_R8W] = */ RT_OFFSETOF(BS3REGCTX, r8.u16),
667 /* [BS3CG1DST_R9W] = */ RT_OFFSETOF(BS3REGCTX, r9.u16),
668 /* [BS3CG1DST_R10W] = */ RT_OFFSETOF(BS3REGCTX, r10.u16),
669 /* [BS3CG1DST_R11W] = */ RT_OFFSETOF(BS3REGCTX, r11.u16),
670 /* [BS3CG1DST_R12W] = */ RT_OFFSETOF(BS3REGCTX, r12.u16),
671 /* [BS3CG1DST_R13W] = */ RT_OFFSETOF(BS3REGCTX, r13.u16),
672 /* [BS3CG1DST_R14W] = */ RT_OFFSETOF(BS3REGCTX, r14.u16),
673 /* [BS3CG1DST_R15W] = */ RT_OFFSETOF(BS3REGCTX, r15.u16),
674
675 /* [BS3CG1DST_EAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u32),
676 /* [BS3CG1DST_ECX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u32),
677 /* [BS3CG1DST_EDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u32),
678 /* [BS3CG1DST_EBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u32),
679 /* [BS3CG1DST_ESP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u32),
680 /* [BS3CG1DST_EBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u32),
681 /* [BS3CG1DST_ESI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u32),
682 /* [BS3CG1DST_EDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u32),
683 /* [BS3CG1DST_R8D] = */ RT_OFFSETOF(BS3REGCTX, r8.u32),
684 /* [BS3CG1DST_R9D] = */ RT_OFFSETOF(BS3REGCTX, r9.u32),
685 /* [BS3CG1DST_R10D] = */ RT_OFFSETOF(BS3REGCTX, r10.u32),
686 /* [BS3CG1DST_R11D] = */ RT_OFFSETOF(BS3REGCTX, r11.u32),
687 /* [BS3CG1DST_R12D] = */ RT_OFFSETOF(BS3REGCTX, r12.u32),
688 /* [BS3CG1DST_R13D] = */ RT_OFFSETOF(BS3REGCTX, r13.u32),
689 /* [BS3CG1DST_R14D] = */ RT_OFFSETOF(BS3REGCTX, r14.u32),
690 /* [BS3CG1DST_R15D] = */ RT_OFFSETOF(BS3REGCTX, r15.u32),
691
692 /* [BS3CG1DST_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u64),
693 /* [BS3CG1DST_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u64),
694 /* [BS3CG1DST_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u64),
695 /* [BS3CG1DST_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u64),
696 /* [BS3CG1DST_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u64),
697 /* [BS3CG1DST_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u64),
698 /* [BS3CG1DST_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u64),
699 /* [BS3CG1DST_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u64),
700 /* [BS3CG1DST_R8] = */ RT_OFFSETOF(BS3REGCTX, r8.u64),
701 /* [BS3CG1DST_R9] = */ RT_OFFSETOF(BS3REGCTX, r9.u64),
702 /* [BS3CG1DST_R10] = */ RT_OFFSETOF(BS3REGCTX, r10.u64),
703 /* [BS3CG1DST_R11] = */ RT_OFFSETOF(BS3REGCTX, r11.u64),
704 /* [BS3CG1DST_R12] = */ RT_OFFSETOF(BS3REGCTX, r12.u64),
705 /* [BS3CG1DST_R13] = */ RT_OFFSETOF(BS3REGCTX, r13.u64),
706 /* [BS3CG1DST_R14] = */ RT_OFFSETOF(BS3REGCTX, r14.u64),
707 /* [BS3CG1DST_R15] = */ RT_OFFSETOF(BS3REGCTX, r15.u64),
708
709 /* [BS3CG1DST_OZ_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax),
710 /* [BS3CG1DST_OZ_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx),
711 /* [BS3CG1DST_OZ_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx),
712 /* [BS3CG1DST_OZ_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx),
713 /* [BS3CG1DST_OZ_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp),
714 /* [BS3CG1DST_OZ_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp),
715 /* [BS3CG1DST_OZ_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi),
716 /* [BS3CG1DST_OZ_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi),
717 /* [BS3CG1DST_OZ_R8] = */ RT_OFFSETOF(BS3REGCTX, r8),
718 /* [BS3CG1DST_OZ_R9] = */ RT_OFFSETOF(BS3REGCTX, r9),
719 /* [BS3CG1DST_OZ_R10] = */ RT_OFFSETOF(BS3REGCTX, r10),
720 /* [BS3CG1DST_OZ_R11] = */ RT_OFFSETOF(BS3REGCTX, r11),
721 /* [BS3CG1DST_OZ_R12] = */ RT_OFFSETOF(BS3REGCTX, r12),
722 /* [BS3CG1DST_OZ_R13] = */ RT_OFFSETOF(BS3REGCTX, r13),
723 /* [BS3CG1DST_OZ_R14] = */ RT_OFFSETOF(BS3REGCTX, r14),
724 /* [BS3CG1DST_OZ_R15] = */ RT_OFFSETOF(BS3REGCTX, r15),
725
726 /* [BS3CG1DST_CR0] = */ RT_OFFSETOF(BS3REGCTX, cr0),
727 /* [BS3CG1DST_CR4] = */ RT_OFFSETOF(BS3REGCTX, cr4),
728 /* [BS3CG1DST_XCR0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, fXcr0Saved),
729
730 /* [BS3CG1DST_FCW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FCW),
731 /* [BS3CG1DST_FSW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FSW),
732 /* [BS3CG1DST_FTW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FTW),
733 /* [BS3CG1DST_FOP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FOP),
734 /* [BS3CG1DST_FPUIP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUIP),
735 /* [BS3CG1DST_FPUCS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.CS),
736 /* [BS3CG1DST_FPUDP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUDP),
737 /* [BS3CG1DST_FPUDS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.DS),
738 /* [BS3CG1DST_MXCSR] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.MXCSR),
739 /* [BS3CG1DST_ST0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
740 /* [BS3CG1DST_ST1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
741 /* [BS3CG1DST_ST2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
742 /* [BS3CG1DST_ST3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
743 /* [BS3CG1DST_ST4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
744 /* [BS3CG1DST_ST5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
745 /* [BS3CG1DST_ST6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
746 /* [BS3CG1DST_ST7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
747 /* [BS3CG1DST_MM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
748 /* [BS3CG1DST_MM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
749 /* [BS3CG1DST_MM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
750 /* [BS3CG1DST_MM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
751 /* [BS3CG1DST_MM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
752 /* [BS3CG1DST_MM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
753 /* [BS3CG1DST_MM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
754 /* [BS3CG1DST_MM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
755 /* [BS3CG1DST_MM0_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
756 /* [BS3CG1DST_MM1_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
757 /* [BS3CG1DST_MM2_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
758 /* [BS3CG1DST_MM3_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
759 /* [BS3CG1DST_MM4_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
760 /* [BS3CG1DST_MM5_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
761 /* [BS3CG1DST_MM6_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
762 /* [BS3CG1DST_MM7_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
763
764 /* [BS3CG1DST_XMM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
765 /* [BS3CG1DST_XMM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
766 /* [BS3CG1DST_XMM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
767 /* [BS3CG1DST_XMM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
768 /* [BS3CG1DST_XMM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
769 /* [BS3CG1DST_XMM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
770 /* [BS3CG1DST_XMM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
771 /* [BS3CG1DST_XMM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
772 /* [BS3CG1DST_XMM8] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
773 /* [BS3CG1DST_XMM9] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
774 /* [BS3CG1DST_XMM10] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
775 /* [BS3CG1DST_XMM11] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
776 /* [BS3CG1DST_XMM12] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
777 /* [BS3CG1DST_XMM13] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
778 /* [BS3CG1DST_XMM14] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
779 /* [BS3CG1DST_XMM15] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
780 /* [BS3CG1DST_XMM0_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
781 /* [BS3CG1DST_XMM1_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
782 /* [BS3CG1DST_XMM2_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
783 /* [BS3CG1DST_XMM3_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
784 /* [BS3CG1DST_XMM4_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
785 /* [BS3CG1DST_XMM5_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
786 /* [BS3CG1DST_XMM6_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
787 /* [BS3CG1DST_XMM7_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
788 /* [BS3CG1DST_XMM8_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
789 /* [BS3CG1DST_XMM9_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
790 /* [BS3CG1DST_XMM10_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
791 /* [BS3CG1DST_XMM11_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
792 /* [BS3CG1DST_XMM12_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
793 /* [BS3CG1DST_XMM13_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
794 /* [BS3CG1DST_XMM14_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
795 /* [BS3CG1DST_XMM15_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
796 /* [BS3CG1DST_XMM0_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]) + sizeof(uint64_t),
797 /* [BS3CG1DST_XMM1_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]) + sizeof(uint64_t),
798 /* [BS3CG1DST_XMM2_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]) + sizeof(uint64_t),
799 /* [BS3CG1DST_XMM3_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]) + sizeof(uint64_t),
800 /* [BS3CG1DST_XMM4_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]) + sizeof(uint64_t),
801 /* [BS3CG1DST_XMM5_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]) + sizeof(uint64_t),
802 /* [BS3CG1DST_XMM6_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]) + sizeof(uint64_t),
803 /* [BS3CG1DST_XMM7_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]) + sizeof(uint64_t),
804 /* [BS3CG1DST_XMM8_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]) + sizeof(uint64_t),
805 /* [BS3CG1DST_XMM9_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]) + sizeof(uint64_t),
806 /* [BS3CG1DST_XMM10_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]) + sizeof(uint64_t),
807 /* [BS3CG1DST_XMM11_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]) + sizeof(uint64_t),
808 /* [BS3CG1DST_XMM12_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]) + sizeof(uint64_t),
809 /* [BS3CG1DST_XMM13_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]) + sizeof(uint64_t),
810 /* [BS3CG1DST_XMM14_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]) + sizeof(uint64_t),
811 /* [BS3CG1DST_XMM15_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) + sizeof(uint64_t),
812 /* [BS3CG1DST_XMM0_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
813 /* [BS3CG1DST_XMM1_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
814 /* [BS3CG1DST_XMM2_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
815 /* [BS3CG1DST_XMM3_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
816 /* [BS3CG1DST_XMM4_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
817 /* [BS3CG1DST_XMM5_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
818 /* [BS3CG1DST_XMM6_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
819 /* [BS3CG1DST_XMM7_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
820 /* [BS3CG1DST_XMM8_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
821 /* [BS3CG1DST_XMM9_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
822 /* [BS3CG1DST_XMM10_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
823 /* [BS3CG1DST_XMM11_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
824 /* [BS3CG1DST_XMM12_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
825 /* [BS3CG1DST_XMM13_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
826 /* [BS3CG1DST_XMM14_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
827 /* [BS3CG1DST_XMM15_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
828 /* [BS3CG1DST_XMM0_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
829 /* [BS3CG1DST_XMM1_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
830 /* [BS3CG1DST_XMM2_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
831 /* [BS3CG1DST_XMM3_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
832 /* [BS3CG1DST_XMM4_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
833 /* [BS3CG1DST_XMM5_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
834 /* [BS3CG1DST_XMM6_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
835 /* [BS3CG1DST_XMM7_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
836 /* [BS3CG1DST_XMM8_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
837 /* [BS3CG1DST_XMM9_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
838 /* [BS3CG1DST_XMM10_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
839 /* [BS3CG1DST_XMM11_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
840 /* [BS3CG1DST_XMM12_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
841 /* [BS3CG1DST_XMM13_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
842 /* [BS3CG1DST_XMM14_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
843 /* [BS3CG1DST_XMM15_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
844 /* [BS3CG1DST_XMM0_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
845 /* [BS3CG1DST_XMM1_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
846 /* [BS3CG1DST_XMM2_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
847 /* [BS3CG1DST_XMM3_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
848 /* [BS3CG1DST_XMM4_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
849 /* [BS3CG1DST_XMM5_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
850 /* [BS3CG1DST_XMM6_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
851 /* [BS3CG1DST_XMM7_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
852 /* [BS3CG1DST_XMM8_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
853 /* [BS3CG1DST_XMM9_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
854 /* [BS3CG1DST_XMM10_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
855 /* [BS3CG1DST_XMM11_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
856 /* [BS3CG1DST_XMM12_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
857 /* [BS3CG1DST_XMM13_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
858 /* [BS3CG1DST_XMM14_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
859 /* [BS3CG1DST_XMM15_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
860 /* [BS3CG1DST_XMM0_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0].au32[1]),
861 /* [BS3CG1DST_XMM1_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1].au32[1]),
862 /* [BS3CG1DST_XMM2_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2].au32[1]),
863 /* [BS3CG1DST_XMM3_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3].au32[1]),
864 /* [BS3CG1DST_XMM4_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4].au32[1]),
865 /* [BS3CG1DST_XMM5_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5].au32[1]),
866 /* [BS3CG1DST_XMM6_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6].au32[1]),
867 /* [BS3CG1DST_XMM7_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7].au32[1]),
868 /* [BS3CG1DST_XMM8_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8].au32[1]),
869 /* [BS3CG1DST_XMM9_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9].au32[1]),
870 /* [BS3CG1DST_XMM10_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10].au32[1]),
871 /* [BS3CG1DST_XMM11_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11].au32[1]),
872 /* [BS3CG1DST_XMM12_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12].au32[1]),
873 /* [BS3CG1DST_XMM13_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13].au32[1]),
874 /* [BS3CG1DST_XMM14_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14].au32[1]),
875 /* [BS3CG1DST_XMM15_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15].au32[1]),
876
877 /* [BS3CG1DST_YMM0] = */ ~0U,
878 /* [BS3CG1DST_YMM1] = */ ~0U,
879 /* [BS3CG1DST_YMM2] = */ ~0U,
880 /* [BS3CG1DST_YMM3] = */ ~0U,
881 /* [BS3CG1DST_YMM4] = */ ~0U,
882 /* [BS3CG1DST_YMM5] = */ ~0U,
883 /* [BS3CG1DST_YMM6] = */ ~0U,
884 /* [BS3CG1DST_YMM7] = */ ~0U,
885 /* [BS3CG1DST_YMM8] = */ ~0U,
886 /* [BS3CG1DST_YMM9] = */ ~0U,
887 /* [BS3CG1DST_YMM10] = */ ~0U,
888 /* [BS3CG1DST_YMM11] = */ ~0U,
889 /* [BS3CG1DST_YMM12] = */ ~0U,
890 /* [BS3CG1DST_YMM13] = */ ~0U,
891 /* [BS3CG1DST_YMM14] = */ ~0U,
892 /* [BS3CG1DST_YMM15] = */ ~0U,
893
894 /* [BS3CG1DST_VALUE_XCPT] = */ ~0U,
895};
896AssertCompile(RT_ELEMENTS(g_aoffBs3Cg1DstFields) == BS3CG1DST_END);
897
898/** Destination field names. */
899static const struct { char sz[12]; } g_aszBs3Cg1DstFields[] =
900{
901 { "INVALID" },
902 { "OP1" },
903 { "OP2" },
904 { "OP3" },
905 { "OP4" },
906 { "EFL" },
907 { "EFL_UND" },
908
909 { "AL" },
910 { "CL" },
911 { "DL" },
912 { "BL" },
913 { "AH" },
914 { "CH" },
915 { "DH" },
916 { "BH" },
917 { "SPL" },
918 { "BPL" },
919 { "SIL" },
920 { "DIL" },
921 { "R8L" },
922 { "R9L" },
923 { "R10L" },
924 { "R11L" },
925 { "R12L" },
926 { "R13L" },
927 { "R14L" },
928 { "R15L" },
929
930 { "AX" },
931 { "CX" },
932 { "DX" },
933 { "BX" },
934 { "SP" },
935 { "BP" },
936 { "SI" },
937 { "DI" },
938 { "R8W" },
939 { "R9W" },
940 { "R10W" },
941 { "R11W" },
942 { "R12W" },
943 { "R13W" },
944 { "R14W" },
945 { "R15W" },
946
947 { "EAX" },
948 { "ECX" },
949 { "EDX" },
950 { "EBX" },
951 { "ESP" },
952 { "EBP" },
953 { "ESI" },
954 { "EDI" },
955 { "R8D" },
956 { "R9D" },
957 { "R10D" },
958 { "R11D" },
959 { "R12D" },
960 { "R13D" },
961 { "R14D" },
962 { "R15D" },
963
964 { "RAX" },
965 { "RCX" },
966 { "RDX" },
967 { "RBX" },
968 { "RSP" },
969 { "RBP" },
970 { "RSI" },
971 { "RDI" },
972 { "R8" },
973 { "R9" },
974 { "R10" },
975 { "R11" },
976 { "R12" },
977 { "R13" },
978 { "R14" },
979 { "R15" },
980
981 { "OZ_RAX" },
982 { "OZ_RCX" },
983 { "OZ_RDX" },
984 { "OZ_RBX" },
985 { "OZ_RSP" },
986 { "OZ_RBP" },
987 { "OZ_RSI" },
988 { "OZ_RDI" },
989 { "OZ_R8" },
990 { "OZ_R9" },
991 { "OZ_R10" },
992 { "OZ_R11" },
993 { "OZ_R12" },
994 { "OZ_R13" },
995 { "OZ_R14" },
996 { "OZ_R15" },
997
998 { "CR0" },
999 { "CR4" },
1000 { "XCR0" },
1001
1002 { "FCW" },
1003 { "FSW" },
1004 { "FTW" },
1005 { "FOP" },
1006 { "FPUIP" },
1007 { "FPUCS" },
1008 { "FPUDP" },
1009 { "FPUDS" },
1010 { "MXCSR" },
1011 { "ST0" },
1012 { "ST1" },
1013 { "ST2" },
1014 { "ST3" },
1015 { "ST4" },
1016 { "ST5" },
1017 { "ST6" },
1018 { "ST7" },
1019 { "MM0" },
1020 { "MM1" },
1021 { "MM2" },
1022 { "MM3" },
1023 { "MM4" },
1024 { "MM5" },
1025 { "MM6" },
1026 { "MM7" },
1027 { "MM0_LO_ZX" },
1028 { "MM1_LO_ZX" },
1029 { "MM2_LO_ZX" },
1030 { "MM3_LO_ZX" },
1031 { "MM4_LO_ZX" },
1032 { "MM5_LO_ZX" },
1033 { "MM6_LO_ZX" },
1034 { "MM7_LO_ZX" },
1035 { "XMM0" },
1036 { "XMM1" },
1037 { "XMM2" },
1038 { "XMM3" },
1039 { "XMM4" },
1040 { "XMM5" },
1041 { "XMM6" },
1042 { "XMM7" },
1043 { "XMM8" },
1044 { "XMM9" },
1045 { "XMM10" },
1046 { "XMM11" },
1047 { "XMM12" },
1048 { "XMM13" },
1049 { "XMM14" },
1050 { "XMM15" },
1051 { "XMM0_LO" },
1052 { "XMM1_LO" },
1053 { "XMM2_LO" },
1054 { "XMM3_LO" },
1055 { "XMM4_LO" },
1056 { "XMM5_LO" },
1057 { "XMM6_LO" },
1058 { "XMM7_LO" },
1059 { "XMM8_LO" },
1060 { "XMM9_LO" },
1061 { "XMM10_LO" },
1062 { "XMM11_LO" },
1063 { "XMM12_LO" },
1064 { "XMM13_LO" },
1065 { "XMM14_LO" },
1066 { "XMM15_LO" },
1067 { "XMM0_HI" },
1068 { "XMM1_HI" },
1069 { "XMM2_HI" },
1070 { "XMM3_HI" },
1071 { "XMM4_HI" },
1072 { "XMM5_HI" },
1073 { "XMM6_HI" },
1074 { "XMM7_HI" },
1075 { "XMM8_HI" },
1076 { "XMM9_HI" },
1077 { "XMM10_HI" },
1078 { "XMM11_HI" },
1079 { "XMM12_HI" },
1080 { "XMM13_HI" },
1081 { "XMM14_HI" },
1082 { "XMM15_HI" },
1083 { "XMM0_LO_ZX" },
1084 { "XMM1_LO_ZX" },
1085 { "XMM2_LO_ZX" },
1086 { "XMM3_LO_ZX" },
1087 { "XMM4_LO_ZX" },
1088 { "XMM5_LO_ZX" },
1089 { "XMM6_LO_ZX" },
1090 { "XMM7_LO_ZX" },
1091 { "XMM8_LO_ZX" },
1092 { "XMM9_LO_ZX" },
1093 { "XMM10_LO_ZX" },
1094 { "XMM11_LO_ZX" },
1095 { "XMM12_LO_ZX" },
1096 { "XMM13_LO_ZX" },
1097 { "XMM14_LO_ZX" },
1098 { "XMM15_LO_ZX" },
1099 { "XMM0_DW0" },
1100 { "XMM1_DW0" },
1101 { "XMM2_DW0" },
1102 { "XMM3_DW0" },
1103 { "XMM4_DW0" },
1104 { "XMM5_DW0" },
1105 { "XMM6_DW0" },
1106 { "XMM7_DW0" },
1107 { "XMM8_DW0" },
1108 { "XMM9_DW0" },
1109 { "XMM10_DW0" },
1110 { "XMM11_DW0" },
1111 { "XMM12_DW0" },
1112 { "XMM13_DW0" },
1113 { "XMM14_DW0" },
1114 { "XMM15_DW0" },
1115 { "XMM0_DW0_ZX" },
1116 { "XMM1_DW0_ZX" },
1117 { "XMM2_DW0_ZX" },
1118 { "XMM3_DW0_ZX" },
1119 { "XMM4_DW0_ZX" },
1120 { "XMM5_DW0_ZX" },
1121 { "XMM6_DW0_ZX" },
1122 { "XMM7_DW0_ZX" },
1123 { "XMM8_DW0_ZX" },
1124 { "XMM9_DW0_ZX" },
1125 { "XMM10_DW0_ZX" },
1126 { "XMM11_DW0_ZX" },
1127 { "XMM12_DW0_ZX" },
1128 { "XMM13_DW0_ZX" },
1129 { "XMM14_DW0_ZX" },
1130 { "XMM15_DW0_ZX" },
1131 { "XMM0_HI96" },
1132 { "XMM1_HI96" },
1133 { "XMM2_HI96" },
1134 { "XMM3_HI96" },
1135 { "XMM4_HI96" },
1136 { "XMM5_HI96" },
1137 { "XMM6_HI96" },
1138 { "XMM7_HI96" },
1139 { "XMM8_HI96" },
1140 { "XMM9_HI96" },
1141 { "XMM10_HI96" },
1142 { "XMM11_HI96" },
1143 { "XMM12_HI96" },
1144 { "XMM13_HI96" },
1145 { "XMM14_HI96" },
1146 { "XMM15_HI96" },
1147 { "YMM0" },
1148 { "YMM1" },
1149 { "YMM2" },
1150 { "YMM3" },
1151 { "YMM4" },
1152 { "YMM5" },
1153 { "YMM6" },
1154 { "YMM7" },
1155 { "YMM8" },
1156 { "YMM9" },
1157 { "YMM10" },
1158 { "YMM11" },
1159 { "YMM12" },
1160 { "YMM13" },
1161 { "YMM14" },
1162 { "YMM15" },
1163
1164 { "VALXCPT" },
1165};
1166AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) >= BS3CG1DST_END);
1167AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) == BS3CG1DST_END);
1168
1169
1170#if 0
1171static const struct
1172{
1173 uint8_t cbPrefixes;
1174 uint8_t abPrefixes[14];
1175 uint16_t fEffective;
1176} g_aPrefixVariations[] =
1177{
1178 { 0, { 0x00 }, BS3CG1_PF_NONE },
1179
1180 { 1, { P_OZ }, BS3CG1_PF_OZ },
1181 { 1, { P_CS }, BS3CG1_PF_CS },
1182 { 1, { P_DS }, BS3CG1_PF_DS },
1183 { 1, { P_ES }, BS3CG1_PF_ES },
1184 { 1, { P_FS }, BS3CG1_PF_FS },
1185 { 1, { P_GS }, BS3CG1_PF_GS },
1186 { 1, { P_SS }, BS3CG1_PF_SS },
1187 { 1, { P_LK }, BS3CG1_PF_LK },
1188
1189 { 2, { P_CS, P_OZ, }, BS3CG1_PF_CS | BS3CFG1_PF_OZ },
1190 { 2, { P_DS, P_OZ, }, BS3CG1_PF_DS | BS3CFG1_PF_OZ },
1191 { 2, { P_ES, P_OZ, }, BS3CG1_PF_ES | BS3CFG1_PF_OZ },
1192 { 2, { P_FS, P_OZ, }, BS3CG1_PF_FS | BS3CFG1_PF_OZ },
1193 { 2, { P_GS, P_OZ, }, BS3CG1_PF_GS | BS3CFG1_PF_OZ },
1194 { 2, { P_GS, P_OZ, }, BS3CG1_PF_SS | BS3CFG1_PF_OZ },
1195 { 2, { P_SS, P_OZ, }, BS3CG1_PF_SS | BS3CFG1_PF_OZ },
1196
1197 { 2, { P_OZ, P_CS, }, BS3CG1_PF_CS | BS3CFG1_PF_OZ },
1198 { 2, { P_OZ, P_DS, }, BS3CG1_PF_DS | BS3CFG1_PF_OZ },
1199 { 2, { P_OZ, P_ES, }, BS3CG1_PF_ES | BS3CFG1_PF_OZ },
1200 { 2, { P_OZ, P_FS, }, BS3CG1_PF_FS | BS3CFG1_PF_OZ },
1201 { 2, { P_OZ, P_GS, }, BS3CG1_PF_GS | BS3CFG1_PF_OZ },
1202 { 2, { P_OZ, P_GS, }, BS3CG1_PF_SS | BS3CFG1_PF_OZ },
1203 { 2, { P_OZ, P_SS, }, BS3CG1_PF_SS | BS3CFG1_PF_OZ },
1204};
1205
1206static const uint16_t g_afPfxKindToIgnoredFlags[BS3CG1PFXKIND_END] =
1207{
1208 /* [BS3CG1PFXKIND_INVALID] = */ UINT16_MAX,
1209 /* [BS3CG1PFXKIND_MODRM] = */ 0,
1210 /* [BS3CG1PFXKIND_MODRM_NO_OP_SIZES] = */ BS3CG1_PF_OZ | BS3CG1_PF_W,
1211};
1212
1213#endif
1214
1215
1216/**
1217 * Checks if >= 16 byte SSE alignment are exempted for the exception type.
1218 *
1219 * @returns true / false.
1220 * @param enmXcptType The type to check.
1221 */
1222static bool BS3_NEAR_CODE Bs3Cg1XcptTypeIsUnaligned(BS3CG1XCPTTYPE enmXcptType)
1223{
1224 switch (enmXcptType)
1225 {
1226 case BS3CG1XCPTTYPE_1:
1227 case BS3CG1XCPTTYPE_2:
1228 case BS3CG1XCPTTYPE_4:
1229 return false;
1230 case BS3CG1XCPTTYPE_NONE:
1231 case BS3CG1XCPTTYPE_3:
1232 case BS3CG1XCPTTYPE_4UA:
1233 case BS3CG1XCPTTYPE_5:
1234 return true;
1235 default:
1236 return false;
1237 }
1238}
1239
1240
1241/**
1242 * Checks if >= 16 byte AVX alignment are exempted for the exception type.
1243 *
1244 * @returns true / false.
1245 * @param enmXcptType The type to check.
1246 */
1247static bool BS3_NEAR_CODE Bs3Cg1XcptTypeIsVexUnaligned(BS3CG1XCPTTYPE enmXcptType)
1248{
1249 switch (enmXcptType)
1250 {
1251 case BS3CG1XCPTTYPE_1:
1252 return false;
1253
1254 case BS3CG1XCPTTYPE_NONE:
1255 case BS3CG1XCPTTYPE_2:
1256 case BS3CG1XCPTTYPE_3:
1257 case BS3CG1XCPTTYPE_4:
1258 case BS3CG1XCPTTYPE_4UA:
1259 case BS3CG1XCPTTYPE_5:
1260 case BS3CG1XCPTTYPE_6:
1261 case BS3CG1XCPTTYPE_11:
1262 case BS3CG1XCPTTYPE_12:
1263 return true;
1264
1265 default:
1266 return false;
1267 }
1268}
1269
1270
1271DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertReqPrefix(PBS3CG1STATE pThis, unsigned offDst)
1272{
1273 switch (pThis->enmPrefixKind)
1274 {
1275 case BS3CG1PFXKIND_REQ_66:
1276 pThis->abCurInstr[offDst] = 0x66;
1277 break;
1278 case BS3CG1PFXKIND_REQ_F2:
1279 pThis->abCurInstr[offDst] = 0xf2;
1280 break;
1281 case BS3CG1PFXKIND_REQ_F3:
1282 pThis->abCurInstr[offDst] = 0xf3;
1283 break;
1284 default:
1285 return offDst;
1286 }
1287 return offDst + 1;
1288}
1289
1290
1291DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertOpcodes(PBS3CG1STATE pThis, unsigned offDst)
1292{
1293 switch (pThis->cbOpcodes)
1294 {
1295 case 4: pThis->abCurInstr[offDst + 3] = pThis->abOpcodes[3];
1296 case 3: pThis->abCurInstr[offDst + 2] = pThis->abOpcodes[2];
1297 case 2: pThis->abCurInstr[offDst + 1] = pThis->abOpcodes[1];
1298 case 1: pThis->abCurInstr[offDst] = pThis->abOpcodes[0];
1299 return offDst + pThis->cbOpcodes;
1300
1301 default:
1302 BS3_ASSERT(0);
1303 return 0;
1304 }
1305}
1306
1307
1308/**
1309 * Inserts a ModR/M byte with mod=3 and set the two idxFields members.
1310 *
1311 * @returns off + 1.
1312 * @param pThis The state.
1313 * @param off Current instruction offset.
1314 * @param uReg Register index for ModR/M.reg.
1315 * @param uRegMem Register index for ModR/M.rm.
1316 */
1317static unsigned Bs3Cg1InsertModRmWithRegFields(PBS3CG1STATE pThis, unsigned off, uint8_t uReg, uint8_t uRegMem)
1318{
1319 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, uReg & 7, uRegMem & 7);
1320 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + uReg;
1321 pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + uRegMem;
1322 return off;
1323}
1324
1325
1326
1327/**
1328 * Cleans up state and context changes made by the encoder.
1329 *
1330 * @param pThis The state.
1331 */
1332static void BS3_NEAR_CODE Bs3Cg1EncodeCleanup(PBS3CG1STATE pThis)
1333{
1334 /* Restore the DS registers in the contexts. */
1335 unsigned iRing = 4;
1336 while (iRing-- > 0)
1337 pThis->aInitialCtxs[iRing].ds = pThis->aSavedSegRegs[iRing].ds;
1338
1339 switch (pThis->enmEncoding)
1340 {
1341 /* Most encodings currently doesn't need any special cleaning up. */
1342 default:
1343 return;
1344 }
1345}
1346
1347
1348static unsigned BS3_NEAR_CODE Bs3Cfg1EncodeMemMod0Disp(PBS3CG1STATE pThis, bool fAddrOverride, unsigned off, uint8_t iReg,
1349 uint8_t cbOp, uint8_t cbMisalign, BS3CG1OPLOC enmLocation)
1350{
1351 pThis->aOperands[pThis->iRmOp].idxField = BS3CG1DST_INVALID;
1352 pThis->aOperands[pThis->iRmOp].enmLocation = enmLocation;
1353 pThis->aOperands[pThis->iRmOp].cbOp = cbOp;
1354 pThis->aOperands[pThis->iRmOp].off = cbOp + cbMisalign;
1355
1356 if ( BS3_MODE_IS_16BIT_CODE(pThis->bMode)
1357 || (fAddrOverride && BS3_MODE_IS_32BIT_CODE(pThis->bMode)) )
1358 {
1359 /*
1360 * 16-bit code doing 16-bit or 32-bit addressing,
1361 * or 32-bit code doing 16-bit addressing.
1362 */
1363 unsigned iRing = 4;
1364 if (BS3_MODE_IS_RM_OR_V86(pThis->bMode))
1365 while (iRing-- > 0)
1366 pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel;
1367 else
1368 while (iRing-- > 0)
1369 pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel | iRing;
1370 if (!fAddrOverride || BS3_MODE_IS_32BIT_CODE(pThis->bMode))
1371 {
1372 pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 6 /*disp16*/);
1373 *(uint16_t *)&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMisalign;
1374 off += 2;
1375 }
1376 else
1377 {
1378 pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /*disp32*/);
1379 *(uint32_t *)&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMisalign;
1380 off += 4;
1381 }
1382 }
1383 else
1384 {
1385 /*
1386 * 32-bit code doing 32-bit addressing,
1387 * or 64-bit code doing either 64-bit or 32-bit addressing.
1388 */
1389 pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /*disp32*/);
1390 *(uint32_t *)&pThis->abCurInstr[off] = BS3_FP_OFF(pThis->pbDataPg) + X86_PAGE_SIZE - cbOp - cbMisalign;
1391
1392#if ARCH_BITS == 64
1393 /* In 64-bit mode we always have a rip relative encoding regardless of fAddrOverride. */
1394 if (BS3CG1_IS_64BIT_TARGET(pThis))
1395 *(uint32_t *)&pThis->abCurInstr[off] -= BS3_FP_OFF(&pThis->pbCodePg[X86_PAGE_SIZE]);
1396#endif
1397 off += 4;
1398 }
1399
1400 /*
1401 * Fill the memory with 0xcc.
1402 */
1403 switch (cbOp + cbMisalign)
1404 {
1405 case 8: pThis->pbDataPg[X86_PAGE_SIZE - 8] = 0xcc; /* fall thru */
1406 case 7: pThis->pbDataPg[X86_PAGE_SIZE - 7] = 0xcc; /* fall thru */
1407 case 6: pThis->pbDataPg[X86_PAGE_SIZE - 6] = 0xcc; /* fall thru */
1408 case 5: pThis->pbDataPg[X86_PAGE_SIZE - 5] = 0xcc; /* fall thru */
1409 case 4: pThis->pbDataPg[X86_PAGE_SIZE - 4] = 0xcc; /* fall thru */
1410 case 3: pThis->pbDataPg[X86_PAGE_SIZE - 3] = 0xcc; /* fall thru */
1411 case 2: pThis->pbDataPg[X86_PAGE_SIZE - 2] = 0xcc; /* fall thru */
1412 case 1: pThis->pbDataPg[X86_PAGE_SIZE - 1] = 0xcc; /* fall thru */
1413 case 0: break;
1414 default:
1415 {
1416 BS3CG1_DPRINTF(("Bs3MemSet(%p,%#x,%#x)\n", &pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMisalign], 0xcc, cbOp - cbMisalign));
1417 Bs3MemSet(&pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMisalign], 0xcc, cbOp - cbMisalign);
1418 break;
1419 }
1420 }
1421
1422 return off;
1423}
1424
1425
1426#if 0 /* unused */
1427/** Also encodes idxField of the register operand using idxFieldBase. */
1428static unsigned BS3_NEAR_CODE
1429Bs3Cfg1EncodeMemMod0DispWithRegField(PBS3CG1STATE pThis, bool fAddrOverride, unsigned off, uint8_t iReg,
1430 uint8_t cbOp, uint8_t cbMisalign, BS3CG1OPLOC enmLocation)
1431{
1432 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1433 return Bs3Cfg1EncodeMemMod0Disp(pThis, fAddrOverride, off, iReg & 7, cbOp, cbMisalign, enmLocation);
1434}
1435#endif
1436
1437/** Also encodes idxField of the register operand using idxFieldBase. */
1438static unsigned BS3_NEAR_CODE
1439Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(PBS3CG1STATE pThis, unsigned off, uint8_t iReg)
1440{
1441 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1442 return Bs3Cfg1EncodeMemMod0Disp(pThis, false /*fAddrOverride*/, off, iReg & 7,
1443 pThis->aOperands[pThis->iRmOp].cbOp,
1444 0 /*cbMisalign*/,
1445 pThis->aOperands[pThis->iRmOp].enmLocation);
1446}
1447
1448/** Also encodes idxField of the register operand using idxFieldBase. */
1449static unsigned BS3_NEAR_CODE
1450Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsAddrOverride(PBS3CG1STATE pThis, unsigned off, uint8_t iReg)
1451{
1452 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1453 return Bs3Cfg1EncodeMemMod0Disp(pThis, true /*fAddrOverride*/, off, iReg & 7,
1454 pThis->aOperands[pThis->iRmOp].cbOp,
1455 0 /*cbMisalign*/,
1456 pThis->aOperands[pThis->iRmOp].enmLocation);
1457}
1458
1459
1460/** Also encodes idxField of the register operand using idxFieldBase. */
1461static unsigned BS3_NEAR_CODE
1462Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(PBS3CG1STATE pThis, unsigned off, uint8_t iReg, uint8_t cbMisalign)
1463{
1464 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1465 return Bs3Cfg1EncodeMemMod0Disp(pThis, false /*fAddrOverride*/, off, iReg & 7,
1466 pThis->aOperands[pThis->iRmOp].cbOp,
1467 cbMisalign,
1468 pThis->aOperands[pThis->iRmOp].enmLocation);
1469}
1470
1471
1472/** Also encodes idxField of the register operand using idxFieldBase. */
1473static unsigned BS3_NEAR_CODE
1474Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaults(PBS3CG1STATE pThis, unsigned off, uint8_t iReg, uint8_t cbOp)
1475{
1476 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1477 return Bs3Cfg1EncodeMemMod0Disp(pThis, false /*fAddrOverride*/, off, iReg & 7, cbOp, 0 /*cbMisalign*/,
1478 pThis->aOperands[pThis->iRmOp].enmLocation);
1479}
1480
1481/** Also encodes idxField of the register operand using idxFieldBase. */
1482static unsigned BS3_NEAR_CODE
1483Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaultsAddrOverride(PBS3CG1STATE pThis, unsigned off, uint8_t iReg, uint8_t cbOp)
1484{
1485 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1486 return Bs3Cfg1EncodeMemMod0Disp(pThis, true /*fAddrOverride*/, off, iReg & 7, cbOp, 0 /*cbMisalign*/,
1487 pThis->aOperands[pThis->iRmOp].enmLocation);
1488}
1489
1490
1491/** The modrm.reg value is taken from the instruction byte at @a off. */
1492static unsigned BS3_NEAR_CODE
1493Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(PBS3CG1STATE pThis, unsigned off)
1494{
1495 return Bs3Cfg1EncodeMemMod0Disp(pThis, false /*fAddrOverride*/, off,
1496 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1497 pThis->aOperands[pThis->iRmOp].cbOp,
1498 0 /*cbMisalign*/,
1499 pThis->aOperands[pThis->iRmOp].enmLocation);
1500}
1501
1502
1503
1504static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Eb_Gb_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
1505{
1506 unsigned off;
1507 switch (iEncoding)
1508 {
1509 /* Start by reg,reg encoding. */
1510 case 0:
1511 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1512 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1513 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, X86_GREG_xAX, X86_GREG_xCX);
1514 break;
1515 case 1:
1516 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1517 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1518 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5 /*CH*/);
1519 break;
1520 case 2:
1521 if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) < BS3CPU_80386)
1522 return 0;
1523 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1524 pThis->abCurInstr[0] = P_OZ;
1525 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1526 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 6 /*DH*/);
1527 break;
1528 /* Tests with address overrides go last! */
1529 case 3:
1530 pThis->abCurInstr[0] = P_AZ;
1531 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1532 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsAddrOverride(pThis, off, 7 /*BH*/);
1533 break;
1534
1535 default:
1536 return 0;
1537 }
1538 pThis->cbCurInstr = off;
1539 return iEncoding + 1;
1540}
1541
1542
1543static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Gv_Ev__OR__MODRM_Ev_Gv(PBS3CG1STATE pThis, unsigned iEncoding)
1544{
1545 unsigned off;
1546 unsigned cbOp;
1547 switch (iEncoding)
1548 {
1549 case 0:
1550 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1551 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1552 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, X86_GREG_xBX, X86_GREG_xDX);
1553 cbOp = pThis->cbOpDefault;
1554 break;
1555 case 1:
1556 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1557 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1558 cbOp = pThis->cbOpDefault;
1559 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaults(pThis, off, X86_GREG_xBP, cbOp);
1560 break;
1561 case 2:
1562 if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) < BS3CPU_80386)
1563 return 0;
1564 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1565 pThis->abCurInstr[0] = P_OZ;
1566 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1567 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, X86_GREG_xAX, X86_GREG_xCX);
1568 cbOp = pThis->cbOpOvrd66;
1569 break;
1570 case 3:
1571 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1572 pThis->abCurInstr[0] = P_OZ;
1573 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1574 cbOp = pThis->cbOpOvrd66;
1575 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaults(pThis, off, X86_GREG_xSI, cbOp);
1576 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 : 0;
1577 break;
1578 case 4:
1579 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1580 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1581 pThis->abCurInstr[off++] = REX_W___;
1582 off = Bs3Cg1InsertOpcodes(pThis, off);
1583 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, X86_GREG_xBX, X86_GREG_xDX);
1584 cbOp = pThis->cbOpOvrdRexW;
1585 break;
1586 case 5:
1587 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1588 pThis->abCurInstr[off++] = REX__RB_;
1589 off = Bs3Cg1InsertOpcodes(pThis, off);
1590 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, X86_GREG_x14, X86_GREG_x12);
1591 cbOp = pThis->cbOpDefault;
1592 break;
1593 /* Tests with address overrides go last!*/
1594 case 6:
1595 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1596 pThis->abCurInstr[0] = P_AZ;
1597 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1598 cbOp = pThis->cbOpDefault;
1599 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaultsAddrOverride(pThis, off, X86_GREG_xDI, cbOp);
1600 break;
1601 case 7:
1602 pThis->abCurInstr[0] = P_OZ;
1603 pThis->abCurInstr[1] = P_AZ;
1604 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
1605 cbOp = pThis->cbOpOvrd66;
1606 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaultsAddrOverride(pThis, off, X86_GREG_xDI, cbOp);
1607 break;
1608 default:
1609 return 0;
1610 }
1611 pThis->aOperands[0].cbOp = cbOp;
1612 pThis->aOperands[1].cbOp = cbOp;
1613 pThis->cbOperand = cbOp;
1614 pThis->cbCurInstr = off;
1615 return iEncoding + 1;
1616}
1617
1618
1619static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Pq_WO_Qq(PBS3CG1STATE pThis, unsigned iEncoding)
1620{
1621 unsigned off;
1622 switch (iEncoding)
1623 {
1624 case 0:
1625 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1626 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1627 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1628 break;
1629 case 1:
1630 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1631 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1632 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 7);
1633 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1634 break;
1635#if ARCH_BITS == 64
1636 case 2:
1637 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1638 pThis->abCurInstr[off++] = REX__RBX;
1639 off = Bs3Cg1InsertOpcodes(pThis, off);
1640 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6 /*no +8*/, 2 /*no +8*/);
1641 break;
1642#endif
1643 case 3:
1644 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1645 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1646 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
1647 break;
1648 case 4:
1649 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1650 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
1651 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1652 break;
1653#if ARCH_BITS == 64
1654 case 5:
1655 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1656 pThis->abCurInstr[off++] = REX__RBX;
1657 off = Bs3Cg1InsertOpcodes(pThis, off);
1658 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /*iReg - no +8*/);
1659 break;
1660#endif
1661
1662 default:
1663 return 0;
1664 }
1665
1666 pThis->cbCurInstr = off;
1667 return iEncoding + 1;
1668}
1669
1670
1671static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Pq_WO_Uq(PBS3CG1STATE pThis, unsigned iEncoding)
1672{
1673 unsigned off;
1674 switch (iEncoding)
1675 {
1676 case 0:
1677 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1678 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1679 break;
1680 case 1:
1681 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1682 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
1683 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1684 break;
1685 case 2:
1686 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1687 pThis->abCurInstr[off++] = REX__RBX;
1688 off = Bs3Cg1InsertOpcodes(pThis, off);
1689 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6 /*no+8*/, 2 + 8);
1690 break;
1691 default:
1692 return 0;
1693 }
1694 pThis->cbCurInstr = off;
1695 return iEncoding + 1;
1696}
1697
1698
1699static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_PdZx_WO_Ed_WZ(PBS3CG1STATE pThis, unsigned iEncoding)
1700{
1701 unsigned off;
1702 switch (iEncoding)
1703 {
1704 case 0:
1705 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1706 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1707 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1708 break;
1709 case 1:
1710 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1711 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
1712 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1713 break;
1714#if ARCH_BITS == 64
1715 case 2:
1716 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1717 pThis->abCurInstr[off++] = REX__RBX;
1718 off = Bs3Cg1InsertOpcodes(pThis, off);
1719 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6 /*no +8*/, 2+8);
1720 break;
1721#endif
1722 case 3:
1723 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1724 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1725 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
1726 break;
1727 case 4:
1728 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1729 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
1730 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1731 break;
1732#if ARCH_BITS == 64
1733 case 5:
1734 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1735 pThis->abCurInstr[off++] = REX__RBX;
1736 off = Bs3Cg1InsertOpcodes(pThis, off);
1737 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /*iReg*/);
1738 break;
1739#endif
1740
1741 default:
1742 return 0;
1743 }
1744 pThis->cbCurInstr = off;
1745 return iEncoding + 1;
1746}
1747
1748
1749static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Pq_WO_Eq_WNZ(PBS3CG1STATE pThis, unsigned iEncoding)
1750{
1751#if ARCH_BITS == 64
1752 if (BS3CG1_IS_64BIT_TARGET(pThis))
1753 {
1754 unsigned off;
1755 switch (iEncoding)
1756 {
1757 case 0:
1758 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1759 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1760 pThis->abCurInstr[off++] = REX_W___;
1761 off = Bs3Cg1InsertOpcodes(pThis, off);
1762 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1763 break;
1764 case 1:
1765 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1766 pThis->abCurInstr[off++] = REX_W___;
1767 off = Bs3Cg1InsertOpcodes(pThis, off);
1768 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
1769 break;
1770 case 2:
1771 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1772 pThis->abCurInstr[off++] = REX_WRBX;
1773 off = Bs3Cg1InsertOpcodes(pThis, off);
1774 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6 /*no +8*/, 2+8);
1775 break;
1776 case 3:
1777 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1778 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1779 pThis->abCurInstr[off++] = REX_W___;
1780 off = Bs3Cg1InsertOpcodes(pThis, off);
1781 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
1782 break;
1783 case 4:
1784 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1785 pThis->abCurInstr[off++] = REX_W___;
1786 off = Bs3Cg1InsertOpcodes(pThis, off);
1787 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
1788 break;
1789 case 5:
1790 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1791 pThis->abCurInstr[off++] = REX_WRBX;
1792 off = Bs3Cg1InsertOpcodes(pThis, off);
1793 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /*iReg*/);
1794 break;
1795
1796 default:
1797 return 0;
1798 }
1799 pThis->cbCurInstr = off;
1800 return iEncoding + 1;
1801 }
1802#endif
1803 return 0;
1804}
1805
1806
1807/* Differs from Bs3Cg1EncodeNext_MODRM_PdZx_WO_Ed_WZ in that REX.R isn't ignored. */
1808static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vd_WO_Ed_WZ(PBS3CG1STATE pThis, unsigned iEncoding)
1809{
1810 unsigned off;
1811 switch (iEncoding)
1812 {
1813 case 0:
1814 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1815 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1816 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1817 break;
1818 case 1:
1819 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1820 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
1821 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1822 break;
1823#if ARCH_BITS == 64
1824 case 2:
1825 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1826 pThis->abCurInstr[off++] = REX__RBX;
1827 off = Bs3Cg1InsertOpcodes(pThis, off);
1828 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6+8, 2+8);
1829 break;
1830#endif
1831 case 3:
1832 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1833 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1834 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
1835 break;
1836 case 4:
1837 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1838 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
1839 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1840 break;
1841#if ARCH_BITS == 64
1842 case 5:
1843 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1844 pThis->abCurInstr[off++] = REX__RBX;
1845 off = Bs3Cg1InsertOpcodes(pThis, off);
1846 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7+8 /*iReg*/);
1847 break;
1848#endif
1849
1850 default:
1851 return 0;
1852 }
1853 pThis->cbCurInstr = off;
1854 return iEncoding + 1;
1855}
1856
1857
1858/* Differs from Bs3Cg1EncodeNext_MODRM_Pq_WO_Eq_WNZ in that REX.R isn't ignored. */
1859static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vq_WO_Eq_WNZ(PBS3CG1STATE pThis, unsigned iEncoding)
1860{
1861#if ARCH_BITS == 64
1862 if (BS3CG1_IS_64BIT_TARGET(pThis))
1863 {
1864 unsigned off;
1865 switch (iEncoding)
1866 {
1867 case 0:
1868 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1869 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1870 pThis->abCurInstr[off++] = REX_W___;
1871 off = Bs3Cg1InsertOpcodes(pThis, off);
1872 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1873 break;
1874 case 1:
1875 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1876 pThis->abCurInstr[off++] = REX_W___;
1877 off = Bs3Cg1InsertOpcodes(pThis, off);
1878 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
1879 break;
1880 case 2:
1881 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1882 pThis->abCurInstr[off++] = REX_WRBX;
1883 off = Bs3Cg1InsertOpcodes(pThis, off);
1884 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6+8, 2+8);
1885 break;
1886 case 4:
1887 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1888 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1889 pThis->abCurInstr[off++] = REX_W___;
1890 off = Bs3Cg1InsertOpcodes(pThis, off);
1891 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
1892 break;
1893 case 5:
1894 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1895 pThis->abCurInstr[off++] = REX_W___;
1896 off = Bs3Cg1InsertOpcodes(pThis, off);
1897 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
1898 break;
1899 case 6:
1900 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1901 pThis->abCurInstr[off++] = REX_WRBX;
1902 off = Bs3Cg1InsertOpcodes(pThis, off);
1903 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7+8 /*iReg*/);
1904 break;
1905
1906 default:
1907 return 0;
1908 }
1909 pThis->cbCurInstr = off;
1910 return iEncoding + 1;
1911 }
1912#endif
1913 return 0;
1914}
1915
1916
1917static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vsomething_Usomething_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
1918{
1919 unsigned off;
1920 switch (iEncoding)
1921 {
1922 case 0:
1923 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1924 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1925 break;
1926 case 1:
1927 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1928 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 2, 2);
1929 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1930 break;
1931 case 2:
1932 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1933 pThis->abCurInstr[off++] = REX__RBX;
1934 off = Bs3Cg1InsertOpcodes(pThis, off);
1935 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 3+8, 7+8);
1936 break;
1937 default:
1938 return 0;
1939 }
1940 pThis->cbCurInstr = off;
1941 return iEncoding + 1;
1942}
1943
1944
1945static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
1946{
1947 unsigned off;
1948 switch (iEncoding)
1949 {
1950 case 0:
1951 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1952 off = Bs3Cg1InsertModRmWithRegFields(pThis, Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)), 1, 0);
1953 break;
1954 case 1:
1955 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1956 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1957 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /*iReg*/);
1958 break;
1959 case 2:
1960 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1961 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /*iReg*/, 1 /*cbMisalign*/);
1962 if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1963 pThis->bAlignmentXcpt = X86_XCPT_GP;
1964 break;
1965 default:
1966 return 0;
1967 }
1968 pThis->cbCurInstr = off;
1969 return iEncoding + 1;
1970}
1971
1972
1973static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vsomething_Nsomething(PBS3CG1STATE pThis, unsigned iEncoding)
1974{
1975 unsigned off;
1976 switch (iEncoding)
1977 {
1978 case 0:
1979 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1980 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1981 break;
1982 case 1:
1983 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1984 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 7);
1985 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1986 break;
1987 case 2:
1988 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1989 pThis->abCurInstr[off++] = REX_WRBX;
1990 off = Bs3Cg1InsertOpcodes(pThis, off);
1991 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6 + 8, 7 /*no +8*/);
1992 break;
1993
1994 default:
1995 return 0;
1996 }
1997 pThis->cbCurInstr = off;
1998 return iEncoding + 1;
1999}
2000
2001
2002static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Gv_RO_Ma(PBS3CG1STATE pThis, unsigned iEncoding) /* bound instr */
2003{
2004 unsigned off;
2005 unsigned cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
2006 switch (iEncoding)
2007 {
2008 case 0:
2009 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2010 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaults(pThis, off, X86_GREG_xBP, cbOp * 2);
2011 break;
2012 case 1:
2013 if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) < BS3CPU_80386)
2014 return 0;
2015 cbOp = cbOp == 2 ? 4 : 2;
2016 pThis->abCurInstr[0] = P_OZ;
2017 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
2018 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaults(pThis, off, X86_GREG_xBP, cbOp * 2);
2019 break;
2020 case 2:
2021 pThis->abCurInstr[0] = P_AZ;
2022 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
2023 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaultsAddrOverride(pThis, off, X86_GREG_xBP, cbOp * 2);
2024 break;
2025 case 3:
2026 cbOp = cbOp == 2 ? 4 : 2;
2027 pThis->abCurInstr[0] = P_AZ;
2028 pThis->abCurInstr[1] = P_OZ;
2029 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
2030 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaultsAddrOverride(pThis, off, X86_GREG_xBP, cbOp * 2);
2031 break;
2032 default:
2033 return 0;
2034 }
2035 pThis->aOperands[pThis->iRegOp].cbOp = cbOp;
2036 pThis->cbOperand = cbOp;
2037 pThis->cbCurInstr = off;
2038 return iEncoding + 1;
2039}
2040
2041
2042static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Msomething(PBS3CG1STATE pThis, unsigned iEncoding)
2043{
2044 unsigned off;
2045 switch (iEncoding)
2046 {
2047 case 0:
2048 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1;
2049 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
2050 break;
2051 default:
2052 return 0;
2053 }
2054 pThis->cbCurInstr = off;
2055 return iEncoding + 1;
2056}
2057
2058
2059static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Msomething_Psomething(PBS3CG1STATE pThis, unsigned iEncoding)
2060{
2061 unsigned off;
2062 switch (iEncoding)
2063 {
2064 case 0:
2065 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2066 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
2067 break;
2068 case 1:
2069 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2070 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
2071 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2072 break;
2073#if ARCH_BITS == 64
2074 case 2:
2075 off = Bs3Cg1InsertReqPrefix(pThis, 0);
2076 pThis->abCurInstr[off++] = REX__RBX;
2077 off = Bs3Cg1InsertOpcodes(pThis, off);
2078 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /*iReg - no +8*/);
2079 break;
2080#endif
2081
2082 default:
2083 return 0;
2084 }
2085
2086 pThis->cbCurInstr = off;
2087 return iEncoding + 1;
2088}
2089
2090
2091static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2092{
2093 unsigned off;
2094 switch (iEncoding)
2095 {
2096 case 0:
2097 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2098 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /*iReg*/);
2099 break;
2100 case 1:
2101 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2102 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 2 /*iReg*/, 1 /*cbMisalign*/ );
2103 if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
2104 pThis->bAlignmentXcpt = X86_XCPT_GP;
2105 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2106 break;
2107 case 2:
2108 off = Bs3Cg1InsertReqPrefix(pThis, 0);
2109 pThis->abCurInstr[off++] = REX__R__;
2110 off = Bs3Cg1InsertOpcodes(pThis, off);
2111 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2+8 /*iReg*/);
2112 break;
2113 default:
2114 return 0;
2115 }
2116 pThis->cbCurInstr = off;
2117 return iEncoding + 1;
2118}
2119
2120
2121static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_FIXED(PBS3CG1STATE pThis, unsigned iEncoding)
2122{
2123 unsigned off;
2124 switch (iEncoding)
2125 {
2126 case 0:
2127 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2128 pThis->cbCurInstr = off;
2129 break;
2130 default:
2131 return 0;
2132 }
2133 return iEncoding + 1;
2134}
2135
2136
2137static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_FIXED_AL_Ib(PBS3CG1STATE pThis, unsigned iEncoding)
2138{
2139 unsigned off;
2140 switch (iEncoding)
2141 {
2142 case 0:
2143 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2144 pThis->aOperands[1].off = (uint8_t)off;
2145 pThis->abCurInstr[off++] = 0xff;
2146 pThis->cbCurInstr = off;
2147 break;
2148 default:
2149 return 0;
2150 }
2151 return iEncoding + 1;
2152}
2153
2154
2155static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_FIXED_rAX_Iz(PBS3CG1STATE pThis, unsigned iEncoding)
2156{
2157 unsigned off;
2158 unsigned cbOp;
2159 switch (iEncoding)
2160 {
2161 case 0:
2162 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2163 pThis->aOperands[1].off = (uint8_t)off;
2164 cbOp = pThis->cbOpDefault;
2165 if (cbOp == 2)
2166 *(uint16_t *)&pThis->abCurInstr[off] = UINT16_MAX;
2167 else
2168 *(uint32_t *)&pThis->abCurInstr[off] = UINT32_MAX;
2169 off += cbOp;
2170 pThis->aOperands[0].cbOp = cbOp;
2171 pThis->aOperands[1].cbOp = cbOp;
2172 pThis->cbOperand = cbOp;
2173 break;
2174 case 1:
2175 if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) < BS3CPU_80386)
2176 return 0;
2177 pThis->abCurInstr[0] = P_OZ;
2178 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
2179 pThis->aOperands[1].off = (uint8_t)off;
2180 cbOp = pThis->cbOpOvrd66;
2181 if (cbOp == 2)
2182 *(uint16_t *)&pThis->abCurInstr[off] = UINT16_MAX;
2183 else
2184 *(uint32_t *)&pThis->abCurInstr[off] = UINT32_MAX;
2185 off += cbOp;
2186 pThis->aOperands[0].cbOp = cbOp;
2187 pThis->aOperands[1].cbOp = cbOp;
2188 pThis->cbOperand = cbOp;
2189 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2190 break;
2191 case 2:
2192 off = Bs3Cg1InsertReqPrefix(pThis, 0);
2193 pThis->abCurInstr[off++] = REX_W___;
2194 off = Bs3Cg1InsertOpcodes(pThis, off);
2195 pThis->aOperands[1].off = (uint8_t)off;
2196 *(uint32_t *)&pThis->abCurInstr[off] = UINT32_MAX;
2197 off += 4;
2198 pThis->aOperands[0].cbOp = 8;
2199 pThis->aOperands[1].cbOp = 4;
2200 pThis->cbOperand = 8;
2201 break;
2202 default:
2203 return 0;
2204
2205 /* IMAGE PADDING - workaround for "rd err" - remove later! */
2206 case 4:
2207 ASMHalt();
2208 ASMHalt();
2209 ASMHalt();
2210 return 0;
2211
2212 }
2213 pThis->cbCurInstr = off;
2214 return iEncoding + 1;
2215}
2216
2217
2218static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_MOD_EQ_3(PBS3CG1STATE pThis, unsigned iEncoding)
2219{
2220 unsigned off;
2221 if (iEncoding < 8)
2222 {
2223 off = Bs3Cg1InsertReqPrefix(pThis, 0);
2224 off = Bs3Cg1InsertOpcodes(pThis, off);
2225 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding, 1);
2226 }
2227 else if (iEncoding < 16)
2228 {
2229 off = Bs3Cg1InsertReqPrefix(pThis, 0);
2230 off = Bs3Cg1InsertOpcodes(pThis, off);
2231 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding & 7);
2232 }
2233 else
2234 return 0;
2235 pThis->cbCurInstr = off;
2236
2237 return iEncoding + 1;
2238}
2239
2240
2241static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_MOD_NE_3(PBS3CG1STATE pThis, unsigned iEncoding)
2242{
2243 unsigned off;
2244 if (iEncoding < 3)
2245 {
2246 off = Bs3Cg1InsertReqPrefix(pThis, 0);
2247 off = Bs3Cg1InsertOpcodes(pThis, off);
2248 pThis->abCurInstr[off++] = X86_MODRM_MAKE(iEncoding, 0, 1);
2249 if (iEncoding >= 1)
2250 pThis->abCurInstr[off++] = 0x7f;
2251 if (iEncoding == 2)
2252 {
2253 pThis->abCurInstr[off++] = 0x5f;
2254 if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
2255 {
2256 pThis->abCurInstr[off++] = 0x3f;
2257 pThis->abCurInstr[off++] = 0x1f;
2258 }
2259 }
2260 }
2261 else
2262 return 0;
2263 pThis->cbCurInstr = off;
2264 return iEncoding + 1;
2265}
2266
2267
2268/*
2269 *
2270 * VEX
2271 * VEX
2272 * VEX
2273 *
2274 */
2275#ifdef BS3CG1_WITH_VEX
2276
2277/**
2278 * Inserts a 3-byte VEX prefix.
2279 *
2280 * @returns New offDst value.
2281 * @param pThis The state.
2282 * @param offDst The current instruction offset.
2283 * @param uVexL The VEX.L value.
2284 * @param uVexV The VEX.V value (caller inverted it already).
2285 * @param uVexR The VEX.R value (caller inverted it already).
2286 * @param uVexX The VEX.X value (caller inverted it already).
2287 * @param uVexB The VEX.B value (caller inverted it already).
2288 * @param uVexW The VEX.W value (straight).
2289 */
2290DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex3bPrefix(PBS3CG1STATE pThis, unsigned offDst, uint8_t uVexV, uint8_t uVexL,
2291 uint8_t uVexR, uint8_t uVexX, uint8_t uVexB, uint8_t uVexW)
2292{
2293 uint8_t b1;
2294 uint8_t b2;
2295 b1 = uVexR << 7;
2296 b1 |= uVexX << 6;
2297 b1 |= uVexB << 5;
2298 b1 |= pThis->uOpcodeMap;
2299 b2 = uVexV << 3;
2300 b2 |= uVexW << 7;
2301 b2 |= uVexL << 2;
2302 switch (pThis->enmPrefixKind)
2303 {
2304 case BS3CG1PFXKIND_NO_F2_F3_66: b2 |= 0; break;
2305 case BS3CG1PFXKIND_REQ_66: b2 |= 1; break;
2306 case BS3CG1PFXKIND_REQ_F3: b2 |= 2; break;
2307 case BS3CG1PFXKIND_REQ_F2: b2 |= 3; break;
2308 default:
2309 Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n", pThis->enmPrefixKind);
2310 break;
2311 }
2312
2313 pThis->abCurInstr[offDst] = 0xc4; /* vex3 */
2314 pThis->abCurInstr[offDst + 1] = b1;
2315 pThis->abCurInstr[offDst + 2] = b2;
2316 pThis->uVexL = uVexL;
2317 return offDst + 3;
2318}
2319
2320
2321/**
2322 * Inserts a 2-byte VEX prefix.
2323 *
2324 * @note Will switch to 3-byte VEX prefix if uOpcodeMap isn't one.
2325 *
2326 * @returns New offDst value.
2327 * @param pThis The state.
2328 * @param offDst The current instruction offset.
2329 * @param uVexL The VEX.L value.
2330 * @param uVexV The VEX.V value (caller inverted it already).
2331 * @param uVexR The VEX.R value (caller inverted it already).
2332 */
2333DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex2bPrefix(PBS3CG1STATE pThis, unsigned offDst,
2334 uint8_t uVexV, uint8_t uVexL, uint8_t uVexR)
2335{
2336 if (pThis->uOpcodeMap == 1)
2337 {
2338 uint8_t b = uVexR << 7;
2339 b |= uVexV << 3;
2340 b |= uVexL << 2;
2341 switch (pThis->enmPrefixKind)
2342 {
2343 case BS3CG1PFXKIND_NO_F2_F3_66: b |= 0; break;
2344 case BS3CG1PFXKIND_REQ_66: b |= 1; break;
2345 case BS3CG1PFXKIND_REQ_F3: b |= 2; break;
2346 case BS3CG1PFXKIND_REQ_F2: b |= 3; break;
2347 default:
2348 Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n");
2349 break;
2350 }
2351
2352 pThis->abCurInstr[offDst] = 0xc5; /* vex2 */
2353 pThis->abCurInstr[offDst + 1] = b;
2354 pThis->uVexL = uVexL;
2355 return offDst + 2;
2356 }
2357 return Bs3Cg1InsertVex3bPrefix(pThis, offDst, uVexV, uVexL, uVexR, 1 /*uVexX*/, 1 /*uVexB*/, 0/*uVexW*/);
2358}
2359
2360
2361/**
2362 * Inserts a ModR/M byte with mod=3 and set the two idxFields members.
2363 *
2364 * @returns off + 1.
2365 * @param pThis The state.
2366 * @param off Current instruction offset.
2367 * @param uReg Register index for ModR/M.reg.
2368 * @param uRegMem Register index for ModR/M.rm.
2369 * @param uVexVvvv The VEX.vvvv register.
2370 */
2371static unsigned Bs3Cg1InsertModRmWithRegFieldsAndVvvv(PBS3CG1STATE pThis, unsigned off,
2372 uint8_t uReg, uint8_t uRegMem, uint8_t uVexVvvv)
2373{
2374 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, uReg & 7, uRegMem & 7);
2375 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + uReg;
2376 pThis->aOperands[1 ].idxField = pThis->aOperands[1 ].idxFieldBase + uVexVvvv;
2377 pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + uRegMem;
2378 return off;
2379}
2380
2381
2382static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_Vd_WO_Ed_WZ(PBS3CG1STATE pThis, unsigned iEncoding)
2383{
2384 unsigned off;
2385 switch (iEncoding)
2386 {
2387 case 0:
2388 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
2389 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
2390 off = Bs3Cg1InsertOpcodes(pThis, off);
2391 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
2392 break;
2393 case 1:
2394 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2395 off = Bs3Cg1InsertOpcodes(pThis, off);
2396 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2397 break;
2398 case 2:
2399 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L-invalid*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2400 off = Bs3Cg1InsertOpcodes(pThis, off);
2401 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2402 pThis->fInvalidEncoding = true;
2403 break;
2404 case 3:
2405 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xe /*~V-invalid*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2406 off = Bs3Cg1InsertOpcodes(pThis, off);
2407 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2408 pThis->fInvalidEncoding = true;
2409 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2410 break;
2411#if ARCH_BITS == 64
2412 case 4:
2413 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 0 /*~B*/, 0 /*W*/);
2414 off = Bs3Cg1InsertOpcodes(pThis, off);
2415 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6+8, 2+8);
2416 break;
2417#endif
2418 case 5:
2419 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
2420 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
2421 off = Bs3Cg1InsertOpcodes(pThis, off);
2422 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
2423 break;
2424 case 6:
2425 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2426 off = Bs3Cg1InsertOpcodes(pThis, off);
2427 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
2428 break;
2429 case 7:
2430 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2431 off = Bs3Cg1InsertOpcodes(pThis, off);
2432 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 4 /*iReg*/, 1 /*cbMisalign*/);
2433 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 : 0;
2434 break;
2435#if ARCH_BITS == 64
2436 case 8:
2437 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2438 off = Bs3Cg1InsertOpcodes(pThis, off);
2439 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4+8 /*iReg*/);
2440 break;
2441 case 9:
2442 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/);
2443 off = Bs3Cg1InsertOpcodes(pThis, off);
2444 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8 /*iReg*/);
2445 iEncoding += 2;
2446 break;
2447#endif
2448 case 10: /* VEX.W is ignored in 32-bit mode. flag? */
2449 BS3_ASSERT(!BS3CG1_IS_64BIT_TARGET(pThis));
2450 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
2451 off = Bs3Cg1InsertOpcodes(pThis, off);
2452 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
2453 break;
2454
2455 default:
2456 return 0;
2457 }
2458 pThis->cbCurInstr = off;
2459 return iEncoding + 1;
2460}
2461
2462
2463/* Differs from Bs3Cg1EncodeNext_MODRM_Pq_WO_Eq_WNZ in that REX.R isn't ignored. */
2464static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_Vq_WO_Eq_WNZ(PBS3CG1STATE pThis, unsigned iEncoding)
2465{
2466#if ARCH_BITS == 64
2467 if (BS3CG1_IS_64BIT_TARGET(pThis))
2468 {
2469 unsigned off;
2470 switch (iEncoding)
2471 {
2472 case 0:
2473 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
2474 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
2475 off = Bs3Cg1InsertOpcodes(pThis, off);
2476 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2477 break;
2478 case 1:
2479 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L-invalid*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
2480 off = Bs3Cg1InsertOpcodes(pThis, off);
2481 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2482 pThis->fInvalidEncoding = true;
2483 break;
2484 case 2:
2485 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xe /*~V-invalid*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
2486 off = Bs3Cg1InsertOpcodes(pThis, off);
2487 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2488 pThis->fInvalidEncoding = true;
2489 break;
2490 case 3:
2491 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 0 /*~B*/, 1 /*W*/);
2492 off = Bs3Cg1InsertOpcodes(pThis, off);
2493 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6+8, 2+8);
2494 break;
2495 case 4:
2496 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
2497 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
2498 off = Bs3Cg1InsertOpcodes(pThis, off);
2499 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
2500 break;
2501 case 5:
2502 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
2503 off = Bs3Cg1InsertOpcodes(pThis, off);
2504 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 4 /*iReg*/, 1 /*cbMisalign*/);
2505 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 : 0;
2506 break;
2507 case 6:
2508 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
2509 off = Bs3Cg1InsertOpcodes(pThis, off);
2510 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4+8 /*iReg*/);
2511 break;
2512
2513 default:
2514 return 0;
2515 }
2516 pThis->cbCurInstr = off;
2517 return iEncoding + 1;
2518 }
2519#endif
2520 return 0;
2521}
2522
2523
2524/**
2525 * Wip - VEX.W ignored.
2526 * Lig - VEX.L ignored.
2527 */
2528static unsigned BS3_NEAR_CODE
2529Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2530{
2531 unsigned off;
2532 switch (iEncoding)
2533 {
2534 case 0:
2535 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
2536 off = Bs3Cg1InsertOpcodes(pThis, off);
2537 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2538 break;
2539 case 1:
2540 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0x8 /*~V*/, 1 /*L-ignored*/, 1 /*~R*/);
2541 off = Bs3Cg1InsertOpcodes(pThis, off);
2542 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 3, 1, 7);
2543 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2544 break;
2545 case 2:
2546#if ARCH_BITS == 64
2547 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 0 /*~R*/);
2548 off = Bs3Cg1InsertOpcodes(pThis, off);
2549 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 3+8, 2, 15);
2550 break;
2551#endif
2552 case 3:
2553 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2554 off = Bs3Cg1InsertOpcodes(pThis, off);
2555 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2556 break;
2557 case 4:
2558 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - ignored*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2559 off = Bs3Cg1InsertOpcodes(pThis, off);
2560 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2561 break;
2562 case 5:
2563 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xc /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
2564 off = Bs3Cg1InsertOpcodes(pThis, off);
2565 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 3);
2566 break;
2567 case 6:
2568 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
2569 off = Bs3Cg1InsertOpcodes(pThis, off);
2570 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, BS3CG1_IS_64BIT_TARGET(pThis) ? 15 : 7);
2571 break;
2572 case 7:
2573 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2574 off = Bs3Cg1InsertOpcodes(pThis, off);
2575 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, BS3CG1_IS_64BIT_TARGET(pThis) ? 15 : 7);
2576 break;
2577 default:
2578 return 0;
2579 }
2580 pThis->cbCurInstr = off;
2581 return iEncoding + 1;
2582}
2583
2584
2585/**
2586 * Wip - VEX.W ignored.
2587 */
2588static unsigned BS3_NEAR_CODE
2589Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2590{
2591 unsigned off;
2592 switch (iEncoding)
2593 {
2594 case 0:
2595 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
2596 off = Bs3Cg1InsertOpcodes(pThis, off);
2597 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2598 break;
2599 case 1:
2600 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0x8 /*~V*/, 1 /*L-ignored*/, 1 /*~R*/);
2601 off = Bs3Cg1InsertOpcodes(pThis, off);
2602 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 3, 1, 7);
2603 pThis->fInvalidEncoding = true;
2604 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2605 break;
2606 case 2:
2607#if ARCH_BITS == 64
2608 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 0 /*~R*/);
2609 off = Bs3Cg1InsertOpcodes(pThis, off);
2610 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 3+8, 2, 15);
2611 break;
2612#endif
2613 case 3:
2614 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2615 off = Bs3Cg1InsertOpcodes(pThis, off);
2616 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2617 break;
2618 case 4:
2619 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - ignored*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2620 off = Bs3Cg1InsertOpcodes(pThis, off);
2621 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2622 pThis->fInvalidEncoding = true;
2623 break;
2624 case 5:
2625 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xc /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
2626 off = Bs3Cg1InsertOpcodes(pThis, off);
2627 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 3);
2628 break;
2629 case 6:
2630 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
2631 off = Bs3Cg1InsertOpcodes(pThis, off);
2632 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, BS3CG1_IS_64BIT_TARGET(pThis) ? 15 : 7);
2633 break;
2634 case 7:
2635 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2636 off = Bs3Cg1InsertOpcodes(pThis, off);
2637 off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, BS3CG1_IS_64BIT_TARGET(pThis) ? 15 : 7);
2638 break;
2639 default:
2640 return 0;
2641 }
2642 pThis->cbCurInstr = off;
2643 return iEncoding + 1;
2644}
2645
2646
2647/**
2648 * Wip - VEX.W ignored.
2649 */
2650static unsigned BS3_NEAR_CODE
2651Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2652{
2653 unsigned off;
2654 switch (iEncoding)
2655 {
2656 case 20: /* Switch to 256-bit operands. */
2657 pThis->aOperands[pThis->iRegOp].idxFieldBase = BS3CG1DST_YMM0;
2658 pThis->aOperands[pThis->iRegOp].cbOp = 32;
2659 pThis->aOperands[pThis->iRmOp ].cbOp = 32;
2660 /* fall thru */
2661 case 0:
2662 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/);
2663 off = Bs3Cg1InsertOpcodes(pThis, off);
2664 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2665 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2666 break;
2667#if ARCH_BITS == 64
2668 case 1:
2669 case 21:
2670 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 0 /*~R*/);
2671 off = Bs3Cg1InsertOpcodes(pThis, off);
2672 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
2673 break;
2674#endif
2675 case 2:
2676 case 22:
2677 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/);
2678 off = Bs3Cg1InsertOpcodes(pThis, off);
2679 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2680 pThis->fInvalidEncoding = true;
2681 break;
2682 case 3:
2683 case 23:
2684 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2685 off = Bs3Cg1InsertOpcodes(pThis, off);
2686 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2687 break;
2688 case 4:
2689 case 24:
2690 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
2691 off = Bs3Cg1InsertOpcodes(pThis, off);
2692 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2693 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
2694 break;
2695#if ARCH_BITS == 64
2696 case 5:
2697 case 25:
2698 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2699 off = Bs3Cg1InsertOpcodes(pThis, off);
2700 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
2701 break;
2702 case 6:
2703 case 26:
2704 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/);
2705 off = Bs3Cg1InsertOpcodes(pThis, off);
2706 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2707 break;
2708 case 7:
2709 case 27:
2710 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/);
2711 off = Bs3Cg1InsertOpcodes(pThis, off);
2712 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2713 break;
2714#endif
2715 case 8:
2716 case 28:
2717 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2718 off = Bs3Cg1InsertOpcodes(pThis, off);
2719 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2720 pThis->fInvalidEncoding = true;
2721 break;
2722 case 9:
2723 case 29:
2724 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 7 /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2725 off = Bs3Cg1InsertOpcodes(pThis, off);
2726 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2727 pThis->fInvalidEncoding = true;
2728 iEncoding += 10;
2729 break;
2730
2731 default:
2732 return 0;
2733 }
2734 pThis->cbCurInstr = off;
2735 return iEncoding + 1;
2736}
2737
2738
2739
2740/**
2741 * Wip - VEX.W ignored.
2742 * Lig - VEX.L ignored.
2743 */
2744static unsigned BS3_NEAR_CODE
2745Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2746{
2747 unsigned off;
2748 switch (iEncoding)
2749 {
2750 case 0:
2751 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
2752 off = Bs3Cg1InsertOpcodes(pThis, off);
2753 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2754 break;
2755 case 1:
2756 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - ignored*/, 1 /*~R*/);
2757 off = Bs3Cg1InsertOpcodes(pThis, off);
2758 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7);
2759 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2760 break;
2761#if ARCH_BITS == 64
2762 case 2:
2763 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - ignored*/, 0 /*~R*/);
2764 off = Bs3Cg1InsertOpcodes(pThis, off);
2765 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
2766 break;
2767#endif
2768 case 3:
2769 iEncoding = 3;
2770 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, 0 /*L*/, 1 /*~R*/);
2771 off = Bs3Cg1InsertOpcodes(pThis, off);
2772 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2773 pThis->fInvalidEncoding = true;
2774 break;
2775 case 4:
2776 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2777 off = Bs3Cg1InsertOpcodes(pThis, off);
2778 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2779 break;
2780 case 5:
2781 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L-ignored*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2782 off = Bs3Cg1InsertOpcodes(pThis, off);
2783 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2784 break;
2785 case 6:
2786 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
2787 off = Bs3Cg1InsertOpcodes(pThis, off);
2788 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2789 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
2790 break;
2791#if ARCH_BITS == 64
2792 case 7:
2793 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2794 off = Bs3Cg1InsertOpcodes(pThis, off);
2795 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
2796 break;
2797 case 8:
2798 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/);
2799 off = Bs3Cg1InsertOpcodes(pThis, off);
2800 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2801 break;
2802 case 9:
2803 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/);
2804 off = Bs3Cg1InsertOpcodes(pThis, off);
2805 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2806 break;
2807#endif
2808 case 10:
2809 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2810 off = Bs3Cg1InsertOpcodes(pThis, off);
2811 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2812 pThis->fInvalidEncoding = true;
2813 break;
2814 case 11:
2815 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 7 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2816 off = Bs3Cg1InsertOpcodes(pThis, off);
2817 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2818 pThis->fInvalidEncoding = true;
2819 break;
2820 default:
2821 return 0;
2822 }
2823 pThis->cbCurInstr = off;
2824 return iEncoding + 1;
2825}
2826
2827
2828/**
2829 * Wip - VEX.W ignored.
2830 * L0 - VEX.L must be zero.
2831 */
2832static unsigned BS3_NEAR_CODE
2833Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lmbz_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2834{
2835 unsigned off;
2836 switch (iEncoding)
2837 {
2838 case 0:
2839 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
2840 off = Bs3Cg1InsertOpcodes(pThis, off);
2841 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2842 break;
2843 case 1:
2844 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - invalid*/, 1 /*~R*/);
2845 off = Bs3Cg1InsertOpcodes(pThis, off);
2846 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7);
2847 pThis->fInvalidEncoding = true;
2848 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 : 0;
2849 break;
2850#if ARCH_BITS == 64
2851 case 2:
2852 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/);
2853 off = Bs3Cg1InsertOpcodes(pThis, off);
2854 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
2855 break;
2856 case 3:
2857 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - invalid*/, 0 /*~R*/);
2858 off = Bs3Cg1InsertOpcodes(pThis, off);
2859 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5 + 8);
2860 pThis->fInvalidEncoding = true;
2861 break;
2862#endif
2863 case 4:
2864 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, 0 /*L*/, 1 /*~R*/);
2865 off = Bs3Cg1InsertOpcodes(pThis, off);
2866 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2867 pThis->fInvalidEncoding = true;
2868 break;
2869 case 5:
2870 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2871 off = Bs3Cg1InsertOpcodes(pThis, off);
2872 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2873 break;
2874 case 6:
2875 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - invalid*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2876 off = Bs3Cg1InsertOpcodes(pThis, off);
2877 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2878 pThis->fInvalidEncoding = true;
2879 break;
2880 case 7:
2881 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
2882 off = Bs3Cg1InsertOpcodes(pThis, off);
2883 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2884 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
2885 break;
2886#if ARCH_BITS == 64
2887 case 8:
2888 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2889 off = Bs3Cg1InsertOpcodes(pThis, off);
2890 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
2891 break;
2892 case 9:
2893 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/);
2894 off = Bs3Cg1InsertOpcodes(pThis, off);
2895 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2896 break;
2897 case 10:
2898 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/);
2899 off = Bs3Cg1InsertOpcodes(pThis, off);
2900 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2901 break;
2902#endif
2903 case 11:
2904 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2905 off = Bs3Cg1InsertOpcodes(pThis, off);
2906 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2907 pThis->fInvalidEncoding = true;
2908 break;
2909 case 12:
2910 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 7 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2911 off = Bs3Cg1InsertOpcodes(pThis, off);
2912 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2913 pThis->fInvalidEncoding = true;
2914 break;
2915 default:
2916 return 0;
2917 }
2918 pThis->cbCurInstr = off;
2919 return iEncoding + 1;
2920}
2921
2922
2923/**
2924 * Wip - VEX.W ignored.
2925 */
2926static unsigned BS3_NEAR_CODE
2927Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding, uint8_t uVexL)
2928{
2929 unsigned off;
2930 switch (iEncoding)
2931 {
2932 case 0:
2933 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/);
2934 off = Bs3Cg1InsertOpcodes(pThis, off);
2935 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2936 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2937 break;
2938#if ARCH_BITS == 64
2939 case 1:
2940 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 0 /*~R*/);
2941 off = Bs3Cg1InsertOpcodes(pThis, off);
2942 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
2943 break;
2944#endif
2945 case 2:
2946 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, uVexL, 1 /*~R*/);
2947 off = Bs3Cg1InsertOpcodes(pThis, off);
2948 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2949 pThis->fInvalidEncoding = true;
2950 break;
2951 case 3:
2952 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2953 off = Bs3Cg1InsertOpcodes(pThis, off);
2954 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2955 break;
2956 case 4:
2957 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
2958 off = Bs3Cg1InsertOpcodes(pThis, off);
2959 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2960 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
2961 break;
2962#if ARCH_BITS == 64
2963 case 5:
2964 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2965 off = Bs3Cg1InsertOpcodes(pThis, off);
2966 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
2967 break;
2968 case 6:
2969 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/);
2970 off = Bs3Cg1InsertOpcodes(pThis, off);
2971 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2972 break;
2973 case 7:
2974 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/);
2975 off = Bs3Cg1InsertOpcodes(pThis, off);
2976 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2977 break;
2978#endif
2979 case 8:
2980 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2981 off = Bs3Cg1InsertOpcodes(pThis, off);
2982 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2983 pThis->fInvalidEncoding = true;
2984 break;
2985 case 9:
2986 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 7 /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
2987 off = Bs3Cg1InsertOpcodes(pThis, off);
2988 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2989 pThis->fInvalidEncoding = true;
2990 break;
2991 default:
2992 return 0;
2993 }
2994 pThis->cbCurInstr = off;
2995 return iEncoding + 1;
2996}
2997
2998
2999/**
3000 * Wip - VEX.W ignored.
3001 * L0 - VEX.L is zero (encoding may exist where it isn't).
3002 */
3003static unsigned BS3_NEAR_CODE
3004Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L0_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
3005{
3006 return Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(pThis, iEncoding, 0 /*uVexL*/);
3007}
3008
3009
3010/**
3011 * Wip - VEX.W ignored.
3012 * L1 - VEX.L is one (encoding may exist where it isn't).
3013 */
3014static unsigned BS3_NEAR_CODE
3015Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L1_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
3016{
3017 return Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(pThis, iEncoding, 1 /*uVexL*/);
3018}
3019
3020
3021
3022/**
3023 * Wip - VEX.W ignored.
3024 */
3025static unsigned BS3_NEAR_CODE
3026Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Msomething_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
3027{
3028 unsigned off;
3029 switch (iEncoding)
3030 {
3031 case 0:
3032 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xc /*~V*/, 0 /*L*/, 1 /*~R*/);
3033 off = Bs3Cg1InsertOpcodes(pThis, off);
3034 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
3035 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 3;
3036 break;
3037 case 1:
3038 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/);
3039 off = Bs3Cg1InsertOpcodes(pThis, off);
3040 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7);
3041 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3042 pThis->fInvalidEncoding = true;
3043 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
3044 break;
3045#if ARCH_BITS == 64
3046 case 2:
3047 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0x1 /*~V*/, 0 /*L*/, 0 /*~R*/);
3048 off = Bs3Cg1InsertOpcodes(pThis, off);
3049 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
3050 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 14;
3051 break;
3052#endif
3053 case 3:
3054 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, 0 /*L*/, 1 /*~R*/);
3055 off = Bs3Cg1InsertOpcodes(pThis, off);
3056 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
3057 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 1;
3058 break;
3059 case 4:
3060 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3061 off = Bs3Cg1InsertOpcodes(pThis, off);
3062 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
3063 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3064 break;
3065 case 5:
3066 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L-ignored*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3067 off = Bs3Cg1InsertOpcodes(pThis, off);
3068 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
3069 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3070 pThis->fInvalidEncoding = true;
3071 break;
3072 case 6:
3073 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
3074 off = Bs3Cg1InsertOpcodes(pThis, off);
3075 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
3076 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3077 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
3078 break;
3079#if ARCH_BITS == 64
3080 case 7:
3081 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3082 off = Bs3Cg1InsertOpcodes(pThis, off);
3083 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
3084 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3085 break;
3086 case 8:
3087 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/);
3088 off = Bs3Cg1InsertOpcodes(pThis, off);
3089 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
3090 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3091 break;
3092 case 9:
3093 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/);
3094 off = Bs3Cg1InsertOpcodes(pThis, off);
3095 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
3096 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3097 break;
3098#endif
3099 case 10:
3100 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3101 off = Bs3Cg1InsertOpcodes(pThis, off);
3102 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
3103 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + (BS3CG1_IS_64BIT_TARGET(pThis) ? 15 : 7);
3104 pThis->fInvalidEncoding = true;
3105 break;
3106 default:
3107 return 0;
3108 }
3109 pThis->cbCurInstr = off;
3110 return iEncoding + 1;
3111}
3112
3113
3114static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_Md_WO(PBS3CG1STATE pThis, unsigned iEncoding)
3115{
3116 unsigned off;
3117 switch (iEncoding)
3118 {
3119 case 0:
3120 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
3121 off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3122 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3123 break;
3124 case 1:
3125 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3126 off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3127 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3128 break;
3129 case 2:
3130 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0x7 /*~V-invalid*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3131 off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3132 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3133 pThis->fInvalidEncoding = true;
3134 break;
3135 case 3:
3136 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3137 off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3138 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3139 pThis->fInvalidEncoding = true;
3140 break;
3141 case 4:
3142 pThis->abCurInstr[0] = P_OZ;
3143 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3144 off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3145 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3146 pThis->fInvalidEncoding = true;
3147 break;
3148 case 5:
3149 pThis->abCurInstr[0] = P_RZ;
3150 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3151 off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3152 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3153 pThis->fInvalidEncoding = true;
3154 break;
3155 case 6:
3156 pThis->abCurInstr[0] = P_RN;
3157 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3158 off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3159 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3160 pThis->fInvalidEncoding = true;
3161 break;
3162 case 7:
3163 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
3164 off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3165 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3166 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
3167 break;
3168#if ARCH_BITS == 64
3169 case 8:
3170 pThis->abCurInstr[0] = REX_____;
3171 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3172 off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3173 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3174 pThis->fInvalidEncoding = true;
3175 break;
3176#endif
3177 default:
3178 return 0;
3179 }
3180
3181 pThis->cbCurInstr = off;
3182 return iEncoding + 1;
3183}
3184
3185
3186/**
3187 * Wip = VEX.W ignored.
3188 * Lmbz = VEX.L must be zero.
3189 */
3190static unsigned BS3_NEAR_CODE
3191Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_Lmbz_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
3192{
3193 unsigned off;
3194 switch (iEncoding)
3195 {
3196 /* 128-bit wide stuff goes first, then we'll update the operand widths afterwards. */
3197 case 0:
3198 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
3199 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
3200 off = Bs3Cg1InsertOpcodes(pThis, off);
3201 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
3202 break;
3203
3204 case 1:
3205 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3206 off = Bs3Cg1InsertOpcodes(pThis, off);
3207 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3208 break;
3209 case 2:
3210 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W - ignored*/);
3211 off = Bs3Cg1InsertOpcodes(pThis, off);
3212 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 5, 4);
3213 break;
3214 case 3:
3215 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
3216 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
3217 off = Bs3Cg1InsertOpcodes(pThis, off);
3218 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /*iReg*/);
3219 break;
3220 case 4:
3221 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3222 off = Bs3Cg1InsertOpcodes(pThis, off);
3223 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /*iReg*/);
3224 break;
3225 case 5:
3226 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W - ignored */);
3227 off = Bs3Cg1InsertOpcodes(pThis, off);
3228 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /*iReg*/);
3229 break;
3230 case 6:
3231 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
3232 off = Bs3Cg1InsertOpcodes(pThis, off);
3233 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /*iReg*/, 1 /*cbMisalign*/);
3234 if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
3235 pThis->bAlignmentXcpt = X86_XCPT_GP;
3236 break;
3237 case 7:
3238 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3239 off = Bs3Cg1InsertOpcodes(pThis, off);
3240 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /*iReg*/, 1 /*cbMisalign*/);
3241 if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
3242 pThis->bAlignmentXcpt = X86_XCPT_GP;
3243 break;
3244 /* 128-bit invalid encodings: */
3245 case 8:
3246 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
3247 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, 0 /*L*/, 1 /*~R*/); /* Bad V value */
3248 off = Bs3Cg1InsertOpcodes(pThis, off);
3249 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
3250 pThis->fInvalidEncoding = true;
3251 break;
3252 case 9:
3253 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3254 off = Bs3Cg1InsertOpcodes(pThis, off);
3255 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3256 pThis->fInvalidEncoding = true;
3257 iEncoding = 20-1;
3258 break;
3259
3260 default:
3261 return 0;
3262 }
3263
3264 pThis->cbCurInstr = off;
3265 return iEncoding + 1;
3266}
3267
3268
3269/**
3270 * Wip = VEX.W ignored.
3271 */
3272static unsigned BS3_NEAR_CODE
3273Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
3274{
3275 unsigned off;
3276
3277 switch (iEncoding)
3278 {
3279 case 20: /* switch to 256-bit */
3280 pThis->aOperands[pThis->iRmOp ].cbOp = 32;
3281 pThis->aOperands[pThis->iRmOp ].idxFieldBase = BS3CG1DST_YMM0;
3282 pThis->aOperands[pThis->iRegOp].cbOp = 32;
3283 pThis->aOperands[pThis->iRegOp].idxFieldBase = BS3CG1DST_YMM0;
3284 /* fall thru */
3285 case 0:
3286 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
3287 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/);
3288 off = Bs3Cg1InsertOpcodes(pThis, off);
3289 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
3290 break;
3291
3292 case 1:
3293 case 21:
3294 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3295 off = Bs3Cg1InsertOpcodes(pThis, off);
3296 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3297 break;
3298 case 2:
3299 case 22:
3300 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W - ignored*/);
3301 off = Bs3Cg1InsertOpcodes(pThis, off);
3302 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 5, 4);
3303 break;
3304 case 3:
3305 case 23:
3306 pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
3307 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/);
3308 off = Bs3Cg1InsertOpcodes(pThis, off);
3309 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /*iReg*/);
3310 break;
3311 case 4:
3312 case 24:
3313 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3314 off = Bs3Cg1InsertOpcodes(pThis, off);
3315 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /*iReg*/);
3316 break;
3317 case 5:
3318 case 25:
3319 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W - ignored */);
3320 off = Bs3Cg1InsertOpcodes(pThis, off);
3321 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /*iReg*/);
3322 break;
3323 case 6:
3324 case 26:
3325 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/);
3326 off = Bs3Cg1InsertOpcodes(pThis, off);
3327 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /*iReg*/, 1 /*cbMisalign*/);
3328 if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
3329 pThis->bAlignmentXcpt = X86_XCPT_GP;
3330 break;
3331 case 7:
3332 case 27:
3333 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3334 off = Bs3Cg1InsertOpcodes(pThis, off);
3335 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /*iReg*/, 1 /*cbMisalign*/);
3336 if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
3337 pThis->bAlignmentXcpt = X86_XCPT_GP;
3338 break;
3339 /* invalid encodings: */
3340 case 8:
3341 case 28:
3342 pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
3343 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/); /* Bad V value */
3344 off = Bs3Cg1InsertOpcodes(pThis, off);
3345 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
3346 pThis->fInvalidEncoding = true;
3347 break;
3348 case 9:
3349 case 29:
3350 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3351 off = Bs3Cg1InsertOpcodes(pThis, off);
3352 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3353 pThis->fInvalidEncoding = true;
3354 break;
3355
3356 case 10:
3357 case 30:
3358 pThis->abCurInstr[0] = P_RN;
3359 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3360 off = Bs3Cg1InsertOpcodes(pThis, off);
3361 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3362 pThis->fInvalidEncoding = true;
3363 break;
3364 case 11:
3365 case 31:
3366 pThis->abCurInstr[0] = P_RZ;
3367 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3368 off = Bs3Cg1InsertOpcodes(pThis, off);
3369 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3370 pThis->fInvalidEncoding = true;
3371 break;
3372 case 12:
3373 case 32:
3374 pThis->abCurInstr[0] = P_OZ;
3375 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3376 off = Bs3Cg1InsertOpcodes(pThis, off);
3377 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3378 pThis->fInvalidEncoding = true;
3379 break;
3380 case 13:
3381 case 33:
3382 pThis->abCurInstr[0] = P_LK;
3383 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3384 off = Bs3Cg1InsertOpcodes(pThis, off);
3385 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3386 pThis->fInvalidEncoding = true;
3387 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 + 4 : 0;
3388 break;
3389
3390#if ARCH_BITS == 64
3391 /* 64-bit mode registers */
3392 case 14:
3393 case 34:
3394 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 0 /*~R*/);
3395 off = Bs3Cg1InsertOpcodes(pThis, off);
3396 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 3+8, 4);
3397 break;
3398 case 15:
3399 case 35:
3400 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 0 /*~R*/, 1 /*~X*/, 0 /*~B*/, 0 /*W*/);
3401 off = Bs3Cg1InsertOpcodes(pThis, off);
3402 off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1+8, 4+8);
3403 iEncoding += 4;
3404 break;
3405#endif
3406 default:
3407 return 0;
3408 }
3409
3410 pThis->cbCurInstr = off;
3411 return iEncoding + 1;
3412}
3413
3414
3415//static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_FIXED(PBS3CG1STATE pThis, unsigned iEncoding)
3416//{
3417// unsigned off;
3418// if (iEncoding == 0)
3419// off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
3420// else if (iEncoding == 0)
3421// off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3422// else
3423// return 0;
3424// pThis->cbCurInstr = off;
3425// return iEncoding + 1;
3426//}
3427
3428
3429static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_MOD_EQ_3(PBS3CG1STATE pThis, unsigned iEncoding)
3430{
3431 unsigned off;
3432 if (iEncoding < 8)
3433 {
3434 if (iEncoding & 1)
3435 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
3436 else
3437 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3438 off = Bs3Cg1InsertOpcodes(pThis, off);
3439 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding, 1);
3440 }
3441 else if (iEncoding < 16)
3442 {
3443 if (iEncoding & 1)
3444 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/);
3445 else
3446 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3447 off = Bs3Cg1InsertOpcodes(pThis, off);
3448 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding & 7, 1);
3449 }
3450 else if (iEncoding < 24)
3451 {
3452 if (iEncoding & 1)
3453 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
3454 else
3455 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
3456 off = Bs3Cg1InsertOpcodes(pThis, off);
3457 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding & 7);
3458 }
3459 else if (iEncoding < 32)
3460 {
3461 if (iEncoding & 1)
3462 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, (iEncoding & 3) != 0 /*L*/, 1 /*~R*/);
3463 else
3464 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, (iEncoding & 2) != 0 /*L*/, 1 /*~R*/, 1 /*~X*/,
3465 1 /*~B*/, (iEncoding & 4) != 0 /*W*/);
3466 off = Bs3Cg1InsertOpcodes(pThis, off);
3467 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding & 7);
3468 }
3469 else
3470 return 0;
3471 pThis->cbCurInstr = off;
3472
3473 return iEncoding + 1;
3474}
3475
3476
3477static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_MOD_NE_3(PBS3CG1STATE pThis, unsigned iEncoding)
3478{
3479 unsigned off;
3480 if (iEncoding < 8)
3481 {
3482 unsigned iMod = iEncoding % 3;
3483 if (iEncoding & 1)
3484 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, (iEncoding & 2) != 0 /*L*/, 1 /*~R*/);
3485 else
3486 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, (iEncoding & 2) != 0 /*L*/, 1 /*~R*/,
3487 1 /*~X*/, 1 /*~B*/, (iEncoding & 4) != 0 /*W*/);
3488 off = Bs3Cg1InsertOpcodes(pThis, off);
3489 pThis->abCurInstr[off++] = X86_MODRM_MAKE(iMod, 0, 1);
3490 if (iMod >= 1)
3491 pThis->abCurInstr[off++] = 0x7f;
3492 if (iMod == 2)
3493 {
3494 pThis->abCurInstr[off++] = 0x5f;
3495 if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
3496 {
3497 pThis->abCurInstr[off++] = 0x3f;
3498 pThis->abCurInstr[off++] = 0x1f;
3499 }
3500 }
3501 }
3502 else
3503 return 0;
3504 pThis->cbCurInstr = off;
3505 return iEncoding + 1;
3506}
3507
3508
3509static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM(PBS3CG1STATE pThis, unsigned iEncoding)
3510{
3511 const unsigned cFirstEncodings = 32;
3512 if (iEncoding < cFirstEncodings)
3513 {
3514 unsigned iRet = Bs3Cg1EncodeNext_VEX_MODRM_MOD_EQ_3(pThis, iEncoding);
3515 BS3_ASSERT(iRet > iEncoding);
3516 return iRet;
3517 }
3518 return Bs3Cg1EncodeNext_VEX_MODRM_MOD_NE_3(pThis, iEncoding - cFirstEncodings) + cFirstEncodings;
3519}
3520
3521#endif /* BS3CG1_WITH_VEX */
3522
3523
3524/**
3525 * Encodes the next instruction.
3526 *
3527 * @returns Next iEncoding value. Returns @a iEncoding unchanged to indicate
3528 * that there are no more encodings to test.
3529 * @param pThis The state.
3530 * @param iEncoding The encoding to produce. Meaning is specific to
3531 * each BS3CG1ENC_XXX value and should be considered
3532 * internal.
3533 */
3534static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext(PBS3CG1STATE pThis, unsigned iEncoding)
3535{
3536 pThis->bAlignmentXcpt = UINT8_MAX;
3537 pThis->uVexL = UINT8_MAX;
3538 if (pThis->pfnEncoder)
3539 return pThis->pfnEncoder(pThis, iEncoding);
3540
3541 Bs3TestFailedF("Internal error! BS3CG1ENC_XXX = %u not implemented", pThis->enmEncoding);
3542 return iEncoding;
3543}
3544
3545
3546/**
3547 * Prepares doing instruction encodings.
3548 *
3549 * This is in part specific to how the instruction is encoded, but generally it
3550 * sets up basic operand values that doesn't change (much) when Bs3Cg1EncodeNext
3551 * is called from within the loop.
3552 *
3553 * @returns Success indicator (true/false).
3554 * @param pThis The state.
3555 */
3556#define Bs3Cg1EncodePrep BS3_CMN_NM(Bs3Cg1EncodePrep)
3557bool BS3_NEAR_CODE Bs3Cg1EncodePrep(PBS3CG1STATE pThis)
3558{
3559 unsigned i = 4;
3560 while (i-- > 0)
3561 pThis->aSavedSegRegs[i].ds = pThis->aInitialCtxs[i].ds;
3562
3563 i = RT_ELEMENTS(pThis->aOperands);
3564 while (i-- > 0)
3565 {
3566 pThis->aOperands[i].enmLocationReg = BS3CG1OPLOC_INVALID;
3567 pThis->aOperands[i].enmLocationMem = BS3CG1OPLOC_INVALID;
3568 pThis->aOperands[i].idxFieldBase = BS3CG1DST_INVALID;
3569 }
3570
3571 pThis->iRmOp = RT_ELEMENTS(pThis->aOperands) - 1;
3572 pThis->iRegOp = RT_ELEMENTS(pThis->aOperands) - 1;
3573 pThis->fSameRingNotOkay = false;
3574 pThis->cbOperand = 0;
3575 pThis->pfnEncoder = NULL;
3576
3577 switch (pThis->enmEncoding)
3578 {
3579 case BS3CG1ENC_MODRM_Eb_Gb:
3580 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Eb_Gb_OR_ViceVersa;
3581 pThis->iRmOp = 0;
3582 pThis->iRegOp = 1;
3583 pThis->aOperands[0].cbOp = 1;
3584 pThis->aOperands[1].cbOp = 1;
3585 pThis->aOperands[0].idxFieldBase = BS3CG1DST_AL;
3586 pThis->aOperands[1].idxFieldBase = BS3CG1DST_AL;
3587 pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3588 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_RW;
3589 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3590 break;
3591
3592 case BS3CG1ENC_MODRM_Ev_Gv:
3593 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Gv_Ev__OR__MODRM_Ev_Gv;
3594 pThis->iRmOp = 0;
3595 pThis->iRegOp = 1;
3596 pThis->cbOperand = 2;
3597 pThis->aOperands[0].idxFieldBase = BS3CG1DST_OZ_RAX;
3598 pThis->aOperands[1].idxFieldBase = BS3CG1DST_OZ_RAX;
3599 pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3600 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_RW;
3601 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3602 break;
3603
3604 case BS3CG1ENC_MODRM_Ed_WO_Pd_WZ:
3605 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_PdZx_WO_Ed_WZ;
3606 pThis->iRmOp = 0;
3607 pThis->iRegOp = 1;
3608 pThis->aOperands[0].cbOp = 4;
3609 pThis->aOperands[1].cbOp = 4;
3610 pThis->aOperands[0].idxFieldBase = BS3CG1DST_EAX;
3611 pThis->aOperands[1].idxFieldBase = BS3CG1DST_MM0;
3612 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3613 pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3614 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3615 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3616 break;
3617
3618 case BS3CG1ENC_MODRM_Eq_WO_Pq_WNZ:
3619 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Pq_WO_Eq_WNZ;
3620 pThis->iRmOp = 0;
3621 pThis->iRegOp = 1;
3622 pThis->aOperands[0].cbOp = 8;
3623 pThis->aOperands[1].cbOp = 8;
3624 pThis->aOperands[0].idxFieldBase = BS3CG1DST_RAX;
3625 pThis->aOperands[1].idxFieldBase = BS3CG1DST_MM0;
3626 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3627 pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3628 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3629 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3630 break;
3631
3632 case BS3CG1ENC_MODRM_Ed_WO_Vd_WZ:
3633 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vd_WO_Ed_WZ;
3634 pThis->iRmOp = 0;
3635 pThis->iRegOp = 1;
3636 pThis->aOperands[0].cbOp = 4;
3637 pThis->aOperands[1].cbOp = 4;
3638 pThis->aOperands[0].idxFieldBase = BS3CG1DST_EAX;
3639 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
3640 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3641 pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3642 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3643 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3644 break;
3645
3646 case BS3CG1ENC_MODRM_Eq_WO_Vq_WNZ:
3647 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vq_WO_Eq_WNZ;
3648 pThis->iRmOp = 0;
3649 pThis->iRegOp = 1;
3650 pThis->aOperands[0].cbOp = 8;
3651 pThis->aOperands[1].cbOp = 8;
3652 pThis->aOperands[0].idxFieldBase = BS3CG1DST_RAX;
3653 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
3654 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3655 pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3656 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3657 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3658 break;
3659
3660 case BS3CG1ENC_MODRM_Gb_Eb:
3661 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Eb_Gb_OR_ViceVersa;
3662 pThis->iRegOp = 0;
3663 pThis->iRmOp = 1;
3664 pThis->aOperands[0].cbOp = 1;
3665 pThis->aOperands[1].cbOp = 1;
3666 pThis->aOperands[0].idxFieldBase = BS3CG1DST_AL;
3667 pThis->aOperands[1].idxFieldBase = BS3CG1DST_AL;
3668 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3669 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3670 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3671 break;
3672
3673 case BS3CG1ENC_MODRM_Gv_Ev:
3674 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Gv_Ev__OR__MODRM_Ev_Gv;
3675 pThis->iRegOp = 0;
3676 pThis->iRmOp = 1;
3677 pThis->cbOperand = 2;
3678 pThis->aOperands[0].idxFieldBase = BS3CG1DST_OZ_RAX;
3679 pThis->aOperands[1].idxFieldBase = BS3CG1DST_OZ_RAX;
3680 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3681 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3682 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3683 break;
3684
3685 case BS3CG1ENC_MODRM_Gv_RO_Ma: /* bound instr */
3686 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Gv_RO_Ma;
3687 pThis->iRmOp = 1;
3688 pThis->iRegOp = 0;
3689 pThis->cbOperand = 2;
3690 pThis->aOperands[0].cbOp = 2;
3691 pThis->aOperands[1].cbOp = 4;
3692 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3693 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
3694 pThis->aOperands[0].idxFieldBase = BS3CG1DST_OZ_RAX;
3695 break;
3696
3697 case BS3CG1ENC_MODRM_Wss_WO_Vss:
3698 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3699 pThis->iRmOp = 0;
3700 pThis->iRegOp = 1;
3701 pThis->aOperands[0].cbOp = 4;
3702 pThis->aOperands[1].cbOp = 4;
3703 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_DW0;
3704 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_DW0;
3705 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3706 pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3707 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3708 break;
3709
3710 case BS3CG1ENC_MODRM_Wsd_WO_Vsd:
3711 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3712 pThis->iRmOp = 0;
3713 pThis->iRegOp = 1;
3714 pThis->aOperands[0].cbOp = 8;
3715 pThis->aOperands[1].cbOp = 8;
3716 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO;
3717 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3718 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3719 pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3720 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3721 break;
3722
3723 case BS3CG1ENC_MODRM_WqZxReg_WO_Vq:
3724 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3725 pThis->iRmOp = 0;
3726 pThis->iRegOp = 1;
3727 pThis->aOperands[0].cbOp = 8;
3728 pThis->aOperands[1].cbOp = 8;
3729 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO_ZX;
3730 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3731 pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3732 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3733 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3734 break;
3735
3736 case BS3CG1ENC_MODRM_Wps_WO_Vps:
3737 case BS3CG1ENC_MODRM_Wpd_WO_Vpd:
3738 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3739 pThis->iRmOp = 0;
3740 pThis->iRegOp = 1;
3741 pThis->aOperands[0].cbOp = 16;
3742 pThis->aOperands[1].cbOp = 16;
3743 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
3744 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
3745 pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3746 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3747 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3748 break;
3749
3750 case BS3CG1ENC_MODRM_Vdq_WO_Mdq:
3751 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
3752 pThis->iRegOp = 0;
3753 pThis->iRmOp = 1;
3754 pThis->aOperands[0].cbOp = 16;
3755 pThis->aOperands[1].cbOp = 16;
3756 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3757 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
3758 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
3759 break;
3760
3761 case BS3CG1ENC_MODRM_Vdq_WO_Wdq:
3762 case BS3CG1ENC_MODRM_Vpd_WO_Wpd:
3763 case BS3CG1ENC_MODRM_Vps_WO_Wps:
3764 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3765 pThis->iRegOp = 0;
3766 pThis->iRmOp = 1;
3767 pThis->aOperands[0].cbOp = 16;
3768 pThis->aOperands[1].cbOp = 16;
3769 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
3770 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
3771 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3772 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3773 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3774 break;
3775
3776 case BS3CG1ENC_MODRM_Pq_WO_Qq:
3777 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Pq_WO_Qq;
3778 pThis->iRegOp = 0;
3779 pThis->iRmOp = 1;
3780 pThis->aOperands[0].cbOp = 8;
3781 pThis->aOperands[1].cbOp = 8;
3782 pThis->aOperands[0].idxFieldBase = BS3CG1DST_MM0;
3783 pThis->aOperands[1].idxFieldBase = BS3CG1DST_MM0;
3784 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3785 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3786 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3787 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3788 break;
3789
3790 case BS3CG1ENC_MODRM_Pq_WO_Uq:
3791 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Pq_WO_Uq;
3792 pThis->iRegOp = 0;
3793 pThis->iRmOp = 1;
3794 pThis->aOperands[0].cbOp = 8;
3795 pThis->aOperands[1].cbOp = 8;
3796 pThis->aOperands[0].idxFieldBase = BS3CG1DST_MM0;
3797 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3798 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3799 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX; /* reg only */
3800 break;
3801
3802 case BS3CG1ENC_MODRM_PdZx_WO_Ed_WZ:
3803 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_PdZx_WO_Ed_WZ;
3804 pThis->iRegOp = 0;
3805 pThis->iRmOp = 1;
3806 pThis->aOperands[0].cbOp = 4;
3807 pThis->aOperands[1].cbOp = 4;
3808 pThis->aOperands[0].idxFieldBase = BS3CG1DST_MM0_LO_ZX;
3809 pThis->aOperands[1].idxFieldBase = BS3CG1DST_EAX;
3810 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3811 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3812 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3813 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3814 break;
3815
3816 case BS3CG1ENC_MODRM_Pq_WO_Eq_WNZ:
3817 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Pq_WO_Eq_WNZ;
3818 pThis->iRegOp = 0;
3819 pThis->iRmOp = 1;
3820 pThis->aOperands[0].cbOp = 8;
3821 pThis->aOperands[1].cbOp = 8;
3822 pThis->aOperands[0].idxFieldBase = BS3CG1DST_MM0;
3823 pThis->aOperands[1].idxFieldBase = BS3CG1DST_RAX;
3824 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3825 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3826 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3827 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3828 break;
3829
3830 case BS3CG1ENC_MODRM_VdZx_WO_Ed_WZ:
3831 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vd_WO_Ed_WZ;
3832 pThis->iRegOp = 0;
3833 pThis->iRmOp = 1;
3834 pThis->aOperands[0].cbOp = 4;
3835 pThis->aOperands[1].cbOp = 4;
3836 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_DW0_ZX;
3837 pThis->aOperands[1].idxFieldBase = BS3CG1DST_EAX;
3838 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3839 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3840 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3841 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3842 break;
3843
3844 case BS3CG1ENC_MODRM_VqZx_WO_Eq_WNZ:
3845 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vq_WO_Eq_WNZ;
3846 pThis->iRegOp = 0;
3847 pThis->iRmOp = 1;
3848 pThis->aOperands[0].cbOp = 8;
3849 pThis->aOperands[1].cbOp = 8;
3850 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO_ZX;
3851 pThis->aOperands[1].idxFieldBase = BS3CG1DST_RAX;
3852 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3853 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3854 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3855 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3856 break;
3857
3858 case BS3CG1ENC_MODRM_Vq_WO_UqHi:
3859 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Usomething_OR_ViceVersa;
3860 pThis->iRegOp = 0;
3861 pThis->iRmOp = 1;
3862 pThis->aOperands[0].cbOp = 8;
3863 pThis->aOperands[1].cbOp = 8;
3864 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO;
3865 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
3866 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3867 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3868 break;
3869
3870 case BS3CG1ENC_MODRM_VqHi_WO_Uq:
3871 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Usomething_OR_ViceVersa;
3872 pThis->iRegOp = 0;
3873 pThis->iRmOp = 1;
3874 pThis->aOperands[0].cbOp = 8;
3875 pThis->aOperands[1].cbOp = 8;
3876 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_HI;
3877 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3878 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3879 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3880 break;
3881
3882 case BS3CG1ENC_MODRM_VqHi_WO_Mq:
3883 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
3884 pThis->iRegOp = 0;
3885 pThis->iRmOp = 1;
3886 pThis->aOperands[0].cbOp = 8;
3887 pThis->aOperands[1].cbOp = 8;
3888 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_HI;
3889 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3890 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
3891 break;
3892
3893 case BS3CG1ENC_MODRM_Vq_WO_Mq:
3894 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
3895 pThis->iRegOp = 0;
3896 pThis->iRmOp = 1;
3897 pThis->aOperands[0].cbOp = 8;
3898 pThis->aOperands[1].cbOp = 8;
3899 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO;
3900 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3901 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
3902 break;
3903
3904 case BS3CG1ENC_MODRM_VssZx_WO_Wss:
3905 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3906 pThis->iRegOp = 0;
3907 pThis->iRmOp = 1;
3908 pThis->aOperands[0].cbOp = 4;
3909 pThis->aOperands[1].cbOp = 4;
3910 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3911 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3912 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3913 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_DW0_ZX;
3914 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3915 break;
3916
3917 case BS3CG1ENC_MODRM_VqZx_WO_Nq:
3918 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Nsomething;
3919 pThis->iRegOp = 0;
3920 pThis->iRmOp = 1;
3921 pThis->aOperands[0].cbOp = 8;
3922 pThis->aOperands[1].cbOp = 8;
3923 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3924 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3925 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO_ZX;
3926 pThis->aOperands[1].idxFieldBase = BS3CG1DST_MM0;
3927 break;
3928
3929 case BS3CG1ENC_MODRM_VsdZx_WO_Wsd:
3930 case BS3CG1ENC_MODRM_VqZx_WO_Wq:
3931 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3932 pThis->iRegOp = 0;
3933 pThis->iRmOp = 1;
3934 pThis->aOperands[0].cbOp = 8;
3935 pThis->aOperands[1].cbOp = 8;
3936 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3937 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3938 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3939 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3940 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO_ZX;
3941 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3942 break;
3943
3944 case BS3CG1ENC_MODRM_Mb_RO:
3945 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething;
3946 pThis->iRmOp = 0;
3947 pThis->aOperands[0].cbOp = 1;
3948 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM;
3949 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM;
3950 break;
3951
3952 case BS3CG1ENC_MODRM_Md_RO:
3953 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething;
3954 pThis->iRmOp = 0;
3955 pThis->aOperands[0].cbOp = 4;
3956 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM;
3957 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM;
3958 break;
3959
3960 case BS3CG1ENC_MODRM_Md_WO:
3961 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething;
3962 pThis->iRmOp = 0;
3963 pThis->aOperands[0].cbOp = 4;
3964 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
3965 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3966 break;
3967
3968 case BS3CG1ENC_MODRM_Mdq_WO_Vdq:
3969 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
3970 pThis->iRmOp = 0;
3971 pThis->iRegOp = 1;
3972 pThis->aOperands[0].cbOp = 16;
3973 pThis->aOperands[1].cbOp = 16;
3974 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
3975 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3976 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
3977 break;
3978
3979 case BS3CG1ENC_MODRM_Mq_WO_Pq:
3980 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Psomething;
3981 pThis->iRmOp = 0;
3982 pThis->iRegOp = 1;
3983 pThis->aOperands[0].cbOp = 8;
3984 pThis->aOperands[1].cbOp = 8;
3985 pThis->aOperands[1].idxFieldBase = BS3CG1DST_MM0;
3986 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
3987 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3988 break;
3989
3990 case BS3CG1ENC_MODRM_Mq_WO_Vq:
3991 case BS3CG1ENC_MODRM_Mq_WO_VqHi:
3992 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
3993 pThis->iRmOp = 0;
3994 pThis->iRegOp = 1;
3995 pThis->aOperands[0].cbOp = 8;
3996 pThis->aOperands[1].cbOp = 8;
3997 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
3998 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3999 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4000 pThis->aOperands[1].idxFieldBase = pThis->enmEncoding == BS3CG1ENC_MODRM_Mq_WO_Vq
4001 ? BS3CG1DST_XMM0_LO : BS3CG1DST_XMM0_HI;
4002 break;
4003
4004 case BS3CG1ENC_MODRM_Mps_WO_Vps:
4005 case BS3CG1ENC_MODRM_Mpd_WO_Vpd:
4006 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
4007 pThis->iRmOp = 0;
4008 pThis->iRegOp = 1;
4009 pThis->aOperands[0].cbOp = 16;
4010 pThis->aOperands[1].cbOp = 16;
4011 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
4012 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4013 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
4014 break;
4015
4016 case BS3CG1ENC_FIXED:
4017 pThis->pfnEncoder = Bs3Cg1EncodeNext_FIXED;
4018 break;
4019
4020 case BS3CG1ENC_FIXED_AL_Ib:
4021 pThis->pfnEncoder = Bs3Cg1EncodeNext_FIXED_AL_Ib;
4022 pThis->aOperands[0].cbOp = 1;
4023 pThis->aOperands[1].cbOp = 1;
4024 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
4025 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
4026 pThis->aOperands[0].idxField = BS3CG1DST_AL;
4027 pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
4028 break;
4029
4030 case BS3CG1ENC_FIXED_rAX_Iz:
4031 pThis->pfnEncoder = Bs3Cg1EncodeNext_FIXED_rAX_Iz;
4032 pThis->aOperands[0].cbOp = 2;
4033 pThis->aOperands[1].cbOp = 2;
4034 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
4035 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
4036 pThis->aOperands[0].idxField = BS3CG1DST_OZ_RAX;
4037 pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
4038 break;
4039
4040 /* Unused or invalid instructions mostly. */
4041 case BS3CG1ENC_MODRM_MOD_EQ_3:
4042 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_MOD_EQ_3;
4043 break;
4044 case BS3CG1ENC_MODRM_MOD_NE_3:
4045 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_MOD_NE_3;
4046 break;
4047
4048#ifdef BS3CG1_WITH_VEX
4049
4050 case BS3CG1ENC_VEX_MODRM_Vd_WO_Ed_WZ:
4051 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_Vd_WO_Ed_WZ;
4052 pThis->iRegOp = 0;
4053 pThis->iRmOp = 1;
4054 pThis->aOperands[0].cbOp = 4;
4055 pThis->aOperands[1].cbOp = 4;
4056 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_DW0_ZX;
4057 pThis->aOperands[1].idxFieldBase = BS3CG1DST_EAX;
4058 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4059 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4060 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
4061 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
4062 break;
4063
4064 case BS3CG1ENC_VEX_MODRM_Vq_WO_Eq_WNZ:
4065 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_Vq_WO_Eq_WNZ;
4066 pThis->iRegOp = 0;
4067 pThis->iRmOp = 1;
4068 pThis->aOperands[0].cbOp = 8;
4069 pThis->aOperands[1].cbOp = 8;
4070 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO_ZX;
4071 pThis->aOperands[1].idxFieldBase = BS3CG1DST_RAX;
4072 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4073 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4074 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
4075 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
4076 break;
4077
4078 case BS3CG1ENC_VEX_MODRM_Vps_WO_Wps:
4079 case BS3CG1ENC_VEX_MODRM_Vpd_WO_Wpd:
4080 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_OR_ViceVersa;
4081 pThis->iRegOp = 0;
4082 pThis->iRmOp = 1;
4083 pThis->aOperands[0].cbOp = 16;
4084 pThis->aOperands[1].cbOp = 16;
4085 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4086 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4087 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
4088 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
4089 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4090 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
4091 break;
4092
4093 case BS3CG1ENC_VEX_MODRM_VssZx_WO_Md:
4094 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa;
4095 pThis->iRmOp = 1;
4096 pThis->iRegOp = 0;
4097 pThis->aOperands[0].cbOp = 4;
4098 pThis->aOperands[1].cbOp = 4;
4099 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4100 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
4101 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_DW0;
4102 pThis->aOperands[1].idxFieldBase = BS3CG1DST_INVALID;
4103 break;
4104
4105 case BS3CG1ENC_VEX_MODRM_Vss_WO_HssHi_Uss:
4106 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa;
4107 pThis->iRegOp = 0;
4108 pThis->iRmOp = 2;
4109 pThis->aOperands[0].cbOp = 16;
4110 pThis->aOperands[1].cbOp = 12;
4111 pThis->aOperands[2].cbOp = 4;
4112 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4113 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4114 pThis->aOperands[2].enmLocation = BS3CG1OPLOC_CTX;
4115 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4116 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI96;
4117 pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_DW0;
4118 break;
4119
4120 case BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq:
4121 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa;
4122 pThis->iRmOp = 1;
4123 pThis->iRegOp = 0;
4124 pThis->aOperands[0].cbOp = 8;
4125 pThis->aOperands[1].cbOp = 8;
4126 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4127 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
4128 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO;
4129 pThis->aOperands[1].idxFieldBase = BS3CG1DST_INVALID;
4130 break;
4131
4132 case BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L0:
4133 BS3_ASSERT(!(pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO));
4134 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L0_OR_ViceVersa;
4135 pThis->iRegOp = 0;
4136 pThis->iRmOp = 1;
4137 pThis->aOperands[0].cbOp = 16;
4138 pThis->aOperands[1].cbOp = 16;
4139 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4140 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
4141 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4142 break;
4143
4144 case BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L1:
4145 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L1_OR_ViceVersa;
4146 pThis->iRegOp = 0;
4147 pThis->iRmOp = 1;
4148 pThis->aOperands[0].cbOp = 32;
4149 pThis->aOperands[1].cbOp = 32;
4150 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4151 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
4152 pThis->aOperands[0].idxFieldBase = BS3CG1DST_YMM0;
4153 break;
4154
4155 case BS3CG1ENC_VEX_MODRM_Vsd_WO_HsdHi_Usd:
4156 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa;
4157 pThis->iRegOp = 0;
4158 pThis->iRmOp = 2;
4159 pThis->aOperands[0].cbOp = 16;
4160 pThis->aOperands[1].cbOp = 8;
4161 pThis->aOperands[2].cbOp = 8;
4162 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4163 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4164 pThis->aOperands[2].enmLocation = BS3CG1OPLOC_CTX;
4165 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4166 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
4167 pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_LO;
4168 break;
4169
4170 case BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_UqHi:
4171 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Wip_OR_ViceVersa;
4172 pThis->iRegOp = 0;
4173 pThis->iRmOp = 2;
4174 pThis->aOperands[0].cbOp = 16;
4175 pThis->aOperands[1].cbOp = 8;
4176 pThis->aOperands[2].cbOp = 8;
4177 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4178 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4179 pThis->aOperands[2].enmLocation = BS3CG1OPLOC_CTX;
4180 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4181 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
4182 pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_HI;
4183 break;
4184
4185 case BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_Mq:
4186 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Msomething_Wip_OR_ViceVersa;
4187 pThis->iRegOp = 0;
4188 pThis->iRmOp = 2;
4189 pThis->aOperands[0].cbOp = 16;
4190 pThis->aOperands[1].cbOp = 8;
4191 pThis->aOperands[2].cbOp = 8;
4192 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4193 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4194 pThis->aOperands[2].enmLocation = BS3CG1OPLOC_MEM;
4195 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4196 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
4197 pThis->aOperands[2].idxFieldBase = BS3CG1DST_INVALID;
4198 break;
4199
4200 case BS3CG1ENC_VEX_MODRM_Vq_WO_Wq:
4201 BS3_ASSERT(pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO);
4202 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_Lmbz_OR_ViceVersa;
4203 pThis->iRegOp = 0;
4204 pThis->iRmOp = 1;
4205 pThis->aOperands[0].cbOp = 8;
4206 pThis->aOperands[1].cbOp = 8;
4207 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4208 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4209 pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
4210 pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
4211 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO;
4212 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
4213 break;
4214
4215 case BS3CG1ENC_VEX_MODRM_Vx_WO_Wx:
4216 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_OR_ViceVersa;
4217 pThis->iRegOp = 0;
4218 pThis->iRmOp = 1;
4219