VirtualBox

source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-apic-1-32.c32@ 103131

Last change on this file since 103131 was 98103, checked in by vboxsync, 21 months ago

Copyright year updates by scm.

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1/* $Id: bs3-apic-1-32.c32 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-apic-1, 32-bit C code.
4 */
5
6/*
7 * Copyright (C) 2022-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * The contents of this file may alternatively be used under the terms
26 * of the Common Development and Distribution License Version 1.0
27 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28 * in the VirtualBox distribution, in which case the provisions of the
29 * CDDL are applicable instead of those of the GPL.
30 *
31 * You may elect to license modified versions of this file under the
32 * terms and conditions of either the GPL or the CDDL or both.
33 *
34 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35 */
36
37
38/*********************************************************************************************************************************
39* Header Files *
40*********************************************************************************************************************************/
41#include <bs3kit.h>
42#include <iprt/asm-amd64-x86.h>
43#include <iprt/x86.h>
44#include <VBox/apic.h>
45
46
47static void printBitmap(const char BS3_FAR *pszName, uint32_t BS3_FAR volatile *pau32Bitmap)
48{
49 unsigned off;
50 Bs3TestPrintf("%s:", pszName);
51 for (off = 0; off < 0x80; off += 0x10)
52 {
53 uint32_t uVal = pau32Bitmap[off / sizeof(uint32_t)];
54 Bs3TestPrintf(off != 0 ? "'%08x" : "%08x", uVal);
55 }
56 Bs3TestPrintf("\n");
57}
58
59
60BS3_DECL(void) ProtModeApicTests(void)
61{
62 uint64_t uApicBase2, uApicBase;
63
64 Bs3TestSub("protected mode");
65 uApicBase = ASMRdMsr(MSR_IA32_APICBASE);
66
67 /* Disable the APIC (according to wiki.osdev.org/APIC, disabling the
68 APIC could require a CPU reset to re-enable it, but it works for us): */
69 ASMWrMsr(MSR_IA32_APICBASE, uApicBase & ~(uint64_t)MSR_IA32_APICBASE_EN);
70 uApicBase2 = ASMRdMsr(MSR_IA32_APICBASE);
71 if (uApicBase2 == (uApicBase & ~(uint64_t)MSR_IA32_APICBASE_EN))
72 Bs3TestPrintf("Disabling worked.\n");
73 else
74 Bs3TestFailedF("Disabling the APIC did not work (%#RX64)", uApicBase2);
75
76 /* Enabling the APIC: */
77 ASMWrMsr(MSR_IA32_APICBASE, uApicBase | MSR_IA32_APICBASE_EN);
78 uApicBase2 = ASMRdMsr(MSR_IA32_APICBASE);
79 if (uApicBase2 == (uApicBase | MSR_IA32_APICBASE_EN))
80 {
81 uint8_t BS3_FAR volatile * const pabApic = (uint8_t BS3_FAR volatile *)((uintptr_t)uApicBase & X86_PAGE_4K_BASE_MASK);
82 uint32_t BS3_FAR volatile * const pau32Apic = (uint32_t BS3_FAR volatile *)pabApic;
83 uint32_t i, uVal, uVal2;
84 Bs3TestPrintf("Enabling worked.\n");
85
86 /*
87 * Do some register reads and such.
88 */
89 uVal = pau32Apic[XAPIC_OFF_VERSION / sizeof(uint32_t)];
90 Bs3TestPrintf("APIC version: %#x\n", uVal);
91 if ( APIC_REG_VERSION_GET_VER(uVal) != XAPIC_HARDWARE_VERSION_P4
92 && APIC_REG_VERSION_GET_VER(uVal) != XAPIC_HARDWARE_VERSION_P6)
93 Bs3TestFailedF("Unexpected APIC version: %#x (%#x)", APIC_REG_VERSION_GET_VER(uVal), uVal);
94
95 Bs3TestPrintf("APIC ID: %#x\n", pau32Apic[XAPIC_OFF_ID / sizeof(uint32_t)]);
96
97 Bs3TestPrintf("TPR: %#x\n", pau32Apic[XAPIC_OFF_TPR / sizeof(uint32_t)]);
98 for (i = 0; i < 5; i++)
99 {
100 Bs3TestPrintf("TPR write test iteration #%u\n", i + 1);
101 uVal = 256;
102 while (uVal-- > 0)
103 {
104 pau32Apic[XAPIC_OFF_TPR / sizeof(uint32_t)] = uVal;
105 uVal2 = pau32Apic[XAPIC_OFF_TPR / sizeof(uint32_t)];
106 if (uVal2 != uVal)
107 Bs3TestFailedF("Setting TPR to %#x failed, read back %#x", uVal, uVal2);
108 }
109 }
110 Bs3TestPrintf("APR: %#x\n", pau32Apic[XAPIC_OFF_APR / sizeof(uint32_t)]);
111 Bs3TestPrintf("PPR: %#x\n", pau32Apic[XAPIC_OFF_PPR / sizeof(uint32_t)]);
112 printBitmap("ISR", &pau32Apic[XAPIC_OFF_ISR0 / sizeof(uint32_t)]);
113 printBitmap("TMR", &pau32Apic[XAPIC_OFF_TMR0 / sizeof(uint32_t)]);
114 printBitmap("IRR", &pau32Apic[XAPIC_OFF_IRR0 / sizeof(uint32_t)]);
115 }
116 else
117 Bs3TestFailedF("Enabling the APIC did not work (%#RX64)", uApicBase2);
118}
119
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