VirtualBox

source: vbox/trunk/src/VBox/VMM/tools/VBoxCpuReport.cpp@ 84044

Last change on this file since 84044 was 82969, checked in by vboxsync, 4 years ago

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1/* $Id: VBoxCpuReport.cpp 82969 2020-02-04 10:54:12Z vboxsync $ */
2/** @file
3 * VBoxCpuReport - Produces the basis for a CPU DB entry.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#include <iprt/asm.h>
23#include <iprt/asm-amd64-x86.h>
24#include <iprt/buildconfig.h>
25#include <iprt/ctype.h>
26#include <iprt/file.h>
27#include <iprt/getopt.h>
28#include <iprt/initterm.h>
29#include <iprt/message.h>
30#include <iprt/mem.h>
31#include <iprt/path.h>
32#include <iprt/string.h>
33#include <iprt/stream.h>
34#include <iprt/symlink.h>
35#include <iprt/thread.h>
36#include <iprt/time.h>
37
38#include <VBox/err.h>
39#include <VBox/vmm/cpum.h>
40#include <VBox/sup.h>
41
42#include "VBoxCpuReport.h"
43
44
45/*********************************************************************************************************************************
46* Structures and Typedefs *
47*********************************************************************************************************************************/
48/** Write only register. */
49#define VBCPUREPMSR_F_WRITE_ONLY RT_BIT(0)
50
51typedef struct VBCPUREPMSR
52{
53 /** The first MSR register number. */
54 uint32_t uMsr;
55 /** Flags (MSRREPORT_F_XXX). */
56 uint32_t fFlags;
57 /** The value we read, unless write-only. */
58 uint64_t uValue;
59} VBCPUREPMSR;
60
61
62/*********************************************************************************************************************************
63* Global Variables *
64*********************************************************************************************************************************/
65/** The CPU vendor. Used by the MSR code. */
66static CPUMCPUVENDOR g_enmVendor = CPUMCPUVENDOR_INVALID;
67/** The CPU microarchitecture. Used by the MSR code. */
68static CPUMMICROARCH g_enmMicroarch = kCpumMicroarch_Invalid;
69/** Set if g_enmMicroarch indicates an Intel NetBurst CPU. */
70static bool g_fIntelNetBurst = false;
71/** The alternative report stream. */
72static PRTSTREAM g_pReportOut;
73/** The alternative debug stream. */
74static PRTSTREAM g_pDebugOut;
75/** Whether to skip MSR collection. */
76static bool g_fNoMsrs = false;
77
78/** Snooping info storage for vbCpuRepGuessScalableBusFrequencyName. */
79static uint64_t g_uMsrIntelP6FsbFrequency = UINT64_MAX;
80
81/** The MSR accessors interface. */
82static VBCPUREPMSRACCESSORS g_MsrAcc;
83
84
85
86void vbCpuRepDebug(const char *pszMsg, ...)
87{
88 va_list va;
89
90 /* Always print a copy of the report to standard error. */
91 va_start(va, pszMsg);
92 RTStrmPrintfV(g_pStdErr, pszMsg, va);
93 va_end(va);
94 RTStrmFlush(g_pStdErr);
95
96 /* Alternatively, also print to a log file. */
97 if (g_pDebugOut)
98 {
99 va_start(va, pszMsg);
100 RTStrmPrintfV(g_pDebugOut, pszMsg, va);
101 va_end(va);
102 RTStrmFlush(g_pDebugOut);
103 }
104
105 /* Give the output device a chance to write / display it. */
106 RTThreadSleep(1);
107}
108
109
110void vbCpuRepPrintf(const char *pszMsg, ...)
111{
112 va_list va;
113
114 /* Output to report file, if requested. */
115 if (g_pReportOut)
116 {
117 va_start(va, pszMsg);
118 RTStrmPrintfV(g_pReportOut, pszMsg, va);
119 va_end(va);
120 RTStrmFlush(g_pReportOut);
121 }
122
123 /* Always print a copy of the report to standard out. */
124 va_start(va, pszMsg);
125 RTStrmPrintfV(g_pStdOut, pszMsg, va);
126 va_end(va);
127 RTStrmFlush(g_pStdOut);
128}
129
130
131
132static int vbCpuRepMsrsAddOne(VBCPUREPMSR **ppaMsrs, uint32_t *pcMsrs,
133 uint32_t uMsr, uint64_t uValue, uint32_t fFlags)
134{
135 /*
136 * Grow the array?
137 */
138 uint32_t cMsrs = *pcMsrs;
139 if ((cMsrs % 64) == 0)
140 {
141 void *pvNew = RTMemRealloc(*ppaMsrs, (cMsrs + 64) * sizeof(**ppaMsrs));
142 if (!pvNew)
143 {
144 RTMemFree(*ppaMsrs);
145 *ppaMsrs = NULL;
146 *pcMsrs = 0;
147 return VERR_NO_MEMORY;
148 }
149 *ppaMsrs = (VBCPUREPMSR *)pvNew;
150 }
151
152 /*
153 * Add it.
154 */
155 VBCPUREPMSR *pEntry = *ppaMsrs + cMsrs;
156 pEntry->uMsr = uMsr;
157 pEntry->fFlags = fFlags;
158 pEntry->uValue = uValue;
159 *pcMsrs = cMsrs + 1;
160
161 return VINF_SUCCESS;
162}
163
164
165/**
166 * Returns the max physical address width as a number of bits.
167 *
168 * @returns Bit count.
169 */
170static uint8_t vbCpuRepGetPhysAddrWidth(void)
171{
172 uint8_t cMaxWidth;
173 if (!ASMHasCpuId())
174 cMaxWidth = 32;
175 else
176 {
177 uint32_t cMaxExt = ASMCpuId_EAX(0x80000000);
178 if (ASMIsValidExtRange(cMaxExt)&& cMaxExt >= 0x80000008)
179 cMaxWidth = ASMCpuId_EAX(0x80000008) & 0xff;
180 else if ( ASMIsValidStdRange(ASMCpuId_EAX(0))
181 && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PSE36))
182 cMaxWidth = 36;
183 else
184 cMaxWidth = 32;
185 }
186 return cMaxWidth;
187}
188
189
190static bool vbCpuRepSupportsPae(void)
191{
192 return ASMHasCpuId()
193 && ASMIsValidStdRange(ASMCpuId_EAX(0))
194 && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE);
195}
196
197
198static bool vbCpuRepSupportsLongMode(void)
199{
200 return ASMHasCpuId()
201 && ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))
202 && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
203}
204
205
206static bool vbCpuRepSupportsNX(void)
207{
208 return ASMHasCpuId()
209 && ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))
210 && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX);
211}
212
213
214static bool vbCpuRepSupportsX2Apic(void)
215{
216 return ASMHasCpuId()
217 && ASMIsValidStdRange(ASMCpuId_EAX(0))
218 && (ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_X2APIC);
219}
220
221
222
223#if 0 /* unused */
224static bool msrProberWrite(uint32_t uMsr, uint64_t uValue)
225{
226 bool fGp;
227 int rc = g_MsrAcc.pfnMsrWrite(uMsr, NIL_RTCPUID, uValue, &fGp);
228 AssertRC(rc);
229 return RT_SUCCESS(rc) && !fGp;
230}
231#endif
232
233
234static bool msrProberRead(uint32_t uMsr, uint64_t *puValue)
235{
236 *puValue = 0;
237 bool fGp;
238 int rc = g_MsrAcc.pfnMsrProberRead(uMsr, NIL_RTCPUID, puValue, &fGp);
239 AssertRC(rc);
240 return RT_SUCCESS(rc) && !fGp;
241}
242
243
244/** Tries to modify the register by writing the original value to it. */
245static bool msrProberModifyNoChange(uint32_t uMsr)
246{
247 SUPMSRPROBERMODIFYRESULT Result;
248 int rc = g_MsrAcc.pfnMsrProberModify(uMsr, NIL_RTCPUID, UINT64_MAX, 0, &Result);
249 return RT_SUCCESS(rc)
250 && !Result.fBeforeGp
251 && !Result.fModifyGp
252 && !Result.fAfterGp
253 && !Result.fRestoreGp;
254}
255
256
257/** Tries to modify the register by writing zero to it. */
258static bool msrProberModifyZero(uint32_t uMsr)
259{
260 SUPMSRPROBERMODIFYRESULT Result;
261 int rc = g_MsrAcc.pfnMsrProberModify(uMsr, NIL_RTCPUID, 0, 0, &Result);
262 return RT_SUCCESS(rc)
263 && !Result.fBeforeGp
264 && !Result.fModifyGp
265 && !Result.fAfterGp
266 && !Result.fRestoreGp;
267}
268
269
270/**
271 * Tries to modify each bit in the MSR and see if we can make it change.
272 *
273 * @returns VBox status code.
274 * @param uMsr The MSR.
275 * @param pfIgnMask The ignore mask to update.
276 * @param pfGpMask The GP mask to update.
277 * @param fSkipMask Mask of bits to skip.
278 */
279static int msrProberModifyBitChanges(uint32_t uMsr, uint64_t *pfIgnMask, uint64_t *pfGpMask, uint64_t fSkipMask)
280{
281 for (unsigned iBit = 0; iBit < 64; iBit++)
282 {
283 uint64_t fBitMask = RT_BIT_64(iBit);
284 if (fBitMask & fSkipMask)
285 continue;
286
287 /* Set it. */
288 SUPMSRPROBERMODIFYRESULT ResultSet;
289 int rc = g_MsrAcc.pfnMsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
290 if (RT_FAILURE(rc))
291 return RTMsgErrorRc(rc, "pfnMsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
292
293 /* Clear it. */
294 SUPMSRPROBERMODIFYRESULT ResultClear;
295 rc = g_MsrAcc.pfnMsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
296 if (RT_FAILURE(rc))
297 return RTMsgErrorRc(rc, "pfnMsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
298
299 if (ResultSet.fModifyGp || ResultClear.fModifyGp)
300 *pfGpMask |= fBitMask;
301 else if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) == 0
302 && !ResultSet.fBeforeGp
303 && !ResultSet.fAfterGp)
304 && ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) == 0
305 && !ResultClear.fBeforeGp
306 && !ResultClear.fAfterGp) )
307 *pfIgnMask |= fBitMask;
308 }
309
310 return VINF_SUCCESS;
311}
312
313
314#if 0 /* currently unused */
315/**
316 * Tries to modify one bit.
317 *
318 * @retval -2 on API error.
319 * @retval -1 on \#GP.
320 * @retval 0 if ignored.
321 * @retval 1 if it changed.
322 *
323 * @param uMsr The MSR.
324 * @param iBit The bit to try modify.
325 */
326static int msrProberModifyBit(uint32_t uMsr, unsigned iBit)
327{
328 uint64_t fBitMask = RT_BIT_64(iBit);
329
330 /* Set it. */
331 SUPMSRPROBERMODIFYRESULT ResultSet;
332 int rc = g_MsrAcc.pfnMsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
333 if (RT_FAILURE(rc))
334 return RTMsgErrorRc(-2, "pfnMsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
335
336 /* Clear it. */
337 SUPMSRPROBERMODIFYRESULT ResultClear;
338 rc = g_MsrAcc.pfnMsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
339 if (RT_FAILURE(rc))
340 return RTMsgErrorRc(-2, "pfnMsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
341
342 if (ResultSet.fModifyGp || ResultClear.fModifyGp)
343 return -1;
344
345 if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) != 0
346 && !ResultSet.fBeforeGp
347 && !ResultSet.fAfterGp)
348 || ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) != 0
349 && !ResultClear.fBeforeGp
350 && !ResultClear.fAfterGp) )
351 return 1;
352
353 return 0;
354}
355#endif
356
357
358/**
359 * Tries to do a simple AND+OR change and see if we \#GP or not.
360 *
361 * @retval @c true if successfully modified.
362 * @retval @c false if \#GP or other error.
363 *
364 * @param uMsr The MSR.
365 * @param fAndMask The AND mask.
366 * @param fOrMask The OR mask.
367 */
368static bool msrProberModifySimpleGp(uint32_t uMsr, uint64_t fAndMask, uint64_t fOrMask)
369{
370 SUPMSRPROBERMODIFYRESULT Result;
371 int rc = g_MsrAcc.pfnMsrProberModify(uMsr, NIL_RTCPUID, fAndMask, fOrMask, &Result);
372 if (RT_FAILURE(rc))
373 {
374 RTMsgError("g_MsrAcc.pfnMsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, fAndMask, fOrMask, rc);
375 return false;
376 }
377 return !Result.fBeforeGp
378 && !Result.fModifyGp
379 && !Result.fAfterGp
380 && !Result.fRestoreGp;
381}
382
383
384
385
386/**
387 * Combination of the basic tests.
388 *
389 * @returns VBox status code.
390 * @param uMsr The MSR.
391 * @param fSkipMask Mask of bits to skip.
392 * @param pfReadOnly Where to return read-only status.
393 * @param pfIgnMask Where to return the write ignore mask. Need not
394 * be initialized.
395 * @param pfGpMask Where to return the write GP mask. Need not
396 * be initialized.
397 */
398static int msrProberModifyBasicTests(uint32_t uMsr, uint64_t fSkipMask, bool *pfReadOnly, uint64_t *pfIgnMask, uint64_t *pfGpMask)
399{
400 if (msrProberModifyNoChange(uMsr))
401 {
402 *pfReadOnly = false;
403 *pfIgnMask = 0;
404 *pfGpMask = 0;
405 return msrProberModifyBitChanges(uMsr, pfIgnMask, pfGpMask, fSkipMask);
406 }
407
408 *pfReadOnly = true;
409 *pfIgnMask = 0;
410 *pfGpMask = UINT64_MAX;
411 return VINF_SUCCESS;
412}
413
414
415
416/**
417 * Determines for the MSR AND mask.
418 *
419 * Older CPUs doesn't necessiarly implement all bits of the MSR register number.
420 * So, we have to approximate how many are used so we don't get an overly large
421 * and confusing set of MSRs when probing.
422 *
423 * @returns The mask.
424 */
425static uint32_t determineMsrAndMask(void)
426{
427#define VBCPUREP_MASK_TEST_MSRS 7
428 static uint32_t const s_aMsrs[VBCPUREP_MASK_TEST_MSRS] =
429 {
430 /* Try a bunch of mostly read only registers: */
431 MSR_P5_MC_TYPE, MSR_IA32_PLATFORM_ID, MSR_IA32_MTRR_CAP, MSR_IA32_MCG_CAP, MSR_IA32_CR_PAT,
432 /* Then some which aren't supposed to be present on any CPU: */
433 0x00000015, 0x00000019,
434 };
435
436 /* Get the base values. */
437 uint64_t auBaseValues[VBCPUREP_MASK_TEST_MSRS];
438 for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
439 {
440 if (!msrProberRead(s_aMsrs[i], &auBaseValues[i]))
441 auBaseValues[i] = UINT64_MAX;
442 //vbCpuRepDebug("Base: %#x -> %#llx\n", s_aMsrs[i], auBaseValues[i]);
443 }
444
445 /* Do the probing. */
446 unsigned iBit;
447 for (iBit = 31; iBit > 8; iBit--)
448 {
449 uint64_t fMsrOrMask = RT_BIT_64(iBit);
450 for (unsigned iTest = 0; iTest <= 64 && fMsrOrMask < UINT32_MAX; iTest++)
451 {
452 for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
453 {
454 uint64_t uValue;
455 if (!msrProberRead(s_aMsrs[i] | fMsrOrMask, &uValue))
456 uValue = UINT64_MAX;
457 if (uValue != auBaseValues[i])
458 {
459 uint32_t fMsrMask = iBit >= 31 ? UINT32_MAX : RT_BIT_32(iBit + 1) - 1;
460 vbCpuRepDebug("MSR AND mask: quit on iBit=%u uMsr=%#x (%#x) %llx != %llx => fMsrMask=%#x\n",
461 iBit, s_aMsrs[i] | (uint32_t)fMsrOrMask, s_aMsrs[i], uValue, auBaseValues[i], fMsrMask);
462 return fMsrMask;
463 }
464 }
465
466 /* Advance. */
467 if (iBit <= 6)
468 fMsrOrMask += RT_BIT_64(iBit);
469 else if (iBit <= 11)
470 fMsrOrMask += RT_BIT_64(iBit) * 33;
471 else if (iBit <= 16)
472 fMsrOrMask += RT_BIT_64(iBit) * 1025;
473 else if (iBit <= 22)
474 fMsrOrMask += RT_BIT_64(iBit) * 65537;
475 else
476 fMsrOrMask += RT_BIT_64(iBit) * 262145;
477 }
478 }
479
480 uint32_t fMsrMask = RT_BIT_32(iBit + 1) - 1;
481 vbCpuRepDebug("MSR AND mask: less that %u bits that matters?!? => fMsrMask=%#x\n", iBit + 1, fMsrMask);
482 return fMsrMask;
483}
484
485
486static int findMsrs(VBCPUREPMSR **ppaMsrs, uint32_t *pcMsrs, uint32_t fMsrMask)
487{
488 /*
489 * Gather them.
490 */
491 static struct { uint32_t uFirst, cMsrs; } const s_aRanges[] =
492 {
493 { 0x00000000, 0x00042000 },
494 { 0x10000000, 0x00001000 },
495 { 0x20000000, 0x00001000 },
496 { 0x40000000, 0x00012000 },
497 { 0x80000000, 0x00012000 },
498 { 0xc0000000, 0x00022000 }, /* Had some trouble here on solaris with the tstVMM setup. */
499 };
500
501 *pcMsrs = 0;
502 *ppaMsrs = NULL;
503
504 for (unsigned i = 0; i < RT_ELEMENTS(s_aRanges); i++)
505 {
506 uint32_t uMsr = s_aRanges[i].uFirst;
507 if ((uMsr & fMsrMask) != uMsr)
508 continue;
509 uint32_t cLeft = s_aRanges[i].cMsrs;
510 while (cLeft-- > 0 && (uMsr & fMsrMask) == uMsr)
511 {
512 if ((uMsr & 0xfff) == 0)
513 {
514 vbCpuRepDebug("testing %#x...\n", uMsr);
515 RTThreadSleep(22);
516 }
517#if 0
518 else if (uMsr >= 0x00003170 && uMsr <= 0xc0000090)
519 {
520 vbCpuRepDebug("testing %#x...\n", uMsr);
521 RTThreadSleep(250);
522 }
523#endif
524 /* Skip 0xc0011012..13 as it seems to be bad for our health (Phenom II X6 1100T). */
525 /* Ditto for 0x0000002a (EBL_CR_POWERON) and 0x00000277 (MSR_IA32_CR_PAT) on Intel (Atom 330). */
526 /* And more of the same for 0x280 on Intel Pentium III. */
527 if ( ((uMsr >= 0xc0011012 && uMsr <= 0xc0011013) && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
528 || ( (uMsr == 0x2a || uMsr == 0x277)
529 && g_enmVendor == CPUMCPUVENDOR_INTEL
530 && g_enmMicroarch == kCpumMicroarch_Intel_Atom_Bonnell)
531 || ( (uMsr == 0x280)
532 && g_enmMicroarch == kCpumMicroarch_Intel_P6_III))
533 vbCpuRepDebug("Skipping %#x\n", uMsr);
534 else
535 {
536 /* Read probing normally does it. */
537 uint64_t uValue = 0;
538 bool fGp = true;
539 int rc = g_MsrAcc.pfnMsrProberRead(uMsr, NIL_RTCPUID, &uValue, &fGp);
540 if (RT_FAILURE(rc))
541 {
542 RTMemFree(*ppaMsrs);
543 *ppaMsrs = NULL;
544 return RTMsgErrorRc(rc, "pfnMsrProberRead failed on %#x: %Rrc\n", uMsr, rc);
545 }
546
547 uint32_t fFlags;
548 if (!fGp)
549 fFlags = 0;
550 /* VIA/Shanghai HACK - writing to 0x0000317e on a quad core make the core unresponsive. */
551 else if (uMsr == 0x0000317e && (g_enmVendor == CPUMCPUVENDOR_VIA || g_enmVendor == CPUMCPUVENDOR_SHANGHAI))
552 {
553 uValue = 0;
554 fFlags = VBCPUREPMSR_F_WRITE_ONLY;
555 fGp = *pcMsrs == 0
556 || (*ppaMsrs)[*pcMsrs - 1].uMsr != 0x0000317d
557 || (*ppaMsrs)[*pcMsrs - 1].fFlags != VBCPUREPMSR_F_WRITE_ONLY;
558 }
559 else
560 {
561 /* Is it a write only register? */
562#if 0
563 if (uMsr >= 0x00003170 && uMsr <= 0xc0000090)
564 {
565 vbCpuRepDebug("test writing %#x...\n", uMsr);
566 RTThreadSleep(250);
567 }
568#endif
569 fGp = true;
570 rc = g_MsrAcc.pfnMsrProberWrite(uMsr, NIL_RTCPUID, 0, &fGp);
571 if (RT_FAILURE(rc))
572 {
573 RTMemFree(*ppaMsrs);
574 *ppaMsrs = NULL;
575 return RTMsgErrorRc(rc, "pfnMsrProberWrite failed on %#x: %Rrc\n", uMsr, rc);
576 }
577 uValue = 0;
578 fFlags = VBCPUREPMSR_F_WRITE_ONLY;
579
580 /*
581 * Tweaks. On Intel CPUs we've got trouble detecting
582 * IA32_BIOS_UPDT_TRIG (0x00000079), so we have to add it manually here.
583 * Ditto on AMD with PATCH_LOADER (0xc0010020).
584 */
585 if ( uMsr == 0x00000079
586 && fGp
587 && g_enmMicroarch >= kCpumMicroarch_Intel_P6_Core_Atom_First
588 && g_enmMicroarch <= kCpumMicroarch_Intel_End)
589 fGp = false;
590 if ( uMsr == 0xc0010020
591 && fGp
592 && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First
593 && g_enmMicroarch <= kCpumMicroarch_AMD_End)
594 fGp = false;
595 }
596
597 if (!fGp)
598 {
599 /* Add it. */
600 rc = vbCpuRepMsrsAddOne(ppaMsrs, pcMsrs, uMsr, uValue, fFlags);
601 if (RT_FAILURE(rc))
602 return RTMsgErrorRc(rc, "Out of memory (uMsr=%#x).\n", uMsr);
603 if ( (g_enmVendor != CPUMCPUVENDOR_VIA && g_enmVendor != CPUMCPUVENDOR_SHANGHAI)
604 || uValue
605 || fFlags)
606 vbCpuRepDebug("%#010x: uValue=%#llx fFlags=%#x\n", uMsr, uValue, fFlags);
607 }
608 }
609
610 uMsr++;
611 }
612 }
613
614 return VINF_SUCCESS;
615}
616
617/**
618 * Get the name of the specified MSR, if we know it and can handle it.
619 *
620 * Do _NOT_ add any new names here without ALSO at the SAME TIME making sure it
621 * is handled correctly by the PROBING CODE and REPORTED correctly!!
622 *
623 * @returns Pointer to name if handled, NULL if not yet explored.
624 * @param uMsr The MSR in question.
625 */
626static const char *getMsrNameHandled(uint32_t uMsr)
627{
628 /** @todo figure out where NCU_EVENT_CORE_MASK might be... */
629 switch (uMsr)
630 {
631 case 0x00000000: return "IA32_P5_MC_ADDR";
632 case 0x00000001: return "IA32_P5_MC_TYPE";
633 case 0x00000006:
634 if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
635 return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
636 return "IA32_MONITOR_FILTER_LINE_SIZE";
637 //case 0x0000000e: return "P?_TR12"; /* K6-III docs */
638 case 0x00000010: return "IA32_TIME_STAMP_COUNTER";
639 case 0x00000017: return "IA32_PLATFORM_ID";
640 case 0x00000018: return "P6_UNK_0000_0018"; /* P6_M_Dothan. */
641 case 0x0000001b: return "IA32_APIC_BASE";
642 case 0x00000021: return "C2_UNK_0000_0021"; /* Core2_Penryn */
643 case 0x0000002a: return g_fIntelNetBurst ? "P4_EBC_HARD_POWERON" : "EBL_CR_POWERON";
644 case 0x0000002b: return g_fIntelNetBurst ? "P4_EBC_SOFT_POWERON" : NULL;
645 case 0x0000002c: return g_fIntelNetBurst ? "P4_EBC_FREQUENCY_ID" : NULL;
646 case 0x0000002e: return "I7_UNK_0000_002e"; /* SandyBridge, IvyBridge. */
647 case 0x0000002f: return "P6_UNK_0000_002f"; /* P6_M_Dothan. */
648 case 0x00000032: return "P6_UNK_0000_0032"; /* P6_M_Dothan. */
649 case 0x00000033: return "TEST_CTL";
650 case 0x00000034: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch)
651 || CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(g_enmMicroarch)
652 ? "MSR_SMI_COUNT" : "P6_UNK_0000_0034"; /* P6_M_Dothan. */
653 case 0x00000035: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "MSR_CORE_THREAD_COUNT" : "P6_UNK_0000_0035"; /* P6_M_Dothan. */
654 case 0x00000036: return "I7_UNK_0000_0036"; /* SandyBridge, IvyBridge. */
655 case 0x00000039: return "C2_UNK_0000_0039"; /* Core2_Penryn */
656 case 0x0000003a: return "IA32_FEATURE_CONTROL";
657 case 0x0000003b: return "P6_UNK_0000_003b"; /* P6_M_Dothan. */
658 case 0x0000003e: return "I7_UNK_0000_003e"; /* SandyBridge, IvyBridge. */
659 case 0x0000003f: return "P6_UNK_0000_003f"; /* P6_M_Dothan. */
660 case 0x00000040: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_0_FROM_IP" : "MSR_LASTBRANCH_0";
661 case 0x00000041: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_1_FROM_IP" : "MSR_LASTBRANCH_1";
662 case 0x00000042: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_2_FROM_IP" : "MSR_LASTBRANCH_2";
663 case 0x00000043: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_3_FROM_IP" : "MSR_LASTBRANCH_3";
664 case 0x00000044: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_4_FROM_IP" : "MSR_LASTBRANCH_4";
665 case 0x00000045: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_5_FROM_IP" : "MSR_LASTBRANCH_5";
666 case 0x00000046: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_6_FROM_IP" : "MSR_LASTBRANCH_6";
667 case 0x00000047: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_7_FROM_IP" : "MSR_LASTBRANCH_7";
668 case 0x00000048: return "MSR_LASTBRANCH_8"; /*??*/
669 case 0x00000049: return "MSR_LASTBRANCH_9"; /*??*/
670 case 0x0000004a: return "P6_UNK_0000_004a"; /* P6_M_Dothan. */
671 case 0x0000004b: return "P6_UNK_0000_004b"; /* P6_M_Dothan. */
672 case 0x0000004c: return "P6_UNK_0000_004c"; /* P6_M_Dothan. */
673 case 0x0000004d: return "P6_UNK_0000_004d"; /* P6_M_Dothan. */
674 case 0x0000004e: return "P6_UNK_0000_004e"; /* P6_M_Dothan. */
675 case 0x0000004f: return "P6_UNK_0000_004f"; /* P6_M_Dothan. */
676 case 0x00000050: return "P6_UNK_0000_0050"; /* P6_M_Dothan. */
677 case 0x00000051: return "P6_UNK_0000_0051"; /* P6_M_Dothan. */
678 case 0x00000052: return "P6_UNK_0000_0052"; /* P6_M_Dothan. */
679 case 0x00000053: return "P6_UNK_0000_0053"; /* P6_M_Dothan. */
680 case 0x00000054: return "P6_UNK_0000_0054"; /* P6_M_Dothan. */
681 case 0x00000060: return "MSR_LASTBRANCH_0_TO_IP"; /* Core2_Penryn */
682 case 0x00000061: return "MSR_LASTBRANCH_1_TO_IP"; /* Core2_Penryn */
683 case 0x00000062: return "MSR_LASTBRANCH_2_TO_IP"; /* Core2_Penryn */
684 case 0x00000063: return "MSR_LASTBRANCH_3_TO_IP"; /* Core2_Penryn */
685 case 0x00000064: return "MSR_LASTBRANCH_4_TO_IP"; /* Atom? */
686 case 0x00000065: return "MSR_LASTBRANCH_5_TO_IP";
687 case 0x00000066: return "MSR_LASTBRANCH_6_TO_IP";
688 case 0x00000067: return "MSR_LASTBRANCH_7_TO_IP";
689 case 0x0000006c: return "P6_UNK_0000_006c"; /* P6_M_Dothan. */
690 case 0x0000006d: return "P6_UNK_0000_006d"; /* P6_M_Dothan. */
691 case 0x0000006e: return "P6_UNK_0000_006e"; /* P6_M_Dothan. */
692 case 0x0000006f: return "P6_UNK_0000_006f"; /* P6_M_Dothan. */
693 case 0x00000079: return "IA32_BIOS_UPDT_TRIG";
694 case 0x00000080: return "P4_UNK_0000_0080";
695 case 0x00000088: return "BBL_CR_D0";
696 case 0x00000089: return "BBL_CR_D1";
697 case 0x0000008a: return "BBL_CR_D2";
698 case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON ? "AMD_K8_PATCH_LEVEL"
699 : g_fIntelNetBurst ? "IA32_BIOS_SIGN_ID" : "BBL_CR_D3|BIOS_SIGN";
700 case 0x0000008c: return "P6_UNK_0000_008c"; /* P6_M_Dothan. */
701 case 0x0000008d: return "P6_UNK_0000_008d"; /* P6_M_Dothan. */
702 case 0x0000008e: return "P6_UNK_0000_008e"; /* P6_M_Dothan. */
703 case 0x0000008f: return "P6_UNK_0000_008f"; /* P6_M_Dothan. */
704 case 0x00000090: return "P6_UNK_0000_0090"; /* P6_M_Dothan. */
705 case 0x0000009b: return "IA32_SMM_MONITOR_CTL";
706 case 0x000000a8: return "C2_EMTTM_CR_TABLES_0";
707 case 0x000000a9: return "C2_EMTTM_CR_TABLES_1";
708 case 0x000000aa: return "C2_EMTTM_CR_TABLES_2";
709 case 0x000000ab: return "C2_EMTTM_CR_TABLES_3";
710 case 0x000000ac: return "C2_EMTTM_CR_TABLES_4";
711 case 0x000000ad: return "C2_EMTTM_CR_TABLES_5";
712 case 0x000000ae: return "P6_UNK_0000_00ae"; /* P6_M_Dothan. */
713 case 0x000000c1: return "IA32_PMC0";
714 case 0x000000c2: return "IA32_PMC1";
715 case 0x000000c3: return "IA32_PMC2";
716 case 0x000000c4: return "IA32_PMC3";
717 /* PMC4+ first seen on SandyBridge. The earlier cut off is just to be
718 on the safe side as we must avoid P6_M_Dothan and possibly others. */
719 case 0x000000c5: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC4" : NULL;
720 case 0x000000c6: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC5" : NULL;
721 case 0x000000c7: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC6" : "P6_UNK_0000_00c7"; /* P6_M_Dothan. */
722 case 0x000000c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC7" : NULL;
723 case 0x000000cd: return "MSR_FSB_FREQ"; /* P6_M_Dothan. */
724 case 0x000000ce: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PLATFORM_INFO" : "P6_UNK_0000_00ce"; /* P6_M_Dothan. */
725 case 0x000000cf: return "C2_UNK_0000_00cf"; /* Core2_Penryn. */
726 case 0x000000e0: return "C2_UNK_0000_00e0"; /* Core2_Penryn. */
727 case 0x000000e1: return "C2_UNK_0000_00e1"; /* Core2_Penryn. */
728 case 0x000000e2: return "MSR_PKG_CST_CONFIG_CONTROL";
729 case 0x000000e3: return "C2_SMM_CST_MISC_INFO"; /* Core2_Penryn. */
730 case 0x000000e4: return "MSR_PMG_IO_CAPTURE_BASE";
731 case 0x000000e5: return "C2_UNK_0000_00e5"; /* Core2_Penryn. */
732 case 0x000000e7: return "IA32_MPERF";
733 case 0x000000e8: return "IA32_APERF";
734 case 0x000000ee: return "C1_EXT_CONFIG"; /* Core2_Penryn. msrtool lists it for Core1 as well. */
735 case 0x000000fe: return "IA32_MTRRCAP";
736 case 0x00000102: return "I7_IB_UNK_0000_0102"; /* IvyBridge. */
737 case 0x00000103: return "I7_IB_UNK_0000_0103"; /* IvyBridge. */
738 case 0x00000104: return "I7_IB_UNK_0000_0104"; /* IvyBridge. */
739 case 0x00000116: return "BBL_CR_ADDR";
740 case 0x00000118: return "BBL_CR_DECC";
741 case 0x00000119: return "BBL_CR_CTL";
742 case 0x0000011a: return "BBL_CR_TRIG";
743 case 0x0000011b: return "P6_UNK_0000_011b"; /* P6_M_Dothan. */
744 case 0x0000011c: return "C2_UNK_0000_011c"; /* Core2_Penryn. */
745 case 0x0000011e: return "BBL_CR_CTL3";
746 case 0x00000120: return "SILV_UNK_0000_0120"; /* Silvermont */
747 case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
748 || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
749 ? "CPUID1_FEATURE_MASK" : NULL;
750 case 0x00000131: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
751 || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
752 ? "CPUID80000001_FEATURE_MASK" : "P6_UNK_0000_0131" /* P6_M_Dothan. */;
753 case 0x00000132: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
754 ? "CPUID1_FEATURE_MASK" : NULL;
755 case 0x00000133: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
756 ? "CPUIDD_01_FEATURE_MASK" : NULL;
757 case 0x00000134: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
758 ? "CPUID80000001_FEATURE_MASK" : NULL;
759 case 0x0000013c: return "I7_SB_AES_NI_CTL"; /* SandyBridge. Bit 0 is lock bit, bit 1 disables AES-NI. */
760 case 0x00000140: return "I7_IB_UNK_0000_0140"; /* IvyBridge. */
761 case 0x00000142: return "I7_IB_UNK_0000_0142"; /* IvyBridge. */
762 case 0x0000014e: return "P6_UNK_0000_014e"; /* P6_M_Dothan. */
763 case 0x0000014f: return "P6_UNK_0000_014f"; /* P6_M_Dothan. */
764 case 0x00000150: return "P6_UNK_0000_0150"; /* P6_M_Dothan. */
765 case 0x00000151: return "P6_UNK_0000_0151"; /* P6_M_Dothan. */
766 case 0x00000154: return "P6_UNK_0000_0154"; /* P6_M_Dothan. */
767 case 0x0000015b: return "P6_UNK_0000_015b"; /* P6_M_Dothan. */
768 case 0x0000015e: return "C2_UNK_0000_015e"; /* Core2_Penryn. */
769 case 0x0000015f: return "C1_DTS_CAL_CTRL"; /* Core2_Penryn. msrtool only docs this for core1! */
770 case 0x00000174: return "IA32_SYSENTER_CS";
771 case 0x00000175: return "IA32_SYSENTER_ESP";
772 case 0x00000176: return "IA32_SYSENTER_EIP";
773 case 0x00000179: return "IA32_MCG_CAP";
774 case 0x0000017a: return "IA32_MCG_STATUS";
775 case 0x0000017b: return "IA32_MCG_CTL";
776 case 0x0000017f: return "I7_SB_ERROR_CONTROL"; /* SandyBridge. */
777 case 0x00000180: return g_fIntelNetBurst ? "MSR_MCG_RAX" : NULL;
778 case 0x00000181: return g_fIntelNetBurst ? "MSR_MCG_RBX" : NULL;
779 case 0x00000182: return g_fIntelNetBurst ? "MSR_MCG_RCX" : NULL;
780 case 0x00000183: return g_fIntelNetBurst ? "MSR_MCG_RDX" : NULL;
781 case 0x00000184: return g_fIntelNetBurst ? "MSR_MCG_RSI" : NULL;
782 case 0x00000185: return g_fIntelNetBurst ? "MSR_MCG_RDI" : NULL;
783 case 0x00000186: return g_fIntelNetBurst ? "MSR_MCG_RBP" : "IA32_PERFEVTSEL0";
784 case 0x00000187: return g_fIntelNetBurst ? "MSR_MCG_RSP" : "IA32_PERFEVTSEL1";
785 case 0x00000188: return g_fIntelNetBurst ? "MSR_MCG_RFLAGS" : "IA32_PERFEVTSEL2";
786 case 0x00000189: return g_fIntelNetBurst ? "MSR_MCG_RIP" : "IA32_PERFEVTSEL3";
787 case 0x0000018a: return g_fIntelNetBurst ? "MSR_MCG_MISC" : "IA32_PERFEVTSEL4";
788 case 0x0000018b: return g_fIntelNetBurst ? "MSR_MCG_RESERVED1" : "IA32_PERFEVTSEL5";
789 case 0x0000018c: return g_fIntelNetBurst ? "MSR_MCG_RESERVED2" : "IA32_PERFEVTSEL6";
790 case 0x0000018d: return g_fIntelNetBurst ? "MSR_MCG_RESERVED3" : "IA32_PERFEVTSEL7";
791 case 0x0000018e: return g_fIntelNetBurst ? "MSR_MCG_RESERVED4" : "IA32_PERFEVTSEL8";
792 case 0x0000018f: return g_fIntelNetBurst ? "MSR_MCG_RESERVED5" : "IA32_PERFEVTSEL9";
793 case 0x00000190: return g_fIntelNetBurst ? "MSR_MCG_R8" : NULL;
794 case 0x00000191: return g_fIntelNetBurst ? "MSR_MCG_R9" : NULL;
795 case 0x00000192: return g_fIntelNetBurst ? "MSR_MCG_R10" : NULL;
796 case 0x00000193: return g_fIntelNetBurst ? "MSR_MCG_R11" : "C2_UNK_0000_0193";
797 case 0x00000194: return g_fIntelNetBurst ? "MSR_MCG_R12" : "CLOCK_FLEX_MAX";
798 case 0x00000195: return g_fIntelNetBurst ? "MSR_MCG_R13" : NULL;
799 case 0x00000196: return g_fIntelNetBurst ? "MSR_MCG_R14" : NULL;
800 case 0x00000197: return g_fIntelNetBurst ? "MSR_MCG_R15" : NULL;
801 case 0x00000198: return "IA32_PERF_STATUS";
802 case 0x00000199: return "IA32_PERF_CTL";
803 case 0x0000019a: return "IA32_CLOCK_MODULATION";
804 case 0x0000019b: return "IA32_THERM_INTERRUPT";
805 case 0x0000019c: return "IA32_THERM_STATUS";
806 case 0x0000019d: return "IA32_THERM2_CTL";
807 case 0x0000019e: return "P6_UNK_0000_019e"; /* P6_M_Dothan. */
808 case 0x0000019f: return "P6_UNK_0000_019f"; /* P6_M_Dothan. */
809 case 0x000001a0: return "IA32_MISC_ENABLE";
810 case 0x000001a1: return g_fIntelNetBurst ? "MSR_PLATFORM_BRV" : "P6_UNK_0000_01a1" /* P6_M_Dothan. */;
811 case 0x000001a2: return g_fIntelNetBurst ? "P4_UNK_0000_01a2" : "I7_MSR_TEMPERATURE_TARGET" /* SandyBridge, IvyBridge. */;
812 case 0x000001a4: return "I7_UNK_0000_01a4"; /* SandyBridge, IvyBridge. */
813 case 0x000001a6: return "I7_MSR_OFFCORE_RSP_0";
814 case 0x000001a7: return "I7_MSR_OFFCORE_RSP_1";
815 case 0x000001a8: return "I7_UNK_0000_01a8"; /* SandyBridge, IvyBridge. */
816 case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "MSR_MISC_PWR_MGMT" : "P6_PIC_SENS_CFG" /* Pentium M. */;
817 case 0x000001ad: return "I7_MSR_TURBO_RATIO_LIMIT"; /* SandyBridge+, Silvermount+ */
818 case 0x000001ae: return "P6_UNK_0000_01ae"; /* P6_M_Dothan. */
819 case 0x000001af: return "P6_UNK_0000_01af"; /* P6_M_Dothan. */
820 case 0x000001b0: return "IA32_ENERGY_PERF_BIAS";
821 case 0x000001b1: return "IA32_PACKAGE_THERM_STATUS";
822 case 0x000001b2: return "IA32_PACKAGE_THERM_INTERRUPT";
823 case 0x000001bf: return "C2_UNK_0000_01bf"; /* Core2_Penryn. */
824 case 0x000001c6: return "I7_UNK_0000_01c6"; /* SandyBridge*/
825 case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "MSR_LBR_SELECT" : NULL;
826 case 0x000001c9: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
827 && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
828 ? "MSR_LASTBRANCH_TOS" : NULL /* Pentium M Dothan seems to have something else here. */;
829 case 0x000001d3: return "P6_UNK_0000_01d3"; /* P6_M_Dothan. */
830 case 0x000001d7: return g_fIntelNetBurst ? "MSR_LER_FROM_LIP" : NULL;
831 case 0x000001d8: return g_fIntelNetBurst ? "MSR_LER_TO_LIP" : NULL;
832 case 0x000001d9: return "IA32_DEBUGCTL";
833 case 0x000001da: return g_fIntelNetBurst ? "MSR_LASTBRANCH_TOS" : NULL;
834 case 0x000001db: return g_fIntelNetBurst ? "P6_LASTBRANCH_0" : "P6_LAST_BRANCH_FROM_IP"; /* Not exclusive to P6, also AMD. */
835 case 0x000001dc: return g_fIntelNetBurst ? "P6_LASTBRANCH_1" : "P6_LAST_BRANCH_TO_IP";
836 case 0x000001dd: return g_fIntelNetBurst ? "P6_LASTBRANCH_2" : "P6_LAST_INT_FROM_IP";
837 case 0x000001de: return g_fIntelNetBurst ? "P6_LASTBRANCH_3" : "P6_LAST_INT_TO_IP";
838 case 0x000001e0: return "MSR_ROB_CR_BKUPTMPDR6";
839 case 0x000001e1: return "I7_SB_UNK_0000_01e1";
840 case 0x000001ef: return "I7_SB_UNK_0000_01ef";
841 case 0x000001f0: return "I7_VLW_CAPABILITY"; /* SandyBridge. Bit 1 is A20M and was implemented incorrectly (AAJ49). */
842 case 0x000001f2: return "IA32_SMRR_PHYSBASE";
843 case 0x000001f3: return "IA32_SMRR_PHYSMASK";
844 case 0x000001f8: return "IA32_PLATFORM_DCA_CAP";
845 case 0x000001f9: return "IA32_CPU_DCA_CAP";
846 case 0x000001fa: return "IA32_DCA_0_CAP";
847 case 0x000001fc: return "I7_MSR_POWER_CTL";
848
849 case 0x00000200: return "IA32_MTRR_PHYS_BASE0";
850 case 0x00000202: return "IA32_MTRR_PHYS_BASE1";
851 case 0x00000204: return "IA32_MTRR_PHYS_BASE2";
852 case 0x00000206: return "IA32_MTRR_PHYS_BASE3";
853 case 0x00000208: return "IA32_MTRR_PHYS_BASE4";
854 case 0x0000020a: return "IA32_MTRR_PHYS_BASE5";
855 case 0x0000020c: return "IA32_MTRR_PHYS_BASE6";
856 case 0x0000020e: return "IA32_MTRR_PHYS_BASE7";
857 case 0x00000210: return "IA32_MTRR_PHYS_BASE8";
858 case 0x00000212: return "IA32_MTRR_PHYS_BASE9";
859 case 0x00000214: return "IA32_MTRR_PHYS_BASE10";
860 case 0x00000216: return "IA32_MTRR_PHYS_BASE11";
861 case 0x00000218: return "IA32_MTRR_PHYS_BASE12";
862 case 0x0000021a: return "IA32_MTRR_PHYS_BASE13";
863 case 0x0000021c: return "IA32_MTRR_PHYS_BASE14";
864 case 0x0000021e: return "IA32_MTRR_PHYS_BASE15";
865
866 case 0x00000201: return "IA32_MTRR_PHYS_MASK0";
867 case 0x00000203: return "IA32_MTRR_PHYS_MASK1";
868 case 0x00000205: return "IA32_MTRR_PHYS_MASK2";
869 case 0x00000207: return "IA32_MTRR_PHYS_MASK3";
870 case 0x00000209: return "IA32_MTRR_PHYS_MASK4";
871 case 0x0000020b: return "IA32_MTRR_PHYS_MASK5";
872 case 0x0000020d: return "IA32_MTRR_PHYS_MASK6";
873 case 0x0000020f: return "IA32_MTRR_PHYS_MASK7";
874 case 0x00000211: return "IA32_MTRR_PHYS_MASK8";
875 case 0x00000213: return "IA32_MTRR_PHYS_MASK9";
876 case 0x00000215: return "IA32_MTRR_PHYS_MASK10";
877 case 0x00000217: return "IA32_MTRR_PHYS_MASK11";
878 case 0x00000219: return "IA32_MTRR_PHYS_MASK12";
879 case 0x0000021b: return "IA32_MTRR_PHYS_MASK13";
880 case 0x0000021d: return "IA32_MTRR_PHYS_MASK14";
881 case 0x0000021f: return "IA32_MTRR_PHYS_MASK15";
882
883 case 0x00000250: return "IA32_MTRR_FIX64K_00000";
884 case 0x00000258: return "IA32_MTRR_FIX16K_80000";
885 case 0x00000259: return "IA32_MTRR_FIX16K_A0000";
886 case 0x00000268: return "IA32_MTRR_FIX4K_C0000";
887 case 0x00000269: return "IA32_MTRR_FIX4K_C8000";
888 case 0x0000026a: return "IA32_MTRR_FIX4K_D0000";
889 case 0x0000026b: return "IA32_MTRR_FIX4K_D8000";
890 case 0x0000026c: return "IA32_MTRR_FIX4K_E0000";
891 case 0x0000026d: return "IA32_MTRR_FIX4K_E8000";
892 case 0x0000026e: return "IA32_MTRR_FIX4K_F0000";
893 case 0x0000026f: return "IA32_MTRR_FIX4K_F8000";
894 case 0x00000277: return "IA32_PAT";
895 case 0x00000280: return "IA32_MC0_CTL2";
896 case 0x00000281: return "IA32_MC1_CTL2";
897 case 0x00000282: return "IA32_MC2_CTL2";
898 case 0x00000283: return "IA32_MC3_CTL2";
899 case 0x00000284: return "IA32_MC4_CTL2";
900 case 0x00000285: return "IA32_MC5_CTL2";
901 case 0x00000286: return "IA32_MC6_CTL2";
902 case 0x00000287: return "IA32_MC7_CTL2";
903 case 0x00000288: return "IA32_MC8_CTL2";
904 case 0x00000289: return "IA32_MC9_CTL2";
905 case 0x0000028a: return "IA32_MC10_CTL2";
906 case 0x0000028b: return "IA32_MC11_CTL2";
907 case 0x0000028c: return "IA32_MC12_CTL2";
908 case 0x0000028d: return "IA32_MC13_CTL2";
909 case 0x0000028e: return "IA32_MC14_CTL2";
910 case 0x0000028f: return "IA32_MC15_CTL2";
911 case 0x00000290: return "IA32_MC16_CTL2";
912 case 0x00000291: return "IA32_MC17_CTL2";
913 case 0x00000292: return "IA32_MC18_CTL2";
914 case 0x00000293: return "IA32_MC19_CTL2";
915 case 0x00000294: return "IA32_MC20_CTL2";
916 case 0x00000295: return "IA32_MC21_CTL2";
917 //case 0x00000296: return "IA32_MC22_CTL2";
918 //case 0x00000297: return "IA32_MC23_CTL2";
919 //case 0x00000298: return "IA32_MC24_CTL2";
920 //case 0x00000299: return "IA32_MC25_CTL2";
921 //case 0x0000029a: return "IA32_MC26_CTL2";
922 //case 0x0000029b: return "IA32_MC27_CTL2";
923 //case 0x0000029c: return "IA32_MC28_CTL2";
924 //case 0x0000029d: return "IA32_MC29_CTL2";
925 //case 0x0000029e: return "IA32_MC30_CTL2";
926 //case 0x0000029f: return "IA32_MC31_CTL2";
927 case 0x000002e0: return "I7_SB_NO_EVICT_MODE"; /* (Bits 1 & 0 are said to have something to do with no-evict cache mode used during early boot.) */
928 case 0x000002e6: return "I7_IB_UNK_0000_02e6"; /* IvyBridge */
929 case 0x000002e7: return "I7_IB_UNK_0000_02e7"; /* IvyBridge */
930 case 0x000002ff: return "IA32_MTRR_DEF_TYPE";
931 case 0x00000300: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER0" : "I7_SB_UNK_0000_0300" /* SandyBridge */;
932 case 0x00000301: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER1" : NULL;
933 case 0x00000302: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER2" : NULL;
934 case 0x00000303: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER3" : NULL;
935 case 0x00000304: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER0" : NULL;
936 case 0x00000305: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER1" : "I7_SB_UNK_0000_0305" /* SandyBridge, IvyBridge */;
937 case 0x00000306: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER2" : NULL;
938 case 0x00000307: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER3" : NULL;
939 case 0x00000308: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER0" : NULL;
940 case 0x00000309: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER1" : "IA32_FIXED_CTR0";
941 case 0x0000030a: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER2" : "IA32_FIXED_CTR1";
942 case 0x0000030b: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER3" : "IA32_FIXED_CTR2";
943 case 0x0000030c: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER0" : NULL;
944 case 0x0000030d: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER1" : NULL;
945 case 0x0000030e: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER2" : NULL;
946 case 0x0000030f: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER3" : NULL;
947 case 0x00000310: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER4" : NULL;
948 case 0x00000311: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER5" : NULL;
949 case 0x00000345: return "IA32_PERF_CAPABILITIES";
950 case 0x00000360: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR0" : NULL;
951 case 0x00000361: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR1" : NULL;
952 case 0x00000362: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR2" : NULL;
953 case 0x00000363: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR3" : NULL;
954 case 0x00000364: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR0" : NULL;
955 case 0x00000365: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR1" : NULL;
956 case 0x00000366: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR2" : NULL;
957 case 0x00000367: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR3" : NULL;
958 case 0x00000368: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR0" : NULL;
959 case 0x00000369: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR1" : NULL;
960 case 0x0000036a: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR2" : NULL;
961 case 0x0000036b: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR3" : NULL;
962 case 0x0000036c: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR0" : NULL;
963 case 0x0000036d: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR1" : NULL;
964 case 0x0000036e: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR2" : NULL;
965 case 0x0000036f: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR3" : NULL;
966 case 0x00000370: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR4" : NULL;
967 case 0x00000371: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR5" : NULL;
968 case 0x0000038d: return "IA32_FIXED_CTR_CTRL";
969 case 0x0000038e: return "IA32_PERF_GLOBAL_STATUS";
970 case 0x0000038f: return "IA32_PERF_GLOBAL_CTRL";
971 case 0x00000390: return "IA32_PERF_GLOBAL_OVF_CTRL";
972 case 0x00000391: return "I7_UNC_PERF_GLOBAL_CTRL"; /* S,H,X */
973 case 0x00000392: return "I7_UNC_PERF_GLOBAL_STATUS"; /* S,H,X */
974 case 0x00000393: return "I7_UNC_PERF_GLOBAL_OVF_CTRL"; /* X. ASSUMING this is the same on sandybridge and later. */
975 case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR" /* X */ : "I7_UNC_PERF_FIXED_CTR_CTRL"; /* >= S,H */
976 case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR_CTRL" /* X*/ : "I7_UNC_PERF_FIXED_CTR"; /* >= S,H */
977 case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_ADDR_OPCODE_MATCH" /* X */ : "I7_UNC_CBO_CONFIG"; /* >= S,H */
978 case 0x00000397: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? NULL : "I7_SB_UNK_0000_0397";
979 case 0x0000039c: return "I7_SB_MSR_PEBS_NUM_ALT";
980 case 0x000003a0: return g_fIntelNetBurst ? "P4_MSR_BSU_ESCR0" : NULL;
981 case 0x000003a1: return g_fIntelNetBurst ? "P4_MSR_BSU_ESCR1" : NULL;
982 case 0x000003a2: return g_fIntelNetBurst ? "P4_MSR_FSB_ESCR0" : NULL;
983 case 0x000003a3: return g_fIntelNetBurst ? "P4_MSR_FSB_ESCR1" : NULL;
984 case 0x000003a4: return g_fIntelNetBurst ? "P4_MSR_FIRM_ESCR0" : NULL;
985 case 0x000003a5: return g_fIntelNetBurst ? "P4_MSR_FIRM_ESCR1" : NULL;
986 case 0x000003a6: return g_fIntelNetBurst ? "P4_MSR_FLAME_ESCR0" : NULL;
987 case 0x000003a7: return g_fIntelNetBurst ? "P4_MSR_FLAME_ESCR1" : NULL;
988 case 0x000003a8: return g_fIntelNetBurst ? "P4_MSR_DAC_ESCR0" : NULL;
989 case 0x000003a9: return g_fIntelNetBurst ? "P4_MSR_DAC_ESCR1" : NULL;
990 case 0x000003aa: return g_fIntelNetBurst ? "P4_MSR_MOB_ESCR0" : NULL;
991 case 0x000003ab: return g_fIntelNetBurst ? "P4_MSR_MOB_ESCR1" : NULL;
992 case 0x000003ac: return g_fIntelNetBurst ? "P4_MSR_PMH_ESCR0" : NULL;
993 case 0x000003ad: return g_fIntelNetBurst ? "P4_MSR_PMH_ESCR1" : NULL;
994 case 0x000003ae: return g_fIntelNetBurst ? "P4_MSR_SAAT_ESCR0" : NULL;
995 case 0x000003af: return g_fIntelNetBurst ? "P4_MSR_SAAT_ESCR1" : NULL;
996 case 0x000003b0: return g_fIntelNetBurst ? "P4_MSR_U2L_ESCR0" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC0" /* X */ : "I7_UNC_ARB_PERF_CTR0"; /* >= S,H */
997 case 0x000003b1: return g_fIntelNetBurst ? "P4_MSR_U2L_ESCR1" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC1" /* X */ : "I7_UNC_ARB_PERF_CTR1"; /* >= S,H */
998 case 0x000003b2: return g_fIntelNetBurst ? "P4_MSR_BPU_ESCR0" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC2" /* X */ : "I7_UNC_ARB_PERF_EVT_SEL0"; /* >= S,H */
999 case 0x000003b3: return g_fIntelNetBurst ? "P4_MSR_BPU_ESCR1" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC3" /* X */ : "I7_UNC_ARB_PERF_EVT_SEL1"; /* >= S,H */
1000 case 0x000003b4: return g_fIntelNetBurst ? "P4_MSR_IS_ESCR0" : "I7_UNC_PMC4";
1001 case 0x000003b5: return g_fIntelNetBurst ? "P4_MSR_IS_ESCR1" : "I7_UNC_PMC5";
1002 case 0x000003b6: return g_fIntelNetBurst ? "P4_MSR_ITLB_ESCR0" : "I7_UNC_PMC6";
1003 case 0x000003b7: return g_fIntelNetBurst ? "P4_MSR_ITLB_ESCR1" : "I7_UNC_PMC7";
1004 case 0x000003b8: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR0" : NULL;
1005 case 0x000003b9: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR1" : NULL;
1006 case 0x000003ba: return g_fIntelNetBurst ? "P4_MSR_IQ_ESCR0" : NULL;
1007 case 0x000003bb: return g_fIntelNetBurst ? "P4_MSR_IQ_ESCR1" : NULL;
1008 case 0x000003bc: return g_fIntelNetBurst ? "P4_MSR_RAT_ESCR0" : NULL;
1009 case 0x000003bd: return g_fIntelNetBurst ? "P4_MSR_RAT_ESCR1" : NULL;
1010 case 0x000003be: return g_fIntelNetBurst ? "P4_MSR_SSU_ESCR0" : NULL;
1011 case 0x000003c0: return g_fIntelNetBurst ? "P4_MSR_MS_ESCR0" : "I7_UNC_PERF_EVT_SEL0";
1012 case 0x000003c1: return g_fIntelNetBurst ? "P4_MSR_MS_ESCR1" : "I7_UNC_PERF_EVT_SEL1";
1013 case 0x000003c2: return g_fIntelNetBurst ? "P4_MSR_TBPU_ESCR0" : "I7_UNC_PERF_EVT_SEL2";
1014 case 0x000003c3: return g_fIntelNetBurst ? "P4_MSR_TBPU_ESCR1" : "I7_UNC_PERF_EVT_SEL3";
1015 case 0x000003c4: return g_fIntelNetBurst ? "P4_MSR_TC_ESCR0" : "I7_UNC_PERF_EVT_SEL4";
1016 case 0x000003c5: return g_fIntelNetBurst ? "P4_MSR_TC_ESCR1" : "I7_UNC_PERF_EVT_SEL5";
1017 case 0x000003c6: return g_fIntelNetBurst ? NULL : "I7_UNC_PERF_EVT_SEL6";
1018 case 0x000003c7: return g_fIntelNetBurst ? NULL : "I7_UNC_PERF_EVT_SEL7";
1019 case 0x000003c8: return g_fIntelNetBurst ? "P4_MSR_IX_ESCR0" : NULL;
1020 case 0x000003c9: return g_fIntelNetBurst ? "P4_MSR_IX_ESCR0" : NULL;
1021 case 0x000003ca: return g_fIntelNetBurst ? "P4_MSR_ALF_ESCR0" : NULL;
1022 case 0x000003cb: return g_fIntelNetBurst ? "P4_MSR_ALF_ESCR1" : NULL;
1023 case 0x000003cc: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR2" : NULL;
1024 case 0x000003cd: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR3" : NULL;
1025 case 0x000003e0: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR4" : NULL;
1026 case 0x000003e1: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR5" : NULL;
1027 case 0x000003f0: return g_fIntelNetBurst ? "P4_MSR_TC_PRECISE_EVENT" : NULL;
1028 case 0x000003f1: return "IA32_PEBS_ENABLE";
1029 case 0x000003f2: return g_fIntelNetBurst ? "P4_MSR_PEBS_MATRIX_VERT" : "IA32_PEBS_ENABLE";
1030 case 0x000003f3: return g_fIntelNetBurst ? "P4_UNK_0000_03f3" : NULL;
1031 case 0x000003f4: return g_fIntelNetBurst ? "P4_UNK_0000_03f4" : NULL;
1032 case 0x000003f5: return g_fIntelNetBurst ? "P4_UNK_0000_03f5" : NULL;
1033 case 0x000003f6: return g_fIntelNetBurst ? "P4_UNK_0000_03f6" : "I7_MSR_PEBS_LD_LAT";
1034 case 0x000003f7: return g_fIntelNetBurst ? "P4_UNK_0000_03f7" : "I7_MSR_PEBS_LD_LAT";
1035 case 0x000003f8: return g_fIntelNetBurst ? "P4_UNK_0000_03f8" : "I7_MSR_PKG_C3_RESIDENCY";
1036 case 0x000003f9: return "I7_MSR_PKG_C6_RESIDENCY";
1037 case 0x000003fa: return "I7_MSR_PKG_C7_RESIDENCY";
1038 case 0x000003fc: return "I7_MSR_CORE_C3_RESIDENCY";
1039 case 0x000003fd: return "I7_MSR_CORE_C6_RESIDENCY";
1040 case 0x000003fe: return "I7_MSR_CORE_C7_RESIDENCY";
1041 case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "CPUID1_FEATURE_MASK" : NULL;
1042 case 0x00000480: return "IA32_VMX_BASIC";
1043 case 0x00000481: return "IA32_VMX_PINBASED_CTLS";
1044 case 0x00000482: return "IA32_VMX_PROCBASED_CTLS";
1045 case 0x00000483: return "IA32_VMX_EXIT_CTLS";
1046 case 0x00000484: return "IA32_VMX_ENTRY_CTLS";
1047 case 0x00000485: return "IA32_VMX_MISC";
1048 case 0x00000486: return "IA32_VMX_CR0_FIXED0";
1049 case 0x00000487: return "IA32_VMX_CR0_FIXED1";
1050 case 0x00000488: return "IA32_VMX_CR4_FIXED0";
1051 case 0x00000489: return "IA32_VMX_CR4_FIXED1";
1052 case 0x0000048a: return "IA32_VMX_VMCS_ENUM";
1053 case 0x0000048b: return "IA32_VMX_PROCBASED_CTLS2";
1054 case 0x0000048c: return "IA32_VMX_EPT_VPID_CAP";
1055 case 0x0000048d: return "IA32_VMX_TRUE_PINBASED_CTLS";
1056 case 0x0000048e: return "IA32_VMX_TRUE_PROCBASED_CTLS";
1057 case 0x0000048f: return "IA32_VMX_TRUE_EXIT_CTLS";
1058 case 0x00000490: return "IA32_VMX_TRUE_ENTRY_CTLS";
1059 case 0x00000491: return "IA32_VMX_VMFUNC";
1060 case 0x000004c1: return "IA32_A_PMC0";
1061 case 0x000004c2: return "IA32_A_PMC1";
1062 case 0x000004c3: return "IA32_A_PMC2";
1063 case 0x000004c4: return "IA32_A_PMC3";
1064 case 0x000004c5: return "IA32_A_PMC4";
1065 case 0x000004c6: return "IA32_A_PMC5";
1066 case 0x000004c7: return "IA32_A_PMC6";
1067 case 0x000004c8: return "IA32_A_PMC7";
1068 case 0x000004f8: return "C2_UNK_0000_04f8"; /* Core2_Penryn. */
1069 case 0x000004f9: return "C2_UNK_0000_04f9"; /* Core2_Penryn. */
1070 case 0x000004fa: return "C2_UNK_0000_04fa"; /* Core2_Penryn. */
1071 case 0x000004fb: return "C2_UNK_0000_04fb"; /* Core2_Penryn. */
1072 case 0x000004fc: return "C2_UNK_0000_04fc"; /* Core2_Penryn. */
1073 case 0x000004fd: return "C2_UNK_0000_04fd"; /* Core2_Penryn. */
1074 case 0x000004fe: return "C2_UNK_0000_04fe"; /* Core2_Penryn. */
1075 case 0x000004ff: return "C2_UNK_0000_04ff"; /* Core2_Penryn. */
1076 case 0x00000502: return "I7_SB_UNK_0000_0502";
1077 case 0x00000590: return "C2_UNK_0000_0590"; /* Core2_Penryn. */
1078 case 0x00000591: return "C2_UNK_0000_0591"; /* Core2_Penryn. */
1079 case 0x000005a0: return "C2_PECI_CTL"; /* Core2_Penryn. */
1080 case 0x000005a1: return "C2_UNK_0000_05a1"; /* Core2_Penryn. */
1081 case 0x00000600: return "IA32_DS_AREA";
1082 case 0x00000601: return "I7_SB_MSR_VR_CURRENT_CONFIG"; /* SandyBridge, IvyBridge. */
1083 case 0x00000602: return "I7_IB_UNK_0000_0602";
1084 case 0x00000603: return "I7_SB_MSR_VR_MISC_CONFIG"; /* SandyBridge, IvyBridge. */
1085 case 0x00000604: return "I7_IB_UNK_0000_0602";
1086 case 0x00000606: return "I7_SB_MSR_RAPL_POWER_UNIT"; /* SandyBridge, IvyBridge. */
1087 case 0x00000609: return "I7_SB_UNK_0000_0609"; /* SandyBridge (non EP). */
1088 case 0x0000060a: return "I7_SB_MSR_PKGC3_IRTL"; /* SandyBridge, IvyBridge. */
1089 case 0x0000060b: return "I7_SB_MSR_PKGC6_IRTL"; /* SandyBridge, IvyBridge. */
1090 case 0x0000060c: return "I7_SB_MSR_PKGC7_IRTL"; /* SandyBridge, IvyBridge. */
1091 case 0x0000060d: return "I7_SB_MSR_PKG_C2_RESIDENCY"; /* SandyBridge, IvyBridge. */
1092 case 0x00000610: return "I7_SB_MSR_PKG_POWER_LIMIT";
1093 case 0x00000611: return "I7_SB_MSR_PKG_ENERGY_STATUS";
1094 case 0x00000613: return "I7_SB_MSR_PKG_PERF_STATUS";
1095 case 0x00000614: return "I7_SB_MSR_PKG_POWER_INFO";
1096 case 0x00000618: return "I7_SB_MSR_DRAM_POWER_LIMIT";
1097 case 0x00000619: return "I7_SB_MSR_DRAM_ENERGY_STATUS";
1098 case 0x0000061b: return "I7_SB_MSR_DRAM_PERF_STATUS";
1099 case 0x0000061c: return "I7_SB_MSR_DRAM_POWER_INFO";
1100 case 0x00000638: return "I7_SB_MSR_PP0_POWER_LIMIT";
1101 case 0x00000639: return "I7_SB_MSR_PP0_ENERGY_STATUS";
1102 case 0x0000063a: return "I7_SB_MSR_PP0_POLICY";
1103 case 0x0000063b: return "I7_SB_MSR_PP0_PERF_STATUS";
1104 case 0x00000640: return "I7_HW_MSR_PP0_POWER_LIMIT";
1105 case 0x00000641: return "I7_HW_MSR_PP0_ENERGY_STATUS";
1106 case 0x00000642: return "I7_HW_MSR_PP0_POLICY";
1107 case 0x00000648: return "I7_IB_MSR_CONFIG_TDP_NOMINAL";
1108 case 0x00000649: return "I7_IB_MSR_CONFIG_TDP_LEVEL1";
1109 case 0x0000064a: return "I7_IB_MSR_CONFIG_TDP_LEVEL2";
1110 case 0x0000064b: return "I7_IB_MSR_CONFIG_TDP_CONTROL";
1111 case 0x0000064c: return "I7_IB_MSR_TURBO_ACTIVATION_RATIO";
1112 case 0x00000660: return "SILV_CORE_C1_RESIDENCY";
1113 case 0x00000661: return "SILV_UNK_0000_0661";
1114 case 0x00000662: return "SILV_UNK_0000_0662";
1115 case 0x00000663: return "SILV_UNK_0000_0663";
1116 case 0x00000664: return "SILV_UNK_0000_0664";
1117 case 0x00000665: return "SILV_UNK_0000_0665";
1118 case 0x00000666: return "SILV_UNK_0000_0666";
1119 case 0x00000667: return "SILV_UNK_0000_0667";
1120 case 0x00000668: return "SILV_UNK_0000_0668";
1121 case 0x00000669: return "SILV_UNK_0000_0669";
1122 case 0x0000066a: return "SILV_UNK_0000_066a";
1123 case 0x0000066b: return "SILV_UNK_0000_066b";
1124 case 0x0000066c: return "SILV_UNK_0000_066c";
1125 case 0x0000066d: return "SILV_UNK_0000_066d";
1126 case 0x0000066e: return "SILV_UNK_0000_066e";
1127 case 0x0000066f: return "SILV_UNK_0000_066f";
1128 case 0x00000670: return "SILV_UNK_0000_0670";
1129 case 0x00000671: return "SILV_UNK_0000_0671";
1130 case 0x00000672: return "SILV_UNK_0000_0672";
1131 case 0x00000673: return "SILV_UNK_0000_0673";
1132 case 0x00000674: return "SILV_UNK_0000_0674";
1133 case 0x00000675: return "SILV_UNK_0000_0675";
1134 case 0x00000676: return "SILV_UNK_0000_0676";
1135 case 0x00000677: return "SILV_UNK_0000_0677";
1136
1137 case 0x00000680: return "MSR_LASTBRANCH_0_FROM_IP";
1138 case 0x00000681: return "MSR_LASTBRANCH_1_FROM_IP";
1139 case 0x00000682: return "MSR_LASTBRANCH_2_FROM_IP";
1140 case 0x00000683: return "MSR_LASTBRANCH_3_FROM_IP";
1141 case 0x00000684: return "MSR_LASTBRANCH_4_FROM_IP";
1142 case 0x00000685: return "MSR_LASTBRANCH_5_FROM_IP";
1143 case 0x00000686: return "MSR_LASTBRANCH_6_FROM_IP";
1144 case 0x00000687: return "MSR_LASTBRANCH_7_FROM_IP";
1145 case 0x00000688: return "MSR_LASTBRANCH_8_FROM_IP";
1146 case 0x00000689: return "MSR_LASTBRANCH_9_FROM_IP";
1147 case 0x0000068a: return "MSR_LASTBRANCH_10_FROM_IP";
1148 case 0x0000068b: return "MSR_LASTBRANCH_11_FROM_IP";
1149 case 0x0000068c: return "MSR_LASTBRANCH_12_FROM_IP";
1150 case 0x0000068d: return "MSR_LASTBRANCH_13_FROM_IP";
1151 case 0x0000068e: return "MSR_LASTBRANCH_14_FROM_IP";
1152 case 0x0000068f: return "MSR_LASTBRANCH_15_FROM_IP";
1153 case 0x000006c0: return "MSR_LASTBRANCH_0_TO_IP";
1154 case 0x000006c1: return "MSR_LASTBRANCH_1_TO_IP";
1155 case 0x000006c2: return "MSR_LASTBRANCH_2_TO_IP";
1156 case 0x000006c3: return "MSR_LASTBRANCH_3_TO_IP";
1157 case 0x000006c4: return "MSR_LASTBRANCH_4_TO_IP";
1158 case 0x000006c5: return "MSR_LASTBRANCH_5_TO_IP";
1159 case 0x000006c6: return "MSR_LASTBRANCH_6_TO_IP";
1160 case 0x000006c7: return "MSR_LASTBRANCH_7_TO_IP";
1161 case 0x000006c8: return "MSR_LASTBRANCH_8_TO_IP";
1162 case 0x000006c9: return "MSR_LASTBRANCH_9_TO_IP";
1163 case 0x000006ca: return "MSR_LASTBRANCH_10_TO_IP";
1164 case 0x000006cb: return "MSR_LASTBRANCH_11_TO_IP";
1165 case 0x000006cc: return "MSR_LASTBRANCH_12_TO_IP";
1166 case 0x000006cd: return "MSR_LASTBRANCH_13_TO_IP";
1167 case 0x000006ce: return "MSR_LASTBRANCH_14_TO_IP";
1168 case 0x000006cf: return "MSR_LASTBRANCH_15_TO_IP";
1169 case 0x000006e0: return "IA32_TSC_DEADLINE";
1170
1171 case 0x00000768: return "SILV_UNK_0000_0768";
1172 case 0x00000769: return "SILV_UNK_0000_0769";
1173 case 0x0000076a: return "SILV_UNK_0000_076a";
1174 case 0x0000076b: return "SILV_UNK_0000_076b";
1175 case 0x0000076c: return "SILV_UNK_0000_076c";
1176 case 0x0000076d: return "SILV_UNK_0000_076d";
1177 case 0x0000076e: return "SILV_UNK_0000_076e";
1178
1179 case 0x00000c80: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "IA32_DEBUG_INTERFACE" : NULL; /* Mentioned in an intel dataskit called 4th-gen-core-family-desktop-vol-1-datasheet.pdf. */
1180 case 0x00000c81: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c81" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
1181 case 0x00000c82: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c82" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
1182 case 0x00000c83: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c83" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
1183
1184 /* 0x1000..0x1004 seems to have been used by IBM 386 and 486 clones too. */
1185 case 0x00001000: return "P6_DEBUG_REGISTER_0";
1186 case 0x00001001: return "P6_DEBUG_REGISTER_1";
1187 case 0x00001002: return "P6_DEBUG_REGISTER_2";
1188 case 0x00001003: return "P6_DEBUG_REGISTER_3";
1189 case 0x00001004: return "P6_DEBUG_REGISTER_4";
1190 case 0x00001005: return "P6_DEBUG_REGISTER_5";
1191 case 0x00001006: return "P6_DEBUG_REGISTER_6";
1192 case 0x00001007: return "P6_DEBUG_REGISTER_7";
1193 case 0x0000103f: return "P6_UNK_0000_103f"; /* P6_M_Dothan. */
1194 case 0x000010cd: return "P6_UNK_0000_10cd"; /* P6_M_Dothan. */
1195
1196 case 0x00001107: return "VIA_UNK_0000_1107";
1197 case 0x0000110f: return "VIA_UNK_0000_110f";
1198 case 0x00001153: return "VIA_UNK_0000_1153";
1199 case 0x00001200: return "VIA_UNK_0000_1200";
1200 case 0x00001201: return "VIA_UNK_0000_1201";
1201 case 0x00001202: return "VIA_UNK_0000_1202";
1202 case 0x00001203: return "VIA_UNK_0000_1203";
1203 case 0x00001204: return "VIA_UNK_0000_1204";
1204 case 0x00001205: return "VIA_UNK_0000_1205";
1205 case 0x00001206: return "VIA_ALT_VENDOR_EBX";
1206 case 0x00001207: return "VIA_ALT_VENDOR_ECDX";
1207 case 0x00001208: return "VIA_UNK_0000_1208";
1208 case 0x00001209: return "VIA_UNK_0000_1209";
1209 case 0x0000120a: return "VIA_UNK_0000_120a";
1210 case 0x0000120b: return "VIA_UNK_0000_120b";
1211 case 0x0000120c: return "VIA_UNK_0000_120c";
1212 case 0x0000120d: return "VIA_UNK_0000_120d";
1213 case 0x0000120e: return "VIA_UNK_0000_120e";
1214 case 0x0000120f: return "VIA_UNK_0000_120f";
1215 case 0x00001210: return "VIA_UNK_0000_1210";
1216 case 0x00001211: return "VIA_UNK_0000_1211";
1217 case 0x00001212: return "VIA_UNK_0000_1212";
1218 case 0x00001213: return "VIA_UNK_0000_1213";
1219 case 0x00001214: return "VIA_UNK_0000_1214";
1220 case 0x00001220: return "VIA_UNK_0000_1220";
1221 case 0x00001221: return "VIA_UNK_0000_1221";
1222 case 0x00001230: return "VIA_UNK_0000_1230";
1223 case 0x00001231: return "VIA_UNK_0000_1231";
1224 case 0x00001232: return "VIA_UNK_0000_1232";
1225 case 0x00001233: return "VIA_UNK_0000_1233";
1226 case 0x00001234: return "VIA_UNK_0000_1234";
1227 case 0x00001235: return "VIA_UNK_0000_1235";
1228 case 0x00001236: return "VIA_UNK_0000_1236";
1229 case 0x00001237: return "VIA_UNK_0000_1237";
1230 case 0x00001238: return "VIA_UNK_0000_1238";
1231 case 0x00001239: return "VIA_UNK_0000_1239";
1232 case 0x00001240: return "VIA_UNK_0000_1240";
1233 case 0x00001241: return "VIA_UNK_0000_1241";
1234 case 0x00001243: return "VIA_UNK_0000_1243";
1235 case 0x00001245: return "VIA_UNK_0000_1245";
1236 case 0x00001246: return "VIA_UNK_0000_1246";
1237 case 0x00001247: return "VIA_UNK_0000_1247";
1238 case 0x00001248: return "VIA_UNK_0000_1248";
1239 case 0x00001249: return "VIA_UNK_0000_1249";
1240 case 0x0000124a: return "VIA_UNK_0000_124a";
1241
1242 case 0x00001301: return "VIA_UNK_0000_1301";
1243 case 0x00001302: return "VIA_UNK_0000_1302";
1244 case 0x00001303: return "VIA_UNK_0000_1303";
1245 case 0x00001304: return "VIA_UNK_0000_1304";
1246 case 0x00001305: return "VIA_UNK_0000_1305";
1247 case 0x00001306: return "VIA_UNK_0000_1306";
1248 case 0x00001307: return "VIA_UNK_0000_1307";
1249 case 0x00001308: return "VIA_UNK_0000_1308";
1250 case 0x00001309: return "VIA_UNK_0000_1309";
1251 case 0x0000130d: return "VIA_UNK_0000_130d";
1252 case 0x0000130e: return "VIA_UNK_0000_130e";
1253 case 0x00001312: return "VIA_UNK_0000_1312";
1254 case 0x00001315: return "VIA_UNK_0000_1315";
1255 case 0x00001317: return "VIA_UNK_0000_1317";
1256 case 0x00001318: return "VIA_UNK_0000_1318";
1257 case 0x0000131a: return "VIA_UNK_0000_131a";
1258 case 0x0000131b: return "VIA_UNK_0000_131b";
1259 case 0x00001402: return "VIA_UNK_0000_1402";
1260 case 0x00001403: return "VIA_UNK_0000_1403";
1261 case 0x00001404: return "VIA_UNK_0000_1404";
1262 case 0x00001405: return "VIA_UNK_0000_1405";
1263 case 0x00001406: return "VIA_UNK_0000_1406";
1264 case 0x00001407: return "VIA_UNK_0000_1407";
1265 case 0x00001410: return "VIA_UNK_0000_1410";
1266 case 0x00001411: return "VIA_UNK_0000_1411";
1267 case 0x00001412: return "VIA_UNK_0000_1412";
1268 case 0x00001413: return "VIA_UNK_0000_1413";
1269 case 0x00001414: return "VIA_UNK_0000_1414";
1270 case 0x00001415: return "VIA_UNK_0000_1415";
1271 case 0x00001416: return "VIA_UNK_0000_1416";
1272 case 0x00001417: return "VIA_UNK_0000_1417";
1273 case 0x00001418: return "VIA_UNK_0000_1418";
1274 case 0x00001419: return "VIA_UNK_0000_1419";
1275 case 0x0000141a: return "VIA_UNK_0000_141a";
1276 case 0x0000141b: return "VIA_UNK_0000_141b";
1277 case 0x0000141c: return "VIA_UNK_0000_141c";
1278 case 0x0000141d: return "VIA_UNK_0000_141d";
1279 case 0x0000141e: return "VIA_UNK_0000_141e";
1280 case 0x0000141f: return "VIA_UNK_0000_141f";
1281 case 0x00001420: return "VIA_UNK_0000_1420";
1282 case 0x00001421: return "VIA_UNK_0000_1421";
1283 case 0x00001422: return "VIA_UNK_0000_1422";
1284 case 0x00001423: return "VIA_UNK_0000_1423";
1285 case 0x00001424: return "VIA_UNK_0000_1424";
1286 case 0x00001425: return "VIA_UNK_0000_1425";
1287 case 0x00001426: return "VIA_UNK_0000_1426";
1288 case 0x00001427: return "VIA_UNK_0000_1427";
1289 case 0x00001428: return "VIA_UNK_0000_1428";
1290 case 0x00001429: return "VIA_UNK_0000_1429";
1291 case 0x0000142a: return "VIA_UNK_0000_142a";
1292 case 0x0000142b: return "VIA_UNK_0000_142b";
1293 case 0x0000142c: return "VIA_UNK_0000_142c";
1294 case 0x0000142d: return "VIA_UNK_0000_142d";
1295 case 0x0000142e: return "VIA_UNK_0000_142e";
1296 case 0x0000142f: return "VIA_UNK_0000_142f";
1297 case 0x00001434: return "VIA_UNK_0000_1434";
1298 case 0x00001435: return "VIA_UNK_0000_1435";
1299 case 0x00001436: return "VIA_UNK_0000_1436";
1300 case 0x00001437: return "VIA_UNK_0000_1437";
1301 case 0x00001438: return "VIA_UNK_0000_1438";
1302 case 0x0000143a: return "VIA_UNK_0000_143a";
1303 case 0x0000143c: return "VIA_UNK_0000_143c";
1304 case 0x0000143d: return "VIA_UNK_0000_143d";
1305 case 0x00001440: return "VIA_UNK_0000_1440";
1306 case 0x00001441: return "VIA_UNK_0000_1441";
1307 case 0x00001442: return "VIA_UNK_0000_1442";
1308 case 0x00001449: return "VIA_UNK_0000_1449";
1309 case 0x00001450: return "VIA_UNK_0000_1450";
1310 case 0x00001451: return "VIA_UNK_0000_1451";
1311 case 0x00001452: return "VIA_UNK_0000_1452";
1312 case 0x00001453: return "VIA_UNK_0000_1453";
1313 case 0x00001460: return "VIA_UNK_0000_1460";
1314 case 0x00001461: return "VIA_UNK_0000_1461";
1315 case 0x00001462: return "VIA_UNK_0000_1462";
1316 case 0x00001463: return "VIA_UNK_0000_1463";
1317 case 0x00001465: return "VIA_UNK_0000_1465";
1318 case 0x00001466: return "VIA_UNK_0000_1466";
1319 case 0x00001470: return "VIA_UNK_0000_1470";
1320 case 0x00001471: return "VIA_UNK_0000_1471";
1321 case 0x00001480: return "VIA_UNK_0000_1480";
1322 case 0x00001481: return "VIA_UNK_0000_1481";
1323 case 0x00001482: return "VIA_UNK_0000_1482";
1324 case 0x00001483: return "VIA_UNK_0000_1483";
1325 case 0x00001484: return "VIA_UNK_0000_1484";
1326 case 0x00001485: return "VIA_UNK_0000_1485";
1327 case 0x00001486: return "VIA_UNK_0000_1486";
1328 case 0x00001490: return "VIA_UNK_0000_1490";
1329 case 0x00001491: return "VIA_UNK_0000_1491";
1330 case 0x00001492: return "VIA_UNK_0000_1492";
1331 case 0x00001493: return "VIA_UNK_0000_1493";
1332 case 0x00001494: return "VIA_UNK_0000_1494";
1333 case 0x00001495: return "VIA_UNK_0000_1495";
1334 case 0x00001496: return "VIA_UNK_0000_1496";
1335 case 0x00001497: return "VIA_UNK_0000_1497";
1336 case 0x00001498: return "VIA_UNK_0000_1498";
1337 case 0x00001499: return "VIA_UNK_0000_1499";
1338 case 0x0000149a: return "VIA_UNK_0000_149a";
1339 case 0x0000149b: return "VIA_UNK_0000_149b";
1340 case 0x0000149c: return "VIA_UNK_0000_149c";
1341 case 0x0000149f: return "VIA_UNK_0000_149f";
1342 case 0x00001523: return "VIA_UNK_0000_1523";
1343
1344 case 0x00002000: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR0" : NULL;
1345 case 0x00002002: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR2" : NULL;
1346 case 0x00002003: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR3" : NULL;
1347 case 0x00002004: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR4" : NULL;
1348 case 0x0000203f: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_203f" /* P6_M_Dothan. */ : NULL;
1349 case 0x000020cd: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_20cd" /* P6_M_Dothan. */ : NULL;
1350 case 0x0000303f: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_303f" /* P6_M_Dothan. */ : NULL;
1351 case 0x000030cd: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_30cd" /* P6_M_Dothan. */ : NULL;
1352
1353 case 0x0000317a: return "VIA_UNK_0000_317a";
1354 case 0x0000317b: return "VIA_UNK_0000_317b";
1355 case 0x0000317d: return "VIA_UNK_0000_317d";
1356 case 0x0000317e: return "VIA_UNK_0000_317e";
1357 case 0x0000317f: return "VIA_UNK_0000_317f";
1358 case 0x80000198: return "VIA_UNK_8000_0198";
1359
1360 case 0xc0000080: return "AMD64_EFER";
1361 case 0xc0000081: return "AMD64_STAR";
1362 case 0xc0000082: return "AMD64_STAR64";
1363 case 0xc0000083: return "AMD64_STARCOMPAT";
1364 case 0xc0000084: return "AMD64_SYSCALL_FLAG_MASK";
1365 case 0xc0000100: return "AMD64_FS_BASE";
1366 case 0xc0000101: return "AMD64_GS_BASE";
1367 case 0xc0000102: return "AMD64_KERNEL_GS_BASE";
1368 case 0xc0000103: return "AMD64_TSC_AUX";
1369 case 0xc0000104: return "AMD_15H_TSC_RATE";
1370 case 0xc0000105: return "AMD_15H_LWP_CFG"; /* Only Family 15h? */
1371 case 0xc0000106: return "AMD_15H_LWP_CBADDR"; /* Only Family 15h? */
1372 case 0xc0000408: return "AMD_10H_MC4_MISC1";
1373 case 0xc0000409: return "AMD_10H_MC4_MISC2";
1374 case 0xc000040a: return "AMD_10H_MC4_MISC3";
1375 case 0xc000040b: return "AMD_10H_MC4_MISC4";
1376 case 0xc000040c: return "AMD_10H_MC4_MISC5";
1377 case 0xc000040d: return "AMD_10H_MC4_MISC6";
1378 case 0xc000040e: return "AMD_10H_MC4_MISC7";
1379 case 0xc000040f: return "AMD_10H_MC4_MISC8";
1380 case 0xc0010000: return "AMD_K8_PERF_CTL_0";
1381 case 0xc0010001: return "AMD_K8_PERF_CTL_1";
1382 case 0xc0010002: return "AMD_K8_PERF_CTL_2";
1383 case 0xc0010003: return "AMD_K8_PERF_CTL_3";
1384 case 0xc0010004: return "AMD_K8_PERF_CTR_0";
1385 case 0xc0010005: return "AMD_K8_PERF_CTR_1";
1386 case 0xc0010006: return "AMD_K8_PERF_CTR_2";
1387 case 0xc0010007: return "AMD_K8_PERF_CTR_3";
1388 case 0xc0010010: return "AMD_K8_SYS_CFG";
1389 case 0xc0010015: return "AMD_K8_HW_CFG";
1390 case 0xc0010016: return "AMD_K8_IORR_BASE_0";
1391 case 0xc0010017: return "AMD_K8_IORR_MASK_0";
1392 case 0xc0010018: return "AMD_K8_IORR_BASE_1";
1393 case 0xc0010019: return "AMD_K8_IORR_MASK_1";
1394 case 0xc001001a: return "AMD_K8_TOP_MEM";
1395 case 0xc001001d: return "AMD_K8_TOP_MEM2";
1396 case 0xc001001e: return "AMD_K8_MANID";
1397 case 0xc001001f: return "AMD_K8_NB_CFG1";
1398 case 0xc0010020: return "AMD_K8_PATCH_LOADER";
1399 case 0xc0010021: return "AMD_K8_UNK_c001_0021";
1400 case 0xc0010022: return "AMD_K8_MC_XCPT_REDIR";
1401 case 0xc0010028: return "AMD_K8_UNK_c001_0028";
1402 case 0xc0010029: return "AMD_K8_UNK_c001_0029";
1403 case 0xc001002a: return "AMD_K8_UNK_c001_002a";
1404 case 0xc001002b: return "AMD_K8_UNK_c001_002b";
1405 case 0xc001002c: return "AMD_K8_UNK_c001_002c";
1406 case 0xc001002d: return "AMD_K8_UNK_c001_002d";
1407 case 0xc0010030: return "AMD_K8_CPU_NAME_0";
1408 case 0xc0010031: return "AMD_K8_CPU_NAME_1";
1409 case 0xc0010032: return "AMD_K8_CPU_NAME_2";
1410 case 0xc0010033: return "AMD_K8_CPU_NAME_3";
1411 case 0xc0010034: return "AMD_K8_CPU_NAME_4";
1412 case 0xc0010035: return "AMD_K8_CPU_NAME_5";
1413 case 0xc001003e: return "AMD_K8_HTC";
1414 case 0xc001003f: return "AMD_K8_STC";
1415 case 0xc0010041: return "AMD_K8_FIDVID_CTL";
1416 case 0xc0010042: return "AMD_K8_FIDVID_STATUS";
1417 case 0xc0010043: return "AMD_K8_THERMTRIP_STATUS"; /* BDKG says it was removed in K8 revision C.*/
1418 case 0xc0010044: return "AMD_K8_MC_CTL_MASK_0";
1419 case 0xc0010045: return "AMD_K8_MC_CTL_MASK_1";
1420 case 0xc0010046: return "AMD_K8_MC_CTL_MASK_2";
1421 case 0xc0010047: return "AMD_K8_MC_CTL_MASK_3";
1422 case 0xc0010048: return "AMD_K8_MC_CTL_MASK_4";
1423 case 0xc0010049: return "AMD_K8_MC_CTL_MASK_5";
1424 case 0xc001004a: return "AMD_K8_MC_CTL_MASK_6";
1425 //case 0xc001004b: return "AMD_K8_MC_CTL_MASK_7";
1426 case 0xc0010050: return "AMD_K8_SMI_ON_IO_TRAP_0";
1427 case 0xc0010051: return "AMD_K8_SMI_ON_IO_TRAP_1";
1428 case 0xc0010052: return "AMD_K8_SMI_ON_IO_TRAP_2";
1429 case 0xc0010053: return "AMD_K8_SMI_ON_IO_TRAP_3";
1430 case 0xc0010054: return "AMD_K8_SMI_ON_IO_TRAP_CTL_STS";
1431 case 0xc0010055: return "AMD_K8_INT_PENDING_MSG";
1432 case 0xc0010056: return "AMD_K8_SMI_TRIGGER_IO_CYCLE";
1433 case 0xc0010057: return "AMD_10H_UNK_c001_0057";
1434 case 0xc0010058: return "AMD_10H_MMIO_CFG_BASE_ADDR";
1435 case 0xc0010059: return "AMD_10H_TRAP_CTL?"; /* Undocumented, only one google hit. */
1436 case 0xc001005a: return "AMD_10H_UNK_c001_005a";
1437 case 0xc001005b: return "AMD_10H_UNK_c001_005b";
1438 case 0xc001005c: return "AMD_10H_UNK_c001_005c";
1439 case 0xc001005d: return "AMD_10H_UNK_c001_005d";
1440 case 0xc0010060: return "AMD_K8_BIST_RESULT"; /* BDKG says it as introduced with revision F. */
1441 case 0xc0010061: return "AMD_10H_P_ST_CUR_LIM";
1442 case 0xc0010062: return "AMD_10H_P_ST_CTL";
1443 case 0xc0010063: return "AMD_10H_P_ST_STS";
1444 case 0xc0010064: return "AMD_10H_P_ST_0";
1445 case 0xc0010065: return "AMD_10H_P_ST_1";
1446 case 0xc0010066: return "AMD_10H_P_ST_2";
1447 case 0xc0010067: return "AMD_10H_P_ST_3";
1448 case 0xc0010068: return "AMD_10H_P_ST_4";
1449 case 0xc0010069: return "AMD_10H_P_ST_5";
1450 case 0xc001006a: return "AMD_10H_P_ST_6";
1451 case 0xc001006b: return "AMD_10H_P_ST_7";
1452 case 0xc0010070: return "AMD_10H_COFVID_CTL";
1453 case 0xc0010071: return "AMD_10H_COFVID_STS";
1454 case 0xc0010073: return "AMD_10H_C_ST_IO_BASE_ADDR";
1455 case 0xc0010074: return "AMD_10H_CPU_WD_TMR_CFG";
1456 // case 0xc0010075: return "AMD_15H_APML_TDP_LIM";
1457 // case 0xc0010077: return "AMD_15H_CPU_PWR_IN_TDP";
1458 // case 0xc0010078: return "AMD_15H_PWR_AVG_PERIOD";
1459 // case 0xc0010079: return "AMD_15H_DRAM_CTR_CMD_THR";
1460 // case 0xc0010080: return "AMD_16H_FSFM_ACT_CNT_0";
1461 // case 0xc0010081: return "AMD_16H_FSFM_REF_CNT_0";
1462 case 0xc0010111: return "AMD_K8_SMM_BASE";
1463 case 0xc0010112: return "AMD_K8_SMM_ADDR";
1464 case 0xc0010113: return "AMD_K8_SMM_MASK";
1465 case 0xc0010114: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_K8_VM_CR" : "AMD_K8_UNK_c001_0114";
1466 case 0xc0010115: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_K8_IGNNE" : "AMD_K8_UNK_c001_0115";
1467 case 0xc0010116: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_K8_SMM_CTL" : "AMD_K8_UNK_c001_0116";
1468 case 0xc0010117: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_K8_VM_HSAVE_PA" : "AMD_K8_UNK_c001_0117";
1469 case 0xc0010118: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_10H_VM_LOCK_KEY" : "AMD_K8_UNK_c001_0118";
1470 case 0xc0010119: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_10H_SSM_LOCK_KEY" : "AMD_K8_UNK_c001_0119";
1471 case 0xc001011a: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_10H_LOCAL_SMI_STS" : "AMD_K8_UNK_c001_011a";
1472 case 0xc001011b: return "AMD_K8_UNK_c001_011b";
1473 case 0xc001011c: return "AMD_K8_UNK_c001_011c";
1474 case 0xc0010140: return "AMD_10H_OSVW_ID_LEN";
1475 case 0xc0010141: return "AMD_10H_OSVW_STS";
1476 case 0xc0010200: return "AMD_K8_PERF_CTL_0";
1477 case 0xc0010202: return "AMD_K8_PERF_CTL_1";
1478 case 0xc0010204: return "AMD_K8_PERF_CTL_2";
1479 case 0xc0010206: return "AMD_K8_PERF_CTL_3";
1480 case 0xc0010208: return "AMD_K8_PERF_CTL_4";
1481 case 0xc001020a: return "AMD_K8_PERF_CTL_5";
1482 //case 0xc001020c: return "AMD_K8_PERF_CTL_6";
1483 //case 0xc001020e: return "AMD_K8_PERF_CTL_7";
1484 case 0xc0010201: return "AMD_K8_PERF_CTR_0";
1485 case 0xc0010203: return "AMD_K8_PERF_CTR_1";
1486 case 0xc0010205: return "AMD_K8_PERF_CTR_2";
1487 case 0xc0010207: return "AMD_K8_PERF_CTR_3";
1488 case 0xc0010209: return "AMD_K8_PERF_CTR_4";
1489 case 0xc001020b: return "AMD_K8_PERF_CTR_5";
1490 //case 0xc001020d: return "AMD_K8_PERF_CTR_6";
1491 //case 0xc001020f: return "AMD_K8_PERF_CTR_7";
1492 case 0xc0010230: return "AMD_16H_L2I_PERF_CTL_0";
1493 case 0xc0010232: return "AMD_16H_L2I_PERF_CTL_1";
1494 case 0xc0010234: return "AMD_16H_L2I_PERF_CTL_2";
1495 case 0xc0010236: return "AMD_16H_L2I_PERF_CTL_3";
1496 //case 0xc0010238: return "AMD_16H_L2I_PERF_CTL_4";
1497 //case 0xc001023a: return "AMD_16H_L2I_PERF_CTL_5";
1498 //case 0xc001030c: return "AMD_16H_L2I_PERF_CTL_6";
1499 //case 0xc001023e: return "AMD_16H_L2I_PERF_CTL_7";
1500 case 0xc0010231: return "AMD_16H_L2I_PERF_CTR_0";
1501 case 0xc0010233: return "AMD_16H_L2I_PERF_CTR_1";
1502 case 0xc0010235: return "AMD_16H_L2I_PERF_CTR_2";
1503 case 0xc0010237: return "AMD_16H_L2I_PERF_CTR_3";
1504 //case 0xc0010239: return "AMD_16H_L2I_PERF_CTR_4";
1505 //case 0xc001023b: return "AMD_16H_L2I_PERF_CTR_5";
1506 //case 0xc001023d: return "AMD_16H_L2I_PERF_CTR_6";
1507 //case 0xc001023f: return "AMD_16H_L2I_PERF_CTR_7";
1508 case 0xc0010240: return "AMD_15H_NB_PERF_CTL_0";
1509 case 0xc0010242: return "AMD_15H_NB_PERF_CTL_1";
1510 case 0xc0010244: return "AMD_15H_NB_PERF_CTL_2";
1511 case 0xc0010246: return "AMD_15H_NB_PERF_CTL_3";
1512 //case 0xc0010248: return "AMD_15H_NB_PERF_CTL_4";
1513 //case 0xc001024a: return "AMD_15H_NB_PERF_CTL_5";
1514 //case 0xc001024c: return "AMD_15H_NB_PERF_CTL_6";
1515 //case 0xc001024e: return "AMD_15H_NB_PERF_CTL_7";
1516 case 0xc0010241: return "AMD_15H_NB_PERF_CTR_0";
1517 case 0xc0010243: return "AMD_15H_NB_PERF_CTR_1";
1518 case 0xc0010245: return "AMD_15H_NB_PERF_CTR_2";
1519 case 0xc0010247: return "AMD_15H_NB_PERF_CTR_3";
1520 //case 0xc0010249: return "AMD_15H_NB_PERF_CTR_4";
1521 //case 0xc001024b: return "AMD_15H_NB_PERF_CTR_5";
1522 //case 0xc001024d: return "AMD_15H_NB_PERF_CTR_6";
1523 //case 0xc001024f: return "AMD_15H_NB_PERF_CTR_7";
1524 case 0xc0011000: return "AMD_K7_MCODE_CTL";
1525 case 0xc0011001: return "AMD_K7_APIC_CLUSTER_ID"; /* Mentioned in BKDG (r3.00) for fam16h when describing EBL_CR_POWERON. */
1526 case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD07" : NULL;
1527 case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD06" : NULL;
1528 case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD01" : NULL;
1529 case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_EXT01" : NULL;
1530 case 0xc0011006: return "AMD_K7_DEBUG_STS?";
1531 case 0xc0011007: return "AMD_K7_BH_TRACE_BASE?";
1532 case 0xc0011008: return "AMD_K7_BH_TRACE_PTR?";
1533 case 0xc0011009: return "AMD_K7_BH_TRACE_LIM?";
1534 case 0xc001100a: return "AMD_K7_HDT_CFG?";
1535 case 0xc001100b: return "AMD_K7_FAST_FLUSH_COUNT?";
1536 case 0xc001100c: return "AMD_K7_NODE_ID";
1537 case 0xc001100d: return "AMD_K8_LOGICAL_CPUS_NUM?";
1538 case 0xc001100e: return "AMD_K8_WRMSR_BP?";
1539 case 0xc001100f: return "AMD_K8_WRMSR_BP_MASK?";
1540 case 0xc0011010: return "AMD_K8_BH_TRACE_CTL?";
1541 case 0xc0011011: return "AMD_K8_BH_TRACE_USRD?";
1542 case 0xc0011012: return "AMD_K7_UNK_c001_1012";
1543 case 0xc0011013: return "AMD_K7_UNK_c001_1013";
1544 case 0xc0011014: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP?" : "AMD_K7_MOBIL_DEBUG?";
1545 case 0xc0011015: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP_MASK?" : NULL;
1546 case 0xc0011016: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL?" : NULL;
1547 case 0xc0011017: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL_MASK?" : NULL;
1548 case 0xc0011018: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_CTL?" : NULL;
1549 case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR1_ADDR_MASK" : NULL;
1550 case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR2_ADDR_MASK" : NULL;
1551 case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR3_ADDR_MASK" : NULL;
1552 case 0xc001101d: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_BIST?" : NULL;
1553 case 0xc001101e: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_THERMTRIP_2?" : NULL;
1554 case 0xc001101f: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_CFG?" : NULL;
1555 case 0xc0011020: return "AMD_K7_LS_CFG";
1556 case 0xc0011021: return "AMD_K7_IC_CFG";
1557 case 0xc0011022: return "AMD_K7_DC_CFG";
1558 case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG" : "AMD_K7_BU_CFG";
1559 case 0xc0011024: return "AMD_K7_DEBUG_CTL_2?";
1560 case 0xc0011025: return "AMD_K7_DR0_DATA_MATCH?";
1561 case 0xc0011026: return "AMD_K7_DR0_DATA_MATCH?";
1562 case 0xc0011027: return "AMD_K7_DR0_ADDR_MASK";
1563 case 0xc0011028: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_FP_CFG"
1564 : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1028"
1565 : NULL;
1566 case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_DC_CFG"
1567 : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1029"
1568 : NULL;
1569 case 0xc001102a: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG2"
1570 : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) || g_enmMicroarch > kCpumMicroarch_AMD_15h_End
1571 ? "AMD_10H_BU_CFG2" /* 10h & 16h */ : NULL;
1572 case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG3" : NULL;
1573 case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_EX_CFG" : NULL;
1574 case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_LS_CFG2" : NULL;
1575 case 0xc0011030: return "AMD_10H_IBS_FETCH_CTL";
1576 case 0xc0011031: return "AMD_10H_IBS_FETCH_LIN_ADDR";
1577 case 0xc0011032: return "AMD_10H_IBS_FETCH_PHYS_ADDR";
1578 case 0xc0011033: return "AMD_10H_IBS_OP_EXEC_CTL";
1579 case 0xc0011034: return "AMD_10H_IBS_OP_RIP";
1580 case 0xc0011035: return "AMD_10H_IBS_OP_DATA";
1581 case 0xc0011036: return "AMD_10H_IBS_OP_DATA2";
1582 case 0xc0011037: return "AMD_10H_IBS_OP_DATA3";
1583 case 0xc0011038: return "AMD_10H_IBS_DC_LIN_ADDR";
1584 case 0xc0011039: return "AMD_10H_IBS_DC_PHYS_ADDR";
1585 case 0xc001103a: return "AMD_10H_IBS_CTL";
1586 case 0xc001103b: return "AMD_14H_IBS_BR_TARGET";
1587
1588 case 0xc0011040: return "AMD_15H_UNK_c001_1040";
1589 case 0xc0011041: return "AMD_15H_UNK_c001_1041";
1590 case 0xc0011042: return "AMD_15H_UNK_c001_1042";
1591 case 0xc0011043: return "AMD_15H_UNK_c001_1043";
1592 case 0xc0011044: return "AMD_15H_UNK_c001_1044";
1593 case 0xc0011045: return "AMD_15H_UNK_c001_1045";
1594 case 0xc0011046: return "AMD_15H_UNK_c001_1046";
1595 case 0xc0011047: return "AMD_15H_UNK_c001_1047";
1596 case 0xc0011048: return "AMD_15H_UNK_c001_1048";
1597 case 0xc0011049: return "AMD_15H_UNK_c001_1049";
1598 case 0xc001104a: return "AMD_15H_UNK_c001_104a";
1599 case 0xc001104b: return "AMD_15H_UNK_c001_104b";
1600 case 0xc001104c: return "AMD_15H_UNK_c001_104c";
1601 case 0xc001104d: return "AMD_15H_UNK_c001_104d";
1602 case 0xc001104e: return "AMD_15H_UNK_c001_104e";
1603 case 0xc001104f: return "AMD_15H_UNK_c001_104f";
1604 case 0xc0011050: return "AMD_15H_UNK_c001_1050";
1605 case 0xc0011051: return "AMD_15H_UNK_c001_1051";
1606 case 0xc0011052: return "AMD_15H_UNK_c001_1052";
1607 case 0xc0011053: return "AMD_15H_UNK_c001_1053";
1608 case 0xc0011054: return "AMD_15H_UNK_c001_1054";
1609 case 0xc0011055: return "AMD_15H_UNK_c001_1055";
1610 case 0xc0011056: return "AMD_15H_UNK_c001_1056";
1611 case 0xc0011057: return "AMD_15H_UNK_c001_1057";
1612 case 0xc0011058: return "AMD_15H_UNK_c001_1058";
1613 case 0xc0011059: return "AMD_15H_UNK_c001_1059";
1614 case 0xc001105a: return "AMD_15H_UNK_c001_105a";
1615 case 0xc001105b: return "AMD_15H_UNK_c001_105b";
1616 case 0xc001105c: return "AMD_15H_UNK_c001_105c";
1617 case 0xc001105d: return "AMD_15H_UNK_c001_105d";
1618 case 0xc001105e: return "AMD_15H_UNK_c001_105e";
1619 case 0xc001105f: return "AMD_15H_UNK_c001_105f";
1620 case 0xc0011060: return "AMD_15H_UNK_c001_1060";
1621 case 0xc0011061: return "AMD_15H_UNK_c001_1061";
1622 case 0xc0011062: return "AMD_15H_UNK_c001_1062";
1623 case 0xc0011063: return "AMD_15H_UNK_c001_1063";
1624 case 0xc0011064: return "AMD_15H_UNK_c001_1064";
1625 case 0xc0011065: return "AMD_15H_UNK_c001_1065";
1626 case 0xc0011066: return "AMD_15H_UNK_c001_1066";
1627 case 0xc0011067: return "AMD_15H_UNK_c001_1067";
1628 case 0xc0011068: return "AMD_15H_UNK_c001_1068";
1629 case 0xc0011069: return "AMD_15H_UNK_c001_1069";
1630 case 0xc001106a: return "AMD_15H_UNK_c001_106a";
1631 case 0xc001106b: return "AMD_15H_UNK_c001_106b";
1632 case 0xc001106c: return "AMD_15H_UNK_c001_106c";
1633 case 0xc001106d: return "AMD_15H_UNK_c001_106d";
1634 case 0xc001106e: return "AMD_15H_UNK_c001_106e";
1635 case 0xc001106f: return "AMD_15H_UNK_c001_106f";
1636 case 0xc0011070: return "AMD_15H_UNK_c001_1070"; /* coreboot defines this, but with a numerical name. */
1637 case 0xc0011071: return "AMD_15H_UNK_c001_1071";
1638 case 0xc0011072: return "AMD_15H_UNK_c001_1072";
1639 case 0xc0011073: return "AMD_15H_UNK_c001_1073";
1640 case 0xc0011080: return "AMD_15H_UNK_c001_1080";
1641 }
1642
1643 /*
1644 * Uncore stuff on Sandy. Putting it here to avoid ugly microarch checks for each register.
1645 * Note! These are found on model 42 (2a) but not 45 (2d), the latter is the EP variant.
1646 */
1647 if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_SandyBridge)
1648 switch (uMsr)
1649 {
1650 case 0x00000700: return "MSR_UNC_CBO_0_PERFEVTSEL0";
1651 case 0x00000701: return "MSR_UNC_CBO_0_PERFEVTSEL1";
1652 case 0x00000702: return "MSR_UNC_CBO_0_PERFEVTSEL2?";
1653 case 0x00000703: return "MSR_UNC_CBO_0_PERFEVTSEL3?";
1654 case 0x00000704: return "MSR_UNC_CBO_0_UNK_4";
1655 case 0x00000705: return "MSR_UNC_CBO_0_UNK_5";
1656 case 0x00000706: return "MSR_UNC_CBO_0_PER_CTR0";
1657 case 0x00000707: return "MSR_UNC_CBO_0_PER_CTR1";
1658 case 0x00000708: return "MSR_UNC_CBO_0_PER_CTR2?";
1659 case 0x00000709: return "MSR_UNC_CBO_0_PER_CTR3?";
1660 case 0x00000710: return "MSR_UNC_CBO_1_PERFEVTSEL0";
1661 case 0x00000711: return "MSR_UNC_CBO_1_PERFEVTSEL1";
1662 case 0x00000712: return "MSR_UNC_CBO_1_PERFEVTSEL2?";
1663 case 0x00000713: return "MSR_UNC_CBO_1_PERFEVTSEL3?";
1664 case 0x00000714: return "MSR_UNC_CBO_1_UNK_4";
1665 case 0x00000715: return "MSR_UNC_CBO_1_UNK_5";
1666 case 0x00000716: return "MSR_UNC_CBO_1_PER_CTR0";
1667 case 0x00000717: return "MSR_UNC_CBO_1_PER_CTR1";
1668 case 0x00000718: return "MSR_UNC_CBO_1_PER_CTR2?";
1669 case 0x00000719: return "MSR_UNC_CBO_1_PER_CTR3?";
1670 case 0x00000720: return "MSR_UNC_CBO_2_PERFEVTSEL0";
1671 case 0x00000721: return "MSR_UNC_CBO_2_PERFEVTSEL1";
1672 case 0x00000722: return "MSR_UNC_CBO_2_PERFEVTSEL2?";
1673 case 0x00000723: return "MSR_UNC_CBO_2_PERFEVTSEL3?";
1674 case 0x00000724: return "MSR_UNC_CBO_2_UNK_4";
1675 case 0x00000725: return "MSR_UNC_CBO_2_UNK_5";
1676 case 0x00000726: return "MSR_UNC_CBO_2_PER_CTR0";
1677 case 0x00000727: return "MSR_UNC_CBO_2_PER_CTR1";
1678 case 0x00000728: return "MSR_UNC_CBO_2_PER_CTR2?";
1679 case 0x00000729: return "MSR_UNC_CBO_2_PER_CTR3?";
1680 case 0x00000730: return "MSR_UNC_CBO_3_PERFEVTSEL0";
1681 case 0x00000731: return "MSR_UNC_CBO_3_PERFEVTSEL1";
1682 case 0x00000732: return "MSR_UNC_CBO_3_PERFEVTSEL2?";
1683 case 0x00000733: return "MSR_UNC_CBO_3_PERFEVTSEL3?";
1684 case 0x00000734: return "MSR_UNC_CBO_3_UNK_4";
1685 case 0x00000735: return "MSR_UNC_CBO_3_UNK_5";
1686 case 0x00000736: return "MSR_UNC_CBO_3_PER_CTR0";
1687 case 0x00000737: return "MSR_UNC_CBO_3_PER_CTR1";
1688 case 0x00000738: return "MSR_UNC_CBO_3_PER_CTR2?";
1689 case 0x00000739: return "MSR_UNC_CBO_3_PER_CTR3?";
1690 case 0x00000740: return "MSR_UNC_CBO_4_PERFEVTSEL0?";
1691 case 0x00000741: return "MSR_UNC_CBO_4_PERFEVTSEL1?";
1692 case 0x00000742: return "MSR_UNC_CBO_4_PERFEVTSEL2?";
1693 case 0x00000743: return "MSR_UNC_CBO_4_PERFEVTSEL3?";
1694 case 0x00000744: return "MSR_UNC_CBO_4_UNK_4";
1695 case 0x00000745: return "MSR_UNC_CBO_4_UNK_5";
1696 case 0x00000746: return "MSR_UNC_CBO_4_PER_CTR0?";
1697 case 0x00000747: return "MSR_UNC_CBO_4_PER_CTR1?";
1698 case 0x00000748: return "MSR_UNC_CBO_4_PER_CTR2?";
1699 case 0x00000749: return "MSR_UNC_CBO_4_PER_CTR3?";
1700
1701 }
1702
1703 /*
1704 * Bunch of unknown sandy bridge registers. They might seem like the
1705 * nehalem based xeon stuff, but the layout doesn't match. I bet it's the
1706 * same kind of registes though (i.e. uncore (UNC)).
1707 *
1708 * Kudos to Intel for keeping these a secret! Many thanks guys!!
1709 */
1710 if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_SandyBridge)
1711 switch (uMsr)
1712 {
1713 case 0x00000a00: return "I7_SB_UNK_0000_0a00"; case 0x00000a01: return "I7_SB_UNK_0000_0a01";
1714 case 0x00000a02: return "I7_SB_UNK_0000_0a02";
1715 case 0x00000c00: return "I7_SB_UNK_0000_0c00"; case 0x00000c01: return "I7_SB_UNK_0000_0c01";
1716 case 0x00000c06: return "I7_SB_UNK_0000_0c06"; case 0x00000c08: return "I7_SB_UNK_0000_0c08";
1717 case 0x00000c09: return "I7_SB_UNK_0000_0c09"; case 0x00000c10: return "I7_SB_UNK_0000_0c10";
1718 case 0x00000c11: return "I7_SB_UNK_0000_0c11"; case 0x00000c14: return "I7_SB_UNK_0000_0c14";
1719 case 0x00000c15: return "I7_SB_UNK_0000_0c15"; case 0x00000c16: return "I7_SB_UNK_0000_0c16";
1720 case 0x00000c17: return "I7_SB_UNK_0000_0c17"; case 0x00000c24: return "I7_SB_UNK_0000_0c24";
1721 case 0x00000c30: return "I7_SB_UNK_0000_0c30"; case 0x00000c31: return "I7_SB_UNK_0000_0c31";
1722 case 0x00000c32: return "I7_SB_UNK_0000_0c32"; case 0x00000c33: return "I7_SB_UNK_0000_0c33";
1723 case 0x00000c34: return "I7_SB_UNK_0000_0c34"; case 0x00000c35: return "I7_SB_UNK_0000_0c35";
1724 case 0x00000c36: return "I7_SB_UNK_0000_0c36"; case 0x00000c37: return "I7_SB_UNK_0000_0c37";
1725 case 0x00000c38: return "I7_SB_UNK_0000_0c38"; case 0x00000c39: return "I7_SB_UNK_0000_0c39";
1726 case 0x00000d04: return "I7_SB_UNK_0000_0d04";
1727 case 0x00000d10: return "I7_SB_UNK_0000_0d10"; case 0x00000d11: return "I7_SB_UNK_0000_0d11";
1728 case 0x00000d12: return "I7_SB_UNK_0000_0d12"; case 0x00000d13: return "I7_SB_UNK_0000_0d13";
1729 case 0x00000d14: return "I7_SB_UNK_0000_0d14"; case 0x00000d15: return "I7_SB_UNK_0000_0d15";
1730 case 0x00000d16: return "I7_SB_UNK_0000_0d16"; case 0x00000d17: return "I7_SB_UNK_0000_0d17";
1731 case 0x00000d18: return "I7_SB_UNK_0000_0d18"; case 0x00000d19: return "I7_SB_UNK_0000_0d19";
1732 case 0x00000d24: return "I7_SB_UNK_0000_0d24";
1733 case 0x00000d30: return "I7_SB_UNK_0000_0d30"; case 0x00000d31: return "I7_SB_UNK_0000_0d31";
1734 case 0x00000d32: return "I7_SB_UNK_0000_0d32"; case 0x00000d33: return "I7_SB_UNK_0000_0d33";
1735 case 0x00000d34: return "I7_SB_UNK_0000_0d34"; case 0x00000d35: return "I7_SB_UNK_0000_0d35";
1736 case 0x00000d36: return "I7_SB_UNK_0000_0d36"; case 0x00000d37: return "I7_SB_UNK_0000_0d37";
1737 case 0x00000d38: return "I7_SB_UNK_0000_0d38"; case 0x00000d39: return "I7_SB_UNK_0000_0d39";
1738 case 0x00000d44: return "I7_SB_UNK_0000_0d44";
1739 case 0x00000d50: return "I7_SB_UNK_0000_0d50"; case 0x00000d51: return "I7_SB_UNK_0000_0d51";
1740 case 0x00000d52: return "I7_SB_UNK_0000_0d52"; case 0x00000d53: return "I7_SB_UNK_0000_0d53";
1741 case 0x00000d54: return "I7_SB_UNK_0000_0d54"; case 0x00000d55: return "I7_SB_UNK_0000_0d55";
1742 case 0x00000d56: return "I7_SB_UNK_0000_0d56"; case 0x00000d57: return "I7_SB_UNK_0000_0d57";
1743 case 0x00000d58: return "I7_SB_UNK_0000_0d58"; case 0x00000d59: return "I7_SB_UNK_0000_0d59";
1744 case 0x00000d64: return "I7_SB_UNK_0000_0d64";
1745 case 0x00000d70: return "I7_SB_UNK_0000_0d70"; case 0x00000d71: return "I7_SB_UNK_0000_0d71";
1746 case 0x00000d72: return "I7_SB_UNK_0000_0d72"; case 0x00000d73: return "I7_SB_UNK_0000_0d73";
1747 case 0x00000d74: return "I7_SB_UNK_0000_0d74"; case 0x00000d75: return "I7_SB_UNK_0000_0d75";
1748 case 0x00000d76: return "I7_SB_UNK_0000_0d76"; case 0x00000d77: return "I7_SB_UNK_0000_0d77";
1749 case 0x00000d78: return "I7_SB_UNK_0000_0d78"; case 0x00000d79: return "I7_SB_UNK_0000_0d79";
1750 case 0x00000d84: return "I7_SB_UNK_0000_0d84";
1751 case 0x00000d90: return "I7_SB_UNK_0000_0d90"; case 0x00000d91: return "I7_SB_UNK_0000_0d91";
1752 case 0x00000d92: return "I7_SB_UNK_0000_0d92"; case 0x00000d93: return "I7_SB_UNK_0000_0d93";
1753 case 0x00000d94: return "I7_SB_UNK_0000_0d94"; case 0x00000d95: return "I7_SB_UNK_0000_0d95";
1754 case 0x00000d96: return "I7_SB_UNK_0000_0d96"; case 0x00000d97: return "I7_SB_UNK_0000_0d97";
1755 case 0x00000d98: return "I7_SB_UNK_0000_0d98"; case 0x00000d99: return "I7_SB_UNK_0000_0d99";
1756 case 0x00000da4: return "I7_SB_UNK_0000_0da4";
1757 case 0x00000db0: return "I7_SB_UNK_0000_0db0"; case 0x00000db1: return "I7_SB_UNK_0000_0db1";
1758 case 0x00000db2: return "I7_SB_UNK_0000_0db2"; case 0x00000db3: return "I7_SB_UNK_0000_0db3";
1759 case 0x00000db4: return "I7_SB_UNK_0000_0db4"; case 0x00000db5: return "I7_SB_UNK_0000_0db5";
1760 case 0x00000db6: return "I7_SB_UNK_0000_0db6"; case 0x00000db7: return "I7_SB_UNK_0000_0db7";
1761 case 0x00000db8: return "I7_SB_UNK_0000_0db8"; case 0x00000db9: return "I7_SB_UNK_0000_0db9";
1762 }
1763
1764 /*
1765 * Ditto for ivy bridge (observed on the i5-3570). There are some haswell
1766 * and sandybridge related docs on registers in this ares, but either
1767 * things are different for ivy or they're very incomplete. Again, kudos
1768 * to intel!
1769 */
1770 if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_IvyBridge)
1771 switch (uMsr)
1772 {
1773 case 0x00000700: return "I7_IB_UNK_0000_0700"; case 0x00000701: return "I7_IB_UNK_0000_0701";
1774 case 0x00000702: return "I7_IB_UNK_0000_0702"; case 0x00000703: return "I7_IB_UNK_0000_0703";
1775 case 0x00000704: return "I7_IB_UNK_0000_0704"; case 0x00000705: return "I7_IB_UNK_0000_0705";
1776 case 0x00000706: return "I7_IB_UNK_0000_0706"; case 0x00000707: return "I7_IB_UNK_0000_0707";
1777 case 0x00000708: return "I7_IB_UNK_0000_0708"; case 0x00000709: return "I7_IB_UNK_0000_0709";
1778 case 0x00000710: return "I7_IB_UNK_0000_0710"; case 0x00000711: return "I7_IB_UNK_0000_0711";
1779 case 0x00000712: return "I7_IB_UNK_0000_0712"; case 0x00000713: return "I7_IB_UNK_0000_0713";
1780 case 0x00000714: return "I7_IB_UNK_0000_0714"; case 0x00000715: return "I7_IB_UNK_0000_0715";
1781 case 0x00000716: return "I7_IB_UNK_0000_0716"; case 0x00000717: return "I7_IB_UNK_0000_0717";
1782 case 0x00000718: return "I7_IB_UNK_0000_0718"; case 0x00000719: return "I7_IB_UNK_0000_0719";
1783 case 0x00000720: return "I7_IB_UNK_0000_0720"; case 0x00000721: return "I7_IB_UNK_0000_0721";
1784 case 0x00000722: return "I7_IB_UNK_0000_0722"; case 0x00000723: return "I7_IB_UNK_0000_0723";
1785 case 0x00000724: return "I7_IB_UNK_0000_0724"; case 0x00000725: return "I7_IB_UNK_0000_0725";
1786 case 0x00000726: return "I7_IB_UNK_0000_0726"; case 0x00000727: return "I7_IB_UNK_0000_0727";
1787 case 0x00000728: return "I7_IB_UNK_0000_0728"; case 0x00000729: return "I7_IB_UNK_0000_0729";
1788 case 0x00000730: return "I7_IB_UNK_0000_0730"; case 0x00000731: return "I7_IB_UNK_0000_0731";
1789 case 0x00000732: return "I7_IB_UNK_0000_0732"; case 0x00000733: return "I7_IB_UNK_0000_0733";
1790 case 0x00000734: return "I7_IB_UNK_0000_0734"; case 0x00000735: return "I7_IB_UNK_0000_0735";
1791 case 0x00000736: return "I7_IB_UNK_0000_0736"; case 0x00000737: return "I7_IB_UNK_0000_0737";
1792 case 0x00000738: return "I7_IB_UNK_0000_0738"; case 0x00000739: return "I7_IB_UNK_0000_0739";
1793 case 0x00000740: return "I7_IB_UNK_0000_0740"; case 0x00000741: return "I7_IB_UNK_0000_0741";
1794 case 0x00000742: return "I7_IB_UNK_0000_0742"; case 0x00000743: return "I7_IB_UNK_0000_0743";
1795 case 0x00000744: return "I7_IB_UNK_0000_0744"; case 0x00000745: return "I7_IB_UNK_0000_0745";
1796 case 0x00000746: return "I7_IB_UNK_0000_0746"; case 0x00000747: return "I7_IB_UNK_0000_0747";
1797 case 0x00000748: return "I7_IB_UNK_0000_0748"; case 0x00000749: return "I7_IB_UNK_0000_0749";
1798
1799 }
1800 return NULL;
1801}
1802
1803
1804/**
1805 * Gets the name of an MSR.
1806 *
1807 * This may return a static buffer, so the content should only be considered
1808 * valid until the next time this function is called!.
1809 *
1810 * @returns MSR name.
1811 * @param uMsr The MSR in question.
1812 */
1813static const char *getMsrName(uint32_t uMsr)
1814{
1815 const char *pszReadOnly = getMsrNameHandled(uMsr);
1816 if (pszReadOnly)
1817 return pszReadOnly;
1818
1819 /*
1820 * This MSR needs looking into, return a TODO_XXXX_XXXX name.
1821 */
1822 static char s_szBuf[32];
1823 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
1824 return s_szBuf;
1825}
1826
1827
1828
1829/**
1830 * Gets the name of an MSR range.
1831 *
1832 * This may return a static buffer, so the content should only be considered
1833 * valid until the next time this function is called!.
1834 *
1835 * @returns MSR name.
1836 * @param uMsr The first MSR in the range.
1837 */
1838static const char *getMsrRangeName(uint32_t uMsr)
1839{
1840 switch (uMsr)
1841 {
1842 case 0x00000040:
1843 return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_n_FROM_IP" : "MSR_LASTBRANCH_n";
1844 case 0x00000060:
1845 if (g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah)
1846 return "MSR_LASTBRANCH_n_TO_IP";
1847 break;
1848
1849 case 0x000003f8:
1850 case 0x000003f9:
1851 case 0x000003fa:
1852 return "I7_MSR_PKG_Cn_RESIDENCY";
1853 case 0x000003fc:
1854 case 0x000003fd:
1855 case 0x000003fe:
1856 return "I7_MSR_CORE_Cn_RESIDENCY";
1857
1858 case 0x00000400:
1859 return "IA32_MCi_CTL_STATUS_ADDR_MISC";
1860
1861 case 0x00000680:
1862 return "MSR_LASTBRANCH_n_FROM_IP";
1863 case 0x000006c0:
1864 return "MSR_LASTBRANCH_n_TO_IP";
1865
1866 case 0x00000800: case 0x00000801: case 0x00000802: case 0x00000803:
1867 case 0x00000804: case 0x00000805: case 0x00000806: case 0x00000807:
1868 case 0x00000808: case 0x00000809: case 0x0000080a: case 0x0000080b:
1869 case 0x0000080c: case 0x0000080d: case 0x0000080e: case 0x0000080f:
1870 return "IA32_X2APIC_n";
1871 }
1872
1873 static char s_szBuf[96];
1874 const char *pszReadOnly = getMsrNameHandled(uMsr);
1875 if (pszReadOnly)
1876 {
1877 /*
1878 * Replace the last char with 'n'.
1879 */
1880 RTStrCopy(s_szBuf, sizeof(s_szBuf), pszReadOnly);
1881 size_t off = strlen(s_szBuf);
1882 if (off > 0)
1883 off--;
1884 if (off + 1 < sizeof(s_szBuf))
1885 {
1886 s_szBuf[off] = 'n';
1887 s_szBuf[off + 1] = '\0';
1888 }
1889 }
1890 else
1891 {
1892 /*
1893 * This MSR needs looking into, return a TODO_XXXX_XXXX_n name.
1894 */
1895 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x_n", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
1896 }
1897 return s_szBuf;
1898}
1899
1900
1901/**
1902 * Returns the function name for MSRs that have one or two.
1903 *
1904 * @returns Function name if applicable, NULL if not.
1905 * @param uMsr The MSR in question.
1906 * @param pfTakesValue Whether this MSR function takes a value or not.
1907 * Optional.
1908 */
1909static const char *getMsrFnName(uint32_t uMsr, bool *pfTakesValue)
1910{
1911 bool fTmp;
1912 if (!pfTakesValue)
1913 pfTakesValue = &fTmp;
1914
1915 *pfTakesValue = false;
1916
1917 switch (uMsr)
1918 {
1919 case 0x00000000: return "Ia32P5McAddr";
1920 case 0x00000001: return "Ia32P5McType";
1921 case 0x00000006:
1922 if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
1923 return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
1924 return "Ia32MonitorFilterLineSize";
1925 case 0x00000010: return "Ia32TimestampCounter";
1926 case 0x00000017: *pfTakesValue = true; return "Ia32PlatformId";
1927 case 0x0000001b: return "Ia32ApicBase";
1928 case 0x0000002a: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcHardPowerOn" : "IntelEblCrPowerOn";
1929 case 0x0000002b: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcSoftPowerOn" : NULL;
1930 case 0x0000002c: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcFrequencyId" : NULL;
1931 //case 0x00000033: return "IntelTestCtl";
1932 case 0x00000034: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch)
1933 || CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(g_enmMicroarch)
1934 ? "IntelI7SmiCount" : NULL;
1935 case 0x00000035: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelI7CoreThreadCount" : NULL;
1936 case 0x0000003a: return "Ia32FeatureControl";
1937
1938 case 0x00000040:
1939 case 0x00000041:
1940 case 0x00000042:
1941 case 0x00000043:
1942 case 0x00000044:
1943 case 0x00000045:
1944 case 0x00000046:
1945 case 0x00000047:
1946 return "IntelLastBranchFromToN";
1947
1948 case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON
1949 ? "AmdK8PatchLevel" : "Ia32BiosSignId";
1950 case 0x0000009b: return "Ia32SmmMonitorCtl";
1951
1952 case 0x000000a8:
1953 case 0x000000a9:
1954 case 0x000000aa:
1955 case 0x000000ab:
1956 case 0x000000ac:
1957 case 0x000000ad:
1958 *pfTakesValue = true;
1959 return "IntelCore2EmttmCrTablesN";
1960
1961 case 0x000000c1:
1962 case 0x000000c2:
1963 case 0x000000c3:
1964 case 0x000000c4:
1965 return "Ia32PmcN";
1966 case 0x000000c5:
1967 case 0x000000c6:
1968 case 0x000000c7:
1969 case 0x000000c8:
1970 if (g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First)
1971 return "Ia32PmcN";
1972 return NULL;
1973
1974 case 0x000000cd: *pfTakesValue = true; return "IntelP6FsbFrequency";
1975 case 0x000000ce: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelPlatformInfo" : NULL;
1976 case 0x000000e2: return "IntelPkgCStConfigControl";
1977 case 0x000000e3: return "IntelCore2SmmCStMiscInfo";
1978 case 0x000000e4: return "IntelPmgIoCaptureBase";
1979 case 0x000000e7: return "Ia32MPerf";
1980 case 0x000000e8: return "Ia32APerf";
1981 case 0x000000ee: return "IntelCore1ExtConfig";
1982 case 0x000000fe: *pfTakesValue = true; return "Ia32MtrrCap";
1983 case 0x00000119: *pfTakesValue = true; return "IntelBblCrCtl";
1984 case 0x0000011e: *pfTakesValue = true; return "IntelBblCrCtl3";
1985
1986 case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
1987 || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
1988 ? "IntelCpuId1FeatureMaskEcdx" : NULL;
1989 case 0x00000131: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
1990 || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
1991 ? "IntelCpuId80000001FeatureMaskEcdx" : NULL;
1992 case 0x00000132: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1993 ? "IntelCpuId1FeatureMaskEax" : NULL;
1994 case 0x00000133: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1995 ? "IntelCpuId1FeatureMaskEcdx" : NULL;
1996 case 0x00000134: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1997 ? "IntelCpuId80000001FeatureMaskEcdx" : NULL;
1998 case 0x0000013c: return "IntelI7SandyAesNiCtl";
1999 case 0x0000015f: return "IntelCore1DtsCalControl";
2000 case 0x00000174: return "Ia32SysEnterCs";
2001 case 0x00000175: return "Ia32SysEnterEsp";
2002 case 0x00000176: return "Ia32SysEnterEip";
2003 case 0x00000179: *pfTakesValue = true; return "Ia32McgCap";
2004 case 0x0000017a: return "Ia32McgStatus";
2005 case 0x0000017b: return "Ia32McgCtl";
2006 case 0x0000017f: return "IntelI7SandyErrorControl"; /* SandyBridge. */
2007 case 0x00000186: return "Ia32PerfEvtSelN";
2008 case 0x00000187: return "Ia32PerfEvtSelN";
2009 case 0x00000193: return /*g_fIntelNetBurst ? NULL :*/ NULL /* Core2_Penryn. */;
2010 case 0x00000194: if (g_fIntelNetBurst) break; *pfTakesValue = true; return "IntelFlexRatio";
2011 case 0x00000198: *pfTakesValue = true; return "Ia32PerfStatus";
2012 case 0x00000199: *pfTakesValue = true; return "Ia32PerfCtl";
2013 case 0x0000019a: *pfTakesValue = true; return "Ia32ClockModulation";
2014 case 0x0000019b: *pfTakesValue = true; return "Ia32ThermInterrupt";
2015 case 0x0000019c: *pfTakesValue = true; return "Ia32ThermStatus";
2016 case 0x0000019d: *pfTakesValue = true; return "Ia32Therm2Ctl";
2017 case 0x000001a0: *pfTakesValue = true; return "Ia32MiscEnable";
2018 case 0x000001a2: *pfTakesValue = true; return "IntelI7TemperatureTarget";
2019 case 0x000001a6: return "IntelI7MsrOffCoreResponseN";
2020 case 0x000001a7: return "IntelI7MsrOffCoreResponseN";
2021 case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelI7MiscPwrMgmt" : NULL /*"P6PicSensCfg"*/;
2022 case 0x000001ad: *pfTakesValue = true; return "IntelI7TurboRatioLimit"; /* SandyBridge+, Silvermount+ */
2023 case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "IntelI7LbrSelect" : NULL;
2024 case 0x000001c9: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
2025 && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
2026 ? "IntelLastBranchTos" : NULL /* Pentium M Dothan seems to have something else here. */;
2027 case 0x000001d7: return g_fIntelNetBurst ? "P6LastIntFromIp" : NULL;
2028 case 0x000001d8: return g_fIntelNetBurst ? "P6LastIntToIp" : NULL;
2029 case 0x000001d9: return "Ia32DebugCtl";
2030 case 0x000001da: return g_fIntelNetBurst ? "IntelLastBranchTos" : NULL;
2031 case 0x000001db: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastBranchFromIp";
2032 case 0x000001dc: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastBranchToIp";
2033 case 0x000001dd: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastIntFromIp";
2034 case 0x000001de: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastIntToIp";
2035 case 0x000001f0: return "IntelI7VirtualLegacyWireCap"; /* SandyBridge. */
2036 case 0x000001f2: return "Ia32SmrrPhysBase";
2037 case 0x000001f3: return "Ia32SmrrPhysMask";
2038 case 0x000001f8: return "Ia32PlatformDcaCap";
2039 case 0x000001f9: return "Ia32CpuDcaCap";
2040 case 0x000001fa: return "Ia32Dca0Cap";
2041 case 0x000001fc: return "IntelI7PowerCtl";
2042
2043 case 0x00000200: case 0x00000202: case 0x00000204: case 0x00000206:
2044 case 0x00000208: case 0x0000020a: case 0x0000020c: case 0x0000020e:
2045 case 0x00000210: case 0x00000212: case 0x00000214: case 0x00000216:
2046 case 0x00000218: case 0x0000021a: case 0x0000021c: case 0x0000021e:
2047 return "Ia32MtrrPhysBaseN";
2048 case 0x00000201: case 0x00000203: case 0x00000205: case 0x00000207:
2049 case 0x00000209: case 0x0000020b: case 0x0000020d: case 0x0000020f:
2050 case 0x00000211: case 0x00000213: case 0x00000215: case 0x00000217:
2051 case 0x00000219: case 0x0000021b: case 0x0000021d: case 0x0000021f:
2052 return "Ia32MtrrPhysMaskN";
2053 case 0x00000250:
2054 case 0x00000258: case 0x00000259:
2055 case 0x00000268: case 0x00000269: case 0x0000026a: case 0x0000026b:
2056 case 0x0000026c: case 0x0000026d: case 0x0000026e: case 0x0000026f:
2057 return "Ia32MtrrFixed";
2058 case 0x00000277: *pfTakesValue = true; return "Ia32Pat";
2059
2060 case 0x00000280: case 0x00000281: case 0x00000282: case 0x00000283:
2061 case 0x00000284: case 0x00000285: case 0x00000286: case 0x00000287:
2062 case 0x00000288: case 0x00000289: case 0x0000028a: case 0x0000028b:
2063 case 0x0000028c: case 0x0000028d: case 0x0000028e: case 0x0000028f:
2064 case 0x00000290: case 0x00000291: case 0x00000292: case 0x00000293:
2065 case 0x00000294: case 0x00000295: //case 0x00000296: case 0x00000297:
2066 //case 0x00000298: case 0x00000299: case 0x0000029a: case 0x0000029b:
2067 //case 0x0000029c: case 0x0000029d: case 0x0000029e: case 0x0000029f:
2068 return "Ia32McNCtl2";
2069
2070 case 0x000002ff: return "Ia32MtrrDefType";
2071 //case 0x00000305: return g_fIntelNetBurst ? TODO : NULL;
2072 case 0x00000309: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
2073 case 0x0000030a: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
2074 case 0x0000030b: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
2075 case 0x00000345: *pfTakesValue = true; return "Ia32PerfCapabilities";
2076 /* Note! Lots of P4 MSR 0x00000360..0x00000371. */
2077 case 0x0000038d: return "Ia32FixedCtrCtrl";
2078 case 0x0000038e: *pfTakesValue = true; return "Ia32PerfGlobalStatus";
2079 case 0x0000038f: return "Ia32PerfGlobalCtrl";
2080 case 0x00000390: return "Ia32PerfGlobalOvfCtrl";
2081 case 0x00000391: return "IntelI7UncPerfGlobalCtrl"; /* S,H,X */
2082 case 0x00000392: return "IntelI7UncPerfGlobalStatus"; /* S,H,X */
2083 case 0x00000393: return "IntelI7UncPerfGlobalOvfCtrl"; /* X. ASSUMING this is the same on sandybridge and later. */
2084 case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtr" /* X */ : "IntelI7UncPerfFixedCtrCtrl"; /* >= S,H */
2085 case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtrCtrl" /* X*/ : "IntelI7UncPerfFixedCtr"; /* >= S,H */
2086 case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncAddrOpcodeMatch" /* X */ : "IntelI7UncCBoxConfig"; /* >= S,H */
2087 case 0x0000039c: return "IntelI7SandyPebsNumAlt";
2088 /* Note! Lots of P4 MSR 0x000003a0..0x000003e1. */
2089 case 0x000003b0: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfCtrN"; /* >= S,H */
2090 case 0x000003b1: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfCtrN"; /* >= S,H */
2091 case 0x000003b2: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfEvtSelN"; /* >= S,H */
2092 case 0x000003b3: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfEvtSelN"; /* >= S,H */
2093 case 0x000003b4: case 0x000003b5: case 0x000003b6: case 0x000003b7:
2094 return g_fIntelNetBurst ? NULL : "IntelI7UncPmcN";
2095 case 0x000003c0: case 0x000003c1: case 0x000003c2: case 0x000003c3:
2096 case 0x000003c4: case 0x000003c5: case 0x000003c6: case 0x000003c7:
2097 return g_fIntelNetBurst ? NULL : "IntelI7UncPerfEvtSelN";
2098 case 0x000003f1: return "Ia32PebsEnable";
2099 case 0x000003f6: return g_fIntelNetBurst ? NULL /*??*/ : "IntelI7PebsLdLat";
2100 case 0x000003f8: return g_fIntelNetBurst ? NULL : "IntelI7PkgCnResidencyN";
2101 case 0x000003f9: return "IntelI7PkgCnResidencyN";
2102 case 0x000003fa: return "IntelI7PkgCnResidencyN";
2103 case 0x000003fc: return "IntelI7CoreCnResidencyN";
2104 case 0x000003fd: return "IntelI7CoreCnResidencyN";
2105 case 0x000003fe: return "IntelI7CoreCnResidencyN";
2106
2107 case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "IntelCpuId1FeatureMaskEcdx" : NULL;
2108 case 0x00000480: *pfTakesValue = true; return "Ia32VmxBasic";
2109 case 0x00000481: *pfTakesValue = true; return "Ia32VmxPinbasedCtls";
2110 case 0x00000482: *pfTakesValue = true; return "Ia32VmxProcbasedCtls";
2111 case 0x00000483: *pfTakesValue = true; return "Ia32VmxExitCtls";
2112 case 0x00000484: *pfTakesValue = true; return "Ia32VmxEntryCtls";
2113 case 0x00000485: *pfTakesValue = true; return "Ia32VmxMisc";
2114 case 0x00000486: *pfTakesValue = true; return "Ia32VmxCr0Fixed0";
2115 case 0x00000487: *pfTakesValue = true; return "Ia32VmxCr0Fixed1";
2116 case 0x00000488: *pfTakesValue = true; return "Ia32VmxCr4Fixed0";
2117 case 0x00000489: *pfTakesValue = true; return "Ia32VmxCr4Fixed1";
2118 case 0x0000048a: *pfTakesValue = true; return "Ia32VmxVmcsEnum";
2119 case 0x0000048b: *pfTakesValue = true; return "Ia32VmxProcBasedCtls2";
2120 case 0x0000048c: *pfTakesValue = true; return "Ia32VmxEptVpidCap";
2121 case 0x0000048d: *pfTakesValue = true; return "Ia32VmxTruePinbasedCtls";
2122 case 0x0000048e: *pfTakesValue = true; return "Ia32VmxTrueProcbasedCtls";
2123 case 0x0000048f: *pfTakesValue = true; return "Ia32VmxTrueExitCtls";
2124 case 0x00000490: *pfTakesValue = true; return "Ia32VmxTrueEntryCtls";
2125 case 0x00000491: *pfTakesValue = true; return "Ia32VmxVmFunc";
2126
2127 case 0x000004c1:
2128 case 0x000004c2:
2129 case 0x000004c3:
2130 case 0x000004c4:
2131 case 0x000004c5:
2132 case 0x000004c6:
2133 case 0x000004c7:
2134 case 0x000004c8:
2135 return "Ia32PmcN";
2136
2137 case 0x000005a0: return "IntelCore2PeciControl"; /* Core2_Penryn. */
2138
2139 case 0x00000600: return "Ia32DsArea";
2140 case 0x00000601: *pfTakesValue = true; return "IntelI7SandyVrCurrentConfig";
2141 case 0x00000603: *pfTakesValue = true; return "IntelI7SandyVrMiscConfig";
2142 case 0x00000606: *pfTakesValue = true; return "IntelI7SandyRaplPowerUnit";
2143 case 0x0000060a: *pfTakesValue = true; return "IntelI7SandyPkgCnIrtlN";
2144 case 0x0000060b: *pfTakesValue = true; return "IntelI7SandyPkgCnIrtlN";
2145 case 0x0000060c: *pfTakesValue = true; return "IntelI7SandyPkgCnIrtlN";
2146 case 0x0000060d: *pfTakesValue = true; return "IntelI7SandyPkgC2Residency";
2147
2148 case 0x00000610: *pfTakesValue = true; return "IntelI7RaplPkgPowerLimit";
2149 case 0x00000611: *pfTakesValue = true; return "IntelI7RaplPkgEnergyStatus";
2150 case 0x00000613: *pfTakesValue = true; return "IntelI7RaplPkgPerfStatus";
2151 case 0x00000614: *pfTakesValue = true; return "IntelI7RaplPkgPowerInfo";
2152 case 0x00000618: *pfTakesValue = true; return "IntelI7RaplDramPowerLimit";
2153 case 0x00000619: *pfTakesValue = true; return "IntelI7RaplDramEnergyStatus";
2154 case 0x0000061b: *pfTakesValue = true; return "IntelI7RaplDramPerfStatus";
2155 case 0x0000061c: *pfTakesValue = true; return "IntelI7RaplDramPowerInfo";
2156 case 0x00000638: *pfTakesValue = true; return "IntelI7RaplPp0PowerLimit";
2157 case 0x00000639: *pfTakesValue = true; return "IntelI7RaplPp0EnergyStatus";
2158 case 0x0000063a: *pfTakesValue = true; return "IntelI7RaplPp0Policy";
2159 case 0x0000063b: *pfTakesValue = true; return "IntelI7RaplPp0PerfStatus";
2160 case 0x00000640: *pfTakesValue = true; return "IntelI7RaplPp1PowerLimit";
2161 case 0x00000641: *pfTakesValue = true; return "IntelI7RaplPp1EnergyStatus";
2162 case 0x00000642: *pfTakesValue = true; return "IntelI7RaplPp1Policy";
2163 case 0x00000648: *pfTakesValue = true; return "IntelI7IvyConfigTdpNominal";
2164 case 0x00000649: *pfTakesValue = true; return "IntelI7IvyConfigTdpLevel1";
2165 case 0x0000064a: *pfTakesValue = true; return "IntelI7IvyConfigTdpLevel2";
2166 case 0x0000064b: return "IntelI7IvyConfigTdpControl";
2167 case 0x0000064c: return "IntelI7IvyTurboActivationRatio";
2168
2169 case 0x00000660: return "IntelAtSilvCoreC1Recidency";
2170
2171 case 0x00000680: case 0x00000681: case 0x00000682: case 0x00000683:
2172 case 0x00000684: case 0x00000685: case 0x00000686: case 0x00000687:
2173 case 0x00000688: case 0x00000689: case 0x0000068a: case 0x0000068b:
2174 case 0x0000068c: case 0x0000068d: case 0x0000068e: case 0x0000068f:
2175 //case 0x00000690: case 0x00000691: case 0x00000692: case 0x00000693:
2176 //case 0x00000694: case 0x00000695: case 0x00000696: case 0x00000697:
2177 //case 0x00000698: case 0x00000699: case 0x0000069a: case 0x0000069b:
2178 //case 0x0000069c: case 0x0000069d: case 0x0000069e: case 0x0000069f:
2179 return "IntelLastBranchFromN";
2180 case 0x000006c0: case 0x000006c1: case 0x000006c2: case 0x000006c3:
2181 case 0x000006c4: case 0x000006c5: case 0x000006c6: case 0x000006c7:
2182 case 0x000006c8: case 0x000006c9: case 0x000006ca: case 0x000006cb:
2183 case 0x000006cc: case 0x000006cd: case 0x000006ce: case 0x000006cf:
2184 //case 0x000006d0: case 0x000006d1: case 0x000006d2: case 0x000006d3:
2185 //case 0x000006d4: case 0x000006d5: case 0x000006d6: case 0x000006d7:
2186 //case 0x000006d8: case 0x000006d9: case 0x000006da: case 0x000006db:
2187 //case 0x000006dc: case 0x000006dd: case 0x000006de: case 0x000006df:
2188 return "IntelLastBranchToN";
2189 case 0x000006e0: return "Ia32TscDeadline"; /** @todo detect this correctly! */
2190
2191 case 0x00000c80: return g_enmMicroarch > kCpumMicroarch_Intel_Core7_Nehalem ? "Ia32DebugInterface" : NULL;
2192
2193 case 0xc0000080: return "Amd64Efer";
2194 case 0xc0000081: return "Amd64SyscallTarget";
2195 case 0xc0000082: return "Amd64LongSyscallTarget";
2196 case 0xc0000083: return "Amd64CompSyscallTarget";
2197 case 0xc0000084: return "Amd64SyscallFlagMask";
2198 case 0xc0000100: return "Amd64FsBase";
2199 case 0xc0000101: return "Amd64GsBase";
2200 case 0xc0000102: return "Amd64KernelGsBase";
2201 case 0xc0000103: return "Amd64TscAux";
2202 case 0xc0000104: return "AmdFam15hTscRate";
2203 case 0xc0000105: return "AmdFam15hLwpCfg";
2204 case 0xc0000106: return "AmdFam15hLwpCbAddr";
2205 case 0xc0000408: return "AmdFam10hMc4MiscN";
2206 case 0xc0000409: return "AmdFam10hMc4MiscN";
2207 case 0xc000040a: return "AmdFam10hMc4MiscN";
2208 case 0xc000040b: return "AmdFam10hMc4MiscN";
2209 case 0xc000040c: return "AmdFam10hMc4MiscN";
2210 case 0xc000040d: return "AmdFam10hMc4MiscN";
2211 case 0xc000040e: return "AmdFam10hMc4MiscN";
2212 case 0xc000040f: return "AmdFam10hMc4MiscN";
2213 case 0xc0010000: return "AmdK8PerfCtlN";
2214 case 0xc0010001: return "AmdK8PerfCtlN";
2215 case 0xc0010002: return "AmdK8PerfCtlN";
2216 case 0xc0010003: return "AmdK8PerfCtlN";
2217 case 0xc0010004: return "AmdK8PerfCtrN";
2218 case 0xc0010005: return "AmdK8PerfCtrN";
2219 case 0xc0010006: return "AmdK8PerfCtrN";
2220 case 0xc0010007: return "AmdK8PerfCtrN";
2221 case 0xc0010010: *pfTakesValue = true; return "AmdK8SysCfg";
2222 case 0xc0010015: return "AmdK8HwCr";
2223 case 0xc0010016: case 0xc0010018: return "AmdK8IorrBaseN";
2224 case 0xc0010017: case 0xc0010019: return "AmdK8IorrMaskN";
2225 case 0xc001001a: case 0xc001001d: return "AmdK8TopOfMemN";
2226 case 0xc001001f: return "AmdK8NbCfg1";
2227 case 0xc0010020: return "AmdK8PatchLoader";
2228 case 0xc0010022: return "AmdK8McXcptRedir";
2229 case 0xc0010030: case 0xc0010031: case 0xc0010032:
2230 case 0xc0010033: case 0xc0010034: case 0xc0010035:
2231 return "AmdK8CpuNameN";
2232 case 0xc001003e: *pfTakesValue = true; return "AmdK8HwThermalCtrl";
2233 case 0xc001003f: return "AmdK8SwThermalCtrl";
2234 case 0xc0010041: *pfTakesValue = true; return "AmdK8FidVidControl";
2235 case 0xc0010042: *pfTakesValue = true; return "AmdK8FidVidStatus";
2236 case 0xc0010044: case 0xc0010045: case 0xc0010046: case 0xc0010047:
2237 case 0xc0010048: case 0xc0010049: case 0xc001004a: //case 0xc001004b:
2238 return "AmdK8McCtlMaskN";
2239 case 0xc0010050: case 0xc0010051: case 0xc0010052: case 0xc0010053:
2240 return "AmdK8SmiOnIoTrapN";
2241 case 0xc0010054: return "AmdK8SmiOnIoTrapCtlSts";
2242 case 0xc0010055: return "AmdK8IntPendingMessage";
2243 case 0xc0010056: return "AmdK8SmiTriggerIoCycle";
2244 case 0xc0010058: return "AmdFam10hMmioCfgBaseAddr";
2245 case 0xc0010059: return "AmdFam10hTrapCtlMaybe";
2246 case 0xc0010061: *pfTakesValue = true; return "AmdFam10hPStateCurLimit";
2247 case 0xc0010062: *pfTakesValue = true; return "AmdFam10hPStateControl";
2248 case 0xc0010063: *pfTakesValue = true; return "AmdFam10hPStateStatus";
2249 case 0xc0010064: case 0xc0010065: case 0xc0010066: case 0xc0010067:
2250 case 0xc0010068: case 0xc0010069: case 0xc001006a: case 0xc001006b:
2251 *pfTakesValue = true; return "AmdFam10hPStateN";
2252 case 0xc0010070: *pfTakesValue = true; return "AmdFam10hCofVidControl";
2253 case 0xc0010071: *pfTakesValue = true; return "AmdFam10hCofVidStatus";
2254 case 0xc0010073: return "AmdFam10hCStateIoBaseAddr";
2255 case 0xc0010074: return "AmdFam10hCpuWatchdogTimer";
2256 // case 0xc0010075: return "AmdFam15hApmlTdpLimit";
2257 // case 0xc0010077: return "AmdFam15hCpuPowerInTdp";
2258 // case 0xc0010078: return "AmdFam15hPowerAveragingPeriod";
2259 // case 0xc0010079: return "AmdFam15hDramCtrlCmdThrottle";
2260 // case 0xc0010080: return "AmdFam16hFreqSensFeedbackMonActCnt0";
2261 // case 0xc0010081: return "AmdFam16hFreqSensFeedbackMonRefCnt0";
2262 case 0xc0010111: return "AmdK8SmmBase"; /** @todo probably misdetected ign/gp due to locking */
2263 case 0xc0010112: return "AmdK8SmmAddr"; /** @todo probably misdetected ign/gp due to locking */
2264 case 0xc0010113: return "AmdK8SmmMask"; /** @todo probably misdetected ign/gp due to locking */
2265 case 0xc0010114: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdK8VmCr" : NULL; /** @todo probably misdetected due to locking */
2266 case 0xc0010115: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdK8IgnNe" : NULL;
2267 case 0xc0010116: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdK8SmmCtl" : NULL;
2268 case 0xc0010117: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdK8VmHSavePa" : NULL; /** @todo probably misdetected due to locking */
2269 case 0xc0010118: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdFam10hVmLockKey" : NULL;
2270 case 0xc0010119: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdFam10hSmmLockKey" : NULL; /* Not documented by BKDG, found in netbsd patch. */
2271 case 0xc001011a: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdFam10hLocalSmiStatus" : NULL;
2272 case 0xc0010140: *pfTakesValue = true; return "AmdFam10hOsVisWrkIdLength";
2273 case 0xc0010141: *pfTakesValue = true; return "AmdFam10hOsVisWrkStatus";
2274 case 0xc0010200: case 0xc0010202: case 0xc0010204: case 0xc0010206:
2275 case 0xc0010208: case 0xc001020a: //case 0xc001020c: case 0xc001020e:
2276 return "AmdK8PerfCtlN";
2277 case 0xc0010201: case 0xc0010203: case 0xc0010205: case 0xc0010207:
2278 case 0xc0010209: case 0xc001020b: //case 0xc001020d: case 0xc001020f:
2279 return "AmdK8PerfCtrN";
2280 case 0xc0010230: case 0xc0010232: case 0xc0010234: case 0xc0010236:
2281 //case 0xc0010238: case 0xc001023a: case 0xc001030c: case 0xc001023e:
2282 return "AmdFam16hL2IPerfCtlN";
2283 case 0xc0010231: case 0xc0010233: case 0xc0010235: case 0xc0010237:
2284 //case 0xc0010239: case 0xc001023b: case 0xc001023d: case 0xc001023f:
2285 return "AmdFam16hL2IPerfCtrN";
2286 case 0xc0010240: case 0xc0010242: case 0xc0010244: case 0xc0010246:
2287 //case 0xc0010248: case 0xc001024a: case 0xc001024c: case 0xc001024e:
2288 return "AmdFam15hNorthbridgePerfCtlN";
2289 case 0xc0010241: case 0xc0010243: case 0xc0010245: case 0xc0010247:
2290 //case 0xc0010249: case 0xc001024b: case 0xc001024d: case 0xc001024f:
2291 return "AmdFam15hNorthbridgePerfCtrN";
2292 case 0xc0011000: *pfTakesValue = true; return "AmdK7MicrocodeCtl";
2293 case 0xc0011001: *pfTakesValue = true; return "AmdK7ClusterIdMaybe";
2294 case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd07hEbax" : NULL;
2295 case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd06hEcx" : NULL;
2296 case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd01hEdcx" : NULL;
2297 case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlExt01hEdcx" : NULL;
2298 case 0xc0011006: return "AmdK7DebugStatusMaybe";
2299 case 0xc0011007: return "AmdK7BHTraceBaseMaybe";
2300 case 0xc0011008: return "AmdK7BHTracePtrMaybe";
2301 case 0xc0011009: return "AmdK7BHTraceLimitMaybe";
2302 case 0xc001100a: return "AmdK7HardwareDebugToolCfgMaybe";
2303 case 0xc001100b: return "AmdK7FastFlushCountMaybe";
2304 case 0xc001100c: return "AmdK7NodeId"; /** @todo dunno if this was there is K7 already. Kinda doubt it. */
2305 case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
2306 case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
2307 case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
2308 case 0xc0011020: return "AmdK7LoadStoreCfg";
2309 case 0xc0011021: return "AmdK7InstrCacheCfg";
2310 case 0xc0011022: return "AmdK7DataCacheCfg";
2311 case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg" : "AmdK7BusUnitCfg";
2312 case 0xc0011024: return "AmdK7DebugCtl2Maybe";
2313 case 0xc0011025: return "AmdK7Dr0DataMatchMaybe";
2314 case 0xc0011026: return "AmdK7Dr0DataMaskMaybe";
2315 case 0xc0011027: return "AmdK7DrXAddrMaskN";
2316 case 0xc0011028: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AmdFam15hFpuCfg" : NULL;
2317 case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AmdFam15hDecoderCfg" : NULL;
2318 case 0xc001102a: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg2"
2319 : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) || g_enmMicroarch > kCpumMicroarch_AMD_15h_End
2320 ? "AmdFam10hBusUnitCfg2" /* 10h & 16h */ : NULL;
2321 case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg3" : NULL;
2322 case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hExecUnitCfg" : NULL;
2323 case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hLoadStoreCfg2" : NULL;
2324 case 0xc0011030: return "AmdFam10hIbsFetchCtl";
2325 case 0xc0011031: return "AmdFam10hIbsFetchLinAddr";
2326 case 0xc0011032: return "AmdFam10hIbsFetchPhysAddr";
2327 case 0xc0011033: return "AmdFam10hIbsOpExecCtl";
2328 case 0xc0011034: return "AmdFam10hIbsOpRip";
2329 case 0xc0011035: return "AmdFam10hIbsOpData";
2330 case 0xc0011036: return "AmdFam10hIbsOpData2";
2331 case 0xc0011037: return "AmdFam10hIbsOpData3";
2332 case 0xc0011038: return "AmdFam10hIbsDcLinAddr";
2333 case 0xc0011039: return "AmdFam10hIbsDcPhysAddr";
2334 case 0xc001103a: return "AmdFam10hIbsCtl";
2335 case 0xc001103b: return "AmdFam14hIbsBrTarget";
2336 }
2337 return NULL;
2338}
2339
2340
2341/**
2342 * Names CPUMCPU variables that MSRs corresponds to.
2343 *
2344 * @returns The variable name @a uMsr corresponds to, NULL if no variable.
2345 * @param uMsr The MSR in question.
2346 */
2347static const char *getMsrCpumCpuVarName(uint32_t uMsr)
2348{
2349 switch (uMsr)
2350 {
2351 case 0x00000250: return "GuestMsrs.msr.MtrrFix64K_00000";
2352 case 0x00000258: return "GuestMsrs.msr.MtrrFix16K_80000";
2353 case 0x00000259: return "GuestMsrs.msr.MtrrFix16K_A0000";
2354 case 0x00000268: return "GuestMsrs.msr.MtrrFix4K_C0000";
2355 case 0x00000269: return "GuestMsrs.msr.MtrrFix4K_C8000";
2356 case 0x0000026a: return "GuestMsrs.msr.MtrrFix4K_D0000";
2357 case 0x0000026b: return "GuestMsrs.msr.MtrrFix4K_D8000";
2358 case 0x0000026c: return "GuestMsrs.msr.MtrrFix4K_E0000";
2359 case 0x0000026d: return "GuestMsrs.msr.MtrrFix4K_E8000";
2360 case 0x0000026e: return "GuestMsrs.msr.MtrrFix4K_F0000";
2361 case 0x0000026f: return "GuestMsrs.msr.MtrrFix4K_F8000";
2362 case 0x00000277: return "Guest.msrPAT";
2363 case 0x000002ff: return "GuestMsrs.msr.MtrrDefType";
2364 }
2365 return NULL;
2366}
2367
2368
2369/**
2370 * Checks whether the MSR should read as zero for some reason.
2371 *
2372 * @returns true if the register should read as zero, false if not.
2373 * @param uMsr The MSR.
2374 */
2375static bool doesMsrReadAsZero(uint32_t uMsr)
2376{
2377 switch (uMsr)
2378 {
2379 case 0x00000088: return true; // "BBL_CR_D0" - RAZ until understood/needed.
2380 case 0x00000089: return true; // "BBL_CR_D1" - RAZ until understood/needed.
2381 case 0x0000008a: return true; // "BBL_CR_D2" - RAZ until understood/needed.
2382
2383 /* Non-zero, but unknown register. */
2384 case 0x0000004a:
2385 case 0x0000004b:
2386 case 0x0000004c:
2387 case 0x0000004d:
2388 case 0x0000004e:
2389 case 0x0000004f:
2390 case 0x00000050:
2391 case 0x00000051:
2392 case 0x00000052:
2393 case 0x00000053:
2394 case 0x00000054:
2395 case 0x0000008c:
2396 case 0x0000008d:
2397 case 0x0000008e:
2398 case 0x0000008f:
2399 case 0x00000090:
2400 case 0xc0011011:
2401 return true;
2402 }
2403
2404 return false;
2405}
2406
2407
2408/**
2409 * Gets the skip mask for the given MSR.
2410 *
2411 * @returns Skip mask (0 means skipping nothing).
2412 * @param uMsr The MSR.
2413 */
2414static uint64_t getGenericSkipMask(uint32_t uMsr)
2415{
2416 switch (uMsr)
2417 {
2418 case 0x0000013c: return 3; /* AES-NI lock bit ++. */
2419
2420 case 0x000001f2: return UINT64_C(0xfffff00f); /* Ia32SmrrPhysBase - Only writable in SMM. */
2421 case 0x000001f3: return UINT64_C(0xfffff800); /* Ia32SmrrPhysMask - Only writable in SMM. */
2422
2423 /* these two have lock bits. */
2424 case 0x0000064b: return UINT64_C(0x80000003);
2425 case 0x0000064c: return UINT64_C(0x800000ff);
2426
2427 case 0xc0010015: return 1; /* SmmLock bit */
2428
2429 /* SmmLock effect: */
2430 case 0xc0010111: return UINT32_MAX;
2431 case 0xc0010112: return UINT64_C(0xfffe0000) | ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
2432 case 0xc0010113: return UINT64_C(0xfffe773f) | ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
2433 case 0xc0010116: return 0x1f;
2434
2435 case 0xc0010114: return RT_BIT_64(3) /* SVM lock */ | RT_BIT_64(4) /* SvmeDisable */;
2436
2437 /* Canonical */
2438 case 0xc0011034:
2439 case 0xc0011038:
2440 case 0xc001103b:
2441 return UINT64_C(0xffff800000000000);
2442
2443 case 0x00000060: case 0x00000061: case 0x00000062: case 0x00000063:
2444 case 0x00000064: case 0x00000065: case 0x00000066: case 0x00000067:
2445 case 0x00000040: case 0x00000041: case 0x00000042: case 0x00000043:
2446 case 0x00000044: case 0x00000045: case 0x00000046: case 0x00000047:
2447 case 0x00000600:
2448 if (g_enmMicroarch >= kCpumMicroarch_Intel_Core2_First)
2449 return UINT64_C(0xffff800000000000);
2450 break;
2451
2452
2453 /* Write only bits. */
2454 case 0xc0010041: return RT_BIT_64(16); /* FIDVID_CTL.InitFidVid */
2455
2456 /* Time counters - fudge them to avoid incorrect ignore masks. */
2457 case 0x00000010:
2458 case 0x000000e7:
2459 case 0x000000e8:
2460 return RT_BIT_32(29) - 1;
2461 }
2462 return 0;
2463}
2464
2465
2466
2467
2468/** queryMsrWriteBadness return values. */
2469typedef enum
2470{
2471 /** . */
2472 VBCPUREPBADNESS_MOSTLY_HARMLESS = 0,
2473 /** Not a problem if accessed with care. */
2474 VBCPUREPBADNESS_MIGHT_BITE,
2475 /** Worse than a bad james bond villain. */
2476 VBCPUREPBADNESS_BOND_VILLAIN
2477} VBCPUREPBADNESS;
2478
2479
2480/**
2481 * Backlisting and graylisting of MSRs which may cause tripple faults.
2482 *
2483 * @returns Badness factor.
2484 * @param uMsr The MSR in question.
2485 */
2486static VBCPUREPBADNESS queryMsrWriteBadness(uint32_t uMsr)
2487{
2488 /** @todo Having trouble in the 0xc0010247,0xc0011006,?? region on Bulldozer. */
2489 /** @todo Having trouble in the 0xc001100f,0xc001100d,?? region on Opteron
2490 * 2384. */
2491
2492 switch (uMsr)
2493 {
2494 case 0x00000050:
2495 case 0x00000051:
2496 case 0x00000052:
2497 case 0x00000053:
2498 case 0x00000054:
2499
2500 case 0x00001006:
2501 case 0x00001007:
2502 return VBCPUREPBADNESS_BOND_VILLAIN;
2503
2504 case 0x0000120e:
2505 case 0x00001233:
2506 case 0x00001239:
2507 case 0x00001249:
2508 case 0x0000124a:
2509 case 0x00001404:
2510 case 0x00001405:
2511 case 0x00001413:
2512 case 0x0000142c: /* Caused rip to be set to 297 or some such weirdness... */
2513 case 0x0000142e:
2514 case 0x00001435:
2515 case 0x00001436:
2516 case 0x00001438:
2517 case 0x0000317f:
2518 if (g_enmVendor == CPUMCPUVENDOR_VIA || g_enmVendor == CPUMCPUVENDOR_SHANGHAI)
2519 return VBCPUREPBADNESS_BOND_VILLAIN;
2520 break;
2521
2522 case 0xc0010010:
2523 case 0xc0010016:
2524 case 0xc0010017:
2525 case 0xc0010018:
2526 case 0xc0010019:
2527 case 0xc001001a:
2528 case 0xc001001d:
2529 case 0xc0010064: /* P-state fequency, voltage, ++. */
2530 case 0xc0010065: /* P-state fequency, voltage, ++. */
2531 case 0xc0010066: /* P-state fequency, voltage, ++. */
2532 case 0xc0010067: /* P-state fequency, voltage, ++. */
2533 case 0xc0010068: /* P-state fequency, voltage, ++. */
2534 case 0xc0010069: /* P-state fequency, voltage, ++. */
2535 case 0xc001006a: /* P-state fequency, voltage, ++. */
2536 case 0xc001006b: /* P-state fequency, voltage, ++. */
2537 case 0xc0010070: /* COFVID Control. */
2538 case 0xc001101e:
2539 case 0xc0011021: /* IC_CFG (instruction cache configuration) */
2540 case 0xc0011023: /* CU_CFG (combined unit configuration) */
2541 case 0xc001102c: /* EX_CFG (execution unit configuration) */
2542 return VBCPUREPBADNESS_BOND_VILLAIN;
2543
2544 case 0xc0011012:
2545 if (CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch))
2546 return VBCPUREPBADNESS_MIGHT_BITE;
2547 break;
2548
2549 /* KVM MSRs that are unsafe to touch. */
2550 case 0x00000011: /* KVM */
2551 case 0x00000012: /* KVM */
2552 return VBCPUREPBADNESS_BOND_VILLAIN;
2553
2554 /*
2555 * The TSC is tricky -- writing it isn't a problem, but if we put back the original
2556 * value, we'll throw it out of whack. If we're on an SMP OS that uses the TSC for timing,
2557 * we'll likely kill it, especially if we can't do the modification very quickly.
2558 */
2559 case 0x00000010: /* IA32_TIME_STAMP_COUNTER */
2560 if (!g_MsrAcc.fAtomic)
2561 return VBCPUREPBADNESS_BOND_VILLAIN;
2562 break;
2563
2564 /*
2565 * The following MSRs are not safe to modify in a typical OS if we can't do it atomically,
2566 * i.e. read/modify/restore without allowing any other code to execute. Everything related
2567 * to syscalls will blow up in our face if we go back to userland with modified MSRs.
2568 */
2569// case 0x0000001b: /* IA32_APIC_BASE */
2570 case 0xc0000081: /* MSR_K6_STAR */
2571 case 0xc0000082: /* AMD64_STAR64 */
2572 case 0xc0000083: /* AMD64_STARCOMPAT */
2573 case 0xc0000084: /* AMD64_SYSCALL_FLAG_MASK */
2574 case 0xc0000100: /* AMD64_FS_BASE */
2575 case 0xc0000101: /* AMD64_GS_BASE */
2576 case 0xc0000102: /* AMD64_KERNEL_GS_BASE */
2577 if (!g_MsrAcc.fAtomic)
2578 return VBCPUREPBADNESS_MIGHT_BITE;
2579 break;
2580
2581 case 0x000001a0: /* IA32_MISC_ENABLE */
2582 case 0x00000199: /* IA32_PERF_CTL */
2583 return VBCPUREPBADNESS_MIGHT_BITE;
2584
2585 case 0x000005a0: /* C2_PECI_CTL */
2586 case 0x000005a1: /* C2_UNK_0000_05a1 */
2587 if (g_enmVendor == CPUMCPUVENDOR_INTEL)
2588 return VBCPUREPBADNESS_MIGHT_BITE;
2589 break;
2590
2591 case 0x00002000: /* P6_CR0. */
2592 case 0x00002003: /* P6_CR3. */
2593 case 0x00002004: /* P6_CR4. */
2594 if (g_enmVendor == CPUMCPUVENDOR_INTEL)
2595 return VBCPUREPBADNESS_MIGHT_BITE;
2596 break;
2597 case 0xc0000080: /* MSR_K6_EFER */
2598 return VBCPUREPBADNESS_MIGHT_BITE;
2599 }
2600 return VBCPUREPBADNESS_MOSTLY_HARMLESS;
2601}
2602
2603
2604/**
2605 * Checks if this might be a VIA/Shanghai dummy register.
2606 *
2607 * @returns true if it's a dummy, false if it isn't.
2608 * @param uMsr The MSR.
2609 * @param uValue The value.
2610 * @param fFlags The flags.
2611 */
2612static bool isMsrViaShanghaiDummy(uint32_t uMsr, uint64_t uValue, uint32_t fFlags)
2613{
2614 if (g_enmVendor != CPUMCPUVENDOR_VIA && g_enmVendor != CPUMCPUVENDOR_SHANGHAI)
2615 return false;
2616
2617 if (uValue)
2618 return false;
2619
2620 if (fFlags)
2621 return false;
2622
2623 switch (uMsr)
2624 {
2625 case 0x00000010:
2626 case 0x0000001b:
2627 case 0x000000c1:
2628 case 0x000000c2:
2629 case 0x0000011e:
2630 case 0x00000186:
2631 case 0x00000187:
2632 //case 0x00000200 ... (mtrrs will be detected)
2633 return false;
2634
2635 case 0xc0000080:
2636 case 0xc0000081:
2637 case 0xc0000082:
2638 case 0xc0000083:
2639 if (vbCpuRepSupportsLongMode())
2640 return false;
2641 break;
2642 }
2643
2644 if (uMsr >= 0x00001200 && uMsr <= 0x00003fff && queryMsrWriteBadness(uMsr) != VBCPUREPBADNESS_MOSTLY_HARMLESS)
2645 return false;
2646
2647 if ( !msrProberModifyNoChange(uMsr)
2648 && !msrProberModifyZero(uMsr))
2649 return false;
2650
2651 uint64_t fIgnMask = 0;
2652 uint64_t fGpMask = 0;
2653 int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, 0);
2654 if (RT_FAILURE(rc))
2655 return false;
2656
2657 if (fIgnMask != UINT64_MAX)
2658 return false;
2659 if (fGpMask != 0)
2660 return false;
2661
2662 return true;
2663}
2664
2665
2666/**
2667 * Adjusts the ignore and GP masks for MSRs which contains canonical addresses.
2668 *
2669 * @param uMsr The MSR.
2670 * @param pfIgn Pointer to the ignore mask.
2671 * @param pfGp Pointer to the GP mask.
2672 */
2673static void adjustCanonicalIgnAndGpMasks(uint32_t uMsr, uint64_t *pfIgn, uint64_t *pfGp)
2674{
2675 RT_NOREF1(pfIgn);
2676 if (!vbCpuRepSupportsLongMode())
2677 return;
2678 switch (uMsr)
2679 {
2680 case 0x00000175:
2681 case 0x00000176:
2682 case 0x000001da:
2683 case 0x000001db:
2684 case 0x000001dc:
2685 case 0x000001de:
2686 case 0x00000600:
2687 if (*pfGp == UINT64_C(0xffff800000000000))
2688 *pfGp = 0;
2689 break;
2690 case 0x000001dd:
2691 if (*pfGp == UINT64_C(0x7fff800000000000) || *pfGp == UINT64_C(0xffff800000000000)) /* why is the top bit writable? */
2692 *pfGp = 0;
2693 break;
2694
2695 case 0xc0000082:
2696 case 0xc0000083:
2697 case 0xc0000100:
2698 case 0xc0000101:
2699 case 0xc0000102:
2700 *pfGp = 0;
2701 break;
2702 }
2703}
2704
2705
2706
2707/**
2708 * Prints a 64-bit value in the best way.
2709 *
2710 * @param uValue The value.
2711 */
2712static void printMsrValueU64(uint64_t uValue)
2713{
2714 if (uValue == 0)
2715 vbCpuRepPrintf(", 0");
2716 else if (uValue == UINT16_MAX)
2717 vbCpuRepPrintf(", UINT16_MAX");
2718 else if (uValue == UINT32_MAX)
2719 vbCpuRepPrintf(", UINT32_MAX");
2720 else if (uValue == UINT64_MAX)
2721 vbCpuRepPrintf(", UINT64_MAX");
2722 else if (uValue == UINT64_C(0xffffffff00000000))
2723 vbCpuRepPrintf(", ~(uint64_t)UINT32_MAX");
2724 else if (uValue <= (UINT32_MAX >> 1))
2725 vbCpuRepPrintf(", %#llx", uValue);
2726 else if (uValue <= UINT32_MAX)
2727 vbCpuRepPrintf(", UINT32_C(%#llx)", uValue);
2728 else
2729 vbCpuRepPrintf(", UINT64_C(%#llx)", uValue);
2730}
2731
2732
2733/**
2734 * Prints the newline after an MSR line has been printed.
2735 *
2736 * This is used as a hook to slow down the output and make sure the remote
2737 * terminal or/and output file has received the last update before we go and
2738 * crash probing the next MSR.
2739 */
2740static void printMsrNewLine(void)
2741{
2742 vbCpuRepPrintf("\n");
2743#if 1
2744 RTThreadSleep(8);
2745#endif
2746}
2747
2748static int printMsrWriteOnly(uint32_t uMsr, const char *pszWrFnName, const char *pszAnnotation)
2749{
2750 if (!pszWrFnName)
2751 pszWrFnName = "IgnoreWrite";
2752 vbCpuRepPrintf(pszAnnotation
2753 ? " MFN(%#010x, \"%s\", WriteOnly, %s), /* %s */"
2754 : " MFN(%#010x, \"%s\", WriteOnly, %s),",
2755 uMsr, getMsrName(uMsr), pszWrFnName, pszAnnotation);
2756 printMsrNewLine();
2757 return VINF_SUCCESS;
2758}
2759
2760
2761static int printMsrValueReadOnly(uint32_t uMsr, uint64_t uValue, const char *pszAnnotation)
2762{
2763 vbCpuRepPrintf(" MVO(%#010x, \"%s\"", uMsr, getMsrName(uMsr));
2764 printMsrValueU64(uValue);
2765 vbCpuRepPrintf("),");
2766 if (pszAnnotation)
2767 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2768 printMsrNewLine();
2769 return VINF_SUCCESS;
2770}
2771
2772
2773
2774static int printMsrValueIgnoreWritesNamed(uint32_t uMsr, uint64_t uValue, const char *pszName, const char *pszAnnotation)
2775{
2776 vbCpuRepPrintf(" MVI(%#010x, \"%s\"", uMsr, pszName);
2777 printMsrValueU64(uValue);
2778 vbCpuRepPrintf("),");
2779 if (pszAnnotation)
2780 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2781 printMsrNewLine();
2782 return VINF_SUCCESS;
2783}
2784
2785
2786static int printMsrValueIgnoreWrites(uint32_t uMsr, uint64_t uValue, const char *pszAnnotation)
2787{
2788 return printMsrValueIgnoreWritesNamed(uMsr, uValue, getMsrName(uMsr), pszAnnotation);
2789}
2790
2791
2792static int printMsrValueExtended(uint32_t uMsr, uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask,
2793 const char *pszAnnotation)
2794{
2795 vbCpuRepPrintf(" MVX(%#010x, \"%s\"", uMsr, getMsrName(uMsr));
2796 printMsrValueU64(uValue);
2797 printMsrValueU64(fIgnMask);
2798 printMsrValueU64(fGpMask);
2799 vbCpuRepPrintf("),");
2800 if (pszAnnotation)
2801 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2802 printMsrNewLine();
2803 return VINF_SUCCESS;
2804}
2805
2806
2807static int printMsrRangeValueReadOnly(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
2808{
2809 vbCpuRepPrintf(" RVO(%#010x, %#010x, \"%s\"", uMsr, uLast, getMsrRangeName(uMsr));
2810 printMsrValueU64(uValue);
2811 vbCpuRepPrintf("),");
2812 if (pszAnnotation)
2813 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2814 printMsrNewLine();
2815 return VINF_SUCCESS;
2816}
2817
2818
2819static int printMsrRangeValueIgnoreWritesNamed(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszName, const char *pszAnnotation)
2820{
2821 vbCpuRepPrintf(" RVI(%#010x, %#010x, \"%s\"", uMsr, uLast, pszName);
2822 printMsrValueU64(uValue);
2823 vbCpuRepPrintf("),");
2824 if (pszAnnotation)
2825 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2826 printMsrNewLine();
2827 return VINF_SUCCESS;
2828}
2829
2830
2831static int printMsrRangeValueIgnoreWrites(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
2832{
2833 return printMsrRangeValueIgnoreWritesNamed(uMsr, uLast, uValue, getMsrRangeName(uMsr), pszAnnotation);
2834}
2835
2836
2837static int printMsrFunction(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, const char *pszAnnotation)
2838{
2839 if (!pszRdFnName)
2840 pszRdFnName = getMsrFnName(uMsr, NULL);
2841 if (!pszWrFnName)
2842 pszWrFnName = pszRdFnName;
2843 vbCpuRepPrintf(" MFN(%#010x, \"%s\", %s, %s),", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
2844 if (pszAnnotation)
2845 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2846 printMsrNewLine();
2847 return VINF_SUCCESS;
2848}
2849
2850
2851static int printMsrFunctionReadOnly(uint32_t uMsr, const char *pszRdFnName, const char *pszAnnotation)
2852{
2853 if (!pszRdFnName)
2854 pszRdFnName = getMsrFnName(uMsr, NULL);
2855 vbCpuRepPrintf(" MFO(%#010x, \"%s\", %s),", uMsr, getMsrName(uMsr), pszRdFnName);
2856 if (pszAnnotation)
2857 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2858 printMsrNewLine();
2859 return VINF_SUCCESS;
2860}
2861
2862
2863static int printMsrFunctionIgnoreWrites(uint32_t uMsr, const char *pszRdFnName, const char *pszAnnotation)
2864{
2865 if (!pszRdFnName)
2866 pszRdFnName = getMsrFnName(uMsr, NULL);
2867 vbCpuRepPrintf(" MFI(%#010x, \"%s\", %s),", uMsr, getMsrName(uMsr), pszRdFnName);
2868 if (pszAnnotation)
2869 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2870 printMsrNewLine();
2871 return VINF_SUCCESS;
2872}
2873
2874
2875static int printMsrFunctionIgnoreMask(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
2876 uint64_t fIgnMask, const char *pszAnnotation)
2877{
2878 if (!pszRdFnName)
2879 pszRdFnName = getMsrFnName(uMsr, NULL);
2880 if (!pszWrFnName)
2881 pszWrFnName = pszRdFnName;
2882 vbCpuRepPrintf(" MFW(%#010x, \"%s\", %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
2883 printMsrValueU64(fIgnMask);
2884 vbCpuRepPrintf("),");
2885 if (pszAnnotation)
2886 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2887 printMsrNewLine();
2888 return VINF_SUCCESS;
2889}
2890
2891
2892static int printMsrFunctionExtended(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, uint64_t uValue,
2893 uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
2894{
2895 if (!pszRdFnName)
2896 pszRdFnName = getMsrFnName(uMsr, NULL);
2897 if (!pszWrFnName)
2898 pszWrFnName = pszRdFnName;
2899 vbCpuRepPrintf(" MFX(%#010x, \"%s\", %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
2900 printMsrValueU64(uValue);
2901 printMsrValueU64(fIgnMask);
2902 printMsrValueU64(fGpMask);
2903 vbCpuRepPrintf("),");
2904 if (pszAnnotation)
2905 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2906 printMsrNewLine();
2907 return VINF_SUCCESS;
2908}
2909
2910
2911static int printMsrFunctionExtendedIdxVal(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, uint64_t uValue,
2912 uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
2913{
2914 if (!pszRdFnName)
2915 pszRdFnName = getMsrFnName(uMsr, NULL);
2916 if (!pszWrFnName)
2917 pszWrFnName = pszRdFnName;
2918 vbCpuRepPrintf(" MFX(%#010x, \"%s\", %s, %s, %#x", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, uValue);
2919 printMsrValueU64(fIgnMask);
2920 printMsrValueU64(fGpMask);
2921 vbCpuRepPrintf("),");
2922 if (pszAnnotation)
2923 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2924 printMsrNewLine();
2925 return VINF_SUCCESS;
2926}
2927
2928
2929static int printMsrFunctionCpumCpu(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
2930 const char *pszCpumCpuStorage, const char *pszAnnotation)
2931{
2932 if (!pszRdFnName)
2933 pszRdFnName = getMsrFnName(uMsr, NULL);
2934 if (!pszWrFnName)
2935 pszWrFnName = pszRdFnName;
2936 if (!pszCpumCpuStorage)
2937 pszCpumCpuStorage = getMsrCpumCpuVarName(uMsr);
2938 if (!pszCpumCpuStorage)
2939 return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
2940 vbCpuRepPrintf(" MFS(%#010x, \"%s\", %s, %s, %s),", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
2941 if (pszAnnotation)
2942 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2943 printMsrNewLine();
2944 return VINF_SUCCESS;
2945}
2946
2947
2948static int printMsrFunctionCpumCpuEx(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
2949 const char *pszCpumCpuStorage, uint64_t fIgnMask, uint64_t fGpMask,
2950 const char *pszAnnotation)
2951{
2952 if (!pszRdFnName)
2953 pszRdFnName = getMsrFnName(uMsr, NULL);
2954 if (!pszWrFnName)
2955 pszWrFnName = pszRdFnName;
2956 if (!pszCpumCpuStorage)
2957 pszCpumCpuStorage = getMsrCpumCpuVarName(uMsr);
2958 if (!pszCpumCpuStorage)
2959 return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
2960 vbCpuRepPrintf(" MFZ(%#010x, \"%s\", %s, %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
2961 printMsrValueU64(fIgnMask);
2962 printMsrValueU64(fGpMask);
2963 vbCpuRepPrintf("),");
2964 if (pszAnnotation)
2965 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2966 printMsrNewLine();
2967 return VINF_SUCCESS;
2968}
2969
2970
2971static int printMsrRangeFunction(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
2972 const char *pszAnnotation)
2973{
2974 if (!pszRdFnName)
2975 pszRdFnName = getMsrFnName(uMsr, NULL);
2976 if (!pszWrFnName)
2977 pszWrFnName = pszRdFnName;
2978 vbCpuRepPrintf(" RFN(%#010x, %#010x, \"%s\", %s, %s),", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
2979 if (pszAnnotation)
2980 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2981 printMsrNewLine();
2982 return VINF_SUCCESS;
2983}
2984
2985
2986static int printMsrRangeFunctionEx(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
2987 uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
2988{
2989 if (!pszRdFnName)
2990 pszRdFnName = getMsrFnName(uMsr, NULL);
2991 if (!pszWrFnName)
2992 pszWrFnName = pszRdFnName;
2993 vbCpuRepPrintf(" RSN(%#010x, %#010x, \"%s\", %s, %s", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
2994 printMsrValueU64(uValue);
2995 printMsrValueU64(fIgnMask);
2996 printMsrValueU64(fGpMask);
2997 vbCpuRepPrintf("),");
2998 if (pszAnnotation)
2999 vbCpuRepPrintf(" /* %s */", pszAnnotation);
3000 printMsrNewLine();
3001 return VINF_SUCCESS;
3002}
3003
3004
3005static int printMsrRangeFunctionExIdxVal(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
3006 uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
3007{
3008 if (!pszRdFnName)
3009 pszRdFnName = getMsrFnName(uMsr, NULL);
3010 if (!pszWrFnName)
3011 pszWrFnName = pszRdFnName;
3012 vbCpuRepPrintf(" RSN(%#010x, %#010x, \"%s\", %s, %s, %#x",
3013 uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName, uValue);
3014 printMsrValueU64(fIgnMask);
3015 printMsrValueU64(fGpMask);
3016 vbCpuRepPrintf("),");
3017 if (pszAnnotation)
3018 vbCpuRepPrintf(" /* %s */", pszAnnotation);
3019 printMsrNewLine();
3020 return VINF_SUCCESS;
3021}
3022
3023
3024static int printMsrAlias(uint32_t uMsr, uint32_t uTarget, const char *pszAnnotation)
3025{
3026 vbCpuRepPrintf(" MAL(%#010x, \"%s\", %#010x),", uMsr, getMsrName(uMsr), uTarget);
3027 if (pszAnnotation)
3028 vbCpuRepPrintf(" /* %s */", pszAnnotation);
3029 printMsrNewLine();
3030 return VINF_SUCCESS;
3031}
3032
3033
3034
3035static const char *annotateValue(uint64_t uValue)
3036{
3037 static char s_szBuf[40];
3038 if (uValue <= UINT32_MAX)
3039 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "value=%#llx", uValue);
3040 else
3041 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "value=%#x`%08x", RT_HI_U32(uValue), RT_LO_U32(uValue));
3042 return s_szBuf;
3043}
3044
3045
3046static const char *annotateValueExtra(const char *pszExtra, uint64_t uValue)
3047{
3048 static char s_szBuf[40];
3049 if (uValue <= UINT32_MAX)
3050 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "%s value=%#llx", pszExtra, uValue);
3051 else
3052 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "%s value=%#x`%08x", pszExtra, RT_HI_U32(uValue), RT_LO_U32(uValue));
3053 return s_szBuf;
3054}
3055
3056
3057static const char *annotateIfMissingBits(uint64_t uValue, uint64_t fBits)
3058{
3059 static char s_szBuf[80];
3060 if ((uValue & fBits) == fBits)
3061 return annotateValue(uValue);
3062 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "XXX: Unexpected value %#llx - wanted bits %#llx to be set.", uValue, fBits);
3063 return s_szBuf;
3064}
3065
3066
3067static int reportMsr_Generic(uint32_t uMsr, uint32_t fFlags, uint64_t uValue)
3068{
3069 int rc;
3070 bool fTakesValue = false;
3071 const char *pszFnName = getMsrFnName(uMsr, &fTakesValue);
3072
3073 if (fFlags & VBCPUREPMSR_F_WRITE_ONLY)
3074 rc = printMsrWriteOnly(uMsr, pszFnName, NULL);
3075 else
3076 {
3077 bool fReadAsZero = doesMsrReadAsZero(uMsr);
3078 fTakesValue = fTakesValue && !fReadAsZero;
3079
3080
3081 switch (queryMsrWriteBadness(uMsr))
3082 {
3083 /* This is what we're here for... */
3084 case VBCPUREPBADNESS_MOSTLY_HARMLESS:
3085 {
3086 if ( msrProberModifyNoChange(uMsr)
3087 || msrProberModifyZero(uMsr))
3088 {
3089 uint64_t fSkipMask = getGenericSkipMask(uMsr);
3090 uint64_t fIgnMask = 0;
3091 uint64_t fGpMask = 0;
3092 rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
3093 if (RT_FAILURE(rc))
3094 return rc;
3095 adjustCanonicalIgnAndGpMasks(uMsr, &fIgnMask, &fGpMask);
3096
3097 if (pszFnName)
3098 {
3099 if (fGpMask == 0 && fIgnMask == UINT64_MAX && !fTakesValue)
3100 rc = printMsrFunctionIgnoreWrites(uMsr, pszFnName, annotateValue(uValue));
3101 else if (fGpMask == 0 && fIgnMask == 0 && (!fTakesValue || uValue == 0))
3102 rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValue(uValue));
3103 else
3104 rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, fTakesValue ? uValue : 0,
3105 fIgnMask, fGpMask, annotateValue(uValue));
3106 }
3107 else if (fGpMask == 0 && fIgnMask == UINT64_MAX)
3108 rc = printMsrValueIgnoreWrites(uMsr, fReadAsZero ? 0 : uValue, fReadAsZero ? annotateValue(uValue) : NULL);
3109 else
3110 rc = printMsrValueExtended(uMsr, fReadAsZero ? 0 : uValue, fIgnMask, fGpMask,
3111 fReadAsZero ? annotateValue(uValue) : NULL);
3112 }
3113 /* Most likely read-only. */
3114 else if (pszFnName && !fTakesValue)
3115 rc = printMsrFunctionReadOnly(uMsr, pszFnName, annotateValue(uValue));
3116 else if (pszFnName)
3117 rc = printMsrFunctionExtended(uMsr, pszFnName, "ReadOnly", uValue, 0, 0, annotateValue(uValue));
3118 else if (fReadAsZero)
3119 rc = printMsrValueReadOnly(uMsr, 0, annotateValue(uValue));
3120 else
3121 rc = printMsrValueReadOnly(uMsr, uValue, NULL);
3122 break;
3123 }
3124
3125 /* These should have special handling, so just do a simple
3126 write back same value check to see if it's writable. */
3127 case VBCPUREPBADNESS_MIGHT_BITE:
3128 if (msrProberModifyNoChange(uMsr))
3129 {
3130 if (pszFnName && !fTakesValue)
3131 rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValueExtra("Might bite.", uValue));
3132 else if (pszFnName)
3133 rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, uValue, 0, 0,
3134 annotateValueExtra("Might bite.", uValue));
3135 else if (fReadAsZero)
3136 rc = printMsrValueIgnoreWrites(uMsr, 0, annotateValueExtra("Might bite.", uValue));
3137 else
3138 rc = printMsrValueIgnoreWrites(uMsr, uValue, "Might bite.");
3139 }
3140 else if (pszFnName && !fTakesValue)
3141 rc = printMsrFunctionReadOnly(uMsr, pszFnName, annotateValueExtra("Might bite.", uValue));
3142 else if (pszFnName)
3143 rc = printMsrFunctionExtended(uMsr, pszFnName, "ReadOnly", uValue, 0, UINT64_MAX,
3144 annotateValueExtra("Might bite.", uValue));
3145 else if (fReadAsZero)
3146 rc = printMsrValueReadOnly(uMsr, 0, annotateValueExtra("Might bite.", uValue));
3147 else
3148 rc = printMsrValueReadOnly(uMsr, uValue, "Might bite.");
3149 break;
3150
3151
3152 /* Don't try anything with these guys. */
3153 case VBCPUREPBADNESS_BOND_VILLAIN:
3154 default:
3155 if (pszFnName && !fTakesValue)
3156 rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValueExtra("Villain?", uValue));
3157 else if (pszFnName)
3158 rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, uValue, 0, 0,
3159 annotateValueExtra("Villain?", uValue));
3160 else if (fReadAsZero)
3161 rc = printMsrValueIgnoreWrites(uMsr, 0, annotateValueExtra("Villain?", uValue));
3162 else
3163 rc = printMsrValueIgnoreWrites(uMsr, uValue, "Villain?");
3164 break;
3165 }
3166 }
3167
3168 return rc;
3169}
3170
3171
3172static int reportMsr_GenRangeFunctionEx(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, const char *pszRdWrFnName,
3173 uint32_t uMsrBase, bool fEarlyEndOk, bool fNoIgnMask, uint64_t fSkipMask, uint32_t *pidxLoop)
3174{
3175 uint32_t uMsr = paMsrs[0].uMsr;
3176 uint32_t iRange = uMsr - uMsrBase;
3177 Assert(cMax > iRange);
3178 cMax -= iRange;
3179
3180 /* Resolve default function name. */
3181 if (!pszRdWrFnName)
3182 {
3183 pszRdWrFnName = getMsrFnName(uMsr, NULL);
3184 if (!pszRdWrFnName)
3185 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "uMsr=%#x no function name\n", uMsr);
3186 }
3187
3188 /* Figure the possible register count. */
3189 if (cMax > cMsrs)
3190 cMax = cMsrs;
3191 uint32_t cRegs = 1;
3192 while ( cRegs < cMax
3193 && paMsrs[cRegs].uMsr == uMsr + cRegs)
3194 cRegs++;
3195
3196 /* Probe the first register and check that the others exhibit
3197 the same characteristics. */
3198 bool fReadOnly0;
3199 uint64_t fIgnMask0, fGpMask0;
3200 int rc = msrProberModifyBasicTests(uMsr, fSkipMask, &fReadOnly0, &fIgnMask0, &fGpMask0);
3201 if (RT_FAILURE(rc))
3202 return rc;
3203
3204 const char *pszAnnotation = NULL;
3205 for (uint32_t i = 1; i < cRegs; i++)
3206 {
3207 bool fReadOnlyN;
3208 uint64_t fIgnMaskN, fGpMaskN;
3209 rc = msrProberModifyBasicTests(paMsrs[i].uMsr, fSkipMask, &fReadOnlyN, &fIgnMaskN, &fGpMaskN);
3210 if (RT_FAILURE(rc))
3211 return rc;
3212 if ( fReadOnlyN != fReadOnly0
3213 || (fIgnMaskN != fIgnMask0 && !fNoIgnMask)
3214 || fGpMaskN != fGpMask0)
3215 {
3216 if (!fEarlyEndOk && !isMsrViaShanghaiDummy(uMsr, paMsrs[i].uValue, paMsrs[i].fFlags))
3217 {
3218 vbCpuRepDebug("MSR %s (%#x) range ended unexpectedly early on %#x: ro=%d ign=%#llx/%#llx gp=%#llx/%#llx [N/0]\n",
3219 getMsrNameHandled(uMsr), uMsr, paMsrs[i].uMsr,
3220 fReadOnlyN, fReadOnly0, fIgnMaskN, fIgnMask0, fGpMaskN, fGpMask0);
3221 pszAnnotation = "XXX: The range ended earlier than expected!";
3222 }
3223 cRegs = i;
3224 break;
3225 }
3226 }
3227
3228 /*
3229 * Report the range (or single MSR as it might be).
3230 */
3231 *pidxLoop += cRegs - 1;
3232
3233 if (fNoIgnMask)
3234 fIgnMask0 = 0;
3235 bool fSimple = fIgnMask0 == 0
3236 && (fGpMask0 == 0 || (fGpMask0 == UINT64_MAX && fReadOnly0))
3237 && iRange == 0;
3238 if (cRegs == 1)
3239 return printMsrFunctionExtendedIdxVal(uMsr, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName,
3240 iRange, fIgnMask0, fGpMask0,
3241 pszAnnotation ? pszAnnotation : annotateValue(paMsrs[0].uValue));
3242 if (fSimple)
3243 return printMsrRangeFunction(uMsr, uMsr + cRegs - 1,
3244 pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName, pszAnnotation);
3245
3246 return printMsrRangeFunctionExIdxVal(uMsr, uMsr + cRegs - 1, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName,
3247 iRange /*uValue*/, fIgnMask0, fGpMask0, pszAnnotation);
3248}
3249
3250
3251static int reportMsr_GenRangeFunction(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, const char *pszRdWrFnName,
3252 uint32_t *pidxLoop)
3253{
3254 return reportMsr_GenRangeFunctionEx(paMsrs, cMsrs, cMax, pszRdWrFnName, paMsrs[0].uMsr, false /*fEarlyEndOk*/, false /*fNoIgnMask*/,
3255 getGenericSkipMask(paMsrs[0].uMsr), pidxLoop);
3256}
3257
3258
3259/**
3260 * Generic report for an MSR implemented by functions, extended version.
3261 *
3262 * @returns VBox status code.
3263 * @param uMsr The MSR.
3264 * @param pszRdWrFnName The read/write function name, optional.
3265 * @param uValue The MSR range value.
3266 * @param fSkipMask Mask of bits to skip.
3267 * @param fNoGpMask Mask of bits to remove from the GP mask after
3268 * probing
3269 * @param pszAnnotate Annotation.
3270 */
3271static int reportMsr_GenFunctionEx(uint32_t uMsr, const char *pszRdWrFnName, uint32_t uValue,
3272 uint64_t fSkipMask, uint64_t fNoGpMask, const char *pszAnnotate)
3273{
3274 /* Resolve default function name. */
3275 if (!pszRdWrFnName)
3276 {
3277 pszRdWrFnName = getMsrFnName(uMsr, NULL);
3278 if (!pszRdWrFnName)
3279 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "uMsr=%#x no function name\n", uMsr);
3280 }
3281
3282 /* Probe the register and report. */
3283 uint64_t fIgnMask = 0;
3284 uint64_t fGpMask = 0;
3285 int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
3286 if (RT_SUCCESS(rc))
3287 {
3288 fGpMask &= ~fNoGpMask;
3289
3290 if (fGpMask == UINT64_MAX && uValue == 0 && !msrProberModifyZero(uMsr))
3291 rc = printMsrFunctionReadOnly(uMsr, pszRdWrFnName, pszAnnotate);
3292 else if (fIgnMask == UINT64_MAX && fGpMask == 0 && uValue == 0)
3293 rc = printMsrFunctionIgnoreWrites(uMsr, pszRdWrFnName, pszAnnotate);
3294 else if (fIgnMask != 0 && fGpMask == 0 && uValue == 0)
3295 rc = printMsrFunctionIgnoreMask(uMsr, pszRdWrFnName, NULL, fIgnMask, pszAnnotate);
3296 else if (fIgnMask == 0 && fGpMask == 0 && uValue == 0)
3297 rc = printMsrFunction(uMsr, pszRdWrFnName, NULL, pszAnnotate);
3298 else
3299 rc = printMsrFunctionExtended(uMsr, pszRdWrFnName, NULL, uValue, fIgnMask, fGpMask, pszAnnotate);
3300 }
3301 return rc;
3302}
3303
3304
3305/**
3306 * Reports a VIA/Shanghai dummy range.
3307 *
3308 * @returns VBox status code.
3309 * @param paMsrs Pointer to the first MSR.
3310 * @param cMsrs The number of MSRs in the array @a paMsr.
3311 * @param pidxLoop Index variable that should be advanced to the
3312 * last MSR entry in the range.
3313 */
3314static int reportMsr_ViaShanghaiDummyRange(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3315{
3316 /* Figure how many. */
3317 uint32_t uMsr = paMsrs[0].uMsr;
3318 uint32_t cRegs = 1;
3319 while ( cRegs < cMsrs
3320 && paMsrs[cRegs].uMsr == uMsr + cRegs
3321 && isMsrViaShanghaiDummy(paMsrs[cRegs].uMsr, paMsrs[cRegs].uValue, paMsrs[cRegs].fFlags))
3322 {
3323 cRegs++;
3324 if (!(cRegs % 0x80))
3325 vbCpuRepDebug("VIA dummy detection %#llx..%#llx (%#x regs)...\n", uMsr, uMsr + cRegs - 1, cRegs);
3326 }
3327
3328 /* Advance. */
3329 *pidxLoop += cRegs - 1;
3330
3331 /* Report it/them. */
3332 char szName[80];
3333 if (cRegs == 1)
3334 {
3335 RTStrPrintf(szName, sizeof(szName), "ZERO_%04x_%04x", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
3336 return printMsrValueIgnoreWritesNamed(uMsr, 0, szName, NULL);
3337 }
3338
3339 uint32_t uMsrLast = uMsr + cRegs - 1;
3340 RTStrPrintf(szName, sizeof(szName), "ZERO_%04x_%04x_THRU_%04x_%04x",
3341 RT_HI_U16(uMsr), RT_LO_U16(uMsr), RT_HI_U16(uMsrLast), RT_LO_U16(uMsrLast));
3342 return printMsrRangeValueIgnoreWritesNamed(uMsr, uMsrLast, 0, szName, NULL);
3343}
3344
3345
3346/**
3347 * Special function for reporting the IA32_APIC_BASE register, as it seems to be
3348 * causing trouble on newer systems.
3349 *
3350 * @returns
3351 * @param uMsr The MSR number.
3352 * @param uValue The value.
3353 */
3354static int reportMsr_Ia32ApicBase(uint32_t uMsr, uint64_t uValue)
3355{
3356 /* Trouble with the generic treatment of both the "APIC Global Enable" and
3357 "Enable x2APIC mode" bits on an i7-3820QM running OS X 10.8.5. */
3358 uint64_t fSkipMask = RT_BIT_64(11);
3359 if (vbCpuRepSupportsX2Apic())
3360 fSkipMask |= RT_BIT_64(10);
3361 /* For some reason, twiddling this bit kills a Tualatin PIII-S. */
3362 if (g_enmMicroarch == kCpumMicroarch_Intel_P6_III)
3363 fSkipMask |= RT_BIT(9);
3364
3365 /* If the OS uses the APIC, we have to be super careful. */
3366 if (!g_MsrAcc.fAtomic)
3367 fSkipMask |= UINT64_C(0x0000000ffffff000);
3368
3369 return reportMsr_GenFunctionEx(uMsr, "Ia32ApicBase", uValue, fSkipMask, 0, NULL);
3370}
3371
3372
3373/**
3374 * Special function for reporting the IA32_MISC_ENABLE register, as it seems to
3375 * be causing trouble on newer systems.
3376 *
3377 * @returns
3378 * @param uMsr The MSR number.
3379 * @param uValue The value.
3380 */
3381static int reportMsr_Ia32MiscEnable(uint32_t uMsr, uint64_t uValue)
3382{
3383 uint64_t fSkipMask = 0;
3384
3385 if ( ( g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Broadwell
3386 && g_enmMicroarch <= kCpumMicroarch_Intel_Core7_End)
3387 || ( g_enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
3388 && g_enmMicroarch <= kCpumMicroarch_Intel_Atom_End)
3389 )
3390 {
3391 vbCpuRepPrintf("WARNING: IA32_MISC_ENABLE probing needs hacking on this CPU!\n");
3392 RTThreadSleep(128);
3393 }
3394
3395 /* If the OS is using MONITOR/MWAIT we'd better not disable it! */
3396 if (!g_MsrAcc.fAtomic)
3397 fSkipMask |= RT_BIT(18);
3398
3399 /* The no execute related flag is deadly if clear. */
3400 if ( !(uValue & MSR_IA32_MISC_ENABLE_XD_DISABLE)
3401 && ( g_enmMicroarch < kCpumMicroarch_Intel_First
3402 || g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
3403 || vbCpuRepSupportsNX() ) )
3404 fSkipMask |= MSR_IA32_MISC_ENABLE_XD_DISABLE;
3405
3406 uint64_t fIgnMask = 0;
3407 uint64_t fGpMask = 0;
3408 int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
3409 if (RT_SUCCESS(rc))
3410 rc = printMsrFunctionExtended(uMsr, "Ia32MiscEnable", "Ia32MiscEnable", uValue,
3411 fIgnMask, fGpMask, annotateValue(uValue));
3412 return rc;
3413}
3414
3415
3416/**
3417 * Verifies that MTRR type field works correctly in the given MSR.
3418 *
3419 * @returns VBox status code (failure if bad MSR behavior).
3420 * @param uMsr The MSR.
3421 * @param iBit The first bit of the type field (8-bit wide).
3422 * @param cExpected The number of types expected - PAT=8, MTRR=7.
3423 */
3424static int msrVerifyMtrrTypeGPs(uint32_t uMsr, uint32_t iBit, uint32_t cExpected)
3425{
3426 uint32_t uEndTypes = 0;
3427 while (uEndTypes < 255)
3428 {
3429 bool fGp = !msrProberModifySimpleGp(uMsr, ~(UINT64_C(0xff) << iBit), (uint64_t)uEndTypes << iBit);
3430 if (!fGp && (uEndTypes == 2 || uEndTypes == 3))
3431 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types %u does not cause a GP as it should. (msr %#x)\n",
3432 uEndTypes, uMsr);
3433 if (fGp && uEndTypes != 2 && uEndTypes != 3)
3434 break;
3435 uEndTypes++;
3436 }
3437 if (uEndTypes != cExpected)
3438 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types detected to be %#x (msr %#x). Expected %#x.\n",
3439 uEndTypes, uMsr, cExpected);
3440 return VINF_SUCCESS;
3441}
3442
3443
3444/**
3445 * Deals with the variable MTRR MSRs.
3446 *
3447 * @returns VBox status code.
3448 * @param paMsrs Pointer to the first variable MTRR MSR (200h).
3449 * @param cMsrs The number of MSRs in the array @a paMsr.
3450 * @param pidxLoop Index variable that should be advanced to the
3451 * last MTRR MSR entry.
3452 */
3453static int reportMsr_Ia32MtrrPhysBaseMaskN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3454{
3455 uint32_t uMsr = paMsrs[0].uMsr;
3456
3457 /* Count them. */
3458 uint32_t cRegs = 1;
3459 while ( cRegs < cMsrs
3460 && paMsrs[cRegs].uMsr == uMsr + cRegs
3461 && !isMsrViaShanghaiDummy(paMsrs[cRegs].uMsr, paMsrs[cRegs].uValue, paMsrs[cRegs].fFlags) )
3462 cRegs++;
3463 if (cRegs & 1)
3464 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR variable MSR range is odd: cRegs=%#x\n", cRegs);
3465 if (cRegs > 0x20)
3466 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR variable MSR range is too large: cRegs=%#x\n", cRegs);
3467
3468 /* Find a disabled register that we can play around with. */
3469 uint32_t iGuineaPig;
3470 for (iGuineaPig = 0; iGuineaPig < cRegs; iGuineaPig += 2)
3471 if (!(paMsrs[iGuineaPig + 1].uValue & RT_BIT_32(11)))
3472 break;
3473 if (iGuineaPig >= cRegs)
3474 iGuineaPig = cRegs - 2;
3475 vbCpuRepDebug("iGuineaPig=%#x -> %#x\n", iGuineaPig, uMsr + iGuineaPig);
3476
3477 /* Probe the base. */
3478 uint64_t fIgnBase = 0;
3479 uint64_t fGpBase = 0;
3480 int rc = msrProberModifyBitChanges(uMsr + iGuineaPig, &fIgnBase, &fGpBase, 0);
3481 if (RT_FAILURE(rc))
3482 return rc;
3483 rc = msrVerifyMtrrTypeGPs(uMsr + iGuineaPig, 0, 7);
3484 if (RT_FAILURE(rc))
3485 return rc;
3486 vbCpuRepDebug("fIgnBase=%#llx fGpBase=%#llx\n", fIgnBase, fGpBase);
3487
3488 /* Probing the mask is relatively straight forward. */
3489 uint64_t fIgnMask = 0;
3490 uint64_t fGpMask = 0;
3491 rc = msrProberModifyBitChanges(uMsr + iGuineaPig + 1, &fIgnMask, &fGpMask, 0x800); /* enabling it may cause trouble */
3492 if (RT_FAILURE(rc))
3493 return rc;
3494 vbCpuRepDebug("fIgnMask=%#llx fGpMask=%#llx\n", fIgnMask, fGpMask);
3495
3496 /* Validate that the whole range subscribes to the apprimately same GP rules. */
3497 for (uint32_t i = 0; i < cRegs; i += 2)
3498 {
3499 uint64_t fSkipBase = ~fGpBase;
3500 uint64_t fSkipMask = ~fGpMask;
3501 if (!(paMsrs[i + 1].uValue & RT_BIT_32(11)))
3502 fSkipBase = fSkipMask = 0;
3503 fSkipBase |= 0x7; /* Always skip the type. */
3504 fSkipMask |= RT_BIT_32(11); /* Always skip the enable bit. */
3505
3506 vbCpuRepDebug("i=%#x fSkipBase=%#llx fSkipMask=%#llx\n", i, fSkipBase, fSkipMask);
3507
3508 if (!(paMsrs[i + 1].uValue & RT_BIT_32(11)))
3509 {
3510 rc = msrVerifyMtrrTypeGPs(uMsr + iGuineaPig, 0, 7);
3511 if (RT_FAILURE(rc))
3512 return rc;
3513 }
3514
3515 uint64_t fIgnBaseN = 0;
3516 uint64_t fGpBaseN = 0;
3517 rc = msrProberModifyBitChanges(uMsr + i, &fIgnBaseN, &fGpBaseN, fSkipBase);
3518 if (RT_FAILURE(rc))
3519 return rc;
3520
3521 if ( fIgnBaseN != (fIgnBase & ~fSkipBase)
3522 || fGpBaseN != (fGpBase & ~fSkipBase) )
3523 return RTMsgErrorRc(VERR_INVALID_PARAMETER,
3524 "MTRR PHYS BASE register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipBase=%#llx)\n",
3525 uMsr + i, uMsr + iGuineaPig,
3526 fIgnBaseN, fIgnBase & ~fSkipBase, fGpBaseN, fGpBase & ~fSkipBase, fSkipBase);
3527
3528 uint64_t fIgnMaskN = 0;
3529 uint64_t fGpMaskN = 0;
3530 rc = msrProberModifyBitChanges(uMsr + i + 1, &fIgnMaskN, &fGpMaskN, fSkipMask);
3531 if (RT_FAILURE(rc))
3532 return rc;
3533 if ( fIgnMaskN != (fIgnMask & ~fSkipMask)
3534 || fGpMaskN != (fGpMask & ~fSkipMask) )
3535 return RTMsgErrorRc(VERR_INVALID_PARAMETER,
3536 "MTRR PHYS MASK register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipMask=%#llx)\n",
3537 uMsr + i + 1, uMsr + iGuineaPig + 1,
3538 fIgnMaskN, fIgnMask & ~fSkipMask, fGpMaskN, fGpMask & ~fSkipMask, fSkipMask);
3539 }
3540
3541 /* Print the whole range. */
3542 fGpBase &= ~(uint64_t)0x7; /* Valid type bits, see msrVerifyMtrrTypeGPs(). */
3543 for (uint32_t i = 0; i < cRegs; i += 2)
3544 {
3545 printMsrFunctionExtendedIdxVal(uMsr + i, "Ia32MtrrPhysBaseN", NULL, i / 2, fIgnBase, fGpBase,
3546 annotateValue(paMsrs[i].uValue));
3547 printMsrFunctionExtendedIdxVal(uMsr + i + 1, "Ia32MtrrPhysMaskN", NULL, i / 2, fIgnMask, fGpMask,
3548 annotateValue(paMsrs[i + 1].uValue));
3549 }
3550
3551 *pidxLoop += cRegs - 1;
3552 return VINF_SUCCESS;
3553}
3554
3555
3556/**
3557 * Deals with fixed MTRR and PAT MSRs, checking the 8 memory type fields.
3558 *
3559 * @returns VBox status code.
3560 * @param uMsr The MSR.
3561 */
3562static int reportMsr_Ia32MtrrFixedOrPat(uint32_t uMsr)
3563{
3564 /* Had a spot of trouble on an old macbook pro with core2 duo T9900 (penryn)
3565 running 64-bit win81pe. Not giving PAT such a scrutiny fixes it. */
3566 if ( uMsr != 0x00000277
3567 || ( g_enmVendor == CPUMCPUVENDOR_INTEL
3568 ? g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First
3569 : g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON
3570 ? g_enmMicroarch != kCpumMicroarch_AMD_K8_90nm_AMDV
3571 : true) )
3572 {
3573 /* Every 8 bytes is a type, check the type ranges one by one. */
3574 for (uint32_t iBit = 0; iBit < 64; iBit += 8)
3575 {
3576 int rc = msrVerifyMtrrTypeGPs(uMsr, iBit, 7 + (uMsr == 0x00000277));
3577 if (RT_FAILURE(rc))
3578 return rc;
3579 }
3580 }
3581
3582 return printMsrFunctionCpumCpu(uMsr, NULL, NULL, NULL, NULL);
3583}
3584
3585
3586/**
3587 * Deals with IA32_MTRR_DEF_TYPE.
3588 *
3589 * @returns VBox status code.
3590 * @param uMsr The MSR.
3591 */
3592static int reportMsr_Ia32MtrrDefType(uint32_t uMsr)
3593{
3594 uint64_t fGpMask = 0;
3595 uint64_t fIgnMask = 0;
3596 if (g_enmMicroarch == kCpumMicroarch_AMD_K8_90nm_AMDV)
3597 {
3598 /* Problematic CPU! Fake it for now. */
3599 fGpMask = ~(uint64_t)0xc07;
3600 fIgnMask = 0;
3601 }
3602 else
3603 {
3604 int rc = msrVerifyMtrrTypeGPs(uMsr, 0, 7);
3605 if (RT_FAILURE(rc))
3606 return rc;
3607
3608 rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, 0x7);
3609 if (RT_FAILURE(rc))
3610 return rc;
3611 Assert(!(fGpMask & 7)); Assert(!(fIgnMask & 7));
3612 }
3613
3614 return printMsrFunctionCpumCpuEx(uMsr, NULL, NULL, NULL, fIgnMask, fGpMask, NULL);
3615}
3616
3617
3618/**
3619 * Deals with the Machine Check (MC) MSRs in the 400h+ area.
3620 *
3621 * @returns VBox status code.
3622 * @param paMsrs Pointer to the first MC MSR (400h).
3623 * @param cMsrs The number of MSRs in the array @a paMsr.
3624 * @param pidxLoop Index variable that should be advanced to the
3625 * last MC MSR entry.
3626 */
3627static int reportMsr_Ia32McCtlStatusAddrMiscN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3628{
3629 uint32_t uMsr = paMsrs[0].uMsr;
3630
3631 /* Count them. */
3632 uint32_t cRegs = 1;
3633 uint32_t cDetectedRegs = 1;
3634 while ( cDetectedRegs < cMsrs
3635 && ( paMsrs[cDetectedRegs].uMsr == uMsr + cRegs
3636 || (cRegs & 3) == 2 /* ADDR may or may not be there, depends on STATUS and CPU. */
3637 || (cRegs & 3) == 3 /* MISC may or may not be there, depends on STATUS and CPU. */
3638 || cRegs == 0x13 /* MC4_MISC may not be there, depends on CPU. */
3639 || cRegs == 0x14 /* MC5_CTL may not be there, depends on CPU. */)
3640 && cRegs < 0x7f )
3641 {
3642 if (paMsrs[cDetectedRegs].uMsr == uMsr + cRegs)
3643 cDetectedRegs++;
3644 cRegs++;
3645 }
3646 if (cRegs & 3)
3647 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MC MSR range is odd: cRegs=%#x\n", cRegs);
3648
3649 /* Just report them. We don't bother probing here as the CTL format
3650 and such seems to be a lot of work to test correctly and changes between
3651 cpu generations. */
3652 *pidxLoop += cDetectedRegs - 1;
3653 return printMsrRangeFunction(uMsr, uMsr + cRegs - 1, "Ia32McCtlStatusAddrMiscN", NULL, NULL);
3654}
3655
3656
3657
3658/**
3659 * Deals with the X2APIC msrs.
3660 *
3661 * @returns VBox status code.
3662 * @param paMsrs Pointer to the first X2APIC MSR.
3663 * @param cMsrs The number of MSRs in the array @a paMsr.
3664 * @param pidxLoop Index variable that should be advanced to the
3665 * last X2APIC MSR entry.
3666 */
3667static int reportMsr_GenX2Apic(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3668{
3669 /* Advance. */
3670 uint32_t cRegs = 1;
3671 while ( cRegs < cMsrs
3672 && paMsrs[cRegs].uMsr <= 0x8ff)
3673 cRegs++;
3674 *pidxLoop += cRegs - 1;
3675
3676 /* Just emit an X2APIC range. */
3677 return printMsrRangeFunction(0x800, 0x8ff, "Ia32X2ApicN", NULL, NULL);
3678}
3679
3680
3681/**
3682 * Deals carefully with the EFER register.
3683 *
3684 * @returns VBox status code.
3685 * @param uMsr The MSR number.
3686 * @param uValue The current value.
3687 */
3688static int reportMsr_Amd64Efer(uint32_t uMsr, uint64_t uValue)
3689{
3690 uint64_t fSkipMask = 0;
3691 if (vbCpuRepSupportsLongMode())
3692 {
3693 fSkipMask |= MSR_K6_EFER_LME;
3694 if (!g_MsrAcc.fAtomic && (uValue & MSR_K6_EFER_SCE))
3695 fSkipMask |= MSR_K6_EFER_SCE;
3696 }
3697 if ( (uValue & MSR_K6_EFER_NXE)
3698 || vbCpuRepSupportsNX())
3699 fSkipMask |= MSR_K6_EFER_NXE;
3700
3701 /* NetBurst prescott 2MB (model 4) hung or triple faulted here. The extra
3702 sleep or something seemed to help for some screwed up reason. */
3703 if (g_fIntelNetBurst)
3704 {
3705 // This doesn't matter:
3706 //fSkipMask |= MSR_K6_EFER_SCE;
3707 //if (vbCpuRepSupportsLongMode())
3708 // fSkipMask |= MSR_K6_EFER_LMA;
3709 //vbCpuRepDebug("EFER - netburst workaround - ignore SCE & LMA (fSkipMask=%#llx)\n", fSkipMask);
3710
3711 vbCpuRepDebug("EFER - netburst sleep fudge - fSkipMask=%#llx\n", fSkipMask);
3712 RTThreadSleep(1000);
3713 }
3714
3715 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, MSR_K6_EFER_LMA, NULL);
3716}
3717
3718
3719/**
3720 * Deals with the MC4_MISCn (n >= 1) range and the following reserved MSRs.
3721 *
3722 * @returns VBox status code.
3723 * @param paMsrs Pointer to the first MSR.
3724 * @param cMsrs The number of MSRs in the array @a paMsr.
3725 * @param pidxLoop Index variable that should be advanced to the
3726 * last MSR entry in the range.
3727 */
3728static int reportMsr_AmdFam10hMc4MiscN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3729{
3730 /* Count registers. */
3731 uint32_t cRegs = 1;
3732 while ( cRegs < cMsrs
3733 && cRegs < 8
3734 && paMsrs[cRegs].uMsr == paMsrs[0].uMsr + cRegs)
3735 cRegs++;
3736
3737 /* Probe & report used MSRs. */
3738 uint64_t fIgnMask = 0;
3739 uint64_t fGpMask = 0;
3740 uint32_t cUsed = 0;
3741 while (cUsed < cRegs)
3742 {
3743 uint64_t fIgnMaskN = 0;
3744 uint64_t fGpMaskN = 0;
3745 int rc = msrProberModifyBitChanges(paMsrs[cUsed].uMsr, &fIgnMaskN, &fGpMaskN, 0);
3746 if (RT_FAILURE(rc))
3747 return rc;
3748 if (fIgnMaskN == UINT64_MAX || fGpMaskN == UINT64_MAX)
3749 break;
3750 if (cUsed == 0)
3751 {
3752 fIgnMask = fIgnMaskN;
3753 fGpMask = fGpMaskN;
3754 }
3755 else if ( fIgnMaskN != fIgnMask
3756 || fGpMaskN != fGpMask)
3757 return RTMsgErrorRc(VERR_NOT_EQUAL, "AmdFam16hMc4MiscN mismatch: fIgn=%#llx/%#llx fGp=%#llx/%#llx uMsr=%#x\n",
3758 fIgnMaskN, fIgnMask, fGpMaskN, fGpMask, paMsrs[cUsed].uMsr);
3759 cUsed++;
3760 }
3761 if (cUsed > 0)
3762 printMsrRangeFunctionEx(paMsrs[0].uMsr, paMsrs[cUsed - 1].uMsr, "AmdFam10hMc4MiscN", NULL, 0, fIgnMask, fGpMask, NULL);
3763
3764 /* Probe & report reserved MSRs. */
3765 uint32_t cReserved = 0;
3766 while (cUsed + cReserved < cRegs)
3767 {
3768 fIgnMask = fGpMask = 0;
3769 int rc = msrProberModifyBitChanges(paMsrs[cUsed + cReserved].uMsr, &fIgnMask, &fGpMask, 0);
3770 if (RT_FAILURE(rc))
3771 return rc;
3772 if ((fIgnMask != UINT64_MAX && fGpMask != UINT64_MAX) || paMsrs[cUsed + cReserved].uValue)
3773 return RTMsgErrorRc(VERR_NOT_EQUAL,
3774 "Unexpected reserved AmdFam16hMc4MiscN: fIgn=%#llx fGp=%#llx uMsr=%#x uValue=%#llx\n",
3775 fIgnMask, fGpMask, paMsrs[cUsed + cReserved].uMsr, paMsrs[cUsed + cReserved].uValue);
3776 cReserved++;
3777 }
3778 if (cReserved > 0 && fIgnMask == UINT64_MAX)
3779 printMsrRangeValueIgnoreWrites(paMsrs[cUsed].uMsr, paMsrs[cUsed + cReserved - 1].uMsr, 0, NULL);
3780 else if (cReserved > 0 && fGpMask == UINT64_MAX)
3781 printMsrRangeValueReadOnly(paMsrs[cUsed].uMsr, paMsrs[cUsed + cReserved - 1].uMsr, 0, NULL);
3782
3783 *pidxLoop += cRegs - 1;
3784 return VINF_SUCCESS;
3785}
3786
3787
3788/**
3789 * Deals with the AMD PERF_CTL range.
3790 *
3791 * @returns VBox status code.
3792 * @param paMsrs Pointer to the first MSR.
3793 * @param cMsrs The number of MSRs in the array @a paMsr.
3794 * @param pidxLoop Index variable that should be advanced to the
3795 * last MSR entry in the range.
3796 */
3797static int reportMsr_AmdK8PerfCtlN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3798{
3799 uint32_t uMsr = paMsrs[0].uMsr;
3800 Assert(uMsr == 0xc0010000);
3801
3802 /* Family 15h (bulldozer +) aliases these registers sparsely onto c001020x. */
3803 if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
3804 {
3805 for (uint32_t i = 0; i < 4; i++)
3806 printMsrAlias(uMsr + i, 0xc0010200 + i * 2, NULL);
3807 *pidxLoop += 3;
3808 }
3809 else
3810 return reportMsr_GenRangeFunction(paMsrs, cMsrs, 4, "AmdK8PerfCtlN", pidxLoop);
3811 return VINF_SUCCESS;
3812}
3813
3814
3815/**
3816 * Deals with the AMD PERF_CTR range.
3817 *
3818 * @returns VBox status code.
3819 * @param paMsrs Pointer to the first MSR.
3820 * @param cMsrs The number of MSRs in the array @a paMsr.
3821 * @param pidxLoop Index variable that should be advanced to the
3822 * last MSR entry in the range.
3823 */
3824static int reportMsr_AmdK8PerfCtrN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3825{
3826 uint32_t uMsr = paMsrs[0].uMsr;
3827 Assert(uMsr == 0xc0010004);
3828
3829 /* Family 15h (bulldozer +) aliases these registers sparsely onto c001020x. */
3830 if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
3831 {
3832 for (uint32_t i = 0; i < 4; i++)
3833 printMsrAlias(uMsr + i, 0xc0010201 + i * 2, NULL);
3834 *pidxLoop += 3;
3835 }
3836 else
3837 return reportMsr_GenRangeFunction(paMsrs, cMsrs, 4, "AmdK8PerfCtrN", pidxLoop);
3838 return VINF_SUCCESS;
3839}
3840
3841
3842/**
3843 * Deals carefully with the SYS_CFG register.
3844 *
3845 * @returns VBox status code.
3846 * @param uMsr The MSR number.
3847 * @param uValue The current value.
3848 */
3849static int reportMsr_AmdK8SysCfg(uint32_t uMsr, uint64_t uValue)
3850{
3851 uint64_t fSkipMask = 0;
3852
3853 /* Bit 21 (MtrrTom2En) is marked reserved in family 0fh, while in family
3854 10h BKDG this changes (as does the document style). Testing this bit
3855 causes bulldozer running win64 to restart, thus this special treatment. */
3856 if (g_enmMicroarch >= kCpumMicroarch_AMD_K10)
3857 fSkipMask |= RT_BIT(21);
3858
3859 /* Turns out there are more killer bits here, at least on Opteron 2384.
3860 Skipping all known bits. */
3861 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV /* Not sure when introduced - harmless? */)
3862 fSkipMask |= RT_BIT(22); /* Tom2ForceMemTypeWB */
3863 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3864 fSkipMask |= RT_BIT(21); /* MtrrTom2En */
3865 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3866 fSkipMask |= RT_BIT(20); /* MtrrVarDramEn*/
3867 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3868 fSkipMask |= RT_BIT(19); /* MtrrFixDramModEn */
3869 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3870 fSkipMask |= RT_BIT(18); /* MtrrFixDramEn */
3871 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3872 fSkipMask |= RT_BIT(17); /* SysUcLockEn */
3873 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3874 fSkipMask |= RT_BIT(16); /* ChgToDirtyDis */
3875 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First && g_enmMicroarch < kCpumMicroarch_AMD_15h_First)
3876 fSkipMask |= RT_BIT(10); /* SetDirtyEnO */
3877 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First && g_enmMicroarch < kCpumMicroarch_AMD_15h_First)
3878 fSkipMask |= RT_BIT(9); /* SetDirtyEnS */
3879 if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3880 || CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
3881 fSkipMask |= RT_BIT(8); /* SetDirtyEnE */
3882 if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3883 || CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
3884 fSkipMask |= RT_BIT(7) /* SysVicLimit */
3885 | RT_BIT(6) /* SysVicLimit */
3886 | RT_BIT(5) /* SysVicLimit */
3887 | RT_BIT(4) /* SysAckLimit */
3888 | RT_BIT(3) /* SysAckLimit */
3889 | RT_BIT(2) /* SysAckLimit */
3890 | RT_BIT(1) /* SysAckLimit */
3891 | RT_BIT(0) /* SysAckLimit */;
3892
3893 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
3894}
3895
3896
3897/**
3898 * Deals carefully with the HWCR register.
3899 *
3900 * @returns VBox status code.
3901 * @param uMsr The MSR number.
3902 * @param uValue The current value.
3903 */
3904static int reportMsr_AmdK8HwCr(uint32_t uMsr, uint64_t uValue)
3905{
3906 uint64_t fSkipMask = 0;
3907
3908 /* Trouble on Opteron 2384, skip some of the known bits. */
3909 if (g_enmMicroarch >= kCpumMicroarch_AMD_K10 && !CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch))
3910 fSkipMask |= /*RT_BIT(10)*/ 0 /* MonMwaitUserEn */
3911 | RT_BIT(9); /* MonMwaitDis */
3912 fSkipMask |= RT_BIT(8); /* #IGNNE port emulation */
3913 if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3914 || CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
3915 fSkipMask |= RT_BIT(7) /* DisLock */
3916 | RT_BIT(6); /* FFDis (TLB flush filter) */
3917 fSkipMask |= RT_BIT(4); /* INVD to WBINVD */
3918 fSkipMask |= RT_BIT(3); /* TLBCACHEDIS */
3919 if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3920 || CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
3921 || CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
3922 fSkipMask |= RT_BIT(1); /* SLOWFENCE */
3923 fSkipMask |= RT_BIT(0); /* SMMLOCK */
3924
3925 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
3926}
3927
3928
3929/**
3930 * Deals carefully with a IORRBasei register.
3931 *
3932 * @returns VBox status code.
3933 * @param uMsr The MSR number.
3934 * @param uValue The current value.
3935 */
3936static int reportMsr_AmdK8IorrBaseN(uint32_t uMsr, uint64_t uValue)
3937{
3938 /* Skip know bits here, as harm seems to come from messing with them. */
3939 uint64_t fSkipMask = RT_BIT(4) | RT_BIT(3);
3940 fSkipMask |= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK;
3941 return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010016) / 2, fSkipMask, 0, annotateValue(uValue));
3942}
3943
3944
3945/**
3946 * Deals carefully with a IORRMaski register.
3947 *
3948 * @returns VBox status code.
3949 * @param uMsr The MSR number.
3950 * @param uValue The current value.
3951 */
3952static int reportMsr_AmdK8IorrMaskN(uint32_t uMsr, uint64_t uValue)
3953{
3954 /* Skip know bits here, as harm seems to come from messing with them. */
3955 uint64_t fSkipMask = RT_BIT(11);
3956 fSkipMask |= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK;
3957 return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010017) / 2, fSkipMask, 0, annotateValue(uValue));
3958}
3959
3960
3961/**
3962 * Deals carefully with a IORRMaski register.
3963 *
3964 * @returns VBox status code.
3965 * @param uMsr The MSR number.
3966 * @param uValue The current value.
3967 */
3968static int reportMsr_AmdK8TopMemN(uint32_t uMsr, uint64_t uValue)
3969{
3970 /* Skip know bits here, as harm seems to come from messing with them. */
3971 uint64_t fSkipMask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(RT_BIT_64(23) - 1);
3972 return reportMsr_GenFunctionEx(uMsr, NULL, uMsr == 0xc001001d, fSkipMask, 0, annotateValue(uValue));
3973}
3974
3975
3976/**
3977 * Deals with the AMD P-state config range.
3978 *
3979 * @returns VBox status code.
3980 * @param paMsrs Pointer to the first MSR.
3981 * @param cMsrs The number of MSRs in the array @a paMsr.
3982 * @param pidxLoop Index variable that should be advanced to the
3983 * last MSR entry in the range.
3984 */
3985static int reportMsr_AmdFam10hPStateN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3986{
3987 uint32_t uMsr = paMsrs[0].uMsr;
3988 AssertRelease(uMsr == 0xc0010064);
3989
3990 /* Count them. */
3991 uint32_t cRegs = 1;
3992 while ( cRegs < 8
3993 && cRegs < cMsrs
3994 && paMsrs[cRegs].uMsr == uMsr + cRegs)
3995 cRegs++;
3996
3997 /* Figure out which bits we should skip when probing. This is based on
3998 specs and may need adjusting for real life when handy. */
3999 uint64_t fSkipMask = RT_BIT_64(63); /* PstateEn */
4000 fSkipMask |= RT_BIT_64(41) | RT_BIT_64(40); /* IddDiv */
4001 fSkipMask |= UINT64_C(0x000000ff00000000); /* IddValue */
4002 if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
4003 fSkipMask |= UINT32_C(0xfe000000); /* NbVid - Northbridge VID */
4004 if ( CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
4005 || CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
4006 fSkipMask |= RT_BIT_32(22); /* NbDid or NbPstate. */
4007 if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
4008 fSkipMask |= RT_BIT_32(16); /* CpuVid[7] */
4009 fSkipMask |= UINT32_C(0x0000fe00); /* CpuVid[6:0] */
4010 fSkipMask |= UINT32_C(0x000001c0); /* CpuDid */
4011 fSkipMask |= UINT32_C(0x0000003f); /* CpuFid */
4012
4013 /* Probe and report them one by one since we're passing values instead of
4014 register indexes to the functions. */
4015 for (uint32_t i = 0; i < cRegs; i++)
4016 {
4017 uint64_t fIgnMask = 0;
4018 uint64_t fGpMask = 0;
4019 int rc = msrProberModifyBitChanges(uMsr + i, &fIgnMask, &fGpMask, fSkipMask);
4020 if (RT_FAILURE(rc))
4021 return rc;
4022 printMsrFunctionExtended(uMsr + i, "AmdFam10hPStateN", NULL, paMsrs[i].uValue, fIgnMask, fGpMask,
4023 annotateValue(paMsrs[i].uValue));
4024 }
4025
4026 /* Advance. */
4027 *pidxLoop += cRegs - 1;
4028 return VINF_SUCCESS;
4029}
4030
4031
4032/**
4033 * Deals carefully with a COFVID control register.
4034 *
4035 * @returns VBox status code.
4036 * @param uMsr The MSR number.
4037 * @param uValue The current value.
4038 */
4039static int reportMsr_AmdFam10hCofVidControl(uint32_t uMsr, uint64_t uValue)
4040{
4041 /* Skip know bits here, as harm seems to come from messing with them. */
4042 uint64_t fSkipMask = 0;
4043 if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
4044 fSkipMask |= UINT32_C(0xfe000000); /* NbVid - Northbridge VID */
4045 else if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_First) /* Listed in preliminary Fam16h BDKG. */
4046 fSkipMask |= UINT32_C(0xff000000); /* NbVid - Northbridge VID - includes bit 24 for Fam15h and Fam16h. Odd... */
4047 if ( CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
4048 || g_enmMicroarch >= kCpumMicroarch_AMD_15h_First) /* Listed in preliminary Fam16h BDKG. */
4049 fSkipMask |= RT_BIT_32(22); /* NbDid or NbPstate. */
4050 if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
4051 fSkipMask |= RT_BIT_32(20); /* CpuVid[7] */
4052 fSkipMask |= UINT32_C(0x00070000); /* PstatId */
4053 fSkipMask |= UINT32_C(0x0000fe00); /* CpuVid[6:0] */
4054 fSkipMask |= UINT32_C(0x000001c0); /* CpuDid */
4055 fSkipMask |= UINT32_C(0x0000003f); /* CpuFid */
4056
4057 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
4058}
4059
4060
4061/**
4062 * Deals with the AMD [|L2I_|NB_]PERF_CT[LR] mixed ranges.
4063 *
4064 * Mixed here refers to the control and counter being in mixed in pairs as
4065 * opposed to them being two separate parallel arrays like in the 0xc0010000
4066 * area.
4067 *
4068 * @returns VBox status code.
4069 * @param paMsrs Pointer to the first MSR.
4070 * @param cMsrs The number of MSRs in the array @a paMsr.
4071 * @param cMax The max number of MSRs (not counters).
4072 * @param pidxLoop Index variable that should be advanced to the
4073 * last MSR entry in the range.
4074 */
4075static int reportMsr_AmdGenPerfMixedRange(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, uint32_t *pidxLoop)
4076{
4077 uint32_t uMsr = paMsrs[0].uMsr;
4078
4079 /* Count them. */
4080 uint32_t cRegs = 1;
4081 while ( cRegs < cMax
4082 && cRegs < cMsrs
4083 && paMsrs[cRegs].uMsr == uMsr + cRegs)
4084 cRegs++;
4085 if (cRegs & 1)
4086 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "PERF range at %#x is odd: cRegs=%#x\n", uMsr, cRegs);
4087
4088 /* Report them as individual entries, using default names and such. */
4089 for (uint32_t i = 0; i < cRegs; i++)
4090 {
4091 uint64_t fIgnMask = 0;
4092 uint64_t fGpMask = 0;
4093 int rc = msrProberModifyBitChanges(uMsr + i, &fIgnMask, &fGpMask, 0);
4094 if (RT_FAILURE(rc))
4095 return rc;
4096 printMsrFunctionExtendedIdxVal(uMsr + i, NULL, NULL, i / 2, fIgnMask, fGpMask, annotateValue(paMsrs[i].uValue));
4097 }
4098
4099 /* Advance. */
4100 *pidxLoop += cRegs - 1;
4101 return VINF_SUCCESS;
4102}
4103
4104
4105/**
4106 * Deals carefully with a LS_CFG register.
4107 *
4108 * @returns VBox status code.
4109 * @param uMsr The MSR number.
4110 * @param uValue The current value.
4111 */
4112static int reportMsr_AmdK7InstrCacheCfg(uint32_t uMsr, uint64_t uValue)
4113{
4114 /* Skip know bits here, as harm seems to come from messing with them. */
4115 uint64_t fSkipMask = RT_BIT_64(9) /* DIS_SPEC_TLB_RLD */;
4116 if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
4117 fSkipMask |= RT_BIT_64(14); /* DIS_IND */
4118 if (CPUMMICROARCH_IS_AMD_FAM_16H(g_enmMicroarch))
4119 fSkipMask |= RT_BIT_64(26); /* DIS_WIDEREAD_PWR_SAVE */
4120 if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
4121 {
4122 fSkipMask |= 0x1e; /* DisIcWayFilter */
4123 fSkipMask |= RT_BIT_64(39); /* DisLoopPredictor */
4124 fSkipMask |= RT_BIT_64(27); /* Unknown killer bit, possibly applicable to other microarchs. */
4125 fSkipMask |= RT_BIT_64(28); /* Unknown killer bit, possibly applicable to other microarchs. */
4126 }
4127 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
4128}
4129
4130
4131/**
4132 * Deals carefully with a CU_CFG register.
4133 *
4134 * @returns VBox status code.
4135 * @param uMsr The MSR number.
4136 * @param uValue The current value.
4137 */
4138static int reportMsr_AmdFam15hCombUnitCfg(uint32_t uMsr, uint64_t uValue)
4139{
4140 /* Skip know bits here, as harm seems to come from messing with them. */
4141 uint64_t fSkipMask = RT_BIT_64(23) /* L2WayLock */
4142 | RT_BIT_64(22) /* L2FirstLockWay */
4143 | RT_BIT_64(21) /* L2FirstLockWay */
4144 | RT_BIT_64(20) /* L2FirstLockWay */
4145 | RT_BIT_64(19) /* L2FirstLockWay */
4146 | RT_BIT_64(10) /* DcacheAggressivePriority */;
4147 fSkipMask |= RT_BIT_64(46) | RT_BIT_64(45); /* Killer field. Seen bit 46 set, 45 clear. Messing with either means reboot/BSOD. */
4148 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
4149}
4150
4151
4152/**
4153 * Deals carefully with a EX_CFG register.
4154 *
4155 * @returns VBox status code.
4156 * @param uMsr The MSR number.
4157 * @param uValue The current value.
4158 */
4159static int reportMsr_AmdFam15hExecUnitCfg(uint32_t uMsr, uint64_t uValue)
4160{
4161 /* Skip know bits here, as harm seems to come from messing with them. */
4162 uint64_t fSkipMask = RT_BIT_64(54) /* LateSbzResync */;
4163 fSkipMask |= RT_BIT_64(35); /* Undocumented killer bit. */
4164 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
4165}
4166
4167
4168
4169static int produceMsrReport(VBCPUREPMSR *paMsrs, uint32_t cMsrs)
4170{
4171 vbCpuRepDebug("produceMsrReport\n");
4172 RTThreadSleep(500);
4173
4174 for (uint32_t i = 0; i < cMsrs; i++)
4175 {
4176 uint32_t uMsr = paMsrs[i].uMsr;
4177 uint32_t fFlags = paMsrs[i].fFlags;
4178 uint64_t uValue = paMsrs[i].uValue;
4179 int rc;
4180#if 0
4181 //if (uMsr < 0x00000000)
4182 // continue;
4183 if (uMsr >= 0x00000277)
4184 {
4185 vbCpuRepDebug("produceMsrReport: uMsr=%#x (%s)...\n", uMsr, getMsrNameHandled(uMsr));
4186 RTThreadSleep(1000);
4187 }
4188#endif
4189 /*
4190 * Deal with write only regs first to avoid having to avoid them all the time.
4191 */
4192 if (fFlags & VBCPUREPMSR_F_WRITE_ONLY)
4193 {
4194 if (uMsr == 0x00000079)
4195 rc = printMsrWriteOnly(uMsr, NULL, NULL);
4196 else
4197 rc = reportMsr_Generic(uMsr, fFlags, uValue);
4198 }
4199 /*
4200 * VIA implement MSRs in a interesting way, so we have to select what we
4201 * want to handle there to avoid making the code below unreadable.
4202 */
4203 /** @todo r=klaus check if Shanghai CPUs really are behaving the same */
4204 else if (isMsrViaShanghaiDummy(uMsr, uValue, fFlags))
4205 rc = reportMsr_ViaShanghaiDummyRange(&paMsrs[i], cMsrs - i, &i);
4206 /*
4207 * This shall be sorted by uMsr as much as possible.
4208 */
4209 else if (uMsr == 0x00000000 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON) && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
4210 rc = printMsrAlias(uMsr, 0x00000402, NULL);
4211 else if (uMsr == 0x00000001 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON) && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
4212 rc = printMsrAlias(uMsr, 0x00000401, NULL); /** @todo not 101% correct on Fam15h and later, 0xc0010015[McstatusWrEn] effect differs. */
4213 else if (uMsr == 0x0000001b)
4214 rc = reportMsr_Ia32ApicBase(uMsr, uValue);
4215 else if (uMsr == 0x00000040 && g_enmMicroarch <= kCpumMicroarch_Intel_P6_M_Dothan)
4216 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromToN", &i);
4217 else if (uMsr == 0x00000040)
4218 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchToN", uMsr, false,
4219 true, getGenericSkipMask(uMsr), &i);
4220 else if (uMsr == 0x00000060 && g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah)
4221 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromN", uMsr, false,
4222 true, getGenericSkipMask(uMsr), &i);
4223 else if (uMsr == 0x000000c1)
4224 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i,
4225 g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? 8 : 4 /*cMax*/,
4226 NULL, &i);
4227 else if (uMsr == 0x00000186 && !g_fIntelNetBurst)
4228 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "Ia32PerfEvtSelN", &i);
4229 else if (uMsr == 0x000001a0)
4230 rc = reportMsr_Ia32MiscEnable(uMsr, uValue);
4231 else if (uMsr >= 0x000001a6 && uMsr <= 0x000001a7)
4232 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 2 /*cMax*/, "IntelI7MsrOffCoreResponseN", &i);
4233 else if (uMsr == 0x000001db && g_fIntelNetBurst)
4234 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 4 /*cMax*/, "IntelLastBranchFromToN", &i);
4235 else if (uMsr == 0x00000200)
4236 rc = reportMsr_Ia32MtrrPhysBaseMaskN(&paMsrs[i], cMsrs - i, &i);
4237 else if (uMsr >= 0x00000250 && uMsr <= 0x00000279)
4238 rc = reportMsr_Ia32MtrrFixedOrPat(uMsr);
4239 else if (uMsr >= 0x00000280 && uMsr <= 0x00000295)
4240 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 22 /*cMax*/, NULL, 0x00000280, true /*fEarlyEndOk*/, false, 0, &i);
4241 else if (uMsr == 0x000002ff)
4242 rc = reportMsr_Ia32MtrrDefType(uMsr);
4243 else if (uMsr >= 0x00000309 && uMsr <= 0x0000030b && !g_fIntelNetBurst)
4244 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3 /*cMax*/, NULL, 0x00000309, true /*fEarlyEndOk*/, false, 0, &i);
4245 else if ((uMsr == 0x000003f8 || uMsr == 0x000003fc || uMsr == 0x0000060a) && !g_fIntelNetBurst)
4246 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 4, NULL, uMsr - 3, true, false, 0, &i);
4247 else if ((uMsr == 0x000003f9 || uMsr == 0x000003fd || uMsr == 0x0000060b) && !g_fIntelNetBurst)
4248 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 6, true, false, 0, &i);
4249 else if ((uMsr == 0x000003fa || uMsr == 0x000003fe || uMsr == 0x0000060c) && !g_fIntelNetBurst)
4250 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 7, true, false, 0, &i);
4251 else if (uMsr >= 0x00000400 && uMsr <= 0x00000477)
4252 rc = reportMsr_Ia32McCtlStatusAddrMiscN(&paMsrs[i], cMsrs - i, &i);
4253 else if (uMsr == 0x000004c1)
4254 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8, NULL, &i);
4255 else if (uMsr == 0x00000680 || uMsr == 0x000006c0)
4256 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 16, NULL, uMsr, false, false,
4257 g_fIntelNetBurst
4258 ? UINT64_C(0xffffffffffffff00) /* kludge */
4259 : UINT64_C(0xffff800000000000), &i);
4260 else if (uMsr >= 0x00000800 && uMsr <= 0x000008ff)
4261 rc = reportMsr_GenX2Apic(&paMsrs[i], cMsrs - i, &i);
4262 else if (uMsr == 0x00002000 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4263 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 0, X86_CR0_PE | X86_CR0_PG, 0,
4264 annotateIfMissingBits(uValue, X86_CR0_PE | X86_CR0_PE | X86_CR0_ET));
4265 else if (uMsr == 0x00002002 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4266 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 2, 0, 0, annotateValue(uValue));
4267 else if (uMsr == 0x00002003 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4268 {
4269 uint64_t fCr3Mask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & (X86_CR3_PAE_PAGE_MASK | X86_CR3_AMD64_PAGE_MASK);
4270 if (!vbCpuRepSupportsPae())
4271 fCr3Mask &= X86_CR3_PAGE_MASK | X86_CR3_AMD64_PAGE_MASK;
4272 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 3, fCr3Mask, 0, annotateValue(uValue));
4273 }
4274 else if (uMsr == 0x00002004 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4275 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 4,
4276 X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE | X86_CR4_SMXE, 0,
4277 annotateValue(uValue));
4278 else if (uMsr == 0xc0000080)
4279 rc = reportMsr_Amd64Efer(uMsr, uValue);
4280 else if (uMsr >= 0xc0000408 && uMsr <= 0xc000040f)
4281 rc = reportMsr_AmdFam10hMc4MiscN(&paMsrs[i], cMsrs - i, &i);
4282 else if (uMsr == 0xc0010000 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4283 rc = reportMsr_AmdK8PerfCtlN(&paMsrs[i], cMsrs - i, &i);
4284 else if (uMsr == 0xc0010004 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4285 rc = reportMsr_AmdK8PerfCtrN(&paMsrs[i], cMsrs - i, &i);
4286 else if (uMsr == 0xc0010010 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4287 rc = reportMsr_AmdK8SysCfg(uMsr, uValue);
4288 else if (uMsr == 0xc0010015 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4289 rc = reportMsr_AmdK8HwCr(uMsr, uValue);
4290 else if ((uMsr == 0xc0010016 || uMsr == 0xc0010018) && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4291 rc = reportMsr_AmdK8IorrBaseN(uMsr, uValue);
4292 else if ((uMsr == 0xc0010017 || uMsr == 0xc0010019) && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4293 rc = reportMsr_AmdK8IorrMaskN(uMsr, uValue);
4294 else if ((uMsr == 0xc001001a || uMsr == 0xc001001d) && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4295 rc = reportMsr_AmdK8TopMemN(uMsr, uValue);
4296 else if (uMsr == 0xc0010030 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4297 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 6, "AmdK8CpuNameN", &i);
4298 else if (uMsr >= 0xc0010044 && uMsr <= 0xc001004a && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4299 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 7, "AmdK8McCtlMaskN", 0xc0010044, true /*fEarlyEndOk*/, false, 0, &i);
4300 else if (uMsr == 0xc0010050 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4301 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 4, "AmdK8SmiOnIoTrapN", &i);
4302 else if (uMsr == 0xc0010064 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4303 rc = reportMsr_AmdFam10hPStateN(&paMsrs[i], cMsrs - i, &i);
4304 else if (uMsr == 0xc0010070 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4305 rc = reportMsr_AmdFam10hCofVidControl(uMsr, uValue);
4306 else if ((uMsr == 0xc0010118 || uMsr == 0xc0010119) && getMsrFnName(uMsr, NULL) && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4307 rc = printMsrFunction(uMsr, NULL, NULL, annotateValue(uValue)); /* RAZ, write key. */
4308 else if (uMsr == 0xc0010200 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4309 rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 12, &i);
4310 else if (uMsr == 0xc0010230 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4311 rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 8, &i);
4312 else if (uMsr == 0xc0010240 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4313 rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 8, &i);
4314 else if (uMsr == 0xc0011019 && g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4315 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3, "AmdK7DrXAddrMaskN", 0xc0011019 - 1,
4316 false /*fEarlyEndOk*/, false /*fNoIgnMask*/, 0, &i);
4317 else if (uMsr == 0xc0011021 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4318 rc = reportMsr_AmdK7InstrCacheCfg(uMsr, uValue);
4319 else if (uMsr == 0xc0011023 && CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
4320 rc = reportMsr_AmdFam15hCombUnitCfg(uMsr, uValue);
4321 else if (uMsr == 0xc0011027 && (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON))
4322 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 1, "AmdK7DrXAddrMaskN", 0xc0011027,
4323 false /*fEarlyEndOk*/, false /*fNoIgnMask*/, 0, &i);
4324 else if (uMsr == 0xc001102c && CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
4325 rc = reportMsr_AmdFam15hExecUnitCfg(uMsr, uValue);
4326 /* generic handling. */
4327 else
4328 rc = reportMsr_Generic(uMsr, fFlags, uValue);
4329
4330 if (RT_FAILURE(rc))
4331 return rc;
4332
4333 /*
4334 * A little ugly snooping.
4335 */
4336 if (uMsr == 0x000000cd && !(fFlags & VBCPUREPMSR_F_WRITE_ONLY))
4337 g_uMsrIntelP6FsbFrequency = uValue;
4338 }
4339
4340 return VINF_SUCCESS;
4341}
4342
4343
4344/**
4345 * Custom MSR hacking & probing.
4346 *
4347 * Called when the '-d' option is given.
4348 *
4349 * @returns VBox status code.
4350 */
4351static int hackingMsrs(void)
4352{
4353#if 0
4354 vbCpuRepDebug("\nhackingMsrs:\n"); RTStrmFlush(g_pDebugOut); RTThreadSleep(2000);
4355
4356 uint32_t uMsr = 0xc0000081;
4357 vbCpuRepDebug("%#x: msrProberModifyNoChange -> %RTbool\n", uMsr, msrProberModifyNoChange(uMsr));
4358 RTThreadSleep(3000);
4359
4360 vbCpuRepDebug("%#x: msrProberModifyBit 30 -> %d\n", uMsr, msrProberModifyBit(uMsr, 30));
4361 RTThreadSleep(3000);
4362
4363 vbCpuRepDebug("%#x: msrProberModifyZero -> %RTbool\n", uMsr, msrProberModifyZero(uMsr));
4364 RTThreadSleep(3000);
4365
4366 for (uint32_t i = 0; i < 63; i++)
4367 {
4368 vbCpuRepDebug("%#x: bit=%02u -> %d\n", msrProberModifyBit(uMsr, i));
4369 RTThreadSleep(500);
4370 }
4371#else
4372
4373 uint32_t uMsr = 0xc0010010;
4374 uint64_t uValue = 0;
4375 msrProberRead(uMsr, &uValue);
4376 reportMsr_AmdK8SysCfg(uMsr, uValue);
4377#endif
4378 return VINF_SUCCESS;
4379}
4380
4381
4382static int probeMsrs(bool fHacking, const char *pszNameC, const char *pszCpuDesc,
4383 char *pszMsrMask, size_t cbMsrMask)
4384{
4385 /* Initialize the mask. */
4386 if (pszMsrMask && cbMsrMask)
4387 RTStrCopy(pszMsrMask, cbMsrMask, "UINT32_MAX /** @todo */");
4388
4389 /*
4390 * Are MSRs supported by the CPU?
4391 */
4392 if ( !ASMIsValidStdRange(ASMCpuId_EAX(0))
4393 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_MSR) )
4394 {
4395 vbCpuRepDebug("Skipping MSR probing, CPUID indicates there isn't any MSR support.\n");
4396 return VINF_SUCCESS;
4397 }
4398 if (g_fNoMsrs)
4399 {
4400 vbCpuRepDebug("Skipping MSR probing (--no-msr).\n");
4401 return VINF_SUCCESS;
4402 }
4403
4404 /*
4405 * First try the the support library (also checks if we can really read MSRs).
4406 */
4407 int rc = VbCpuRepMsrProberInitSupDrv(&g_MsrAcc);
4408 if (RT_FAILURE(rc))
4409 {
4410#ifdef VBCR_HAVE_PLATFORM_MSR_PROBER
4411 /* Next try a platform-specific interface. */
4412 rc = VbCpuRepMsrProberInitPlatform(&g_MsrAcc);
4413#endif
4414 if (RT_FAILURE(rc))
4415 {
4416 vbCpuRepDebug("warning: Unable to initialize any MSR access interface (%Rrc), skipping MSR detection.\n", rc);
4417 return VINF_SUCCESS;
4418 }
4419 }
4420
4421 uint64_t uValue;
4422 bool fGp;
4423 rc = g_MsrAcc.pfnMsrProberRead(MSR_IA32_TSC, NIL_RTCPUID, &uValue, &fGp);
4424 if (RT_FAILURE(rc))
4425 {
4426 vbCpuRepDebug("warning: MSR probing not supported by the support driver (%Rrc), skipping MSR detection.\n", rc);
4427 return VINF_SUCCESS;
4428 }
4429 vbCpuRepDebug("MSR_IA32_TSC: %#llx fGp=%RTbool\n", uValue, fGp);
4430 rc = g_MsrAcc.pfnMsrProberRead(0xdeadface, NIL_RTCPUID, &uValue, &fGp);
4431 vbCpuRepDebug("0xdeadface: %#llx fGp=%RTbool rc=%Rrc\n", uValue, fGp, rc);
4432
4433 /*
4434 * Initialize globals we use.
4435 */
4436 uint32_t uEax, uEbx, uEcx, uEdx;
4437 ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4438 if (!ASMIsValidStdRange(uEax))
4439 return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax);
4440 g_enmVendor = CPUMR3CpuIdDetectVendorEx(uEax, uEbx, uEcx, uEdx);
4441
4442 ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4443 g_enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(g_enmVendor,
4444 ASMGetCpuFamily(uEax),
4445 ASMGetCpuModel(uEax, g_enmVendor == CPUMCPUVENDOR_INTEL),
4446 ASMGetCpuStepping(uEax));
4447 g_fIntelNetBurst = CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch);
4448
4449 /*
4450 * Do the probing.
4451 */
4452 if (fHacking)
4453 rc = hackingMsrs();
4454 else
4455 {
4456 /* Determine the MSR mask. */
4457 uint32_t fMsrMask = determineMsrAndMask();
4458 if (fMsrMask == UINT32_MAX)
4459 RTStrCopy(pszMsrMask, cbMsrMask, "UINT32_MAX");
4460 else
4461 RTStrPrintf(pszMsrMask, cbMsrMask, "UINT32_C(%#x)", fMsrMask);
4462
4463 /* Detect MSR. */
4464 VBCPUREPMSR *paMsrs;
4465 uint32_t cMsrs;
4466 rc = findMsrs(&paMsrs, &cMsrs, fMsrMask);
4467 if (RT_FAILURE(rc))
4468 return rc;
4469
4470 /* Probe the MSRs and spit out the database table. */
4471 vbCpuRepPrintf("\n"
4472 "#ifndef CPUM_DB_STANDALONE\n"
4473 "/**\n"
4474 " * MSR ranges for %s.\n"
4475 " */\n"
4476 "static CPUMMSRRANGE const g_aMsrRanges_%s[] =\n{\n",
4477 pszCpuDesc,
4478 pszNameC);
4479 rc = produceMsrReport(paMsrs, cMsrs);
4480 vbCpuRepPrintf("};\n"
4481 "#endif /* !CPUM_DB_STANDALONE */\n"
4482 "\n"
4483 );
4484
4485 RTMemFree(paMsrs);
4486 paMsrs = NULL;
4487 }
4488 if (g_MsrAcc.pfnTerm)
4489 g_MsrAcc.pfnTerm();
4490 RT_ZERO(g_MsrAcc);
4491 return rc;
4492}
4493
4494
4495static int produceCpuIdArray(const char *pszNameC, const char *pszCpuDesc)
4496{
4497 /*
4498 * Collect the data.
4499 */
4500 PCPUMCPUIDLEAF paLeaves;
4501 uint32_t cLeaves;
4502 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
4503 if (RT_FAILURE(rc))
4504 return RTMsgErrorRc(rc, "CPUMR3CollectCpuIdInfo failed: %Rrc\n", rc);
4505
4506 /*
4507 * Dump the array.
4508 */
4509 vbCpuRepPrintf("\n"
4510 "#ifndef CPUM_DB_STANDALONE\n"
4511 "/**\n"
4512 " * CPUID leaves for %s.\n"
4513 " */\n"
4514 "static CPUMCPUIDLEAF const g_aCpuIdLeaves_%s[] = \n{\n",
4515 pszCpuDesc,
4516 pszNameC);
4517 for (uint32_t i = 0; i < cLeaves; i++)
4518 {
4519 vbCpuRepPrintf(" { %#010x, %#010x, ", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf);
4520 if (paLeaves[i].fSubLeafMask == UINT32_MAX)
4521 vbCpuRepPrintf("UINT32_MAX, ");
4522 else
4523 vbCpuRepPrintf("%#010x, ", paLeaves[i].fSubLeafMask);
4524 vbCpuRepPrintf("%#010x, %#010x, %#010x, %#010x, ",
4525 paLeaves[i].uEax, paLeaves[i].uEbx, paLeaves[i].uEcx, paLeaves[i].uEdx);
4526 if (paLeaves[i].fFlags == 0)
4527 vbCpuRepPrintf("0 },\n");
4528 else
4529 {
4530 vbCpuRepPrintf("0");
4531 uint32_t fFlags = paLeaves[i].fFlags;
4532 if (paLeaves[i].fFlags & CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)
4533 {
4534 vbCpuRepPrintf(" | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES");
4535 fFlags &= ~CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
4536 }
4537 if (paLeaves[i].fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
4538 {
4539 vbCpuRepPrintf(" | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID");
4540 fFlags &= ~CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
4541 }
4542 if (paLeaves[i].fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC)
4543 {
4544 vbCpuRepPrintf(" | CPUMCPUIDLEAF_F_CONTAINS_APIC");
4545 fFlags &= ~CPUMCPUIDLEAF_F_CONTAINS_APIC;
4546 }
4547 if (fFlags)
4548 {
4549 RTMemFree(paLeaves);
4550 return RTMsgErrorRc(rc, "Unknown CPUID flags %#x\n", fFlags);
4551 }
4552 vbCpuRepPrintf(" },\n");
4553 }
4554 }
4555 vbCpuRepPrintf("};\n"
4556 "#endif /* !CPUM_DB_STANDALONE */\n"
4557 "\n");
4558 RTMemFree(paLeaves);
4559 return VINF_SUCCESS;
4560}
4561
4562
4563static const char *cpuVendorToString(CPUMCPUVENDOR enmCpuVendor)
4564{
4565 switch (enmCpuVendor)
4566 {
4567 case CPUMCPUVENDOR_INTEL: return "Intel";
4568 case CPUMCPUVENDOR_AMD: return "AMD";
4569 case CPUMCPUVENDOR_VIA: return "VIA";
4570 case CPUMCPUVENDOR_CYRIX: return "Cyrix";
4571 case CPUMCPUVENDOR_SHANGHAI: return "Shanghai";
4572 case CPUMCPUVENDOR_HYGON: return "Hygon";
4573 case CPUMCPUVENDOR_INVALID:
4574 case CPUMCPUVENDOR_UNKNOWN:
4575 case CPUMCPUVENDOR_32BIT_HACK:
4576 break;
4577 }
4578 return "invalid-cpu-vendor";
4579}
4580
4581
4582/**
4583 * Takes a shot a the bus frequency name (last part).
4584 *
4585 * @returns Name suffix.
4586 */
4587static const char *vbCpuRepGuessScalableBusFrequencyName(void)
4588{
4589 if (CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch))
4590 return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge ? "100MHZ" : "133MHZ";
4591
4592 if (g_uMsrIntelP6FsbFrequency != UINT64_MAX)
4593 switch (g_uMsrIntelP6FsbFrequency & 0x7)
4594 {
4595 case 5: return "100MHZ";
4596 case 1: return "133MHZ";
4597 case 3: return "167MHZ";
4598 case 2: return "200MHZ";
4599 case 0: return "267MHZ";
4600 case 4: return "333MHZ";
4601 case 6: return "400MHZ";
4602 }
4603
4604 return "UNKNOWN";
4605}
4606
4607
4608static int produceCpuReport(void)
4609{
4610 /*
4611 * Figure the cpu vendor.
4612 */
4613 if (!ASMHasCpuId())
4614 return RTMsgErrorRc(VERR_NOT_SUPPORTED, "No CPUID support.\n");
4615 uint32_t uEax, uEbx, uEcx, uEdx;
4616 ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4617 if (!ASMIsValidStdRange(uEax))
4618 return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax);
4619
4620 CPUMCPUVENDOR enmVendor = CPUMR3CpuIdDetectVendorEx(uEax, uEbx, uEcx, uEdx);
4621 if (enmVendor == CPUMCPUVENDOR_UNKNOWN)
4622 return RTMsgErrorRc(VERR_NOT_IMPLEMENTED, "Unknown CPU vendor: %.4s%.4s%.4s\n", &uEbx, &uEdx, &uEcx);
4623 vbCpuRepDebug("CPU Vendor: %s - %.4s%.4s%.4s\n", CPUMR3CpuVendorName(enmVendor), &uEbx, &uEdx, &uEcx);
4624
4625 /*
4626 * Determine the micro arch.
4627 */
4628 ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4629 CPUMMICROARCH enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor,
4630 ASMGetCpuFamily(uEax),
4631 ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),
4632 ASMGetCpuStepping(uEax));
4633
4634 /*
4635 * Generate a name.
4636 */
4637 char szName[16*3+1];
4638 char szNameC[16*3+1];
4639 char szNameRaw[16*3+1];
4640 char *pszName = szName;
4641 char *pszCpuDesc = (char *)"";
4642
4643 ASMCpuIdExSlow(0x80000000, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4644 if (ASMIsValidExtRange(uEax) && uEax >= UINT32_C(0x80000004))
4645 {
4646 /* Get the raw name and strip leading spaces. */
4647 ASMCpuIdExSlow(0x80000002, 0, 0, 0, &szNameRaw[0 + 0], &szNameRaw[4 + 0], &szNameRaw[8 + 0], &szNameRaw[12 + 0]);
4648 ASMCpuIdExSlow(0x80000003, 0, 0, 0, &szNameRaw[0 + 16], &szNameRaw[4 + 16], &szNameRaw[8 + 16], &szNameRaw[12 + 16]);
4649 ASMCpuIdExSlow(0x80000004, 0, 0, 0, &szNameRaw[0 + 32], &szNameRaw[4 + 32], &szNameRaw[8 + 32], &szNameRaw[12 + 32]);
4650 szNameRaw[48] = '\0';
4651 pszCpuDesc = RTStrStrip(szNameRaw);
4652 vbCpuRepDebug("Name2: %s\n", pszCpuDesc);
4653
4654 /* Reduce the name. */
4655 pszName = strcpy(szName, pszCpuDesc);
4656
4657 static const char * const s_apszSuffixes[] =
4658 {
4659 "CPU @",
4660 };
4661 for (uint32_t i = 0; i < RT_ELEMENTS(s_apszSuffixes); i++)
4662 {
4663 char *pszHit = strstr(pszName, s_apszSuffixes[i]);
4664 if (pszHit)
4665 RT_BZERO(pszHit, strlen(pszHit));
4666 }
4667
4668 static const char * const s_apszWords[] =
4669 {
4670 "(TM)", "(tm)", "(R)", "(r)", "Processor", "CPU", "@",
4671 };
4672 for (uint32_t i = 0; i < RT_ELEMENTS(s_apszWords); i++)
4673 {
4674 const char *pszWord = s_apszWords[i];
4675 size_t cchWord = strlen(pszWord);
4676 char *pszHit;
4677 while ((pszHit = strstr(pszName, pszWord)) != NULL)
4678 memset(pszHit, ' ', cchWord);
4679 }
4680
4681 RTStrStripR(pszName);
4682 for (char *psz = pszName; *psz; psz++)
4683 if (RT_C_IS_BLANK(*psz))
4684 {
4685 size_t cchBlanks = 1;
4686 while (RT_C_IS_BLANK(psz[cchBlanks]))
4687 cchBlanks++;
4688 *psz = ' ';
4689 if (cchBlanks > 1)
4690 memmove(psz + 1, psz + cchBlanks, strlen(psz + cchBlanks) + 1);
4691 }
4692 pszName = RTStrStripL(pszName);
4693 vbCpuRepDebug("Name: %s\n", pszName);
4694
4695 /* Make it C/C++ acceptable. */
4696 strcpy(szNameC, pszName);
4697 unsigned offDst = 0;
4698 for (unsigned offSrc = 0; ; offSrc++)
4699 {
4700 char ch = szNameC[offSrc];
4701 if (!RT_C_IS_ALNUM(ch) && ch != '_' && ch != '\0')
4702 ch = '_';
4703 if (ch == '_' && offDst > 0 && szNameC[offDst - 1] == '_')
4704 offDst--;
4705 szNameC[offDst++] = ch;
4706 if (!ch)
4707 break;
4708 }
4709 while (offDst > 1 && szNameC[offDst - 1] == '_')
4710 szNameC[--offDst] = '\0';
4711
4712 vbCpuRepDebug("NameC: %s\n", szNameC);
4713 }
4714 else
4715 {
4716 ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4717 RTStrPrintf(szNameC, sizeof(szNameC), "%s_%u_%u_%u", cpuVendorToString(enmVendor), ASMGetCpuFamily(uEax),
4718 ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL), ASMGetCpuStepping(uEax));
4719 pszCpuDesc = pszName = szNameC;
4720 vbCpuRepDebug("Name/NameC: %s\n", szNameC);
4721 }
4722
4723 /*
4724 * Print a file header, if we're not outputting to stdout (assumption being
4725 * that stdout is used while hacking the reporter and too much output is
4726 * unwanted).
4727 */
4728 if (g_pReportOut)
4729 {
4730 RTTIMESPEC Now;
4731 char szNow[64];
4732 RTTimeSpecToString(RTTimeNow(&Now), szNow, sizeof(szNow));
4733 char *pchDot = strchr(szNow, '.');
4734 if (pchDot)
4735 strcpy(pchDot, "Z");
4736
4737 vbCpuRepPrintf("/* $" "Id" "$ */\n"
4738 "/** @file\n"
4739 " * CPU database entry \"%s\".\n"
4740 " * Generated at %s by VBoxCpuReport v%sr%s on %s.%s.\n"
4741 " */\n"
4742 "\n"
4743 "/*\n"
4744 " * Copyright (C) 2013-2020 Oracle Corporation\n"
4745 " *\n"
4746 " * This file is part of VirtualBox Open Source Edition (OSE), as\n"
4747 " * available from http://www.virtualbox.org. This file is free software;\n"
4748 " * you can redistribute it and/or modify it under the terms of the GNU\n"
4749 " * General Public License (GPL) as published by the Free Software\n"
4750 " * Foundation, in version 2 as it comes in the \"COPYING\" file of the\n"
4751 " * VirtualBox OSE distribution. VirtualBox OSE is distributed in the\n"
4752 " * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.\n"
4753 " */\n"
4754 "\n"
4755 "#ifndef VBOX_CPUDB_%s_h\n"
4756 "#define VBOX_CPUDB_%s_h\n"
4757 "#ifndef RT_WITHOUT_PRAGMA_ONCE\n"
4758 "# pragma once\n"
4759 "#endif\n"
4760 "\n",
4761 pszName,
4762 szNow, RTBldCfgVersion(), RTBldCfgRevisionStr(), RTBldCfgTarget(), RTBldCfgTargetArch(),
4763 szNameC, szNameC);
4764 }
4765
4766 /*
4767 * Extract CPUID based data.
4768 */
4769 int rc = produceCpuIdArray(szNameC, pszCpuDesc);
4770 if (RT_FAILURE(rc))
4771 return rc;
4772
4773 CPUMUNKNOWNCPUID enmUnknownMethod;
4774 CPUMCPUID DefUnknown;
4775 rc = CPUMR3CpuIdDetectUnknownLeafMethod(&enmUnknownMethod, &DefUnknown);
4776 if (RT_FAILURE(rc))
4777 return RTMsgErrorRc(rc, "CPUMR3DetectCpuIdUnknownMethod failed: %Rrc\n", rc);
4778 vbCpuRepDebug("enmUnknownMethod=%s\n", CPUMR3CpuIdUnknownLeafMethodName(enmUnknownMethod));
4779
4780 /*
4781 * Do the MSRs, if we can.
4782 */
4783 char szMsrMask[64];
4784 probeMsrs(false /*fHacking*/, szNameC, pszCpuDesc, szMsrMask, sizeof(szMsrMask));
4785
4786 /*
4787 * Emit the CPUMDBENTRY record.
4788 */
4789 ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4790 vbCpuRepPrintf("\n"
4791 "/**\n"
4792 " * Database entry for %s.\n"
4793 " */\n"
4794 "static CPUMDBENTRY const g_Entry_%s = \n"
4795 "{\n"
4796 " /*.pszName = */ \"%s\",\n"
4797 " /*.pszFullName = */ \"%s\",\n"
4798 " /*.enmVendor = */ CPUMCPUVENDOR_%s,\n"
4799 " /*.uFamily = */ %u,\n"
4800 " /*.uModel = */ %u,\n"
4801 " /*.uStepping = */ %u,\n"
4802 " /*.enmMicroarch = */ kCpumMicroarch_%s,\n"
4803 " /*.uScalableBusFreq = */ CPUM_SBUSFREQ_%s,\n"
4804 " /*.fFlags = */ 0,\n"
4805 " /*.cMaxPhysAddrWidth= */ %u,\n"
4806 " /*.fMxCsrMask = */ %#010x,\n"
4807 " /*.paCpuIdLeaves = */ NULL_ALONE(g_aCpuIdLeaves_%s),\n"
4808 " /*.cCpuIdLeaves = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_%s)),\n"
4809 " /*.enmUnknownCpuId = */ CPUMUNKNOWNCPUID_%s,\n"
4810 " /*.DefUnknownCpuId = */ { %#010x, %#010x, %#010x, %#010x },\n"
4811 " /*.fMsrMask = */ %s,\n"
4812 " /*.cMsrRanges = */ ZERO_ALONE(RT_ELEMENTS(g_aMsrRanges_%s)),\n"
4813 " /*.paMsrRanges = */ NULL_ALONE(g_aMsrRanges_%s),\n"
4814 "};\n"
4815 "\n"
4816 "#endif /* !VBOX_CPUDB_%s_h */\n"
4817 "\n",
4818 pszCpuDesc,
4819 szNameC,
4820 pszName,
4821 pszCpuDesc,
4822 CPUMR3CpuVendorName(enmVendor),
4823 ASMGetCpuFamily(uEax),
4824 ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),
4825 ASMGetCpuStepping(uEax),
4826 CPUMR3MicroarchName(enmMicroarch),
4827 vbCpuRepGuessScalableBusFrequencyName(),
4828 vbCpuRepGetPhysAddrWidth(),
4829 CPUMR3DeterminHostMxCsrMask(),
4830 szNameC,
4831 szNameC,
4832 CPUMR3CpuIdUnknownLeafMethodName(enmUnknownMethod),
4833 DefUnknown.uEax,
4834 DefUnknown.uEbx,
4835 DefUnknown.uEcx,
4836 DefUnknown.uEdx,
4837 szMsrMask,
4838 szNameC,
4839 szNameC,
4840 szNameC
4841 );
4842
4843 return VINF_SUCCESS;
4844}
4845
4846
4847int main(int argc, char **argv)
4848{
4849 int rc = RTR3InitExe(argc, &argv, 0 /*fFlags*/);
4850 if (RT_FAILURE(rc))
4851 return RTMsgInitFailure(rc);
4852
4853 /*
4854 * Argument parsing?
4855 */
4856 static const RTGETOPTDEF s_aOptions[] =
4857 {
4858 { "--msrs-only", 'm', RTGETOPT_REQ_NOTHING },
4859 { "--msrs-dev", 'd', RTGETOPT_REQ_NOTHING },
4860 { "--no-msrs", 'n', RTGETOPT_REQ_NOTHING },
4861 { "--output", 'o', RTGETOPT_REQ_STRING },
4862 { "--log", 'l', RTGETOPT_REQ_STRING },
4863 };
4864 RTGETOPTSTATE State;
4865 RTGetOptInit(&State, argc, argv, &s_aOptions[0], RT_ELEMENTS(s_aOptions), 1, RTGETOPTINIT_FLAGS_OPTS_FIRST);
4866
4867 enum
4868 {
4869 kCpuReportOp_Normal,
4870 kCpuReportOp_MsrsOnly,
4871 kCpuReportOp_MsrsHacking
4872 } enmOp = kCpuReportOp_Normal;
4873 g_pReportOut = NULL;
4874 g_pDebugOut = NULL;
4875 const char *pszOutput = NULL;
4876 const char *pszDebugOut = NULL;
4877
4878 int iOpt;
4879 RTGETOPTUNION ValueUnion;
4880 while ((iOpt = RTGetOpt(&State, &ValueUnion)) != 0)
4881 {
4882 switch (iOpt)
4883 {
4884 case 'm':
4885 enmOp = kCpuReportOp_MsrsOnly;
4886 break;
4887
4888 case 'd':
4889 enmOp = kCpuReportOp_MsrsHacking;
4890 break;
4891
4892 case 'n':
4893 g_fNoMsrs = true;
4894 break;
4895
4896 case 'o':
4897 pszOutput = ValueUnion.psz;
4898 break;
4899
4900 case 'l':
4901 pszDebugOut = ValueUnion.psz;
4902 break;
4903
4904 case 'h':
4905 RTPrintf("Usage: VBoxCpuReport [-m|--msrs-only] [-d|--msrs-dev] [-n|--no-msrs] [-h|--help] [-V|--version] [-o filename.h] [-l debug.log]\n");
4906 RTPrintf("Internal tool for gathering information to the VMM CPU database.\n");
4907 return RTEXITCODE_SUCCESS;
4908 case 'V':
4909 RTPrintf("%sr%s\n", RTBldCfgVersion(), RTBldCfgRevisionStr());
4910 return RTEXITCODE_SUCCESS;
4911 default:
4912 return RTGetOptPrintError(iOpt, &ValueUnion);
4913 }
4914 }
4915
4916 /*
4917 * Open the alternative debug log stream.
4918 */
4919 if (pszDebugOut)
4920 {
4921 if (RTFileExists(pszDebugOut) && !RTSymlinkExists(pszDebugOut))
4922 {
4923 char szOld[RTPATH_MAX];
4924 rc = RTStrCopy(szOld, sizeof(szOld), pszDebugOut);
4925 if (RT_SUCCESS(rc))
4926 rc = RTStrCat(szOld, sizeof(szOld), ".old");
4927 if (RT_SUCCESS(rc))
4928 RTFileRename(pszDebugOut, szOld, RTFILEMOVE_FLAGS_REPLACE);
4929 }
4930 rc = RTStrmOpen(pszDebugOut, "w", &g_pDebugOut);
4931 if (RT_FAILURE(rc))
4932 {
4933 RTMsgError("Error opening '%s': %Rrc", pszDebugOut, rc);
4934 g_pDebugOut = NULL;
4935 }
4936 }
4937
4938 /*
4939 * Do the requested job.
4940 */
4941 rc = VERR_INTERNAL_ERROR;
4942 switch (enmOp)
4943 {
4944 case kCpuReportOp_Normal:
4945 /* switch output file. */
4946 if (pszOutput)
4947 {
4948 if (RTFileExists(pszOutput) && !RTSymlinkExists(pszOutput))
4949 {
4950 char szOld[RTPATH_MAX];
4951 rc = RTStrCopy(szOld, sizeof(szOld), pszOutput);
4952 if (RT_SUCCESS(rc))
4953 rc = RTStrCat(szOld, sizeof(szOld), ".old");
4954 if (RT_SUCCESS(rc))
4955 RTFileRename(pszOutput, szOld, RTFILEMOVE_FLAGS_REPLACE);
4956 }
4957 rc = RTStrmOpen(pszOutput, "w", &g_pReportOut);
4958 if (RT_FAILURE(rc))
4959 {
4960 RTMsgError("Error opening '%s': %Rrc", pszOutput, rc);
4961 break;
4962 }
4963 }
4964 rc = produceCpuReport();
4965 break;
4966 case kCpuReportOp_MsrsOnly:
4967 case kCpuReportOp_MsrsHacking:
4968 rc = probeMsrs(enmOp == kCpuReportOp_MsrsHacking, NULL, NULL, NULL, 0);
4969 break;
4970 }
4971
4972 /*
4973 * Close the output files.
4974 */
4975 if (g_pReportOut)
4976 {
4977 RTStrmClose(g_pReportOut);
4978 g_pReportOut = NULL;
4979 }
4980
4981 if (g_pDebugOut)
4982 {
4983 RTStrmClose(g_pDebugOut);
4984 g_pDebugOut = NULL;
4985 }
4986
4987 return RT_SUCCESS(rc) ? RTEXITCODE_SUCCESS : RTEXITCODE_FAILURE;
4988}
4989
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