VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 96860

Last change on this file since 96860 was 96759, checked in by vboxsync, 21 months ago

VMM/PGM: Nested VMX: bugref:10092 SLAT type direct.
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1/* $Id: PGMInternal.h 96759 2022-09-16 04:01:12Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
29#define VMM_INCLUDED_SRC_include_PGMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/cdefs.h>
35#include <VBox/types.h>
36#include <VBox/err.h>
37#include <VBox/dbg.h>
38#include <VBox/vmm/stam.h>
39#include <VBox/param.h>
40#include <VBox/vmm/vmm.h>
41#include <VBox/vmm/mm.h>
42#include <VBox/vmm/pdmcritsect.h>
43#include <VBox/vmm/pdmapi.h>
44#include <VBox/dis.h>
45#include <VBox/vmm/dbgf.h>
46#include <VBox/log.h>
47#include <VBox/vmm/gmm.h>
48#include <VBox/vmm/hm.h>
49#include <iprt/asm.h>
50#include <iprt/assert.h>
51#include <iprt/avl.h>
52#include <iprt/critsect.h>
53#include <iprt/list-off32.h>
54#include <iprt/sha.h>
55#include <iprt/cpp/hardavlrange.h>
56
57
58
59/** @defgroup grp_pgm_int Internals
60 * @ingroup grp_pgm
61 * @internal
62 * @{
63 */
64
65
66/** @name PGM Compile Time Config
67 * @{
68 */
69
70/**
71 * Check and skip global PDEs for non-global flushes
72 */
73#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
74
75/**
76 * Optimization for PAE page tables that are modified often
77 */
78//#if 0 /* disabled again while debugging */
79#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
80//#endif
81
82/**
83 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
84 */
85#define PGM_WITH_LARGE_PAGES
86
87/**
88 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
89 * VMX_EXIT_EPT_MISCONFIG.
90 */
91#define PGM_WITH_MMIO_OPTIMIZATIONS
92
93/**
94 * Sync N pages instead of a whole page table
95 */
96#define PGM_SYNC_N_PAGES
97
98/**
99 * Number of pages to sync during a page fault
100 *
101 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
102 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
103 *
104 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
105 * world switch overhead, so let's sync more.
106 */
107#ifdef IN_RING0
108/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
109 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
110 * but ~5% fewer faults.
111 */
112# define PGM_SYNC_NR_PAGES 32
113#else
114# define PGM_SYNC_NR_PAGES 8
115#endif
116
117/**
118 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
119 */
120#define PGM_MAX_PHYSCACHE_ENTRIES 64
121#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
122
123
124/** @def PGMPOOL_CFG_MAX_GROW
125 * The maximum number of pages to add to the pool in one go.
126 */
127#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
128
129/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
130 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
131 */
132#ifdef VBOX_STRICT
133# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
134#endif
135
136/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
137 * Enables the experimental lazy page allocation code. */
138#ifdef DOXYGEN_RUNNING
139# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
140#endif
141
142/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
143 * Enables real write monitoring of pages, i.e. mapping them read-only and
144 * only making them writable when getting a write access \#PF. */
145#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
146
147/** @def VBOX_WITH_PGM_NEM_MODE
148 * Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
149 * details. */
150#ifdef DOXYGEN_RUNNING
151# define VBOX_WITH_PGM_NEM_MODE
152#endif
153
154/** @} */
155
156
157/** @name PDPT and PML4 flags.
158 * These are placed in the three bits available for system programs in
159 * the PDPT and PML4 entries.
160 * @{ */
161/** The entry is a permanent one and it's must always be present.
162 * Never free such an entry. */
163#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
164/** PGM specific bits in PML4 entries. */
165#define PGM_PML4_FLAGS 0
166/** PGM specific bits in PDPT entries. */
167#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
168/** @} */
169
170/** @name Page directory flags.
171 * These are placed in the three bits available for system programs in
172 * the page directory entries.
173 * @{ */
174/** Indicates the original entry was a big page.
175 * @remarks This is currently only used for statistics and can be recycled. */
176#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
177/** Made read-only to facilitate dirty bit tracking. */
178#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
179/** @} */
180
181/** @name Page flags.
182 * These are placed in the three bits available for system programs in
183 * the page entries.
184 * @{ */
185/** Made read-only to facilitate dirty bit tracking. */
186#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
187
188#ifndef PGM_PTFLAGS_CSAM_VALIDATED
189/** Scanned and approved by CSAM (tm).
190 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
191 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
192#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
193#endif
194
195/** @} */
196
197/** @name Defines used to indicate the shadow and guest paging in the templates.
198 * @{ */
199#define PGM_TYPE_REAL 1
200#define PGM_TYPE_PROT 2
201#define PGM_TYPE_32BIT 3
202#define PGM_TYPE_PAE 4
203#define PGM_TYPE_AMD64 5
204#define PGM_TYPE_NESTED_32BIT 6
205#define PGM_TYPE_NESTED_PAE 7
206#define PGM_TYPE_NESTED_AMD64 8
207#define PGM_TYPE_EPT 9
208#define PGM_TYPE_NONE 10 /**< Dummy shadow paging mode for NEM. */
209#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
210#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /**< The first type used by shadow paging. */
211/** @} */
212
213/** @name Defines used to indicate the second-level
214 * address translation (SLAT) modes in the templates.
215 * @{ */
216#define PGM_SLAT_TYPE_DIRECT (PGM_TYPE_END + 1)
217#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 2)
218#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 3)
219#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 4)
220#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 5)
221/** @} */
222
223/** Macro for checking if the guest is using paging.
224 * @param uGstType PGM_TYPE_*
225 * @param uShwType PGM_TYPE_*
226 * @remark ASSUMES certain order of the PGM_TYPE_* values.
227 */
228#define PGM_WITH_PAGING(uGstType, uShwType) \
229 ( (uGstType) >= PGM_TYPE_32BIT \
230 && (uShwType) < PGM_TYPE_NESTED_32BIT)
231
232/** Macro for checking if the guest supports the NX bit.
233 * @param uGstType PGM_TYPE_*
234 * @param uShwType PGM_TYPE_*
235 * @remark ASSUMES certain order of the PGM_TYPE_* values.
236 */
237#define PGM_WITH_NX(uGstType, uShwType) \
238 ( (uGstType) >= PGM_TYPE_PAE \
239 && (uShwType) < PGM_TYPE_NESTED_32BIT)
240
241/** Macro for checking for nested.
242 * @param uType PGM_TYPE_*
243 */
244#define PGM_TYPE_IS_NESTED(uType) \
245 ( (uType) == PGM_TYPE_NESTED_32BIT \
246 || (uType) == PGM_TYPE_NESTED_PAE \
247 || (uType) == PGM_TYPE_NESTED_AMD64)
248
249/** Macro for checking for nested or EPT.
250 * @param uType PGM_TYPE_*
251 */
252#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
253 ( (uType) == PGM_TYPE_NESTED_32BIT \
254 || (uType) == PGM_TYPE_NESTED_PAE \
255 || (uType) == PGM_TYPE_NESTED_AMD64 \
256 || (uType) == PGM_TYPE_EPT)
257
258
259
260/** @def PGM_HCPHYS_2_PTR
261 * Maps a HC physical page pool address to a virtual address.
262 *
263 * @returns VBox status code.
264 * @param pVM The cross context VM structure.
265 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
266 * @param HCPhys The HC physical address to map to a virtual one.
267 * @param ppv Where to store the virtual address. No need to cast
268 * this.
269 *
270 * @remark There is no need to assert on the result.
271 */
272#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
273
274/** @def PGM_GCPHYS_2_PTR_V2
275 * Maps a GC physical page address to a virtual address.
276 *
277 * @returns VBox status code.
278 * @param pVM The cross context VM structure.
279 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
280 * @param GCPhys The GC physical address to map to a virtual one.
281 * @param ppv Where to store the virtual address. No need to cast this.
282 *
283 * @remark Use with care as we don't have so much dynamic mapping space in
284 * ring-0 on 32-bit darwin and in RC.
285 * @remark There is no need to assert on the result.
286 */
287#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
288 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
289
290/** @def PGM_GCPHYS_2_PTR
291 * Maps a GC physical page address to a virtual address.
292 *
293 * @returns VBox status code.
294 * @param pVM The cross context VM structure.
295 * @param GCPhys The GC physical address to map to a virtual one.
296 * @param ppv Where to store the virtual address. No need to cast this.
297 *
298 * @remark Use with care as we don't have so much dynamic mapping space in
299 * ring-0 on 32-bit darwin and in RC.
300 * @remark There is no need to assert on the result.
301 */
302#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
303
304/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
305 * Maps a GC physical page address to a virtual address.
306 *
307 * @returns VBox status code.
308 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
309 * @param GCPhys The GC physical address to map to a virtual one.
310 * @param ppv Where to store the virtual address. No need to cast this.
311 *
312 * @remark Use with care as we don't have so much dynamic mapping space in
313 * ring-0 on 32-bit darwin and in RC.
314 * @remark There is no need to assert on the result.
315 */
316#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
317
318/** @def PGM_GCPHYS_2_PTR_EX
319 * Maps a unaligned GC physical page address to a virtual address.
320 *
321 * @returns VBox status code.
322 * @param pVM The cross context VM structure.
323 * @param GCPhys The GC physical address to map to a virtual one.
324 * @param ppv Where to store the virtual address. No need to cast this.
325 *
326 * @remark Use with care as we don't have so much dynamic mapping space in
327 * ring-0 on 32-bit darwin and in RC.
328 * @remark There is no need to assert on the result.
329 */
330#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
331 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
332
333/** @def PGM_DYNMAP_UNUSED_HINT
334 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
335 * is no longer used.
336 *
337 * For best effect only apply this to the page that was mapped most recently.
338 *
339 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
340 * @param pvPage The pool page.
341 */
342#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
343
344/** @def PGM_DYNMAP_UNUSED_HINT_VM
345 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
346 * is no longer used.
347 *
348 * For best effect only apply this to the page that was mapped most recently.
349 *
350 * @param pVM The cross context VM structure.
351 * @param pvPage The pool page.
352 */
353#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
354
355
356/** @def PGM_INVL_PG
357 * Invalidates a page.
358 *
359 * @param pVCpu The cross context virtual CPU structure.
360 * @param GCVirt The virtual address of the page to invalidate.
361 */
362#ifdef IN_RING0
363# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
364#elif defined(IN_RING3)
365# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
366#else
367# error "Not IN_RING0 or IN_RING3!"
368#endif
369
370/** @def PGM_INVL_PG_ALL_VCPU
371 * Invalidates a page on all VCPUs
372 *
373 * @param pVM The cross context VM structure.
374 * @param GCVirt The virtual address of the page to invalidate.
375 */
376#ifdef IN_RING0
377# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
378#else
379# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
380#endif
381
382/** @def PGM_INVL_BIG_PG
383 * Invalidates a 4MB page directory entry.
384 *
385 * @param pVCpu The cross context virtual CPU structure.
386 * @param GCVirt The virtual address within the page directory to invalidate.
387 */
388#ifdef IN_RING0
389# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
390#else
391# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
392#endif
393
394/** @def PGM_INVL_VCPU_TLBS()
395 * Invalidates the TLBs of the specified VCPU
396 *
397 * @param pVCpu The cross context virtual CPU structure.
398 */
399#ifdef IN_RING0
400# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
401#else
402# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
403#endif
404
405/** @def PGM_INVL_ALL_VCPU_TLBS()
406 * Invalidates the TLBs of all VCPUs
407 *
408 * @param pVM The cross context VM structure.
409 */
410#ifdef IN_RING0
411# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
412#else
413# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
414#endif
415
416
417/** @name Safer Shadow PAE PT/PTE
418 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419 * present.
420 *
421 * @{
422 */
423#if 1
424/**
425 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
426 * invalid entries for present.
427 * @sa X86PTEPAE.
428 */
429typedef union PGMSHWPTEPAE
430{
431 /** Unsigned integer view */
432 X86PGPAEUINT uCareful;
433 /* Not other views. */
434} PGMSHWPTEPAE;
435
436# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
443# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
446# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
452
453/**
454 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
455 * invalid entries for present.
456 * @sa X86PTPAE.
457 */
458typedef struct PGMSHWPTPAE
459{
460 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461} PGMSHWPTPAE;
462
463#else
464typedef X86PTEPAE PGMSHWPTEPAE;
465typedef X86PTPAE PGMSHWPTPAE;
466# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
473# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
476# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
482
483#endif
484
485/** Pointer to a shadow PAE PTE. */
486typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487/** Pointer to a const shadow PAE PTE. */
488typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490/** Pointer to a shadow PAE page table. */
491typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492/** Pointer to a const shadow PAE page table. */
493typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494/** @} */
495
496
497/** The physical access handler type handle count (power of two). */
498#define PGMPHYSHANDLERTYPE_COUNT 0x20
499/** Mask for getting the array index from an access handler type handle.
500 * The other handle bits are random and non-zero to avoid mixups due to zero
501 * initialized fields. */
502#define PGMPHYSHANDLERTYPE_IDX_MASK 0x1f
503
504/**
505 * Physical page access handler type registration, ring-0 part.
506 */
507typedef struct PGMPHYSHANDLERTYPEINTR0
508{
509 /** The handle value for verfication. */
510 PGMPHYSHANDLERTYPE hType;
511 /** The kind of accesses we're handling. */
512 PGMPHYSHANDLERKIND enmKind;
513 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
514 uint8_t uState;
515 /** Whether to keep the PGM lock when calling the handler.
516 * @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
517 bool fKeepPgmLock;
518 /** Set if this is registered by a device instance and uUser should be
519 * translated from a device instance ID to a pointer.
520 * @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
521 bool fRing0DevInsIdx;
522 bool afPadding[1];
523 /** Pointer to the ring-0 callback function. */
524 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
525 /** Pointer to the ring-0 callback function for \#PFs, can be NULL. */
526 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandler;
527 /** Description / Name. For easing debugging. */
528 R0PTRTYPE(const char *) pszDesc;
529} PGMPHYSHANDLERTYPEINTR0;
530/** Pointer to a physical access handler type registration. */
531typedef PGMPHYSHANDLERTYPEINTR0 *PPGMPHYSHANDLERTYPEINTR0;
532
533/**
534 * Physical page access handler type registration, shared/ring-3 part.
535 */
536typedef struct PGMPHYSHANDLERTYPEINTR3
537{
538 /** The handle value for verfication. */
539 PGMPHYSHANDLERTYPE hType;
540 /** The kind of accesses we're handling. */
541 PGMPHYSHANDLERKIND enmKind;
542 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
543 uint8_t uState;
544 /** Whether to keep the PGM lock when calling the handler.
545 * @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
546 bool fKeepPgmLock;
547 /** Set if this is registered by a device instance and uUser should be
548 * translated from a device instance ID to a pointer.
549 * @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
550 bool fRing0DevInsIdx;
551 /** Set by ring-0 if the handler is ring-0 enabled (for debug). */
552 bool fRing0Enabled : 1;
553 /** Pointer to the ring-3 callback function. */
554 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
555 /** Description / Name. For easing debugging. */
556 R3PTRTYPE(const char *) pszDesc;
557} PGMPHYSHANDLERTYPEINTR3;
558/** Pointer to a physical access handler type registration. */
559typedef PGMPHYSHANDLERTYPEINTR3 *PPGMPHYSHANDLERTYPEINTR3;
560
561/** Pointer to a physical access handler type record for the current context. */
562typedef CTX_SUFF(PPGMPHYSHANDLERTYPEINT) PPGMPHYSHANDLERTYPEINT;
563/** Pointer to a const physical access handler type record for the current context. */
564typedef CTX_SUFF(PGMPHYSHANDLERTYPEINT) const *PCPGMPHYSHANDLERTYPEINT;
565/** Dummy physical access handler type record. */
566extern CTX_SUFF(PGMPHYSHANDLERTYPEINT) const g_pgmHandlerPhysicalDummyType;
567
568
569/**
570 * Physical page access handler structure.
571 *
572 * This is used to keep track of physical address ranges
573 * which are being monitored in some kind of way.
574 */
575typedef struct PGMPHYSHANDLER
576{
577 /** @name Tree stuff.
578 * @{ */
579 /** First address. */
580 RTGCPHYS Key;
581 /** Last address. */
582 RTGCPHYS KeyLast;
583 uint32_t idxLeft;
584 uint32_t idxRight;
585 uint8_t cHeight;
586 /** @} */
587 uint8_t abPadding[3];
588 /** Number of pages to update. */
589 uint32_t cPages;
590 /** Set if we have pages that have been aliased. */
591 uint32_t cAliasedPages;
592 /** Set if we have pages that have temporarily been disabled. */
593 uint32_t cTmpOffPages;
594 /** Registered handler type handle.
595 * @note Marked volatile to prevent re-reading after validation. */
596 PGMPHYSHANDLERTYPE volatile hType;
597 /** User argument for the handlers. */
598 uint64_t uUser;
599 /** Description / Name. For easing debugging. */
600 R3PTRTYPE(const char *) pszDesc;
601 /** Profiling of this handler.
602 * @note VBOX_WITH_STATISTICS only, but included to keep structure stable. */
603 STAMPROFILE Stat;
604} PGMPHYSHANDLER;
605AssertCompileSize(PGMPHYSHANDLER, 12*8);
606/** Pointer to a physical page access handler structure. */
607typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
608
609/**
610 * Gets the type record for a physical handler (no reference added).
611 * @returns PCPGMPHYSHANDLERTYPEINT, can be NULL
612 * @param a_pVM The cross context VM structure.
613 * @param a_pPhysHandler Pointer to the physical handler structure
614 * (PGMPHYSHANDLER).
615 */
616#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) \
617 pgmHandlerPhysicalTypeHandleToPtr(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
618
619/**
620 * Gets the type record for a physical handler, never returns NULL.
621 *
622 * @returns PCPGMPHYSHANDLERTYPEINT, never NULL.
623 * @param a_pVM The cross context VM structure.
624 * @param a_pPhysHandler Pointer to the physical handler structure
625 * (PGMPHYSHANDLER).
626 */
627#define PGMPHYSHANDLER_GET_TYPE_NO_NULL(a_pVM, a_pPhysHandler) \
628 pgmHandlerPhysicalTypeHandleToPtr2(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
629
630/** Physical access handler allocator. */
631typedef RTCHardAvlTreeSlabAllocator<PGMPHYSHANDLER> PGMPHYSHANDLERALLOCATOR;
632
633/** Physical access handler tree. */
634typedef RTCHardAvlRangeTree<PGMPHYSHANDLER, RTGCPHYS> PGMPHYSHANDLERTREE;
635/** Pointer to a physical access handler tree. */
636typedef PGMPHYSHANDLERTREE *PPGMPHYSHANDLERTREE;
637
638
639/**
640 * A Physical Guest Page tracking structure.
641 *
642 * The format of this structure is complicated because we have to fit a lot
643 * of information into as few bits as possible. The format is also subject
644 * to change (there is one coming up soon). Which means that for we'll be
645 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
646 * accesses to the structure.
647 */
648typedef union PGMPAGE
649{
650 /** Structured view. */
651 struct
652 {
653 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
654 uint64_t u2HandlerPhysStateY : 2;
655 /** 3:2 - Paging structure needed to map the page
656 * (PGM_PAGE_PDE_TYPE_*). */
657 uint64_t u2PDETypeY : 2;
658 /** 4 - Unused (was used by FTE for dirty tracking). */
659 uint64_t fUnused1 : 1;
660 /** 5 - Flag indicating that a write monitored page was written to
661 * when set. */
662 uint64_t fWrittenToY : 1;
663 /** 7:6 - Unused. */
664 uint64_t u2Unused0 : 2;
665 /** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_*). */
666 uint64_t u2Unused1 : 2;
667 /** 11:10 - NEM state bits. */
668 uint64_t u2NemStateY : 2;
669 /** 12:48 - The host physical frame number (shift left to get the
670 * address). */
671 uint64_t HCPhysFN : 36;
672 /** 50:48 - The page state. */
673 uint64_t uStateY : 3;
674 /** 51:53 - The page type (PGMPAGETYPE). */
675 uint64_t uTypeY : 3;
676 /** 63:54 - PTE index for usage tracking (page pool). */
677 uint64_t u10PteIdx : 10;
678
679 /** The GMM page ID.
680 * @remarks In the current implementation, MMIO2 and pages aliased to
681 * MMIO2 pages will be exploiting this field to calculate the
682 * ring-3 mapping address corresponding to the page.
683 * Later we may consider including MMIO2 management into GMM. */
684 uint32_t idPage;
685 /** Usage tracking (page pool). */
686 uint16_t u16TrackingY;
687 /** The number of read locks on this page. */
688 uint8_t cReadLocksY;
689 /** The number of write locks on this page. */
690 uint8_t cWriteLocksY;
691 } s;
692
693 /** 64-bit integer view. */
694 uint64_t au64[2];
695 /** 16-bit view. */
696 uint32_t au32[4];
697 /** 16-bit view. */
698 uint16_t au16[8];
699 /** 8-bit view. */
700 uint8_t au8[16];
701} PGMPAGE;
702AssertCompileSize(PGMPAGE, 16);
703/** Pointer to a physical guest page. */
704typedef PGMPAGE *PPGMPAGE;
705/** Pointer to a const physical guest page. */
706typedef const PGMPAGE *PCPGMPAGE;
707/** Pointer to a physical guest page pointer. */
708typedef PPGMPAGE *PPPGMPAGE;
709
710
711/**
712 * Clears the page structure.
713 * @param a_pPage Pointer to the physical guest page tracking structure.
714 */
715#define PGM_PAGE_CLEAR(a_pPage) \
716 do { \
717 (a_pPage)->au64[0] = 0; \
718 (a_pPage)->au64[1] = 0; \
719 } while (0)
720
721/**
722 * Initializes the page structure.
723 * @param a_pPage Pointer to the physical guest page tracking structure.
724 * @param a_HCPhys The host physical address of the page.
725 * @param a_idPage The (GMM) page ID of the page.
726 * @param a_uType The page type (PGMPAGETYPE).
727 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
728 */
729#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
730 do { \
731 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
732 AssertFatalMsg(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000)), ("%RHp\n", SetHCPhysTmp)); \
733 (a_pPage)->au64[0] = SetHCPhysTmp; \
734 (a_pPage)->au64[1] = 0; \
735 (a_pPage)->s.idPage = (a_idPage); \
736 (a_pPage)->s.uStateY = (a_uState); \
737 (a_pPage)->s.uTypeY = (a_uType); \
738 } while (0)
739
740/**
741 * Initializes the page structure of a ZERO page.
742 * @param a_pPage Pointer to the physical guest page tracking structure.
743 * @param a_pVM The VM handle (for getting the zero page address).
744 * @param a_uType The page type (PGMPAGETYPE).
745 */
746#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
747 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
748
749
750/** @name The Page state, PGMPAGE::uStateY.
751 * @{ */
752/** The zero page.
753 * This is a per-VM page that's never ever mapped writable. */
754#define PGM_PAGE_STATE_ZERO 0U
755/** A allocated page.
756 * This is a per-VM page allocated from the page pool (or wherever
757 * we get MMIO2 pages from if the type is MMIO2).
758 */
759#define PGM_PAGE_STATE_ALLOCATED 1U
760/** A allocated page that's being monitored for writes.
761 * The shadow page table mappings are read-only. When a write occurs, the
762 * fWrittenTo member is set, the page remapped as read-write and the state
763 * moved back to allocated. */
764#define PGM_PAGE_STATE_WRITE_MONITORED 2U
765/** The page is shared, aka. copy-on-write.
766 * This is a page that's shared with other VMs. */
767#define PGM_PAGE_STATE_SHARED 3U
768/** The page is ballooned, so no longer available for this VM. */
769#define PGM_PAGE_STATE_BALLOONED 4U
770/** @} */
771
772
773/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
774#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
775# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
776#else
777# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
778#endif
779
780/**
781 * Gets the page state.
782 * @returns page state (PGM_PAGE_STATE_*).
783 * @param a_pPage Pointer to the physical guest page tracking structure.
784 *
785 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
786 * builds.
787 */
788#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
789#if defined(__GNUC__) && defined(VBOX_STRICT)
790# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
791#else
792# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
793#endif
794
795/**
796 * Sets the page state.
797 * @param a_pVM The VM handle, only used for lock ownership assertions.
798 * @param a_pPage Pointer to the physical guest page tracking structure.
799 * @param a_uState The new page state.
800 */
801#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
802 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
803
804
805/**
806 * Gets the host physical address of the guest page.
807 * @returns host physical address (RTHCPHYS).
808 * @param a_pPage Pointer to the physical guest page tracking structure.
809 *
810 * @remarks In strict builds on gcc platforms, this macro will make some ugly
811 * assumption about a valid pVM variable/parameter being in the
812 * current context. It will use this pVM variable to assert that the
813 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
814 * pVM is not around.
815 */
816#if 0
817# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
818# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
819#else
820# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
821# if defined(__GNUC__) && defined(VBOX_STRICT)
822# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
823# else
824# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
825# endif
826#endif
827
828/**
829 * Sets the host physical address of the guest page.
830 *
831 * @param a_pVM The VM handle, only used for lock ownership assertions.
832 * @param a_pPage Pointer to the physical guest page tracking structure.
833 * @param a_HCPhys The new host physical address.
834 */
835#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
836 do { \
837 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
838 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
839 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
840 PGM_PAGE_ASSERT_LOCK(a_pVM); \
841 } while (0)
842
843/**
844 * Get the Page ID.
845 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
846 * @param a_pPage Pointer to the physical guest page tracking structure.
847 */
848#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
849
850/**
851 * Sets the Page ID.
852 * @param a_pVM The VM handle, only used for lock ownership assertions.
853 * @param a_pPage Pointer to the physical guest page tracking structure.
854 * @param a_idPage The new page ID.
855 */
856#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
857 do { \
858 (a_pPage)->s.idPage = (a_idPage); \
859 PGM_PAGE_ASSERT_LOCK(a_pVM); \
860 } while (0)
861
862/**
863 * Get the Chunk ID.
864 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
865 * @param a_pPage Pointer to the physical guest page tracking structure.
866 */
867#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
868
869/**
870 * Get the index of the page within the allocation chunk.
871 * @returns The page index.
872 * @param a_pPage Pointer to the physical guest page tracking structure.
873 */
874#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
875
876/**
877 * Gets the page type.
878 * @returns The page type.
879 * @param a_pPage Pointer to the physical guest page tracking structure.
880 *
881 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
882 * builds.
883 */
884#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
885#if defined(__GNUC__) && defined(VBOX_STRICT)
886# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
887#else
888# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
889#endif
890
891/**
892 * Sets the page type.
893 *
894 * @param a_pVM The VM handle, only used for lock ownership assertions.
895 * @param a_pPage Pointer to the physical guest page tracking structure.
896 * @param a_enmType The new page type (PGMPAGETYPE).
897 */
898#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
899 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
900
901/**
902 * Gets the page table index
903 * @returns The page table index.
904 * @param a_pPage Pointer to the physical guest page tracking structure.
905 */
906#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
907
908/**
909 * Sets the page table index.
910 * @param a_pVM The VM handle, only used for lock ownership assertions.
911 * @param a_pPage Pointer to the physical guest page tracking structure.
912 * @param a_iPte New page table index.
913 */
914#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
915 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
916
917/**
918 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
919 * @returns true/false.
920 * @param a_pPage Pointer to the physical guest page tracking structure.
921 */
922#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
923
924/**
925 * Checks if the page is marked for MMIO, including both aliases.
926 * @returns true/false.
927 * @param a_pPage Pointer to the physical guest page tracking structure.
928 */
929#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
930 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
931 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
932 )
933
934/**
935 * Checks if the page is marked for MMIO, including special aliases.
936 * @returns true/false.
937 * @param a_pPage Pointer to the physical guest page tracking structure.
938 */
939#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
940 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
941
942/**
943 * Checks if the page is a special aliased MMIO page.
944 * @returns true/false.
945 * @param a_pPage Pointer to the physical guest page tracking structure.
946 */
947#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
948
949/**
950 * Checks if the page is backed by the ZERO page.
951 * @returns true/false.
952 * @param a_pPage Pointer to the physical guest page tracking structure.
953 */
954#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
955
956/**
957 * Checks if the page is backed by a SHARED page.
958 * @returns true/false.
959 * @param a_pPage Pointer to the physical guest page tracking structure.
960 */
961#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
962
963/**
964 * Checks if the page is ballooned.
965 * @returns true/false.
966 * @param a_pPage Pointer to the physical guest page tracking structure.
967 */
968#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
969
970/**
971 * Checks if the page is allocated.
972 * @returns true/false.
973 * @param a_pPage Pointer to the physical guest page tracking structure.
974 */
975#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
976
977/**
978 * Marks the page as written to (for GMM change monitoring).
979 * @param a_pVM The VM handle, only used for lock ownership assertions.
980 * @param a_pPage Pointer to the physical guest page tracking structure.
981 */
982#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
983 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
984
985/**
986 * Clears the written-to indicator.
987 * @param a_pVM The VM handle, only used for lock ownership assertions.
988 * @param a_pPage Pointer to the physical guest page tracking structure.
989 */
990#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
991 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
992
993/**
994 * Checks if the page was marked as written-to.
995 * @returns true/false.
996 * @param a_pPage Pointer to the physical guest page tracking structure.
997 */
998#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
999
1000
1001/** @name PT usage values (PGMPAGE::u2PDEType).
1002 *
1003 * @{ */
1004/** Either as a PT or PDE. */
1005#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1006/** Must use a page table to map the range. */
1007#define PGM_PAGE_PDE_TYPE_PT 1
1008/** Can use a page directory entry to map the continuous range. */
1009#define PGM_PAGE_PDE_TYPE_PDE 2
1010/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1011#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1012/** @} */
1013
1014/**
1015 * Set the PDE type of the page
1016 * @param a_pVM The VM handle, only used for lock ownership assertions.
1017 * @param a_pPage Pointer to the physical guest page tracking structure.
1018 * @param a_uType PGM_PAGE_PDE_TYPE_*.
1019 */
1020#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1021 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1022
1023/**
1024 * Checks if the page was marked being part of a large page
1025 * @returns true/false.
1026 * @param a_pPage Pointer to the physical guest page tracking structure.
1027 */
1028#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1029
1030/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1031 *
1032 * @remarks The values are assigned in order of priority, so we can calculate
1033 * the correct state for a page with different handlers installed.
1034 * @{ */
1035/** No handler installed. */
1036#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1037/** Monitoring is temporarily disabled. */
1038#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1039/** Write access is monitored. */
1040#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1041/** All access is monitored. */
1042#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1043/** @} */
1044
1045/**
1046 * Gets the physical access handler state of a page.
1047 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1048 * @param a_pPage Pointer to the physical guest page tracking structure.
1049 */
1050#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1051
1052/**
1053 * Sets the physical access handler state of a page.
1054 * @param a_pPage Pointer to the physical guest page tracking structure.
1055 * @param a_uState The new state value.
1056 */
1057#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1058 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1059
1060/**
1061 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1062 * @returns true/false
1063 * @param a_pPage Pointer to the physical guest page tracking structure.
1064 */
1065#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1066 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1067
1068/**
1069 * Checks if the page has any active physical access handlers.
1070 * @returns true/false
1071 * @param a_pPage Pointer to the physical guest page tracking structure.
1072 */
1073#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1074 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1075
1076/**
1077 * Checks if the page has any access handlers, including temporarily disabled ones.
1078 * @returns true/false
1079 * @param a_pPage Pointer to the physical guest page tracking structure.
1080 */
1081#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1082 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1083
1084/**
1085 * Checks if the page has any active access handlers.
1086 * @returns true/false
1087 * @param a_pPage Pointer to the physical guest page tracking structure.
1088 */
1089#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1090 (PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1091
1092/**
1093 * Checks if the page has any active access handlers catching all accesses.
1094 * @returns true/false
1095 * @param a_pPage Pointer to the physical guest page tracking structure.
1096 */
1097#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1098 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1099
1100
1101/** @def PGM_PAGE_GET_TRACKING
1102 * Gets the packed shadow page pool tracking data associated with a guest page.
1103 * @returns uint16_t containing the data.
1104 * @param a_pPage Pointer to the physical guest page tracking structure.
1105 */
1106#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1107#if defined(__GNUC__) && defined(VBOX_STRICT)
1108# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1109#else
1110# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1111#endif
1112
1113/** @def PGM_PAGE_SET_TRACKING
1114 * Sets the packed shadow page pool tracking data associated with a guest page.
1115 * @param a_pVM The VM handle, only used for lock ownership assertions.
1116 * @param a_pPage Pointer to the physical guest page tracking structure.
1117 * @param a_u16TrackingData The tracking data to store.
1118 */
1119#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1120 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1121
1122/** @def PGM_PAGE_GET_TD_CREFS
1123 * Gets the @a cRefs tracking data member.
1124 * @returns cRefs.
1125 * @param a_pPage Pointer to the physical guest page tracking structure.
1126 */
1127#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1128 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1129#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1130 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1131
1132/** @def PGM_PAGE_GET_TD_IDX
1133 * Gets the @a idx tracking data member.
1134 * @returns idx.
1135 * @param a_pPage Pointer to the physical guest page tracking structure.
1136 */
1137#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1138 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1139#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1140 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1141
1142
1143/** Max number of locks on a page. */
1144#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1145
1146/** Get the read lock count.
1147 * @returns count.
1148 * @param a_pPage Pointer to the physical guest page tracking structure.
1149 */
1150#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1151
1152/** Get the write lock count.
1153 * @returns count.
1154 * @param a_pPage Pointer to the physical guest page tracking structure.
1155 */
1156#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1157
1158/** Decrement the read lock counter.
1159 * @param a_pPage Pointer to the physical guest page tracking structure.
1160 */
1161#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1162
1163/** Decrement the write lock counter.
1164 * @param a_pPage Pointer to the physical guest page tracking structure.
1165 */
1166#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1167
1168/** Increment the read lock counter.
1169 * @param a_pPage Pointer to the physical guest page tracking structure.
1170 */
1171#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1172
1173/** Increment the write lock counter.
1174 * @param a_pPage Pointer to the physical guest page tracking structure.
1175 */
1176#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1177
1178
1179/** Gets the NEM state.
1180 * @returns NEM state value (two bits).
1181 * @param a_pPage Pointer to the physical guest page tracking structure.
1182 */
1183#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1184
1185/** Sets the NEM state.
1186 * @param a_pPage Pointer to the physical guest page tracking structure.
1187 * @param a_u2State The NEM state value (specific to NEM impl.).
1188 */
1189#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1190 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1191
1192
1193#if 0
1194/** Enables sanity checking of write monitoring using CRC-32. */
1195# define PGMLIVESAVERAMPAGE_WITH_CRC32
1196#endif
1197
1198/**
1199 * Per page live save tracking data.
1200 */
1201typedef struct PGMLIVESAVERAMPAGE
1202{
1203 /** Number of times it has been dirtied. */
1204 uint32_t cDirtied : 24;
1205 /** Whether it is currently dirty. */
1206 uint32_t fDirty : 1;
1207 /** Ignore the page.
1208 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1209 * deal with these after pausing the VM and DevPCI have said it bit about
1210 * remappings. */
1211 uint32_t fIgnore : 1;
1212 /** Was a ZERO page last time around. */
1213 uint32_t fZero : 1;
1214 /** Was a SHARED page last time around. */
1215 uint32_t fShared : 1;
1216 /** Whether the page is/was write monitored in a previous pass. */
1217 uint32_t fWriteMonitored : 1;
1218 /** Whether the page is/was write monitored earlier in this pass. */
1219 uint32_t fWriteMonitoredJustNow : 1;
1220 /** Bits reserved for future use. */
1221 uint32_t u2Reserved : 2;
1222#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1223 /** CRC-32 for the page. This is for internal consistency checks. */
1224 uint32_t u32Crc;
1225#endif
1226} PGMLIVESAVERAMPAGE;
1227#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1228AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1229#else
1230AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1231#endif
1232/** Pointer to the per page live save tracking data. */
1233typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1234
1235/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1236#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1237
1238
1239/**
1240 * RAM range for GC Phys to HC Phys conversion.
1241 *
1242 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1243 * conversions too, but we'll let MM handle that for now.
1244 *
1245 * This structure is used by linked lists in both GC and HC.
1246 */
1247typedef struct PGMRAMRANGE
1248{
1249 /** Start of the range. Page aligned. */
1250 RTGCPHYS GCPhys;
1251 /** Size of the range. (Page aligned of course). */
1252 RTGCPHYS cb;
1253 /** Pointer to the next RAM range - for R3. */
1254 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1255 /** Pointer to the next RAM range - for R0. */
1256 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1257 /** PGM_RAM_RANGE_FLAGS_* flags. */
1258 uint32_t fFlags;
1259 /** NEM specific info, UINT32_MAX if not used. */
1260 uint32_t uNemRange;
1261 /** Last address in the range (inclusive). Page aligned (-1). */
1262 RTGCPHYS GCPhysLast;
1263 /** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1264 R3PTRTYPE(void *) pvR3;
1265 /** Live save per page tracking data. */
1266 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1267 /** The range description. */
1268 R3PTRTYPE(const char *) pszDesc;
1269 /** Pointer to self - R0 pointer. */
1270 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1271
1272 /** Pointer to the left search three node - ring-3 context. */
1273 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1274 /** Pointer to the right search three node - ring-3 context. */
1275 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1276 /** Pointer to the left search three node - ring-0 context. */
1277 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1278 /** Pointer to the right search three node - ring-0 context. */
1279 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1280
1281 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1282#if HC_ARCH_BITS == 32
1283 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1284#endif
1285 /** Array of physical guest page tracking structures.
1286 * @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1287 PGMPAGE aPages[1];
1288} PGMRAMRANGE;
1289/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1290typedef PGMRAMRANGE *PPGMRAMRANGE;
1291
1292/** @name PGMRAMRANGE::fFlags
1293 * @{ */
1294/** The RAM range is floating around as an independent guest mapping. */
1295#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1296/** Ad hoc RAM range for an ROM mapping. */
1297#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1298/** Ad hoc RAM range for an MMIO mapping. */
1299#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1300/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1301#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1302/** @} */
1303
1304/** Tests if a RAM range is an ad hoc one or not.
1305 * @returns true/false.
1306 * @param pRam The RAM range.
1307 */
1308#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1309 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1310
1311/** The number of entries in the RAM range TLBs (there is one for each
1312 * context). Must be a power of two. */
1313#define PGM_RAMRANGE_TLB_ENTRIES 8
1314
1315/**
1316 * Calculates the RAM range TLB index for the physical address.
1317 *
1318 * @returns RAM range TLB index.
1319 * @param a_GCPhys The guest physical address.
1320 */
1321#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1322
1323/**
1324 * Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1325 * mapping address.
1326 */
1327#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1328 ( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1329
1330
1331/**
1332 * Per page tracking structure for ROM image.
1333 *
1334 * A ROM image may have a shadow page, in which case we may have two pages
1335 * backing it. This structure contains the PGMPAGE for both while
1336 * PGMRAMRANGE have a copy of the active one. It is important that these
1337 * aren't out of sync in any regard other than page pool tracking data.
1338 */
1339typedef struct PGMROMPAGE
1340{
1341 /** The page structure for the virgin ROM page. */
1342 PGMPAGE Virgin;
1343 /** The page structure for the shadow RAM page. */
1344 PGMPAGE Shadow;
1345 /** The current protection setting. */
1346 PGMROMPROT enmProt;
1347 /** Live save status information. Makes use of unused alignment space. */
1348 struct
1349 {
1350 /** The previous protection value. */
1351 uint8_t u8Prot;
1352 /** Written to flag set by the handler. */
1353 bool fWrittenTo;
1354 /** Whether the shadow page is dirty or not. */
1355 bool fDirty;
1356 /** Whether it was dirtied in the recently. */
1357 bool fDirtiedRecently;
1358 } LiveSave;
1359} PGMROMPAGE;
1360AssertCompileSizeAlignment(PGMROMPAGE, 8);
1361/** Pointer to a ROM page tracking structure. */
1362typedef PGMROMPAGE *PPGMROMPAGE;
1363
1364
1365/**
1366 * A registered ROM image.
1367 *
1368 * This is needed to keep track of ROM image since they generally intrude
1369 * into a PGMRAMRANGE. It also keeps track of additional info like the
1370 * two page sets (read-only virgin and read-write shadow), the current
1371 * state of each page.
1372 *
1373 * Because access handlers cannot easily be executed in a different
1374 * context, the ROM ranges needs to be accessible and in all contexts.
1375 */
1376typedef struct PGMROMRANGE
1377{
1378 /** Pointer to the next range - R3. */
1379 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1380 /** Pointer to the next range - R0. */
1381 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1382 /** Pointer to the this range - R0. */
1383 R0PTRTYPE(struct PGMROMRANGE *) pSelfR0;
1384 /** Address of the range. */
1385 RTGCPHYS GCPhys;
1386 /** Address of the last byte in the range. */
1387 RTGCPHYS GCPhysLast;
1388 /** Size of the range. */
1389 RTGCPHYS cb;
1390 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1391 uint8_t fFlags;
1392 /** The saved state range ID. */
1393 uint8_t idSavedState;
1394 /** Alignment padding. */
1395 uint8_t au8Alignment[2];
1396 /** The size bits pvOriginal points to. */
1397 uint32_t cbOriginal;
1398 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1399 * This is used for strictness checks. */
1400 R3PTRTYPE(const void *) pvOriginal;
1401 /** The ROM description. */
1402 R3PTRTYPE(const char *) pszDesc;
1403#ifdef VBOX_WITH_PGM_NEM_MODE
1404 /** In simplified memory mode this provides alternate backing for shadowed ROMs.
1405 * - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1406 * - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1407 * - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1408 * - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1409 R3PTRTYPE(uint8_t *) pbR3Alternate;
1410 RTR3PTR pvAlignment2;
1411#endif
1412 /** The per page tracking structures. */
1413 PGMROMPAGE aPages[1];
1414} PGMROMRANGE;
1415/** Pointer to a ROM range. */
1416typedef PGMROMRANGE *PPGMROMRANGE;
1417
1418
1419/**
1420 * Live save per page data for an MMIO2 page.
1421 *
1422 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1423 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1424 * CRC-32 for detecting changes as well as special handling of zero pages. This
1425 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1426 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1427 * because of speed (2.5x and 6x slower).)
1428 *
1429 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1430 * save but normally is disabled. Since we can write monitor guest
1431 * accesses on our own, we only need this for host accesses. Shouldn't be
1432 * too difficult for DevVGA, VMMDev might be doable, the planned
1433 * networking fun will be fun since it involves ring-0.
1434 */
1435typedef struct PGMLIVESAVEMMIO2PAGE
1436{
1437 /** Set if the page is considered dirty. */
1438 bool fDirty;
1439 /** The number of scans this page has remained unchanged for.
1440 * Only updated for dirty pages. */
1441 uint8_t cUnchangedScans;
1442 /** Whether this page was zero at the last scan. */
1443 bool fZero;
1444 /** Alignment padding. */
1445 bool fReserved;
1446 /** CRC-32 for the first half of the page.
1447 * This is used together with u32CrcH2 to quickly detect changes in the page
1448 * during the non-final passes. */
1449 uint32_t u32CrcH1;
1450 /** CRC-32 for the second half of the page. */
1451 uint32_t u32CrcH2;
1452 /** SHA-1 for the saved page.
1453 * This is used in the final pass to skip pages without changes. */
1454 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1455} PGMLIVESAVEMMIO2PAGE;
1456/** Pointer to a live save status data for an MMIO2 page. */
1457typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1458
1459/**
1460 * A registered MMIO2 (= Device RAM) range.
1461 *
1462 * There are a few reason why we need to keep track of these registrations. One
1463 * of them is the deregistration & cleanup stuff, while another is that the
1464 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1465 * range list.
1466 *
1467 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1468 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1469 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1470 * overlap we will free all the existing RAM pages and put in the ram range
1471 * pages instead.
1472 */
1473typedef struct PGMREGMMIO2RANGE
1474{
1475 /** The owner of the range. (a device) */
1476 PPDMDEVINSR3 pDevInsR3;
1477 /** Pointer to the ring-3 mapping of the allocation. */
1478 RTR3PTR pvR3;
1479#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1480 /** Pointer to the ring-0 mapping of the allocation. */
1481 RTR0PTR pvR0;
1482#endif
1483 /** Pointer to the next range - R3. */
1484 R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1485 /** Flags (PGMREGMMIO2RANGE_F_XXX). */
1486 uint16_t fFlags;
1487 /** The sub device number (internal PCI config (CFGM) number). */
1488 uint8_t iSubDev;
1489 /** The PCI region number. */
1490 uint8_t iRegion;
1491 /** The saved state range ID. */
1492 uint8_t idSavedState;
1493 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1494 uint8_t idMmio2;
1495 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1496#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1497 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1498#else
1499 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1500#endif
1501 /** The real size.
1502 * This may be larger than indicated by RamRange.cb if the range has been
1503 * reduced during saved state loading. */
1504 RTGCPHYS cbReal;
1505 /** Pointer to the physical handler for MMIO.
1506 * If NEM is responsible for tracking dirty pages in simple memory mode, this
1507 * will be NULL. */
1508 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1509 /** Live save per page tracking data for MMIO2. */
1510 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1511 /** The associated RAM range. */
1512 PGMRAMRANGE RamRange;
1513} PGMREGMMIO2RANGE;
1514AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1515/** Pointer to a MMIO2 or pre-registered MMIO range. */
1516typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1517
1518/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1519 * @{ */
1520/** Set if this is the first chunk in the MMIO2 range. */
1521#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1522/** Set if this is the last chunk in the MMIO2 range. */
1523#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1524/** Set if the whole range is mapped. */
1525#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1526/** Set if it's overlapping, clear if not. */
1527#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1528/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1529#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1530/** Set if the access handler is registered. */
1531#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1532/** Set if dirty page tracking is currently enabled. */
1533#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1534/** Set if there are dirty pages in the range. */
1535#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1536/** @} */
1537
1538
1539/** @name Internal MMIO2 constants.
1540 * @{ */
1541/** The maximum number of MMIO2 ranges. */
1542#define PGM_MMIO2_MAX_RANGES 32
1543/** The maximum number of pages in a MMIO2 range. */
1544#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1545/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1546#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1547/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1548#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1549/** Gets the MMIO2 page index from an MMIO2 page ID. */
1550#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1551/** @} */
1552
1553
1554
1555/**
1556 * PGMPhysRead/Write cache entry
1557 */
1558typedef struct PGMPHYSCACHEENTRY
1559{
1560 /** R3 pointer to physical page. */
1561 R3PTRTYPE(uint8_t *) pbR3;
1562 /** GC Physical address for cache entry */
1563 RTGCPHYS GCPhys;
1564#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1565 RTGCPHYS u32Padding0; /**< alignment padding. */
1566#endif
1567} PGMPHYSCACHEENTRY;
1568
1569/**
1570 * PGMPhysRead/Write cache to reduce REM memory access overhead
1571 */
1572typedef struct PGMPHYSCACHE
1573{
1574 /** Bitmap of valid cache entries */
1575 uint64_t aEntries;
1576 /** Cache entries */
1577 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1578} PGMPHYSCACHE;
1579
1580
1581/** @name Ring-3 page mapping TLBs
1582 * @{ */
1583
1584/** Pointer to an allocation chunk ring-3 mapping. */
1585typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1586/** Pointer to an allocation chunk ring-3 mapping pointer. */
1587typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1588
1589/**
1590 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1591 *
1592 * The primary tree (Core) uses the chunk id as key.
1593 */
1594typedef struct PGMCHUNKR3MAP
1595{
1596 /** The key is the chunk id. */
1597 AVLU32NODECORE Core;
1598 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1599 * selection. */
1600 uint32_t iLastUsed;
1601 /** The current reference count. */
1602 uint32_t volatile cRefs;
1603 /** The current permanent reference count. */
1604 uint32_t volatile cPermRefs;
1605 /** The mapping address. */
1606 void *pv;
1607} PGMCHUNKR3MAP;
1608
1609/**
1610 * Allocation chunk ring-3 mapping TLB entry.
1611 */
1612typedef struct PGMCHUNKR3MAPTLBE
1613{
1614 /** The chunk id. */
1615 uint32_t volatile idChunk;
1616#if HC_ARCH_BITS == 64
1617 uint32_t u32Padding; /**< alignment padding. */
1618#endif
1619 /** The chunk map. */
1620 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1621} PGMCHUNKR3MAPTLBE;
1622/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1623typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1624
1625/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1626 * @remark Must be a power of two value. */
1627#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1628
1629/**
1630 * Allocation chunk ring-3 mapping TLB.
1631 *
1632 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1633 * At first glance this might look kinda odd since AVL trees are
1634 * supposed to give the most optimal lookup times of all trees
1635 * due to their balancing. However, take a tree with 1023 nodes
1636 * in it, that's 10 levels, meaning that most searches has to go
1637 * down 9 levels before they find what they want. This isn't fast
1638 * compared to a TLB hit. There is the factor of cache misses,
1639 * and of course the problem with trees and branch prediction.
1640 * This is why we use TLBs in front of most of the trees.
1641 *
1642 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1643 * difficult when we switch to the new inlined AVL trees (from kStuff).
1644 */
1645typedef struct PGMCHUNKR3MAPTLB
1646{
1647 /** The TLB entries. */
1648 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1649} PGMCHUNKR3MAPTLB;
1650
1651/**
1652 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1653 * @returns Chunk TLB index.
1654 * @param idChunk The Chunk ID.
1655 */
1656#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1657
1658
1659/**
1660 * Ring-3 guest page mapping TLB entry.
1661 * @remarks used in ring-0 as well at the moment.
1662 */
1663typedef struct PGMPAGER3MAPTLBE
1664{
1665 /** Address of the page. */
1666 RTGCPHYS volatile GCPhys;
1667 /** The guest page. */
1668 R3PTRTYPE(PPGMPAGE) volatile pPage;
1669 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1670 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1671 /** The address */
1672 R3PTRTYPE(void *) volatile pv;
1673#if HC_ARCH_BITS == 32
1674 uint32_t u32Padding; /**< alignment padding. */
1675#endif
1676} PGMPAGER3MAPTLBE;
1677/** Pointer to an entry in the HC physical TLB. */
1678typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1679
1680
1681/** The number of entries in the ring-3 guest page mapping TLB.
1682 * @remarks The value must be a power of two. */
1683#define PGM_PAGER3MAPTLB_ENTRIES 256
1684
1685/**
1686 * Ring-3 guest page mapping TLB.
1687 * @remarks used in ring-0 as well at the moment.
1688 */
1689typedef struct PGMPAGER3MAPTLB
1690{
1691 /** The TLB entries. */
1692 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1693} PGMPAGER3MAPTLB;
1694/** Pointer to the ring-3 guest page mapping TLB. */
1695typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1696
1697/**
1698 * Calculates the index of the TLB entry for the specified guest page.
1699 * @returns Physical TLB index.
1700 * @param GCPhys The guest physical address.
1701 */
1702#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1703
1704/** @} */
1705
1706
1707/** @name Ring-0 page mapping TLB
1708 * @{ */
1709/**
1710 * Ring-0 guest page mapping TLB entry.
1711 */
1712typedef struct PGMPAGER0MAPTLBE
1713{
1714 /** Address of the page. */
1715 RTGCPHYS volatile GCPhys;
1716 /** The guest page. */
1717 R0PTRTYPE(PPGMPAGE) volatile pPage;
1718 /** The address */
1719 R0PTRTYPE(void *) volatile pv;
1720} PGMPAGER0MAPTLBE;
1721/** Pointer to an entry in the HC physical TLB. */
1722typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1723
1724
1725/** The number of entries in the ring-3 guest page mapping TLB.
1726 * @remarks The value must be a power of two. */
1727#define PGM_PAGER0MAPTLB_ENTRIES 256
1728
1729/**
1730 * Ring-3 guest page mapping TLB.
1731 * @remarks used in ring-0 as well at the moment.
1732 */
1733typedef struct PGMPAGER0MAPTLB
1734{
1735 /** The TLB entries. */
1736 PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1737} PGMPAGER0MAPTLB;
1738/** Pointer to the ring-3 guest page mapping TLB. */
1739typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1740
1741/**
1742 * Calculates the index of the TLB entry for the specified guest page.
1743 * @returns Physical TLB index.
1744 * @param GCPhys The guest physical address.
1745 */
1746#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1747/** @} */
1748
1749
1750/** @name Context neutral page mapper TLB.
1751 *
1752 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1753 * code is writting in a kind of context neutral way. Time will show whether
1754 * this actually makes sense or not...
1755 *
1756 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1757 * context ends up using a global mapping cache on some platforms
1758 * (darwin).
1759 *
1760 * @{ */
1761/** @typedef PPGMPAGEMAPTLB
1762 * The page mapper TLB pointer type for the current context. */
1763/** @typedef PPGMPAGEMAPTLB
1764 * The page mapper TLB entry pointer type for the current context. */
1765/** @typedef PPGMPAGEMAPTLB
1766 * The page mapper TLB entry pointer pointer type for the current context. */
1767/** @def PGM_PAGEMAPTLB_ENTRIES
1768 * The number of TLB entries in the page mapper TLB for the current context. */
1769/** @def PGM_PAGEMAPTLB_IDX
1770 * Calculate the TLB index for a guest physical address.
1771 * @returns The TLB index.
1772 * @param GCPhys The guest physical address. */
1773/** @typedef PPGMPAGEMAP
1774 * Pointer to a page mapper unit for current context. */
1775/** @typedef PPPGMPAGEMAP
1776 * Pointer to a page mapper unit pointer for current context. */
1777#if defined(IN_RING0)
1778typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1779typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1780typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1781# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1782# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1783typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1784typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1785#else
1786typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1787typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1788typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1789# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1790# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1791typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1792typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1793#endif
1794/** @} */
1795
1796
1797/** @name PGM Pool Indexes.
1798 * Aka. the unique shadow page identifier.
1799 * @{ */
1800/** NIL page pool IDX. */
1801#define NIL_PGMPOOL_IDX 0
1802/** The first normal index. There used to be 5 fictive pages up front, now
1803 * there is only the NIL page. */
1804#define PGMPOOL_IDX_FIRST 1
1805/** The last valid index. (inclusive, 14 bits) */
1806#define PGMPOOL_IDX_LAST 0x3fff
1807/** @} */
1808
1809/** The NIL index for the parent chain. */
1810#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1811#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1812
1813/**
1814 * Node in the chain linking a shadowed page to it's parent (user).
1815 */
1816#pragma pack(1)
1817typedef struct PGMPOOLUSER
1818{
1819 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1820 uint16_t iNext;
1821 /** The user page index. */
1822 uint16_t iUser;
1823 /** Index into the user table. */
1824 uint32_t iUserTable;
1825} PGMPOOLUSER, *PPGMPOOLUSER;
1826typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1827#pragma pack()
1828
1829
1830/** The NIL index for the phys ext chain. */
1831#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1832/** The NIL pte index for a phys ext chain slot. */
1833#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1834
1835/**
1836 * Node in the chain of physical cross reference extents.
1837 * @todo Calling this an 'extent' is not quite right, find a better name.
1838 * @todo find out the optimal size of the aidx array
1839 */
1840#pragma pack(1)
1841typedef struct PGMPOOLPHYSEXT
1842{
1843 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1844 uint16_t iNext;
1845 /** Alignment. */
1846 uint16_t u16Align;
1847 /** The user page index. */
1848 uint16_t aidx[3];
1849 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1850 uint16_t apte[3];
1851} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1852typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1853#pragma pack()
1854
1855
1856/**
1857 * The kind of page that's being shadowed.
1858 */
1859typedef enum PGMPOOLKIND
1860{
1861 /** The virtual invalid 0 entry. */
1862 PGMPOOLKIND_INVALID = 0,
1863 /** The entry is free (=unused). */
1864 PGMPOOLKIND_FREE,
1865
1866 /** Shw: 32-bit page table; Gst: no paging. */
1867 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1868 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1869 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1870 /** Shw: 32-bit page table; Gst: 4MB page. */
1871 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1872 /** Shw: PAE page table; Gst: no paging. */
1873 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1874 /** Shw: PAE page table; Gst: 32-bit page table. */
1875 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1876 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1877 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1878 /** Shw: PAE page table; Gst: PAE page table. */
1879 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1880 /** Shw: PAE page table; Gst: 2MB page. */
1881 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1882
1883 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1884 PGMPOOLKIND_32BIT_PD,
1885 /** Shw: 32-bit page directory. Gst: no paging. */
1886 PGMPOOLKIND_32BIT_PD_PHYS,
1887 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1888 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1889 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1890 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1891 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1892 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1893 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1894 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1895 /** Shw: PAE page directory; Gst: PAE page directory. */
1896 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1897 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1898 PGMPOOLKIND_PAE_PD_PHYS,
1899
1900 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1901 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1902 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1903 PGMPOOLKIND_PAE_PDPT,
1904 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1905 PGMPOOLKIND_PAE_PDPT_PHYS,
1906
1907 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1908 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1909 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
1910 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1911 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1912 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1913 /** Shw: 64-bit page directory table; Gst: no paging. */
1914 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1915
1916 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1917 PGMPOOLKIND_64BIT_PML4,
1918
1919 /** Shw: EPT page directory pointer table; Gst: no paging. */
1920 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1921 /** Shw: EPT page directory table; Gst: no paging. */
1922 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1923 /** Shw: EPT page table; Gst: no paging. */
1924 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1925
1926 /** Shw: Root Nested paging table. */
1927 PGMPOOLKIND_ROOT_NESTED,
1928
1929 /** The last valid entry. */
1930 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1931} PGMPOOLKIND;
1932
1933/**
1934 * The access attributes of the page; only applies to big pages.
1935 */
1936typedef enum
1937{
1938 PGMPOOLACCESS_DONTCARE = 0,
1939 PGMPOOLACCESS_USER_RW,
1940 PGMPOOLACCESS_USER_R,
1941 PGMPOOLACCESS_USER_RW_NX,
1942 PGMPOOLACCESS_USER_R_NX,
1943 PGMPOOLACCESS_SUPERVISOR_RW,
1944 PGMPOOLACCESS_SUPERVISOR_R,
1945 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1946 PGMPOOLACCESS_SUPERVISOR_R_NX
1947} PGMPOOLACCESS;
1948
1949/**
1950 * The tracking data for a page in the pool.
1951 */
1952typedef struct PGMPOOLPAGE
1953{
1954 /** AVL node code with the (HC) physical address of this page. */
1955 AVLOHCPHYSNODECORE Core;
1956 /** Pointer to the R3 mapping of the page. */
1957 R3PTRTYPE(void *) pvPageR3;
1958 /** Pointer to the R0 mapping of the page. */
1959 R0PTRTYPE(void *) pvPageR0;
1960 /** The guest physical address. */
1961 RTGCPHYS GCPhys;
1962 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1963 uint8_t enmKind;
1964 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1965 uint8_t enmAccess;
1966 /** This supplements enmKind and enmAccess */
1967 bool fA20Enabled : 1;
1968
1969 /** Used to indicate that the page is zeroed. */
1970 bool fZeroed : 1;
1971 /** Used to indicate that a PT has non-global entries. */
1972 bool fSeenNonGlobal : 1;
1973 /** Used to indicate that we're monitoring writes to the guest page. */
1974 bool fMonitored : 1;
1975 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1976 * (All pages are in the age list.) */
1977 bool fCached : 1;
1978 /** This is used by the R3 access handlers when invoked by an async thread.
1979 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1980 bool volatile fReusedFlushPending : 1;
1981 /** Used to mark the page as dirty (write monitoring is temporarily
1982 * off). */
1983 bool fDirty : 1;
1984 bool fPadding1 : 1;
1985 bool fPadding2;
1986
1987 /** The index of this page. */
1988 uint16_t idx;
1989 /** The next entry in the list this page currently resides in.
1990 * It's either in the free list or in the GCPhys hash. */
1991 uint16_t iNext;
1992 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1993 uint16_t iUserHead;
1994 /** The number of present entries. */
1995 uint16_t cPresent;
1996 /** The first entry in the table which is present. */
1997 uint16_t iFirstPresent;
1998 /** The number of modifications to the monitored page. */
1999 uint16_t cModifications;
2000 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2001 uint16_t iModifiedNext;
2002 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2003 uint16_t iModifiedPrev;
2004 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2005 uint16_t iMonitoredNext;
2006 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2007 uint16_t iMonitoredPrev;
2008 /** The next page in the age list. */
2009 uint16_t iAgeNext;
2010 /** The previous page in the age list. */
2011 uint16_t iAgePrev;
2012 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2013 uint8_t idxDirtyEntry;
2014
2015 /** @name Access handler statistics to determine whether the guest is
2016 * (re)initializing a page table.
2017 * @{ */
2018 RTGCPTR GCPtrLastAccessHandlerRip;
2019 RTGCPTR GCPtrLastAccessHandlerFault;
2020 uint64_t cLastAccessHandler;
2021 /** @} */
2022 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2023 uint32_t volatile cLocked;
2024#if GC_ARCH_BITS == 64
2025 uint32_t u32Alignment3;
2026#endif
2027# ifdef VBOX_STRICT
2028 RTGCPTR GCPtrDirtyFault;
2029# endif
2030} PGMPOOLPAGE;
2031/** Pointer to a pool page. */
2032typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2033/** Pointer to a const pool page. */
2034typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2035/** Pointer to a pool page pointer. */
2036typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2037
2038
2039/** The hash table size. */
2040# define PGMPOOL_HASH_SIZE 0x40
2041/** The hash function. */
2042# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2043
2044
2045/**
2046 * The shadow page pool instance data.
2047 *
2048 * It's all one big allocation made at init time, except for the
2049 * pages that is. The user nodes follows immediately after the
2050 * page structures.
2051 */
2052typedef struct PGMPOOL
2053{
2054 /** The VM handle - R3 Ptr. */
2055 PVMR3 pVMR3;
2056 /** The VM handle - R0 Ptr. */
2057 R0PTRTYPE(PVMCC) pVMR0;
2058 /** The ring-3 pointer to this structure. */
2059 R3PTRTYPE(struct PGMPOOL *) pPoolR3;
2060 /** The ring-0 pointer to this structure. */
2061 R0PTRTYPE(struct PGMPOOL *) pPoolR0;
2062 /** The max pool size. This includes the special IDs. */
2063 uint16_t cMaxPages;
2064 /** The current pool size. */
2065 uint16_t cCurPages;
2066 /** The head of the free page list. */
2067 uint16_t iFreeHead;
2068 /* Padding. */
2069 uint16_t u16Padding;
2070 /** Head of the chain of free user nodes. */
2071 uint16_t iUserFreeHead;
2072 /** The number of user nodes we've allocated. */
2073 uint16_t cMaxUsers;
2074 /** The number of present page table entries in the entire pool. */
2075 uint32_t cPresent;
2076 /** Pointer to the array of user nodes - R3 pointer. */
2077 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2078 /** Pointer to the array of user nodes - R0 pointer. */
2079 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2080 /** Head of the chain of free phys ext nodes. */
2081 uint16_t iPhysExtFreeHead;
2082 /** The number of user nodes we've allocated. */
2083 uint16_t cMaxPhysExts;
2084 uint32_t u32Padding0b;
2085 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2086 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2087 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2088 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2089 /** Hash table for GCPhys addresses. */
2090 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2091 /** The head of the age list. */
2092 uint16_t iAgeHead;
2093 /** The tail of the age list. */
2094 uint16_t iAgeTail;
2095 /** Set if the cache is enabled. */
2096 bool fCacheEnabled;
2097 /** Alignment padding. */
2098 bool afPadding1[3];
2099 /** Head of the list of modified pages. */
2100 uint16_t iModifiedHead;
2101 /** The current number of modified pages. */
2102 uint16_t cModifiedPages;
2103 /** Alignment padding. */
2104 uint32_t u32Padding2;
2105 /** Physical access handler type registration handle. */
2106 PGMPHYSHANDLERTYPE hAccessHandlerType;
2107 /** Next available slot (in aDirtyPages). */
2108 uint32_t idxFreeDirtyPage;
2109 /** Number of active dirty pages. */
2110 uint32_t cDirtyPages;
2111 /** Array of current dirty pgm pool page indices. */
2112 uint16_t aidxDirtyPages[16];
2113 /** Array running in parallel to aidxDirtyPages with the page data. */
2114 struct
2115 {
2116 uint64_t aPage[512];
2117 } aDirtyPages[16];
2118
2119 /** The number of pages currently in use. */
2120 uint16_t cUsedPages;
2121#ifdef VBOX_WITH_STATISTICS
2122 /** The high water mark for cUsedPages. */
2123 uint16_t cUsedPagesHigh;
2124 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2125 /** Profiling pgmPoolAlloc(). */
2126 STAMPROFILEADV StatAlloc;
2127 /** Profiling pgmR3PoolClearDoIt(). */
2128 STAMPROFILE StatClearAll;
2129 /** Profiling pgmR3PoolReset(). */
2130 STAMPROFILE StatR3Reset;
2131 /** Profiling pgmPoolFlushPage(). */
2132 STAMPROFILE StatFlushPage;
2133 /** Profiling pgmPoolFree(). */
2134 STAMPROFILE StatFree;
2135 /** Counting explicit flushes by PGMPoolFlushPage(). */
2136 STAMCOUNTER StatForceFlushPage;
2137 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2138 STAMCOUNTER StatForceFlushDirtyPage;
2139 /** Counting flushes for reused pages. */
2140 STAMCOUNTER StatForceFlushReused;
2141 /** Profiling time spent zeroing pages. */
2142 STAMPROFILE StatZeroPage;
2143 /** Profiling of pgmPoolTrackDeref. */
2144 STAMPROFILE StatTrackDeref;
2145 /** Profiling pgmTrackFlushGCPhysPT. */
2146 STAMPROFILE StatTrackFlushGCPhysPT;
2147 /** Profiling pgmTrackFlushGCPhysPTs. */
2148 STAMPROFILE StatTrackFlushGCPhysPTs;
2149 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2150 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2151 /** Number of times we've been out of user records. */
2152 STAMCOUNTER StatTrackFreeUpOneUser;
2153 /** Nr of flushed entries. */
2154 STAMCOUNTER StatTrackFlushEntry;
2155 /** Nr of updated entries. */
2156 STAMCOUNTER StatTrackFlushEntryKeep;
2157 /** Profiling deref activity related tracking GC physical pages. */
2158 STAMPROFILE StatTrackDerefGCPhys;
2159 /** Number of linear searches for a HCPhys in the ram ranges. */
2160 STAMCOUNTER StatTrackLinearRamSearches;
2161 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2162 STAMCOUNTER StamTrackPhysExtAllocFailures;
2163
2164 /** Profiling the RC/R0 \#PF access handler. */
2165 STAMPROFILE StatMonitorPfRZ;
2166 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2167 STAMPROFILE StatMonitorPfRZHandled;
2168 /** Times we've failed interpreting the instruction. */
2169 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2170 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2171 STAMPROFILE StatMonitorPfRZFlushPage;
2172 /** Times we've detected a page table reinit. */
2173 STAMCOUNTER StatMonitorPfRZFlushReinit;
2174 /** Counting flushes for pages that are modified too often. */
2175 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2176 /** Times we've detected fork(). */
2177 STAMCOUNTER StatMonitorPfRZFork;
2178 /** Times we've failed interpreting a patch code instruction. */
2179 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2180 /** Times we've failed interpreting a patch code instruction during flushing. */
2181 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2182 /** The number of times we've seen rep prefixes we can't handle. */
2183 STAMCOUNTER StatMonitorPfRZRepPrefix;
2184 /** Profiling the REP STOSD cases we've handled. */
2185 STAMPROFILE StatMonitorPfRZRepStosd;
2186
2187 /** Profiling the R0/RC regular access handler. */
2188 STAMPROFILE StatMonitorRZ;
2189 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2190 STAMPROFILE StatMonitorRZFlushPage;
2191 /** Per access size counts indexed by size minus 1, last for larger. */
2192 STAMCOUNTER aStatMonitorRZSizes[16+3];
2193 /** Missaligned access counts indexed by offset - 1. */
2194 STAMCOUNTER aStatMonitorRZMisaligned[7];
2195
2196 /** Nr of handled PT faults. */
2197 STAMCOUNTER StatMonitorRZFaultPT;
2198 /** Nr of handled PD faults. */
2199 STAMCOUNTER StatMonitorRZFaultPD;
2200 /** Nr of handled PDPT faults. */
2201 STAMCOUNTER StatMonitorRZFaultPDPT;
2202 /** Nr of handled PML4 faults. */
2203 STAMCOUNTER StatMonitorRZFaultPML4;
2204
2205 /** Profiling the R3 access handler. */
2206 STAMPROFILE StatMonitorR3;
2207 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2208 STAMPROFILE StatMonitorR3FlushPage;
2209 /** Per access size counts indexed by size minus 1, last for larger. */
2210 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2211 /** Missaligned access counts indexed by offset - 1. */
2212 STAMCOUNTER aStatMonitorR3Misaligned[7];
2213 /** Nr of handled PT faults. */
2214 STAMCOUNTER StatMonitorR3FaultPT;
2215 /** Nr of handled PD faults. */
2216 STAMCOUNTER StatMonitorR3FaultPD;
2217 /** Nr of handled PDPT faults. */
2218 STAMCOUNTER StatMonitorR3FaultPDPT;
2219 /** Nr of handled PML4 faults. */
2220 STAMCOUNTER StatMonitorR3FaultPML4;
2221
2222 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2223 STAMCOUNTER StatResetDirtyPages;
2224 /** Times we've called pgmPoolAddDirtyPage. */
2225 STAMCOUNTER StatDirtyPage;
2226 /** Times we've had to flush duplicates for dirty page management. */
2227 STAMCOUNTER StatDirtyPageDupFlush;
2228 /** Times we've had to flush because of overflow. */
2229 STAMCOUNTER StatDirtyPageOverFlowFlush;
2230
2231 /** The high water mark for cModifiedPages. */
2232 uint16_t cModifiedPagesHigh;
2233 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2234
2235 /** The number of cache hits. */
2236 STAMCOUNTER StatCacheHits;
2237 /** The number of cache misses. */
2238 STAMCOUNTER StatCacheMisses;
2239 /** The number of times we've got a conflict of 'kind' in the cache. */
2240 STAMCOUNTER StatCacheKindMismatches;
2241 /** Number of times we've been out of pages. */
2242 STAMCOUNTER StatCacheFreeUpOne;
2243 /** The number of cacheable allocations. */
2244 STAMCOUNTER StatCacheCacheable;
2245 /** The number of uncacheable allocations. */
2246 STAMCOUNTER StatCacheUncacheable;
2247#else
2248 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2249#endif
2250 /** Profiling PGMR0PoolGrow(). */
2251 STAMPROFILE StatGrow;
2252 /** The AVL tree for looking up a page by its HC physical address. */
2253 AVLOHCPHYSTREE HCPhysTree;
2254 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2255 /** Array of pages. (cMaxPages in length)
2256 * The Id is the index into thist array.
2257 */
2258 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2259} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2260AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2261AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2262AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2263#ifdef VBOX_WITH_STATISTICS
2264AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2265#endif
2266AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2267
2268
2269/** @def PGMPOOL_PAGE_2_PTR
2270 * Maps a pool page pool into the current context.
2271 *
2272 * @returns VBox status code.
2273 * @param a_pVM Pointer to the VM.
2274 * @param a_pPage The pool page.
2275 *
2276 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2277 * small page window employeed by that function. Be careful.
2278 * @remark There is no need to assert on the result.
2279 */
2280#if defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2281# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2282DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2283{
2284 RT_NOREF(pszCaller);
2285 AssertPtr(a_pPage);
2286 AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2287 ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2288 a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2289 return a_pPage->CTX_SUFF(pvPage);
2290}
2291#else
2292# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2293#endif
2294
2295
2296/** @def PGMPOOL_PAGE_2_PTR_V2
2297 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2298 *
2299 * @returns VBox status code.
2300 * @param a_pVM Pointer to the VM.
2301 * @param a_pVCpu The current CPU.
2302 * @param a_pPage The pool page.
2303 *
2304 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2305 * small page window employeed by that function. Be careful.
2306 * @remark There is no need to assert on the result.
2307 */
2308#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2309
2310
2311/** @name Per guest page tracking data.
2312 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2313 * is to use more bits for it and split it up later on. But for now we'll play
2314 * safe and change as little as possible.
2315 *
2316 * The 16-bit word has two parts:
2317 *
2318 * The first 14-bit forms the @a idx field. It is either the index of a page in
2319 * the shadow page pool, or and index into the extent list.
2320 *
2321 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2322 * shadow page pool references to the page. If cRefs equals
2323 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2324 * (misnomer) table and not the shadow page pool.
2325 *
2326 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2327 * the 16-bit word.
2328 *
2329 * @{ */
2330/** The shift count for getting to the cRefs part. */
2331#define PGMPOOL_TD_CREFS_SHIFT 14
2332/** The mask applied after shifting the tracking data down by
2333 * PGMPOOL_TD_CREFS_SHIFT. */
2334#define PGMPOOL_TD_CREFS_MASK 0x3
2335/** The cRefs value used to indicate that the idx is the head of a
2336 * physical cross reference list. */
2337#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2338/** The shift used to get idx. */
2339#define PGMPOOL_TD_IDX_SHIFT 0
2340/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2341#define PGMPOOL_TD_IDX_MASK 0x3fff
2342/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2343 * simply too many mappings of this page. */
2344#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2345
2346/** @def PGMPOOL_TD_MAKE
2347 * Makes a 16-bit tracking data word.
2348 *
2349 * @returns tracking data.
2350 * @param cRefs The @a cRefs field. Must be within bounds!
2351 * @param idx The @a idx field. Must also be within bounds! */
2352#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2353
2354/** @def PGMPOOL_TD_GET_CREFS
2355 * Get the @a cRefs field from a tracking data word.
2356 *
2357 * @returns The @a cRefs field
2358 * @param u16 The tracking data word.
2359 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2360 * non-zero @a u16. */
2361#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2362
2363/** @def PGMPOOL_TD_GET_IDX
2364 * Get the @a idx field from a tracking data word.
2365 *
2366 * @returns The @a idx field
2367 * @param u16 The tracking data word. */
2368#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2369/** @} */
2370
2371
2372
2373/** @name A20 gate macros
2374 * @{ */
2375#define PGM_WITH_A20
2376#ifdef PGM_WITH_A20
2377# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2378# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2379# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2380 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2381# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2382#else
2383# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2384# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2385# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2386# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2387#endif
2388/** @} */
2389
2390
2391/**
2392 * Guest page table walk for the AMD64 mode.
2393 */
2394typedef struct PGMPTWALKGSTAMD64
2395{
2396 PX86PML4 pPml4;
2397 PX86PML4E pPml4e;
2398 X86PML4E Pml4e;
2399
2400 PX86PDPT pPdpt;
2401 PX86PDPE pPdpe;
2402 X86PDPE Pdpe;
2403
2404 PX86PDPAE pPd;
2405 PX86PDEPAE pPde;
2406 X86PDEPAE Pde;
2407
2408 PX86PTPAE pPt;
2409 PX86PTEPAE pPte;
2410 X86PTEPAE Pte;
2411} PGMPTWALKGSTAMD64;
2412/** Pointer to a AMD64 guest page table walk. */
2413typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2414/** Pointer to a const AMD64 guest page table walk. */
2415typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2416
2417/**
2418 * Guest page table walk for the EPT mode.
2419 */
2420typedef struct PGMPTWALKGSTEPT
2421{
2422 PEPTPML4 pPml4;
2423 PEPTPML4E pPml4e;
2424 EPTPML4E Pml4e;
2425
2426 PEPTPDPT pPdpt;
2427 PEPTPDPTE pPdpte;
2428 EPTPDPTE Pdpte;
2429
2430 PEPTPD pPd;
2431 PEPTPDE pPde;
2432 EPTPDE Pde;
2433
2434 PEPTPT pPt;
2435 PEPTPTE pPte;
2436 EPTPTE Pte;
2437} PGMPTWALKGSTEPT;
2438/** Pointer to an EPT guest page table walk. */
2439typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2440/** Pointer to a const EPT guest page table walk. */
2441typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2442
2443/**
2444 * Guest page table walk for the PAE mode.
2445 */
2446typedef struct PGMPTWALKGSTPAE
2447{
2448 PX86PDPT pPdpt;
2449 PX86PDPE pPdpe;
2450 X86PDPE Pdpe;
2451
2452 PX86PDPAE pPd;
2453 PX86PDEPAE pPde;
2454 X86PDEPAE Pde;
2455
2456 PX86PTPAE pPt;
2457 PX86PTEPAE pPte;
2458 X86PTEPAE Pte;
2459} PGMPTWALKGSTPAE;
2460/** Pointer to a PAE guest page table walk. */
2461typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2462/** Pointer to a const AMD64 guest page table walk. */
2463typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2464
2465/**
2466 * Guest page table walk for the 32-bit mode.
2467 */
2468typedef struct PGMPTWALKGST32BIT
2469{
2470 PX86PD pPd;
2471 PX86PDE pPde;
2472 X86PDE Pde;
2473
2474 PX86PT pPt;
2475 PX86PTE pPte;
2476 X86PTE Pte;
2477} PGMPTWALKGST32BIT;
2478/** Pointer to a 32-bit guest page table walk. */
2479typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2480/** Pointer to a const 32-bit guest page table walk. */
2481typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2482
2483/**
2484 * Which part of PGMPTWALKGST that is valid.
2485 */
2486typedef enum PGMPTWALKGSTTYPE
2487{
2488 /** Customary invalid 0 value. */
2489 PGMPTWALKGSTTYPE_INVALID = 0,
2490 /** PGMPTWALKGST::u.Amd64 is valid. */
2491 PGMPTWALKGSTTYPE_AMD64,
2492 /** PGMPTWALKGST::u.Pae is valid. */
2493 PGMPTWALKGSTTYPE_PAE,
2494 /** PGMPTWALKGST::u.Legacy is valid. */
2495 PGMPTWALKGSTTYPE_32BIT,
2496 /** PGMPTWALKGST::u.Ept is valid. */
2497 PGMPTWALKGSTTYPE_EPT,
2498 /** Customary 32-bit type hack. */
2499 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2500} PGMPTWALKGSTTYPE;
2501
2502/**
2503 * Combined guest page table walk result.
2504 */
2505typedef struct PGMPTWALKGST
2506{
2507 union
2508 {
2509 /** The page walker for AMD64. */
2510 PGMPTWALKGSTAMD64 Amd64;
2511 /** The page walker for PAE (32-bit). */
2512 PGMPTWALKGSTPAE Pae;
2513 /** The page walker for 32-bit paging (called legacy due to C naming
2514 * convension). */
2515 PGMPTWALKGST32BIT Legacy;
2516 /** The page walker for EPT (SLAT). */
2517 PGMPTWALKGSTEPT Ept;
2518 } u;
2519 /** Indicates which part of the union is valid. */
2520 PGMPTWALKGSTTYPE enmType;
2521} PGMPTWALKGST;
2522/** Pointer to a combined guest page table walk result. */
2523typedef PGMPTWALKGST *PPGMPTWALKGST;
2524/** Pointer to a read-only combined guest page table walk result. */
2525typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2526
2527
2528/** @name Paging mode macros
2529 * @{
2530 */
2531#ifdef IN_RING3
2532# define PGM_CTX(a,b) a##R3##b
2533# define PGM_CTX_STR(a,b) a "R3" b
2534# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2535#elif defined(IN_RING0)
2536# define PGM_CTX(a,b) a##R0##b
2537# define PGM_CTX_STR(a,b) a "R0" b
2538# define PGM_CTX_DECL(type) VMMDECL(type)
2539#else
2540# error "Not IN_RING3 or IN_RING0!"
2541#endif
2542
2543#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2544#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2545#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2546#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2547#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2548#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2549#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2550#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2551#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2552#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2553#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2554#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2555#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2556#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2557#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2558#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2559
2560#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2561#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2562#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2563#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2564
2565#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2566#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2567#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2568#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2569#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2570#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2571#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2572#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2573#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2574#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2575#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2576#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2577#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2578#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2579#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2580#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2581#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2582#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2583#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2584#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2585#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2586#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2587#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2588#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2589#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2590
2591/* Shw_Gst */
2592#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2593#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2594#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2595#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2596#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2597#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2598#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2599#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2600#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2601#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2602#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2603#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2604#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2605#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2606#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2607#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2608#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2609#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2610#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2611#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2612#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2613#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2614#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2615#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2616#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2617#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2618#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2619#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2620#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2621#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2622#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2623#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2624#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2625#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2626
2627#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2628#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2629#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2630#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2631#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2632#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2633#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2634#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2635#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2636#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2637#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2638#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2639#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2640#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2641#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2642#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2643#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2644#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2645#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2646#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2647#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2648#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2649#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2650#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2651#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2652#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2653#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2654#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2655
2656#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2657#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2658#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2659#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2660#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2661#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2662#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2663#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2664#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2665#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2666#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2667#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2668#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2669#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2670#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2671#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2672#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2673#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2674#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2675#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2676#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2677#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2678#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2679#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2680#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2681#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2682#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2683#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2684#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2685
2686#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2687/** @} */
2688
2689
2690/**
2691 * Function pointers for guest paging.
2692 */
2693typedef struct PGMMODEDATAGST
2694{
2695 /** The guest mode type. */
2696 uint32_t uType;
2697 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2698 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2699 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2700 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2701#ifdef IN_RING3
2702 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2703#endif
2704} PGMMODEDATAGST;
2705
2706/** The length of g_aPgmGuestModeData. */
2707#if VBOX_WITH_64_BITS_GUESTS
2708# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2709#else
2710# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2711#endif
2712/** The guest mode data array. */
2713extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2714
2715
2716/**
2717 * Function pointers for shadow paging.
2718 */
2719typedef struct PGMMODEDATASHW
2720{
2721 /** The shadow mode type. */
2722 uint32_t uType;
2723 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2724 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2725 uint64_t fMask, uint32_t fOpFlags));
2726 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, bool fIs64BitsPagingMode));
2727 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2728#ifdef IN_RING3
2729 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2730#endif
2731} PGMMODEDATASHW;
2732
2733/** The length of g_aPgmShadowModeData. */
2734#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2735/** The shadow mode data array. */
2736extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2737
2738
2739/**
2740 * Function pointers for guest+shadow paging.
2741 */
2742typedef struct PGMMODEDATABTH
2743{
2744 /** The shadow mode type. */
2745 uint32_t uShwType;
2746 /** The guest mode type. */
2747 uint32_t uGstType;
2748
2749 DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2750 DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2751 DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2752 DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2753 DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2754 DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2755 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2756#ifndef IN_RING3
2757 DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2758 DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysNested,
2759 bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
2760 bool *pfLockTaken));
2761#endif
2762#ifdef VBOX_STRICT
2763 DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2764#endif
2765} PGMMODEDATABTH;
2766
2767/** The length of g_aPgmBothModeData. */
2768#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2769/** The guest+shadow mode data array. */
2770extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2771
2772
2773#ifdef VBOX_WITH_STATISTICS
2774/**
2775 * PGM statistics.
2776 */
2777typedef struct PGMSTATS
2778{
2779 /* R3 only: */
2780 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2781 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2782
2783 /* R3+RZ */
2784 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2785 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2786 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2787 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2788 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2789 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2790 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2791 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2792 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2793 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2794 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
2795 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
2796 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
2797 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
2798 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2799 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2800 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2801 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2802 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2803 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2804 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2805 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2806/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2807 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2808 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2809/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2810
2811 /* RC only: */
2812 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2813 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2814
2815 STAMCOUNTER StatRZPhysRead;
2816 STAMCOUNTER StatRZPhysReadBytes;
2817 STAMCOUNTER StatRZPhysWrite;
2818 STAMCOUNTER StatRZPhysWriteBytes;
2819 STAMCOUNTER StatR3PhysRead;
2820 STAMCOUNTER StatR3PhysReadBytes;
2821 STAMCOUNTER StatR3PhysWrite;
2822 STAMCOUNTER StatR3PhysWriteBytes;
2823 STAMCOUNTER StatRCPhysRead;
2824 STAMCOUNTER StatRCPhysReadBytes;
2825 STAMCOUNTER StatRCPhysWrite;
2826 STAMCOUNTER StatRCPhysWriteBytes;
2827
2828 STAMCOUNTER StatRZPhysSimpleRead;
2829 STAMCOUNTER StatRZPhysSimpleReadBytes;
2830 STAMCOUNTER StatRZPhysSimpleWrite;
2831 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2832 STAMCOUNTER StatR3PhysSimpleRead;
2833 STAMCOUNTER StatR3PhysSimpleReadBytes;
2834 STAMCOUNTER StatR3PhysSimpleWrite;
2835 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2836 STAMCOUNTER StatRCPhysSimpleRead;
2837 STAMCOUNTER StatRCPhysSimpleReadBytes;
2838 STAMCOUNTER StatRCPhysSimpleWrite;
2839 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2840
2841 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2842 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2843 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2844 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2845 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2846 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2847 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2848
2849 STAMPROFILE StatLargePageAlloc2; /**< Time spent setting up newly allocated large pages. */
2850 STAMPROFILE StatLargePageSetup; /**< Time spent setting up newly allocated large pages. */
2851 /** pgmPhysIsValidLargePage profiling - R3 */
2852 STAMPROFILE StatR3IsValidLargePage;
2853 /** pgmPhysIsValidLargePage profiling - RZ*/
2854 STAMPROFILE StatRZIsValidLargePage;
2855
2856 STAMPROFILE StatChunkAging;
2857 STAMPROFILE StatChunkFindCandidate;
2858 STAMPROFILE StatChunkUnmap;
2859 STAMPROFILE StatChunkMap;
2860} PGMSTATS;
2861#endif /* VBOX_WITH_STATISTICS */
2862
2863
2864/**
2865 * PGM Data (part of VM)
2866 */
2867typedef struct PGM
2868{
2869 /** The zero page. */
2870 uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2871 /** The MMIO placeholder page. */
2872 uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2873
2874 /** @name The zero page (abPagePg).
2875 * @{ */
2876 /** The host physical address of the zero page. */
2877 RTHCPHYS HCPhysZeroPg;
2878 /** @}*/
2879
2880 /** @name The Invalid MMIO page (abMmioPg).
2881 * This page is filled with 0xfeedface.
2882 * @{ */
2883 /** The host physical address of the invalid MMIO page. */
2884 RTHCPHYS HCPhysMmioPg;
2885 /** The host pysical address of the invalid MMIO page plus all invalid
2886 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
2887 * @remarks Check fLessThan52PhysicalAddressBits before use. */
2888 RTHCPHYS HCPhysInvMmioPg;
2889 /** @} */
2890
2891 /** @cfgm{/RamPreAlloc, boolean, false}
2892 * Indicates whether the base RAM should all be allocated before starting
2893 * the VM (default), or if it should be allocated when first written to.
2894 */
2895 bool fRamPreAlloc;
2896#ifdef VBOX_WITH_PGM_NEM_MODE
2897 /** Set if we're operating in NEM memory mode.
2898 *
2899 * NEM mode implies that memory is allocated in big chunks for each RAM range
2900 * rather than on demand page by page. Memory is also not locked and PGM has
2901 * therefore no physical addresses for them. Page sharing is out of the
2902 * question. Ballooning depends on the native execution engine, but probably
2903 * pointless as well. */
2904 bool fNemMode;
2905# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
2906#else
2907# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
2908#endif
2909 /** Indicates whether write monitoring is currently in use.
2910 * This is used to prevent conflicts between live saving and page sharing
2911 * detection. */
2912 bool fPhysWriteMonitoringEngaged;
2913 /** Set if the CPU has less than 52-bit physical address width.
2914 * This is used */
2915 bool fLessThan52PhysicalAddressBits;
2916 /** Set when nested paging is active.
2917 * This is meant to save calls to HMIsNestedPagingActive and let the
2918 * compilers optimize the code better. Whether we use nested paging or
2919 * not is something we find out during VMM initialization and we won't
2920 * change this later on. */
2921 bool fNestedPaging;
2922 /** We're not in a state which permits writes to guest memory.
2923 * (Only used in strict builds.) */
2924 bool fNoMorePhysWrites;
2925 /** @cfgm{/PageFusionAllowed, boolean, false}
2926 * Whether page fusion is allowed. */
2927 bool fPageFusionAllowed;
2928 /** @cfgm{/PGM/PciPassThrough, boolean, false}
2929 * Whether PCI passthrough is enabled. */
2930 bool fPciPassthrough;
2931 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
2932 uint8_t cMmio2Regions;
2933 /** Restore original ROM page content when resetting after loading state.
2934 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
2935 * enables the VM to start using an updated ROM without requiring powering
2936 * down the VM, just rebooting or resetting it. */
2937 bool fRestoreRomPagesOnReset;
2938 /** Whether to automatically clear all RAM pages on reset. */
2939 bool fZeroRamPagesOnReset;
2940 /** Large page enabled flag. */
2941 bool fUseLargePages;
2942 /** Alignment padding. */
2943#ifndef VBOX_WITH_PGM_NEM_MODE
2944 bool afAlignment3[1];
2945#endif
2946 /** The host paging mode. (This is what SUPLib reports.) */
2947 SUPPAGINGMODE enmHostMode;
2948 bool afAlignment3b[2];
2949
2950 /** Generation ID for the RAM ranges. This member is incremented everytime
2951 * a RAM range is linked or unlinked. */
2952 uint32_t volatile idRamRangesGen;
2953
2954 /** Physical access handler type for ROM protection. */
2955 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
2956 /** Physical access handler type for MMIO2 dirty page tracing. */
2957 PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
2958
2959 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2960 RTGCPHYS GCPhys4MBPSEMask;
2961 /** Mask containing the invalid bits of a guest physical address.
2962 * @remarks this does not stop at bit 52. */
2963 RTGCPHYS GCPhysInvAddrMask;
2964
2965
2966 /** RAM range TLB for R3. */
2967 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
2968 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2969 * This is sorted by physical address and contains no overlapping ranges. */
2970 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
2971 /** Root of the RAM range search tree for ring-3. */
2972 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
2973 /** Shadow Page Pool - R3 Ptr. */
2974 R3PTRTYPE(PPGMPOOL) pPoolR3;
2975 /** Pointer to the list of ROM ranges - for R3.
2976 * This is sorted by physical address and contains no overlapping ranges. */
2977 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2978 /** Pointer to the list of MMIO2 ranges - for R3.
2979 * Registration order. */
2980 R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
2981 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
2982 R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
2983
2984 /** RAM range TLB for R0. */
2985 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
2986 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
2987 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
2988 /** Root of the RAM range search tree for ring-0. */
2989 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
2990 /** Shadow Page Pool - R0 Ptr. */
2991 R0PTRTYPE(PPGMPOOL) pPoolR0;
2992 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2993 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2994 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
2995 R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
2996
2997 /** Hack: Number of deprecated page mapping locks taken by the current lock
2998 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
2999 uint32_t cDeprecatedPageLocks;
3000
3001 /** Registered physical access handler types. */
3002 uint32_t cPhysHandlerTypes;
3003 /** Physical access handler types.
3004 * Initialized to callback causing guru meditations and invalid enmKind. */
3005 PGMPHYSHANDLERTYPEINTR3 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3006 /** Physical handler allocator, ring-3 edition. */
3007#ifdef IN_RING3
3008 PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3009#else
3010 RTCHardAvlTreeSlabAllocatorR3_T PhysHandlerAllocator;
3011#endif
3012 /** The pointer to the ring-3 mapping of the physical access handler tree. */
3013 R3PTRTYPE(PPGMPHYSHANDLERTREE) pPhysHandlerTree;
3014 /** Caching the last physical handler we looked. */
3015 uint32_t idxLastPhysHandler;
3016
3017 uint32_t au64Padding3[5];
3018
3019 /** PGM critical section.
3020 * This protects the physical, ram ranges, and the page flag updating (some of
3021 * it anyway).
3022 */
3023 PDMCRITSECT CritSectX;
3024
3025 /**
3026 * Data associated with managing the ring-3 mappings of the allocation chunks.
3027 */
3028 struct
3029 {
3030 /** The chunk mapping TLB. */
3031 PGMCHUNKR3MAPTLB Tlb;
3032 /** The chunk tree, ordered by chunk id. */
3033 R3PTRTYPE(PAVLU32NODECORE) pTree;
3034#if HC_ARCH_BITS == 32
3035 uint32_t u32Alignment0;
3036#endif
3037 /** The number of mapped chunks. */
3038 uint32_t c;
3039 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3040 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3041 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3042 uint32_t cMax;
3043 /** The current time. This is incremented whenever a chunk is inserted. */
3044 uint32_t iNow;
3045 /** Alignment padding. */
3046 uint32_t au32Alignment1[3];
3047 } ChunkR3Map;
3048
3049 /** The page mapping TLB for ring-3. */
3050 PGMPAGER3MAPTLB PhysTlbR3;
3051 /** The page mapping TLB for ring-0. */
3052 PGMPAGER0MAPTLB PhysTlbR0;
3053
3054 /** The number of handy pages. */
3055 uint32_t cHandyPages;
3056
3057 /** The number of large handy pages. */
3058 uint32_t cLargeHandyPages;
3059
3060 /**
3061 * Array of handy pages.
3062 *
3063 * This array is used in a two way communication between pgmPhysAllocPage
3064 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3065 * an intermediary.
3066 *
3067 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3068 * (The current size of 32 pages, means 128 KB of handy memory.)
3069 */
3070 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3071
3072 /**
3073 * Array of large handy pages. (currently size 1)
3074 *
3075 * This array is used in a two way communication between pgmPhysAllocLargePage
3076 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3077 * an intermediary.
3078 */
3079 GMMPAGEDESC aLargeHandyPage[1];
3080 /** When to try allocate large pages again after a failure. */
3081 uint64_t nsLargePageRetry;
3082 /** Number of repeated long allocation times. */
3083 uint32_t cLargePageLongAllocRepeats;
3084 uint32_t uPadding5;
3085
3086 /**
3087 * Live save data.
3088 */
3089 struct
3090 {
3091 /** Per type statistics. */
3092 struct
3093 {
3094 /** The number of ready pages. */
3095 uint32_t cReadyPages;
3096 /** The number of dirty pages. */
3097 uint32_t cDirtyPages;
3098 /** The number of ready zero pages. */
3099 uint32_t cZeroPages;
3100 /** The number of write monitored pages. */
3101 uint32_t cMonitoredPages;
3102 } Rom,
3103 Mmio2,
3104 Ram;
3105 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3106 uint32_t cIgnoredPages;
3107 /** Indicates that a live save operation is active. */
3108 bool fActive;
3109 /** Padding. */
3110 bool afReserved[2];
3111 /** The next history index. */
3112 uint8_t iDirtyPagesHistory;
3113 /** History of the total amount of dirty pages. */
3114 uint32_t acDirtyPagesHistory[64];
3115 /** Short term dirty page average. */
3116 uint32_t cDirtyPagesShort;
3117 /** Long term dirty page average. */
3118 uint32_t cDirtyPagesLong;
3119 /** The number of saved pages. This is used to get some kind of estimate of the
3120 * link speed so we can decide when we're done. It is reset after the first
3121 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3122 * zero pages. */
3123 uint64_t cSavedPages;
3124 /** The nanosecond timestamp when cSavedPages was 0. */
3125 uint64_t uSaveStartNS;
3126 /** Pages per second (for statistics). */
3127 uint32_t cPagesPerSecond;
3128 uint32_t cAlignment;
3129 } LiveSave;
3130
3131 /** @name Error injection.
3132 * @{ */
3133 /** Inject handy page allocation errors pretending we're completely out of
3134 * memory. */
3135 bool volatile fErrInjHandyPages;
3136 /** Padding. */
3137 bool afReserved[3];
3138 /** @} */
3139
3140 /** @name Release Statistics
3141 * @{ */
3142 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3143 uint32_t cPrivatePages; /**< The number of private pages. */
3144 uint32_t cSharedPages; /**< The number of shared pages. */
3145 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3146 uint32_t cZeroPages; /**< The number of zero backed pages. */
3147 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3148 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3149 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3150 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3151 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3152 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3153 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3154 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3155 uint32_t cLargePages; /**< The number of large pages. */
3156 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3157/* uint32_t aAlignment4[1]; */
3158
3159 STAMPROFILE StatLargePageAlloc; /**< Time spent by the host OS for large page allocation. */
3160 STAMCOUNTER StatLargePageAllocFailed; /**< Count allocation failures. */
3161 STAMCOUNTER StatLargePageOverflow; /**< The number of times allocating a large pages takes more than the allowed period. */
3162 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3163 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3164 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3165 STAMCOUNTER StatLargePageTlbFlush; /**< The number of a full VCPU TLB flush was required after allocation. */
3166 STAMCOUNTER StatLargePageZeroEvict; /**< The number of zero page mappings we had to evict when allocating a large page. */
3167
3168 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3169
3170 STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /**< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. */
3171 /** @} */
3172
3173#ifdef VBOX_WITH_STATISTICS
3174 /** These are optional statistics that used to be on the hyper heap. */
3175 PGMSTATS Stats;
3176#endif
3177} PGM;
3178#ifndef IN_TSTVMSTRUCTGC /* HACK */
3179AssertCompileMemberAlignment(PGM, CritSectX, 8);
3180AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3181AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3182AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3183AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3184AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3185#endif /* !IN_TSTVMSTRUCTGC */
3186/** Pointer to the PGM instance data. */
3187typedef PGM *PPGM;
3188
3189
3190#ifdef VBOX_WITH_STATISTICS
3191/**
3192 * Per CPU statistis for PGM (used to be on the heap).
3193 */
3194typedef struct PGMCPUSTATS
3195{
3196 /* Common */
3197 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3198 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3199
3200 /* R0 only: */
3201 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3202 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3203
3204 /* RZ only: */
3205 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3206 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3207 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3208 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3209 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3210 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3211 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3212 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3213 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3214 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3215 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3216 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3217 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3218 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3219 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3220 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3221 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3222 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3223 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3224 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3225 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3226 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3227 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3228 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3229 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3230 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3231 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3232 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3233 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3234 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3235 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3236 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3237 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3238 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3239 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3240 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3241 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3242 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3243 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3244 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3245 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3246 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3247 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3248 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3249 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3250 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3251 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3252 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3253 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3254 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3255 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3256 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3257 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3258 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3259 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3260 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3261 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3262 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3263 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3264 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3265 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3266 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3267 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3268 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3269 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3270 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3271 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3272 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3273 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3274 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3275
3276 /* HC - R3 and (maybe) R0: */
3277
3278 /* RZ & R3: */
3279 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3280 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3281 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3282 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3283 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3284 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3285 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3286 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3287 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3288 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3289 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3290 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3291 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3292 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3293 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3294 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3295 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3296 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3297 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3298 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3299 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3300 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3301 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3302 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3303 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3304 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3305 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3306 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3307 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3308 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3309 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3310 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3311 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3312 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3313 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3314 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3315 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3316 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3317 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3318 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3319 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3320 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3321 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3322 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3323 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3324 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3325 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3326
3327 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3328 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3329 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3330 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3331 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3332 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3333 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3334 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3335 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3336 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3337 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3338 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3339 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3340 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3341 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3342 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3343 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3344 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3345 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3346 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3347 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3348 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3349 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3350 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3351 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3352 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3353 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3354 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3355 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3356 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3357 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3358 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3359 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3360 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3361 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3362 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3363 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3364 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3365 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3366 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3367 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3368 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3369 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3370 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3371 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3372 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3373} PGMCPUSTATS;
3374#endif /* VBOX_WITH_STATISTICS */
3375
3376
3377/**
3378 * PGMCPU Data (part of VMCPU).
3379 */
3380typedef struct PGMCPU
3381{
3382 /** A20 gate mask.
3383 * Our current approach to A20 emulation is to let REM do it and don't bother
3384 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3385 * But whould need arrise, we'll subject physical addresses to this mask. */
3386 RTGCPHYS GCPhysA20Mask;
3387 /** A20 gate state - boolean! */
3388 bool fA20Enabled;
3389 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3390 bool fNoExecuteEnabled;
3391 /** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3392 * active. */
3393 bool fPaePdpesAndCr3MappedR3;
3394 bool fPaePdpesAndCr3MappedR0;
3395
3396 /** What needs syncing (PGM_SYNC_*).
3397 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3398 * PGMFlushTLB, and PGMR3Load. */
3399 uint32_t fSyncFlags;
3400
3401 /** The shadow paging mode. */
3402 PGMMODE enmShadowMode;
3403 /** The guest paging mode. */
3404 PGMMODE enmGuestMode;
3405 /** The guest second level address translation mode. */
3406 PGMSLAT enmGuestSlatMode;
3407 /** Guest mode data table index (PGM_TYPE_XXX). */
3408 uint8_t volatile idxGuestModeData;
3409 /** Shadow mode data table index (PGM_TYPE_XXX). */
3410 uint8_t volatile idxShadowModeData;
3411 /** Both mode data table index (complicated). */
3412 uint8_t volatile idxBothModeData;
3413 /** Alignment padding. */
3414 uint8_t abPadding[1];
3415
3416 /** The guest CR3.
3417 * When SLAT is active, this is the translated physical address.
3418 * When SLAT is inactive, this is the physical address in CR3. */
3419 RTGCPHYS GCPhysCR3;
3420
3421 /** The nested-guest CR3.
3422 * When SLAT is active, this is CR3 prior to translation.
3423 * When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3424 RTGCPHYS GCPhysNstGstCR3;
3425
3426 /** The cached guest CR3 when it has been mapped in PAE mode.
3427 * This allows us to skip remapping the CR3 and PAE PDPEs
3428 * (in PGMFlushTLB or similar) when it was already done as
3429 * part of MOV CRx instruction emulation.
3430 */
3431 RTGCPHYS GCPhysPaeCR3;
3432
3433 /** @name 32-bit Guest Paging.
3434 * @{ */
3435 /** The guest's page directory, R3 pointer. */
3436 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3437 /** The guest's page directory, R0 pointer. */
3438 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3439 /** Mask containing the MBZ bits of a big page PDE. */
3440 uint32_t fGst32BitMbzBigPdeMask;
3441 /** Set if the page size extension (PSE) is enabled. */
3442 bool fGst32BitPageSizeExtension;
3443 /** Alignment padding. */
3444 bool afAlignment2[3];
3445 /** @} */
3446
3447 /** @name PAE Guest Paging.
3448 * @{ */
3449 /** The guest's page directory pointer table, R3 pointer. */
3450 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3451 /** The guest's page directory pointer table, R0 pointer. */
3452 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3453
3454 /** The guest's page directories, R3 pointers.
3455 * These are individual pointers and don't have to be adjacent.
3456 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3457 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3458 /** The guest's page directories, R0 pointers.
3459 * Same restrictions as apGstPaePDsR3. */
3460 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3461 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3462 RTGCPHYS aGCPhysGstPaePDs[4];
3463 /** The physical addresses of the monitored guest page directories (PAE). */
3464 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3465 /** Mask containing the MBZ PTE bits. */
3466 uint64_t fGstPaeMbzPteMask;
3467 /** Mask containing the MBZ PDE bits. */
3468 uint64_t fGstPaeMbzPdeMask;
3469 /** Mask containing the MBZ big page PDE bits. */
3470 uint64_t fGstPaeMbzBigPdeMask;
3471 /** Mask containing the MBZ PDPE bits. */
3472 uint64_t fGstPaeMbzPdpeMask;
3473 /** @} */
3474
3475 /** @name AMD64 Guest Paging.
3476 * @{ */
3477 /** The guest's page directory pointer table, R3 pointer. */
3478 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3479 /** The guest's page directory pointer table, R0 pointer. */
3480 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3481 /** Mask containing the MBZ PTE bits. */
3482 uint64_t fGstAmd64MbzPteMask;
3483 /** Mask containing the MBZ PDE bits. */
3484 uint64_t fGstAmd64MbzPdeMask;
3485 /** Mask containing the MBZ big page PDE bits. */
3486 uint64_t fGstAmd64MbzBigPdeMask;
3487 /** Mask containing the MBZ PDPE bits. */
3488 uint64_t fGstAmd64MbzPdpeMask;
3489 /** Mask containing the MBZ big page PDPE bits. */
3490 uint64_t fGstAmd64MbzBigPdpeMask;
3491 /** Mask containing the MBZ PML4E bits. */
3492 uint64_t fGstAmd64MbzPml4eMask;
3493 /** Mask containing the PDPE bits that we shadow. */
3494 uint64_t fGstAmd64ShadowedPdpeMask;
3495 /** Mask containing the PML4E bits that we shadow. */
3496 uint64_t fGstAmd64ShadowedPml4eMask;
3497 /** @} */
3498
3499 /** @name PAE and AMD64 Guest Paging.
3500 * @{ */
3501 /** Mask containing the PTE bits that we shadow. */
3502 uint64_t fGst64ShadowedPteMask;
3503 /** Mask containing the PDE bits that we shadow. */
3504 uint64_t fGst64ShadowedPdeMask;
3505 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3506 uint64_t fGst64ShadowedBigPdeMask;
3507 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3508 uint64_t fGst64ShadowedBigPde4PteMask;
3509 /** @} */
3510
3511 /** @name EPT Guest Paging.
3512 * @{ */
3513 /** The guest's EPT PML4 table, R3 pointer. */
3514 R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3515 /** The guest's EPT PML4 table, R0 pointer. */
3516 R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3517 /** The guest's EPT pointer (copy of virtual VMCS). */
3518 uint64_t uEptPtr;
3519 /** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3520 * change through the lifetime of the VM. */
3521 uint64_t uEptVpidCapMsr;
3522 /** Mask containing the MBZ PTE bits. */
3523 uint64_t fGstEptMbzPteMask;
3524 /** Mask containing the MBZ PDE bits. */
3525 uint64_t fGstEptMbzPdeMask;
3526 /** Mask containing the MBZ big page (2M) PDE bits. */
3527 uint64_t fGstEptMbzBigPdeMask;
3528 /** Mask containing the MBZ PDPTE bits. */
3529 uint64_t fGstEptMbzPdpteMask;
3530 /** Mask containing the MBZ big page (1G) PDPTE bits. */
3531 uint64_t fGstEptMbzBigPdpteMask;
3532 /** Mask containing the MBZ PML4E bits. */
3533 uint64_t fGstEptMbzPml4eMask;
3534 /** Mask to determine whether an entry is present. */
3535 uint64_t fGstEptPresentMask;
3536
3537 /** Mask containing the EPT PTE bits we shadow. */
3538 uint64_t fGstEptShadowedPteMask;
3539 /** Mask containing the EPT PDE bits we shadow. */
3540 uint64_t fGstEptShadowedPdeMask;
3541 /** Mask containing the EPT PDPTE bits we shadow. */
3542 uint64_t fGstEptShadowedPdpteMask;
3543 /** Mask containing the EPT PML4E bits we shadow. */
3544 uint64_t fGstEptShadowedPml4eMask;
3545 /** @} */
3546
3547 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3548 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3549 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3550 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3551
3552 /** For saving stack space, the disassembler state is allocated here instead of
3553 * on the stack. */
3554 DISCPUSTATE DisState;
3555
3556 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
3557 uint64_t cNetwareWp0Hacks;
3558
3559 /** Count the number of pgm pool access handler calls. */
3560 uint64_t cPoolAccessHandler;
3561
3562 /** @name Release Statistics
3563 * @{ */
3564 /** The number of times the guest has switched mode since last reset or statistics reset. */
3565 STAMCOUNTER cGuestModeChanges;
3566 /** The number of times the guest has switched mode since last reset or statistics reset. */
3567 STAMCOUNTER cA20Changes;
3568 /** @} */
3569
3570#ifdef VBOX_WITH_STATISTICS
3571 /** These are statistics that used to be on the hyper heap. */
3572 PGMCPUSTATS Stats;
3573#endif
3574} PGMCPU;
3575/** Pointer to the per-cpu PGM data. */
3576typedef PGMCPU *PPGMCPU;
3577
3578
3579/** @name PGM::fSyncFlags Flags
3580 * @note Was part of saved state a long time ago.
3581 * @{
3582 */
3583/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3584/** Always sync CR3. */
3585#define PGM_SYNC_ALWAYS RT_BIT(1)
3586/** Check guest mapping in SyncCR3. */
3587#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3588/** Clear the page pool (a light weight flush). */
3589#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3590#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3591/** @} */
3592
3593
3594#if defined(IN_RING0) || defined(DOXYGEN_RUNNING)
3595
3596/**
3597 * PGM GVMCPU instance data.
3598 */
3599typedef struct PGMR0PERVCPU
3600{
3601# ifdef VBOX_WITH_STATISTICS
3602 /** R0: Which statistic this \#PF should be attributed to. */
3603 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3604# endif
3605 uint64_t u64Dummy;
3606} PGMR0PERVCPU;
3607
3608
3609/**
3610 * PGM GVM instance data.
3611 */
3612typedef struct PGMR0PERVM
3613{
3614 /** @name PGM Pool related stuff.
3615 * @{ */
3616 /** Critical section for serializing pool growth. */
3617 RTCRITSECT PoolGrowCritSect;
3618 /** The memory objects for the pool pages. */
3619 RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3620 /** The ring-3 mapping objects for the pool pages. */
3621 RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3622 /** @} */
3623
3624 /** Physical access handler types for ring-0.
3625 * Initialized to callback causing return to ring-3 and invalid enmKind. */
3626 PGMPHYSHANDLERTYPEINTR0 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3627 /** Physical handler allocator, ring-3 edition. */
3628 PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3629 /** The pointer to the ring-3 mapping of the physical access handler tree. */
3630 PPGMPHYSHANDLERTREE pPhysHandlerTree;
3631 /** The allocation object for the physical access handler tree. */
3632 RTR0MEMOBJ hPhysHandlerMemObj;
3633 /** The ring-3 mapping object for the physicall access handler tree. */
3634 RTR0MEMOBJ hPhysHandlerMapObj;
3635} PGMR0PERVM;
3636
3637#endif /* IN_RING0 || DOXYGEN_RUNNING */
3638
3639RT_C_DECLS_BEGIN
3640
3641#if defined(VBOX_STRICT)
3642int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3643# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3644# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3645#else
3646int pgmLock(PVMCC pVM, bool fVoid);
3647# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3648# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3649#endif
3650void pgmUnlock(PVMCC pVM);
3651# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3652/**
3653 * Asserts that the caller owns the PDM lock.
3654 * This is the internal variant of PGMIsLockOwner.
3655 * @param a_pVM Pointer to the VM.
3656 */
3657#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3658/**
3659 * Asserts that the caller owns the PDM lock.
3660 * This is the internal variant of PGMIsLockOwner.
3661 * @param a_pVM Pointer to the VM.
3662 * @param a_pVCpu The current CPU handle.
3663 */
3664#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3665
3666uint32_t pgmHandlerPhysicalCalcTableSizes(uint32_t *pcEntries, uint32_t *pcbTreeAndBitmap);
3667int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3668 R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
3669int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3670int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3671int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3672int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3673void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3674bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3675void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam, bool fDoAccounting);
3676DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3677DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3678DECLCALLBACK(FNPGMPHYSHANDLER) pgmR3HandlerPhysicalHandlerInvalid;
3679#ifndef IN_RING3
3680DECLCALLBACK(FNPGMPHYSHANDLER) pgmR0HandlerPhysicalHandlerToRing3;
3681DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmR0HandlerPhysicalPfHandlerToRing3;
3682#endif
3683
3684int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3685
3686int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3687int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3688#ifdef IN_RING0
3689int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
3690int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3691#endif
3692int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3693int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3694int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3695void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3696int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3697int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3698int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3699int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3700int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3701int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3702int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3703int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3704int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3705int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3706void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3707DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3708DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3709#ifndef IN_RING3
3710DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3711DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3712#endif
3713int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3714 PGMPAGETYPE enmNewType);
3715void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3716void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3717void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3718PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3719PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3720PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3721int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3722int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3723#ifdef VBOX_WITH_NATIVE_NEM
3724void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3725#endif
3726
3727#ifdef IN_RING3
3728void pgmR3PhysRelinkRamRanges(PVM pVM);
3729int pgmR3PhysRamPreAllocate(PVM pVM);
3730int pgmR3PhysRamReset(PVM pVM);
3731int pgmR3PhysRomReset(PVM pVM);
3732int pgmR3PhysRamZeroAll(PVM pVM);
3733int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3734int pgmR3PhysRamTerm(PVM pVM);
3735void pgmR3PhysRomTerm(PVM pVM);
3736void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3737
3738int pgmR3PoolInit(PVM pVM);
3739void pgmR3PoolRelocate(PVM pVM);
3740void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3741void pgmR3PoolReset(PVM pVM);
3742void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3743DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3744void pgmR3PoolWriteProtectPages(PVM pVM);
3745
3746#endif /* IN_RING3 */
3747#ifdef IN_RING0
3748int pgmR0PoolInitVM(PGVM pGVM);
3749#endif
3750int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3751 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3752void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3753void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3754int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3755void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3756PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3757PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3758int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3759int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3760bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3761void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3762int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3763void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3764uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3765void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3766void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3767void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3768FNPGMPHYSHANDLER pgmPoolAccessHandler;
3769#ifndef IN_RING3
3770FNPGMRZPHYSPFHANDLER pgmRZPoolAccessPfHandler;
3771#endif
3772
3773void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3774void pgmPoolResetDirtyPages(PVMCC pVM);
3775void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3776
3777/** Gets the ring-0 pointer for the given pool page. */
3778DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3779{
3780#ifdef IN_RING3
3781 size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3782# ifdef VBOX_STRICT
3783 size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3784 AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
3785 AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
3786# endif
3787 return pPool->pPoolR0 + offPage;
3788#else
3789 RT_NOREF(pPool);
3790 return pPage;
3791#endif
3792}
3793
3794/** Gets the ring-3 pointer for the given pool page. */
3795DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3796{
3797#ifdef IN_RING3
3798 RT_NOREF(pPool);
3799 return pPage;
3800#else
3801 size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3802# ifdef VBOX_STRICT
3803 size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3804 AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
3805 AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
3806# endif
3807 return pPool->pPoolR3 + offPage;
3808#endif
3809}
3810
3811int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3812int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3813void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3814
3815int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3816int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3817int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3818
3819int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3820int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3821int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3822int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3823#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3824int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3825#endif
3826int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3827int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3828
3829# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3830FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3831FNDBGCCMD pgmR3CmdShowSharedModules;
3832# endif
3833
3834void pgmLogState(PVM pVM);
3835
3836RT_C_DECLS_END
3837
3838/** @} */
3839
3840#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3841
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