PGMInternal.h@ 108843

Last change on this file since 108843 was 108843, checked in by vboxsync, 5 weeks ago
VMM/PGM,NEM: Some early page table management infrastructure for ARMv8, bugref:10388
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1	/* $Id: PGMInternal.h 108843 2025-04-04 08:36:32Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
29	#define VMM_INCLUDED_SRC_include_PGMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/cdefs.h>
35	#include <VBox/types.h>
36	#include <VBox/err.h>
37	#include <VBox/dbg.h>
38	#include <VBox/vmm/stam.h>
39	#include <VBox/param.h>
40	#include <VBox/vmm/vmm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmapi.h>
44	#include <VBox/dis.h>
45	#include <VBox/vmm/dbgf.h>
46	#include <VBox/log.h>
47	#include <VBox/vmm/gmm.h>
48	#include <VBox/vmm/hm.h>
49	#include <iprt/asm.h>
50	#include <iprt/assert.h>
51	#include <iprt/avl.h>
52	#include <iprt/critsect.h>
53	#include <iprt/list-off32.h>
54	#include <iprt/sha.h>
55	#include <iprt/cpp/hardavlrange.h>
56
57
58
59	/** @defgroup grp_pgm_int Internals
60	* @ingroup grp_pgm
61	* @internal
62	* @{
63	*/
64
65
66	/** @name PGM Compile Time Config
67	* @{
68	*/
69
70	/**
71	* Check and skip global PDEs for non-global flushes
72	*/
73	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
74
75	/**
76	* Optimization for PAE page tables that are modified often
77	*/
78	#if !defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITH_ONLY_PGM_NEM_MODE)
79	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
80	#endif
81
82	/**
83	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
84	*/
85	#define PGM_WITH_LARGE_PAGES
86
87	/**
88	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
89	* VMX_EXIT_EPT_MISCONFIG.
90	*/
91	#define PGM_WITH_MMIO_OPTIMIZATIONS
92
93	/**
94	* Sync N pages instead of a whole page table
95	*/
96	#define PGM_SYNC_N_PAGES
97
98	/**
99	* Number of pages to sync during a page fault
100	*
101	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
102	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
103	*
104	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
105	* world switch overhead, so let's sync more.
106	*/
107	#ifdef IN_RING0
108	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
109	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
110	* but ~5% fewer faults.
111	*/
112	# define PGM_SYNC_NR_PAGES 32
113	#else
114	# define PGM_SYNC_NR_PAGES 8
115	#endif
116
117	/** Maximum number of RAM ranges.
118	* @note This can be increased to 4096 (at least when targeting x86). */
119	#define PGM_MAX_RAM_RANGES 3072
120
121	/** Maximum pages per RAM range.
122	*
123	* The PGMRAMRANGE structures for the high memory can get very big. There
124	* used to be some limitations on SUPR3PageAllocEx allocation sizes, so
125	* traditionally we limited this to 16MB chunks. These days we do ~64 MB
126	* chunks each covering 16GB of guest RAM, making sure each range is a
127	* multiple of 1GB to enable eager hosts to use 1GB pages for NEM mode.
128	*
129	* See also pgmPhysMmio2CalcChunkCount.
130	*/
131	#define PGM_MAX_PAGES_PER_RAM_RANGE _4M
132	#if defined(X86_PD_PAE_SHIFT) && defined(AssertCompile)
133	AssertCompile(RT_ALIGN_32(PGM_MAX_PAGES_PER_RAM_RANGE, X86_PD_PAE_SHIFT - X86_PAGE_SHIFT)); /* NEM large page requirement: 1GB pages. */
134	#endif
135
136	/** The maximum number of MMIO2 ranges. */
137	#define PGM_MAX_MMIO2_RANGES 32
138	/** The maximum number of pages in a MMIO2 PCI region.
139	*
140	* The memory for a MMIO2 PCI region is a single chunk of host virtual memory,
141	* but may be handled internally by PGM as a set of multiple MMIO2/RAM ranges,
142	* since PGM_MAX_PAGES_PER_RAM_RANGE is currently lower than this value (4 GiB
143	* vs 16 GiB).
144	*/
145	#define PGM_MAX_PAGES_PER_MMIO2_REGION _16M
146
147	/** Maximum number of ROM ranges. */
148	#define PGM_MAX_ROM_RANGES 16
149	/** The maximum pages per ROM range.
150	* Currently 512K pages, or 2GB with 4K pages. */
151	#define PGM_MAX_PAGES_PER_ROM_RANGE _512K
152	AssertCompile(PGM_MAX_PAGES_PER_ROM_RANGE <= PGM_MAX_PAGES_PER_RAM_RANGE);
153
154	/**
155	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
156	*/
157	#define PGM_MAX_PHYSCACHE_ENTRIES 64
158	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
159
160
161	/** @def PGMPOOL_CFG_MAX_GROW
162	* The maximum number of pages to add to the pool in one go.
163	*/
164	#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
165
166	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
167	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
168	*/
169	#ifdef VBOX_STRICT
170	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
171	#endif
172
173	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
174	* Enables the experimental lazy page allocation code.
175	* @todo Problems with zero page tracking, see \@bugref{10509}. */
176	#if defined(DOXYGEN_RUNNING)
177	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
178	#endif
179
180	/** @def PGM_WITH_PAGE_ZEROING_DETECTION
181	* Enables the code for detecting guest zeroing page in the ZERO state and
182	* tries to avoid allocating them in response.
183	* This kind of relies upon VBOX_WITH_NEW_LAZY_PAGE_ALLOC to work atm. */
184	#if defined(DOXYGEN_RUNNING)
185	# define PGM_WITH_PAGE_ZEROING_DETECTION
186	#endif
187
188	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
189	* Enables real write monitoring of pages, i.e. mapping them read-only and
190	* only making them writable when getting a write access \#PF. */
191	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
192
193	/** @def VBOX_WITH_PGM_NEM_MODE
194	* Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
195	* details. */
196	#ifdef DOXYGEN_RUNNING
197	# define VBOX_WITH_PGM_NEM_MODE
198	#endif
199
200	/** @} */
201
202	#if defined(VBOX_WITH_PAGE_SHARING) && defined(VBOX_WITH_ONLY_PGM_NEM_MODE)
203	# error "Misconfig! VBOX_WITH_ONLY_PGM_NEM_MODE implies no VBOX_WITH_PAGE_SHARING. Fix VBox/param.h."
204	#endif
205
206	/** @name PDPT and PML4 flags.
207	* These are placed in the three bits available for system programs in
208	* the PDPT and PML4 entries.
209	* @{ */
210	/** The entry is a permanent one and it's must always be present.
211	* Never free such an entry. */
212	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
213	/** PGM specific bits in PML4 entries. */
214	#define PGM_PML4_FLAGS 0
215	/** PGM specific bits in PDPT entries. */
216	#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
217	/** @} */
218
219	/** @name Page directory flags.
220	* These are placed in the three bits available for system programs in
221	* the page directory entries.
222	* @{ */
223	/** Indicates the original entry was a big page.
224	* @remarks This is currently only used for statistics and can be recycled. */
225	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
226	/** Made read-only to facilitate dirty bit tracking. */
227	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
228	/** @} */
229
230	/** @name Page flags.
231	* These are placed in the three bits available for system programs in
232	* the page entries.
233	* @{ */
234	/** Made read-only to facilitate dirty bit tracking. */
235	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
236	/** @} */
237
238	#if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
239	/** @name Defines used to indicate the shadow and guest paging in the templates.
240	* @{ */
241	# define PGM_TYPE_REAL 1
242	# define PGM_TYPE_PROT 2
243	# define PGM_TYPE_32BIT 3
244	# define PGM_TYPE_PAE 4
245	# define PGM_TYPE_AMD64 5
246	# define PGM_TYPE_NESTED_32BIT 6
247	# define PGM_TYPE_NESTED_PAE 7
248	# define PGM_TYPE_NESTED_AMD64 8
249	# define PGM_TYPE_EPT 9
250	# define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
251	# define PGM_TYPE_END (PGM_TYPE_NONE + 1)
252	# define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
253	/** @} */
254
255	/** @name Defines used to indicate the second-level
256	* address translation (SLAT) modes in the templates.
257	* @{ */
258	# define PGM_SLAT_TYPE_DIRECT (PGM_TYPE_END + 1)
259	# define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 2)
260	# define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 3)
261	# define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 4)
262	# define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 5)
263	/** @} */
264
265	/** Macro for checking if the guest is using paging.
266	* @param uGstType PGM_TYPE_*
267	* @param uShwType PGM_TYPE_*
268	* @remark ASSUMES certain order of the PGM_TYPE_* values.
269	*/
270	# define PGM_WITH_PAGING(uGstType, uShwType) \
271	( (uGstType) >= PGM_TYPE_32BIT \
272	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
273
274	/** Macro for checking if the guest supports the NX bit.
275	* @param uGstType PGM_TYPE_*
276	* @param uShwType PGM_TYPE_*
277	* @remark ASSUMES certain order of the PGM_TYPE_* values.
278	*/
279	# define PGM_WITH_NX(uGstType, uShwType) \
280	( (uGstType) >= PGM_TYPE_PAE \
281	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
282
283	/** Macro for checking for nested.
284	* @param uType PGM_TYPE_*
285	*/
286	# define PGM_TYPE_IS_NESTED(uType) \
287	( (uType) == PGM_TYPE_NESTED_32BIT \
288	\|\| (uType) == PGM_TYPE_NESTED_PAE \
289	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
290
291	/** Macro for checking for nested or EPT.
292	* @param uType PGM_TYPE_*
293	*/
294	# define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
295	( (uType) == PGM_TYPE_NESTED_32BIT \
296	\|\| (uType) == PGM_TYPE_NESTED_PAE \
297	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
298	\|\| (uType) == PGM_TYPE_EPT)
299
300	#elif defined(VBOX_VMM_TARGET_ARMV8)
301	/** @name Defines used to indicate the guest paging in the templates.
302	* @{ */
303	/** MMU disabled. */
304	# define PGM_TYPE_NONE 1
305	/** @} */
306
307	#else
308	# error "Port me"
309	#endif
310
311
312	/** @def PGM_HCPHYS_2_PTR
313	* Maps a HC physical page pool address to a virtual address.
314	*
315	* @returns VBox status code.
316	* @param pVM The cross context VM structure.
317	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
318	* @param HCPhys The HC physical address to map to a virtual one.
319	* @param ppv Where to store the virtual address. No need to cast
320	* this.
321	*
322	* @remark There is no need to assert on the result.
323	*/
324	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
325
326	/** @def PGM_GCPHYS_2_PTR_V2
327	* Maps a GC physical page address to a virtual address.
328	*
329	* @returns VBox status code.
330	* @param pVM The cross context VM structure.
331	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
332	* @param GCPhys The GC physical address to map to a virtual one.
333	* @param ppv Where to store the virtual address. No need to cast this.
334	*
335	* @remark Use with care as we don't have so much dynamic mapping space in
336	* ring-0 on 32-bit darwin and in RC.
337	* @remark There is no need to assert on the result.
338	*/
339	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
340	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
341
342	/** @def PGM_GCPHYS_2_PTR
343	* Maps a GC physical page address to a virtual address.
344	*
345	* @returns VBox status code.
346	* @param pVM The cross context VM structure.
347	* @param GCPhys The GC physical address to map to a virtual one.
348	* @param ppv Where to store the virtual address. No need to cast this.
349	*
350	* @remark Use with care as we don't have so much dynamic mapping space in
351	* ring-0 on 32-bit darwin and in RC.
352	* @remark There is no need to assert on the result.
353	*/
354	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
355
356	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
357	* Maps a GC physical page address to a virtual address.
358	*
359	* @returns VBox status code.
360	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
361	* @param GCPhys The GC physical address to map to a virtual one.
362	* @param ppv Where to store the virtual address. No need to cast this.
363	*
364	* @remark Use with care as we don't have so much dynamic mapping space in
365	* ring-0 on 32-bit darwin and in RC.
366	* @remark There is no need to assert on the result.
367	*/
368	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
369
370	/** @def PGM_GCPHYS_2_PTR_EX
371	* Maps a unaligned GC physical page address to a virtual address.
372	*
373	* @returns VBox status code.
374	* @param pVM The cross context VM structure.
375	* @param GCPhys The GC physical address to map to a virtual one.
376	* @param ppv Where to store the virtual address. No need to cast this.
377	*
378	* @remark Use with care as we don't have so much dynamic mapping space in
379	* ring-0 on 32-bit darwin and in RC.
380	* @remark There is no need to assert on the result.
381	*/
382	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
383	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
384
385	/** @def PGM_DYNMAP_UNUSED_HINT
386	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
387	* is no longer used.
388	*
389	* For best effect only apply this to the page that was mapped most recently.
390	*
391	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
392	* @param pvPage The pool page.
393	*/
394	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
395
396	/** @def PGM_DYNMAP_UNUSED_HINT_VM
397	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
398	* is no longer used.
399	*
400	* For best effect only apply this to the page that was mapped most recently.
401	*
402	* @param pVM The cross context VM structure.
403	* @param pvPage The pool page.
404	*/
405	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
406
407
408	/** @def PGM_INVL_PG
409	* Invalidates a page.
410	*
411	* @param pVCpu The cross context virtual CPU structure.
412	* @param GCVirt The virtual address of the page to invalidate.
413	*/
414	#ifdef IN_RING0
415	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
416	#elif defined(IN_RING3)
417	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
418	#else
419	# error "Not IN_RING0 or IN_RING3!"
420	#endif
421
422	/** @def PGM_INVL_PG_ALL_VCPU
423	* Invalidates a page on all VCPUs
424	*
425	* @param pVM The cross context VM structure.
426	* @param GCVirt The virtual address of the page to invalidate.
427	*/
428	#if defined(VBOX_VMM_TARGET_ARMV8)
429	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) do { } while(0)
430	#else
431	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
432	#endif
433
434	/** @def PGM_INVL_BIG_PG
435	* Invalidates a 4MB page directory entry.
436	*
437	* @param pVCpu The cross context virtual CPU structure.
438	* @param GCVirt The virtual address within the page directory to invalidate.
439	*/
440	#if defined(VBOX_VMM_TARGET_ARMV8)
441	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) do { } while(0)
442	#else
443	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
444	#endif
445
446	/** @def PGM_INVL_VCPU_TLBS()
447	* Invalidates the TLBs of the specified VCPU
448	*
449	* @param pVCpu The cross context virtual CPU structure.
450	*/
451	#if defined(VBOX_VMM_TARGET_ARMV8)
452	# define PGM_INVL_VCPU_TLBS(pVCpu) do { } while(0)
453	#else
454	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
455	#endif
456
457	/** @def PGM_INVL_ALL_VCPU_TLBS()
458	* Invalidates the TLBs of all VCPUs
459	*
460	* @param pVM The cross context VM structure.
461	*/
462	#if defined(VBOX_VMM_TARGET_ARMV8)
463	# define PGM_INVL_ALL_VCPU_TLBS(pVM) do { } while(0)
464	#else
465	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
466	#endif
467
468
469	/** @name Safer Shadow PAE PT/PTE
470	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
471	* present.
472	*
473	* @{
474	*/
475	#if 1
476	/**
477	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
478	* invalid entries for present.
479	* @sa X86PTEPAE.
480	*/
481	typedef union PGMSHWPTEPAE
482	{
483	/** Unsigned integer view */
484	X86PGPAEUINT uCareful;
485	/* Not other views. */
486	} PGMSHWPTEPAE;
487
488	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
489	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
490	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
491	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
492	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
493	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
494	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
495	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
496	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
497	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
498	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
499	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
500	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
501	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
502	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
503	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
504
505	/**
506	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
507	* invalid entries for present.
508	* @sa X86PTPAE.
509	*/
510	typedef struct PGMSHWPTPAE
511	{
512	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
513	} PGMSHWPTPAE;
514
515	#else
516	typedef X86PTEPAE PGMSHWPTEPAE;
517	typedef X86PTPAE PGMSHWPTPAE;
518	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
519	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
520	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
521	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
522	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
523	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
524	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
525	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
526	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
527	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
528	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
529	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
530	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
531	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
532	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
533	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
534
535	#endif
536
537	/** Pointer to a shadow PAE PTE. */
538	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
539	/** Pointer to a const shadow PAE PTE. */
540	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
541
542	/** Pointer to a shadow PAE page table. */
543	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
544	/** Pointer to a const shadow PAE page table. */
545	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
546	/** @} */
547
548
549	/** The physical access handler type handle count (power of two). */
550	#define PGMPHYSHANDLERTYPE_COUNT 0x20
551	/** Mask for getting the array index from an access handler type handle.
552	* The other handle bits are random and non-zero to avoid mixups due to zero
553	* initialized fields. */
554	#define PGMPHYSHANDLERTYPE_IDX_MASK 0x1f
555
556	/**
557	* Physical page access handler type registration, ring-0 part.
558	*/
559	typedef struct PGMPHYSHANDLERTYPEINTR0
560	{
561	/** The handle value for verfication. */
562	PGMPHYSHANDLERTYPE hType;
563	/** The kind of accesses we're handling. */
564	PGMPHYSHANDLERKIND enmKind;
565	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
566	uint8_t uState;
567	/** Whether to keep the PGM lock when calling the handler.
568	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
569	bool fKeepPgmLock;
570	/** Set if this is registered by a device instance and uUser should be
571	* translated from a device instance ID to a pointer.
572	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
573	bool fRing0DevInsIdx;
574	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
575	bool fNotInHm : 1;
576	/** Pointer to the ring-0 callback function. */
577	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
578	/** Pointer to the ring-0 callback function for \#PFs, can be NULL. */
579	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandler;
580	/** Description / Name. For easing debugging. */
581	R0PTRTYPE(const char *) pszDesc;
582	} PGMPHYSHANDLERTYPEINTR0;
583	/** Pointer to a physical access handler type registration. */
584	typedef PGMPHYSHANDLERTYPEINTR0 *PPGMPHYSHANDLERTYPEINTR0;
585
586	/**
587	* Physical page access handler type registration, shared/ring-3 part.
588	*/
589	typedef struct PGMPHYSHANDLERTYPEINTR3
590	{
591	/** The handle value for verfication. */
592	PGMPHYSHANDLERTYPE hType;
593	/** The kind of accesses we're handling. */
594	PGMPHYSHANDLERKIND enmKind;
595	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
596	uint8_t uState;
597	/** Whether to keep the PGM lock when calling the handler.
598	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
599	bool fKeepPgmLock;
600	/** Set if this is registered by a device instance and uUser should be
601	* translated from a device instance ID to a pointer.
602	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
603	bool fRing0DevInsIdx;
604	/** Set by ring-0 if the handler is ring-0 enabled (for debug). */
605	bool fRing0Enabled : 1;
606	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
607	bool fNotInHm : 1;
608	/** Pointer to the ring-3 callback function. */
609	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
610	/** Description / Name. For easing debugging. */
611	R3PTRTYPE(const char *) pszDesc;
612	} PGMPHYSHANDLERTYPEINTR3;
613	/** Pointer to a physical access handler type registration. */
614	typedef PGMPHYSHANDLERTYPEINTR3 *PPGMPHYSHANDLERTYPEINTR3;
615
616	/** Pointer to a physical access handler type record for the current context. */
617	typedef CTX_SUFF(PPGMPHYSHANDLERTYPEINT) PPGMPHYSHANDLERTYPEINT;
618	/** Pointer to a const physical access handler type record for the current context. */
619	typedef CTX_SUFF(PGMPHYSHANDLERTYPEINT) const *PCPGMPHYSHANDLERTYPEINT;
620	/** Dummy physical access handler type record. */
621	extern CTX_SUFF(PGMPHYSHANDLERTYPEINT) const g_pgmHandlerPhysicalDummyType;
622
623
624	/**
625	* Physical page access handler structure.
626	*
627	* This is used to keep track of physical address ranges
628	* which are being monitored in some kind of way.
629	*/
630	typedef struct PGMPHYSHANDLER
631	{
632	/** @name Tree stuff.
633	* @{ */
634	/** First address. */
635	RTGCPHYS Key;
636	/** Last address. */
637	RTGCPHYS KeyLast;
638	uint32_t idxLeft;
639	uint32_t idxRight;
640	uint8_t cHeight;
641	/** @} */
642	uint8_t abPadding[3];
643	/** Number of pages to update. */
644	uint32_t cPages;
645	/** Set if we have pages that have been aliased. */
646	uint32_t cAliasedPages;
647	/** Set if we have pages that have temporarily been disabled. */
648	uint32_t cTmpOffPages;
649	/** Registered handler type handle.
650	* @note Marked volatile to prevent re-reading after validation. */
651	PGMPHYSHANDLERTYPE volatile hType;
652	/** User argument for the handlers. */
653	uint64_t uUser;
654	/** Description / Name. For easing debugging. */
655	R3PTRTYPE(const char *) pszDesc;
656	/** Profiling of this handler.
657	* @note VBOX_WITH_STATISTICS only, but included to keep structure stable. */
658	STAMPROFILE Stat;
659	} PGMPHYSHANDLER;
660	AssertCompileSize(PGMPHYSHANDLER, 12*8);
661	/** Pointer to a physical page access handler structure. */
662	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
663
664	/**
665	* Gets the type record for a physical handler (no reference added).
666	* @returns PCPGMPHYSHANDLERTYPEINT, can be NULL
667	* @param a_pVM The cross context VM structure.
668	* @param a_pPhysHandler Pointer to the physical handler structure
669	* (PGMPHYSHANDLER).
670	*/
671	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) \
672	pgmHandlerPhysicalTypeHandleToPtr(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
673
674	/**
675	* Gets the type record for a physical handler, never returns NULL.
676	*
677	* @returns PCPGMPHYSHANDLERTYPEINT, never NULL.
678	* @param a_pVM The cross context VM structure.
679	* @param a_pPhysHandler Pointer to the physical handler structure
680	* (PGMPHYSHANDLER).
681	*/
682	#define PGMPHYSHANDLER_GET_TYPE_NO_NULL(a_pVM, a_pPhysHandler) \
683	pgmHandlerPhysicalTypeHandleToPtr2(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
684
685	/** Physical access handler allocator. */
686	typedef RTCHardAvlTreeSlabAllocator<PGMPHYSHANDLER> PGMPHYSHANDLERALLOCATOR;
687
688	/** Physical access handler tree. */
689	typedef RTCHardAvlRangeTree<PGMPHYSHANDLER, RTGCPHYS> PGMPHYSHANDLERTREE;
690	/** Pointer to a physical access handler tree. */
691	typedef PGMPHYSHANDLERTREE *PPGMPHYSHANDLERTREE;
692
693
694	/**
695	* A Physical Guest Page tracking structure.
696	*
697	* The format of this structure is complicated because we have to fit a lot
698	* of information into as few bits as possible. The format is also subject
699	* to change (there is one coming up soon). Which means that for we'll be
700	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
701	* accesses to the structure.
702	*/
703	typedef union PGMPAGE
704	{
705	/** 64-bit integer view. */
706	uint64_t au64[2];
707	/** 16-bit view. */
708	uint32_t au32[4];
709	/** 16-bit view. */
710	uint16_t au16[8];
711	/** 8-bit view. */
712	uint8_t au8[16];
713
714	/** Structured view. */
715	struct
716	{
717	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
718	uint64_t u2HandlerPhysStateY : 2;
719	/** 2 - Don't apply the physical handler in HM mode (nested APIC hack). */
720	uint64_t fHandlerPhysNotInHm : 1;
721	/** 3 - Flag indicating that a write monitored page was written to when set. */
722	uint64_t fWrittenToY : 1;
723	/** 4 - Set when the page is write monitored because it's an IEM TB code
724	* page. Save recompiled code the need to verify opcode bytes.
725	*
726	* IEM fetches this flag as part of the TLB queries. The flag is cleared when
727	* the page is made writable and IEM is informed and will invalidate its
728	* physical TLB layer.
729	*
730	* @note Can possibly be set on ROM pages that are not in the monitored state. */
731	uint64_t fCodePageY : 1;
732	/** 7:5 - Unused. */
733	uint64_t u2Unused0 : 3;
734	/** 9:8 - Paging structure needed to map the page
735	* (PGM_PAGE_PDE_TYPE_). /
736	uint64_t u2PDETypeY : 2;
737	/** 11:10 - NEM state bits. */
738	uint64_t u2NemStateY : 2;
739	/** 12:48 - The host physical frame number (shift left to get the
740	* address). */
741	uint64_t HCPhysFN : 36;
742	/** 50:48 - The page state. */
743	uint64_t uStateY : 3;
744	/** 51:53 - The page type (PGMPAGETYPE). */
745	uint64_t uTypeY : 3;
746	/** 63:54 - PTE index for usage tracking (page pool). */
747	uint64_t u10PteIdx : 10;
748
749	/** The GMM page ID.
750	* @remarks In the current implementation, MMIO2 and pages aliased to
751	* MMIO2 pages will be exploiting this field to calculate the
752	* ring-3 mapping address corresponding to the page.
753	* Later we may consider including MMIO2 management into GMM. */
754	uint32_t idPage;
755	/** Usage tracking (page pool). */
756	uint16_t u16TrackingY;
757	/** The number of read locks on this page. */
758	uint8_t cReadLocksY;
759	/** The number of write locks on this page. */
760	uint8_t cWriteLocksY;
761	} s;
762	} PGMPAGE;
763	AssertCompileSize(PGMPAGE, 16);
764	/** Pointer to a physical guest page. */
765	typedef PGMPAGE *PPGMPAGE;
766	/** Pointer to a const physical guest page. */
767	typedef const PGMPAGE *PCPGMPAGE;
768	/** Pointer to a physical guest page pointer. */
769	typedef PPGMPAGE *PPPGMPAGE;
770
771
772	/**
773	* Clears the page structure.
774	* @param a_pPage Pointer to the physical guest page tracking structure.
775	*/
776	#define PGM_PAGE_CLEAR(a_pPage) \
777	do { \
778	(a_pPage)->au64[0] = 0; \
779	(a_pPage)->au64[1] = 0; \
780	} while (0)
781
782	/**
783	* Initializes the page structure.
784	* @param a_pPage Pointer to the physical guest page tracking structure.
785	* @param a_HCPhys The host physical address of the page.
786	* @param a_idPage The (GMM) page ID of the page.
787	* @param a_uType The page type (PGMPAGETYPE).
788	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
789	*/
790	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
791	# define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
792	do { \
793	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
794	AssertFatalMsg(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000)), ("%RHp\n", SetHCPhysTmp)); \
795	(a_pPage)->au64[0] = SetHCPhysTmp; \
796	(a_pPage)->au64[1] = 0; \
797	(a_pPage)->s.idPage = (a_idPage); \
798	(a_pPage)->s.uStateY = (a_uState); \
799	(a_pPage)->s.uTypeY = (a_uType); \
800	} while (0)
801	#else
802	# define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
803	do { \
804	(a_pPage)->au64[0] = 0; \
805	(a_pPage)->au64[1] = 0; \
806	(a_pPage)->s.idPage = (a_idPage); \
807	(a_pPage)->s.uStateY = (a_uState); \
808	(a_pPage)->s.uTypeY = (a_uType); \
809	} while (0)
810	#endif
811
812	/**
813	* Initializes the page structure of a ZERO page.
814	* @param a_pPage Pointer to the physical guest page tracking structure.
815	* @param a_pVM The VM handle (for getting the zero page address).
816	* @param a_uType The page type (PGMPAGETYPE).
817	*/
818	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
819	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
820
821
822	/** @name The Page state, PGMPAGE::uStateY.
823	* @{ */
824	/** The zero page.
825	* This is a per-VM page that's never ever mapped writable. */
826	#define PGM_PAGE_STATE_ZERO 0U
827	/** A allocated page.
828	* This is a per-VM page allocated from the page pool (or wherever
829	* we get MMIO2 pages from if the type is MMIO2).
830	*/
831	#define PGM_PAGE_STATE_ALLOCATED 1U
832	/** A allocated page that's being monitored for writes.
833	* The shadow page table mappings are read-only. When a write occurs, the
834	* fWrittenTo member is set, the page remapped as read-write and the state
835	* moved back to allocated. */
836	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
837	/** The page is shared, aka. copy-on-write.
838	* This is a page that's shared with other VMs. */
839	#define PGM_PAGE_STATE_SHARED 3U
840	/** The page is ballooned, so no longer available for this VM. */
841	#define PGM_PAGE_STATE_BALLOONED 4U
842	/** @} */
843
844
845	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
846	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
847	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
848	#else
849	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
850	#endif
851
852	/**
853	* Gets the page state.
854	* @returns page state (PGM_PAGE_STATE_*).
855	* @param a_pPage Pointer to the physical guest page tracking structure.
856	*
857	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
858	* builds.
859	*/
860	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
861	#if defined(__GNUC__) && defined(VBOX_STRICT)
862	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
863	#else
864	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
865	#endif
866
867	/**
868	* Sets the page state.
869	* @param a_pVM The VM handle, only used for lock ownership assertions.
870	* @param a_pPage Pointer to the physical guest page tracking structure.
871	* @param a_uState The new page state.
872	*/
873	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
874	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
875
876
877	/**
878	* Gets the host physical address of the guest page.
879	* @returns host physical address (RTHCPHYS).
880	* @param a_pPage Pointer to the physical guest page tracking structure.
881	*
882	* @remarks In strict builds on gcc platforms, this macro will make some ugly
883	* assumption about a valid pVM variable/parameter being in the
884	* current context. It will use this pVM variable to assert that the
885	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
886	* pVM is not around.
887	*/
888	#if 0
889	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
890	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
891	#else
892	# ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
893	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
894	# else
895	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( 0 )
896	# endif
897	# if defined(__GNUC__) && defined(VBOX_STRICT)
898	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
899	# else
900	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
901	# endif
902	#endif
903
904	/**
905	* Sets the host physical address of the guest page.
906	*
907	* @param a_pVM The VM handle, only used for lock ownership assertions.
908	* @param a_pPage Pointer to the physical guest page tracking structure.
909	* @param a_HCPhys The new host physical address.
910	*/
911	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
912	# define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
913	do { \
914	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
915	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
916	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
917	PGM_PAGE_ASSERT_LOCK(a_pVM); \
918	} while (0)
919	#else
920	# define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
921	do { \
922	(a_pPage)->s.HCPhysFN = 0; \
923	PGM_PAGE_ASSERT_LOCK(a_pVM); \
924	} while (0)
925	#endif
926
927	/**
928	* Get the Page ID.
929	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
930	* @param a_pPage Pointer to the physical guest page tracking structure.
931	*/
932	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
933
934	/**
935	* Sets the Page ID.
936	* @param a_pVM The VM handle, only used for lock ownership assertions.
937	* @param a_pPage Pointer to the physical guest page tracking structure.
938	* @param a_idPage The new page ID.
939	*/
940	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
941	do { \
942	(a_pPage)->s.idPage = (a_idPage); \
943	PGM_PAGE_ASSERT_LOCK(a_pVM); \
944	} while (0)
945
946	/**
947	* Get the Chunk ID.
948	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
949	* @param a_pPage Pointer to the physical guest page tracking structure.
950	*/
951	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
952
953	/**
954	* Get the index of the page within the allocation chunk.
955	* @returns The page index.
956	* @param a_pPage Pointer to the physical guest page tracking structure.
957	*/
958	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
959
960	/**
961	* Gets the page type.
962	* @returns The page type.
963	* @param a_pPage Pointer to the physical guest page tracking structure.
964	*
965	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
966	* builds.
967	*/
968	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
969	#if defined(__GNUC__) && defined(VBOX_STRICT)
970	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
971	#else
972	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
973	#endif
974
975	/**
976	* Sets the page type.
977	*
978	* @param a_pVM The VM handle, only used for lock ownership assertions.
979	* @param a_pPage Pointer to the physical guest page tracking structure.
980	* @param a_enmType The new page type (PGMPAGETYPE).
981	*/
982	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
983	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
984
985	/**
986	* Gets the page table index
987	* @returns The page table index.
988	* @param a_pPage Pointer to the physical guest page tracking structure.
989	*/
990	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
991
992	/**
993	* Sets the page table index.
994	* @param a_pVM The VM handle, only used for lock ownership assertions.
995	* @param a_pPage Pointer to the physical guest page tracking structure.
996	* @param a_iPte New page table index.
997	*/
998	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
999	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1000
1001	/**
1002	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
1003	* @returns true/false.
1004	* @param a_pPage Pointer to the physical guest page tracking structure.
1005	*/
1006	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1007
1008	/**
1009	* Checks if the page is marked for MMIO, including both aliases.
1010	* @returns true/false.
1011	* @param a_pPage Pointer to the physical guest page tracking structure.
1012	*/
1013	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1014	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1015	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1016	)
1017
1018	/**
1019	* Checks if the page is marked for MMIO, including special aliases.
1020	* @returns true/false.
1021	* @param a_pPage Pointer to the physical guest page tracking structure.
1022	*/
1023	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1024	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1025
1026	/**
1027	* Checks if the page is a special aliased MMIO page.
1028	* @returns true/false.
1029	* @param a_pPage Pointer to the physical guest page tracking structure.
1030	*/
1031	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1032
1033	/**
1034	* Checks if the page is backed by the ZERO page.
1035	* @returns true/false.
1036	* @param a_pPage Pointer to the physical guest page tracking structure.
1037	*/
1038	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1039
1040	/**
1041	* Checks if the page is backed by a SHARED page.
1042	* @returns true/false.
1043	* @param a_pPage Pointer to the physical guest page tracking structure.
1044	*/
1045	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1046
1047	/**
1048	* Checks if the page is ballooned.
1049	* @returns true/false.
1050	* @param a_pPage Pointer to the physical guest page tracking structure.
1051	*/
1052	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1053
1054	/**
1055	* Checks if the page is allocated.
1056	* @returns true/false.
1057	* @param a_pPage Pointer to the physical guest page tracking structure.
1058	*/
1059	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1060
1061
1062	/**
1063	* Marks the page as written to (for GMM change monitoring).
1064	* @param a_pVM The VM handle, only used for lock ownership assertions.
1065	* @param a_pPage Pointer to the physical guest page tracking structure.
1066	*/
1067	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1068	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1069
1070	/**
1071	* Clears the written-to indicator.
1072	* @param a_pVM The VM handle, only used for lock ownership assertions.
1073	* @param a_pPage Pointer to the physical guest page tracking structure.
1074	*/
1075	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1076	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1077
1078	/**
1079	* Checks if the page was marked as written-to.
1080	* @returns true/false.
1081	* @param a_pPage Pointer to the physical guest page tracking structure.
1082	*/
1083	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1084
1085
1086	/**
1087	* Marks the page as an IEM code page (being write monitored or a ROM page).
1088	* @param a_pVM The VM handle, only used for lock ownership assertions.
1089	* @param a_pPage Pointer to the physical guest page tracking structure.
1090	*/
1091	#define PGM_PAGE_SET_CODE_PAGE(a_pVM, a_pPage) \
1092	do { (a_pPage)->s.fCodePageY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1093
1094	/**
1095	* Clears the code page indicator.
1096	* @param a_pVM The VM handle, only used for lock ownership assertions.
1097	* @param a_pPage Pointer to the physical guest page tracking structure.
1098	*/
1099	#define PGM_PAGE_CLEAR_CODE_PAGE(a_pVM, a_pPage) \
1100	do { (a_pPage)->s.fCodePageY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1101
1102	/**
1103	* Checks if the page is an IEM code page (implies write monitored or ROM page).
1104	* @returns true/false.
1105	* @param a_pPage Pointer to the physical guest page tracking structure.
1106	*/
1107	#define PGM_PAGE_IS_CODE_PAGE(a_pPage) ( (a_pPage)->s.fCodePageY )
1108
1109
1110	/** @name PT usage values (PGMPAGE::u2PDEType).
1111	*
1112	* @{ */
1113	/** Either as a PT or PDE. */
1114	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1115	/** Must use a page table to map the range. */
1116	#define PGM_PAGE_PDE_TYPE_PT 1
1117	/** Can use a page directory entry to map the continuous range. */
1118	#define PGM_PAGE_PDE_TYPE_PDE 2
1119	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1120	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1121	/** @} */
1122
1123	/**
1124	* Set the PDE type of the page
1125	* @param a_pVM The VM handle, only used for lock ownership assertions.
1126	* @param a_pPage Pointer to the physical guest page tracking structure.
1127	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1128	*/
1129	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1130	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1131
1132	/**
1133	* Checks if the page was marked being part of a large page
1134	* @returns true/false.
1135	* @param a_pPage Pointer to the physical guest page tracking structure.
1136	*/
1137	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1138
1139	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1140	*
1141	* @remarks The values are assigned in order of priority, so we can calculate
1142	* the correct state for a page with different handlers installed.
1143	* @{ */
1144	/** No handler installed. */
1145	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1146	/** Monitoring is temporarily disabled. */
1147	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1148	/** Write access is monitored. */
1149	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1150	/** All access is monitored. */
1151	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1152	/** @} */
1153
1154	/**
1155	* Gets the physical access handler state of a page.
1156	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1157	* @param a_pPage Pointer to the physical guest page tracking structure.
1158	*/
1159	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1160
1161	/**
1162	* Sets the physical access handler state of a page.
1163	* @param a_pPage Pointer to the physical guest page tracking structure.
1164	* @param a_uState The new state value.
1165	* @param a_fNotInHm The PGMPHYSHANDLER_F_NOT_HM bit.
1166	*/
1167	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState, a_fNotInHm) \
1168	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); (a_pPage)->s.fHandlerPhysNotInHm = (a_fNotInHm); } while (0)
1169
1170	/**
1171	* Sets the physical access handler state of a page.
1172	* @param a_pPage Pointer to the physical guest page tracking structure.
1173	* @param a_uState The new state value.
1174	*/
1175	#define PGM_PAGE_SET_HNDL_PHYS_STATE_ONLY(a_pPage, a_uState) \
1176	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1177
1178	/**
1179	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1180	* @returns true/false
1181	* @param a_pPage Pointer to the physical guest page tracking structure.
1182	*/
1183	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1184	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1185
1186	/**
1187	* Checks if the page has any active physical access handlers.
1188	* @returns true/false
1189	* @param a_pPage Pointer to the physical guest page tracking structure.
1190	*/
1191	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1192	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1193
1194	/**
1195	* Checks if the page has any access handlers, including temporarily disabled ones.
1196	* @returns true/false
1197	* @param a_pPage Pointer to the physical guest page tracking structure.
1198	*/
1199	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1200	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1201
1202	/**
1203	* Checks if the page has any active access handlers.
1204	* @returns true/false
1205	* @param a_pPage Pointer to the physical guest page tracking structure.
1206	*/
1207	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1208	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1209
1210	/**
1211	* Checks if the page has any active access handlers catching all accesses.
1212	* @returns true/false
1213	* @param a_pPage Pointer to the physical guest page tracking structure.
1214	*/
1215	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1216	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1217
1218	/** @def PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM
1219	* Checks if the physical handlers of the page should be ignored in shadow page
1220	* tables and such.
1221	* @returns true/false
1222	* @param a_pPage Pointer to the physical guest page tracking structure.
1223	*/
1224	#define PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(a_pPage) ((a_pPage)->s.fHandlerPhysNotInHm)
1225
1226	/** @def PGM_PAGE_GET_TRACKING
1227	* Gets the packed shadow page pool tracking data associated with a guest page.
1228	* @returns uint16_t containing the data.
1229	* @param a_pPage Pointer to the physical guest page tracking structure.
1230	*/
1231	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1232	#if defined(__GNUC__) && defined(VBOX_STRICT)
1233	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1234	#else
1235	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1236	#endif
1237
1238	/** @def PGM_PAGE_SET_TRACKING
1239	* Sets the packed shadow page pool tracking data associated with a guest page.
1240	* @param a_pVM The VM handle, only used for lock ownership assertions.
1241	* @param a_pPage Pointer to the physical guest page tracking structure.
1242	* @param a_u16TrackingData The tracking data to store.
1243	*/
1244	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1245	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1246
1247	/** @def PGM_PAGE_GET_TD_CREFS
1248	* Gets the @a cRefs tracking data member.
1249	* @returns cRefs.
1250	* @param a_pPage Pointer to the physical guest page tracking structure.
1251	*/
1252	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1253	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1254	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1255	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1256
1257	/** @def PGM_PAGE_GET_TD_IDX
1258	* Gets the @a idx tracking data member.
1259	* @returns idx.
1260	* @param a_pPage Pointer to the physical guest page tracking structure.
1261	*/
1262	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1263	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1264	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1265	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1266
1267
1268	/** Max number of locks on a page. */
1269	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1270
1271	/** Get the read lock count.
1272	* @returns count.
1273	* @param a_pPage Pointer to the physical guest page tracking structure.
1274	*/
1275	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1276
1277	/** Get the write lock count.
1278	* @returns count.
1279	* @param a_pPage Pointer to the physical guest page tracking structure.
1280	*/
1281	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1282
1283	/** Decrement the read lock counter.
1284	* @param a_pPage Pointer to the physical guest page tracking structure.
1285	*/
1286	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1287
1288	/** Decrement the write lock counter.
1289	* @param a_pPage Pointer to the physical guest page tracking structure.
1290	*/
1291	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1292
1293	/** Increment the read lock counter.
1294	* @param a_pPage Pointer to the physical guest page tracking structure.
1295	*/
1296	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1297
1298	/** Increment the write lock counter.
1299	* @param a_pPage Pointer to the physical guest page tracking structure.
1300	*/
1301	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1302
1303
1304	/** Gets the NEM state.
1305	* @returns NEM state value (two bits).
1306	* @param a_pPage Pointer to the physical guest page tracking structure.
1307	*/
1308	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1309
1310	/** Sets the NEM state.
1311	* @param a_pPage Pointer to the physical guest page tracking structure.
1312	* @param a_u2State The NEM state value (specific to NEM impl.).
1313	*/
1314	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1315	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1316
1317
1318	#if 0
1319	/** Enables sanity checking of write monitoring using CRC-32. */
1320	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1321	#endif
1322
1323	/**
1324	* Per page live save tracking data.
1325	*/
1326	typedef struct PGMLIVESAVERAMPAGE
1327	{
1328	/** Number of times it has been dirtied. */
1329	uint32_t cDirtied : 24;
1330	/** Whether it is currently dirty. */
1331	uint32_t fDirty : 1;
1332	/** Ignore the page.
1333	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1334	* deal with these after pausing the VM and DevPCI have said it bit about
1335	* remappings. */
1336	uint32_t fIgnore : 1;
1337	/** Was a ZERO page last time around. */
1338	uint32_t fZero : 1;
1339	/** Was a SHARED page last time around. */
1340	uint32_t fShared : 1;
1341	/** Whether the page is/was write monitored in a previous pass. */
1342	uint32_t fWriteMonitored : 1;
1343	/** Whether the page is/was write monitored earlier in this pass. */
1344	uint32_t fWriteMonitoredJustNow : 1;
1345	/** Bits reserved for future use. */
1346	uint32_t u2Reserved : 2;
1347	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1348	/** CRC-32 for the page. This is for internal consistency checks. */
1349	uint32_t u32Crc;
1350	#endif
1351	} PGMLIVESAVERAMPAGE;
1352	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1353	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1354	#else
1355	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1356	#endif
1357	/** Pointer to the per page live save tracking data. */
1358	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1359
1360	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1361	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1362
1363
1364	/**
1365	* RAM range lookup table entry.
1366	*/
1367	typedef union PGMRAMRANGELOOKUPENTRY
1368	{
1369	RT_GCC_EXTENSION struct
1370	{
1371	/** Page aligned start address of the range, with page offset holding the ID. */
1372	RTGCPHYS GCPhysFirstAndId;
1373	/** The last address in the range (inclusive). Page aligned (-1). */
1374	RTGCPHYS GCPhysLast;
1375	};
1376	/** Alternative 128-bit view for atomic updating. */
1377	RTUINT128U volatile u128Volatile;
1378	/** Alternative 128-bit view for atomic updating. */
1379	RTUINT128U u128Normal;
1380	} PGMRAMRANGELOOKUPENTRY;
1381	/** Pointer to a lookup table entry. */
1382	typedef PGMRAMRANGELOOKUPENTRY *PPGMRAMRANGELOOKUPENTRY;
1383
1384	/** Extracts the ID from PGMRAMRANGELOOKUPENTRY::GCPhysFirstAndId. */
1385	#define PGMRAMRANGELOOKUPENTRY_GET_ID(a_LookupEntry) ((uint32_t)((a_LookupEntry).GCPhysFirstAndId & GUEST_PAGE_OFFSET_MASK))
1386	/** Extracts the GCPhysFirst from PGMRAMRANGELOOKUPENTRY::GCPhysFirstAndId. */
1387	#define PGMRAMRANGELOOKUPENTRY_GET_FIRST(a_LookupEntry) (((a_LookupEntry).GCPhysFirstAndId) & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK)
1388
1389
1390	/**
1391	* RAM range for GC Phys to HC Phys & R3 Ptr conversion.
1392	*
1393	* This structure is addressed via context specific pointer tables. Lookup is
1394	* organized via the lookup table (PGMRAMRANGELOOKUPENTRY).
1395	*/
1396	typedef struct PGMRAMRANGE
1397	{
1398	/** Start of the range. Page aligned. */
1399	RTGCPHYS GCPhys;
1400	/** Size of the range. (Page aligned of course).
1401	* Ring-0 duplicates this in a PGMR0PERVM::acRamRangePages (shifted by
1402	* guest page size). */
1403	RTGCPHYS cb;
1404	/** PGM_RAM_RANGE_FLAGS_* flags. */
1405	uint32_t fFlags;
1406	/** NEM specific info, UINT32_MAX if not used. */
1407	uint32_t uNemRange;
1408	/** Last address in the range (inclusive). Page aligned (-1). */
1409	RTGCPHYS GCPhysLast;
1410	/** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1411	R3PTRTYPE(uint8_t *) pbR3;
1412	/** The RAM range identifier (index into the pointer table). */
1413	uint32_t idRange;
1414	#if HC_ARCH_BITS != 32
1415	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1416	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 0 : 1];
1417	#endif
1418	/** Live save per page tracking data. */
1419	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1420	/** The range description. */
1421	R3PTRTYPE(const char *) pszDesc;
1422
1423	/** Array of physical guest page tracking structures.
1424	* @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1425	PGMPAGE aPages[1];
1426	} PGMRAMRANGE;
1427	AssertCompileMemberAlignment(PGMRAMRANGE, aPages, 16);
1428	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1429	typedef PGMRAMRANGE *PPGMRAMRANGE;
1430
1431	/** @name PGMRAMRANGE::fFlags
1432	* @{ */
1433	/** Ad hoc RAM range for an ROM mapping. */
1434	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1435	/** Ad hoc RAM range for an MMIO mapping. */
1436	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1437	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1438	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1439	/** Valid RAM range flags. */
1440	#define PGM_RAM_RANGE_FLAGS_VALID_MASK (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX)
1441	/** @} */
1442
1443	/** Tests if a RAM range is an ad hoc one or not.
1444	* @returns true/false.
1445	* @param pRam The RAM range.
1446	*/
1447	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1448	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1449
1450	/** The number of entries in the RAM range TLBs (there is one for each
1451	* context). Must be a power of two. */
1452	#define PGM_RAMRANGE_TLB_ENTRIES 64
1453
1454	/**
1455	* Calculates the RAM range TLB index for the physical address.
1456	*
1457	* @returns RAM range TLB index.
1458	* @param a_GCPhys The guest physical address.
1459	*/
1460	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 19) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1461
1462	/**
1463	* Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1464	* mapping address.
1465	*/
1466	#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1467	( (a_pRam)->pbR3 ? (a_pRam)->pbR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1468
1469
1470	/**
1471	* Per page tracking structure for ROM image.
1472	*
1473	* A ROM image may have a shadow page, in which case we may have two pages
1474	* backing it. This structure contains the PGMPAGE for both while
1475	* PGMRAMRANGE have a copy of the active one. It is important that these
1476	* aren't out of sync in any regard other than page pool tracking data.
1477	*/
1478	typedef struct PGMROMPAGE
1479	{
1480	/** The page structure for the virgin ROM page. */
1481	PGMPAGE Virgin;
1482	/** The page structure for the shadow RAM page. */
1483	PGMPAGE Shadow;
1484	/** The current protection setting. */
1485	PGMROMPROT enmProt;
1486	/** Live save status information. Makes use of unused alignment space. */
1487	struct
1488	{
1489	/** The previous protection value. */
1490	uint8_t u8Prot;
1491	/** Written to flag set by the handler. */
1492	bool fWrittenTo;
1493	/** Whether the shadow page is dirty or not. */
1494	bool fDirty;
1495	/** Whether it was dirtied in the recently. */
1496	bool fDirtiedRecently;
1497	} LiveSave;
1498	} PGMROMPAGE;
1499	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1500	/** Pointer to a ROM page tracking structure. */
1501	typedef PGMROMPAGE *PPGMROMPAGE;
1502
1503
1504	/**
1505	* A registered ROM image.
1506	*
1507	* This is needed to keep track of ROM image since they generally intrude
1508	* into a PGMRAMRANGE. It also keeps track of additional info like the
1509	* two page sets (read-only virgin and read-write shadow), the current
1510	* state of each page.
1511	*
1512	* Because access handlers cannot easily be executed in a different
1513	* context, the ROM ranges needs to be accessible and in all contexts.
1514	*/
1515	typedef struct PGMROMRANGE
1516	{
1517	/** Address of the range. */
1518	RTGCPHYS GCPhys;
1519	/** Address of the last byte in the range. */
1520	RTGCPHYS GCPhysLast;
1521	/** Size of the range. */
1522	RTGCPHYS cb;
1523	/** The flags (PGMPHYS_ROM_FLAGS_). /
1524	uint8_t fFlags;
1525	/** The saved state range ID. */
1526	uint8_t idSavedState;
1527	/** The ID of the associated RAM range. */
1528	#ifdef IN_RING0
1529	volatile
1530	#endif
1531	uint16_t idRamRange;
1532	/** The size bits pvOriginal points to. */
1533	uint32_t cbOriginal;
1534	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1535	* This is used for strictness checks. */
1536	R3PTRTYPE(const void *) pvOriginal;
1537	/** The ROM description. */
1538	R3PTRTYPE(const char *) pszDesc;
1539	#ifdef VBOX_WITH_PGM_NEM_MODE
1540	/** In simplified memory mode this provides alternate backing for shadowed ROMs.
1541	* - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1542	* - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1543	* - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1544	* - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1545	R3PTRTYPE(uint8_t *) pbR3Alternate;
1546	RTR3PTR pvAlignment2;
1547	#else
1548	RTR3PTR apvUnused[2];
1549	#endif
1550	/** The per page tracking structures. */
1551	PGMROMPAGE aPages[1];
1552	} PGMROMRANGE;
1553	/** Pointer to a ROM range. */
1554	typedef PGMROMRANGE *PPGMROMRANGE;
1555
1556
1557	/**
1558	* Live save per page data for an MMIO2 page.
1559	*
1560	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1561	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1562	* CRC-32 for detecting changes as well as special handling of zero pages. This
1563	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1564	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1565	* because of speed (2.5x and 6x slower).)
1566	*
1567	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1568	* save but normally is disabled. Since we can write monitor guest
1569	* accesses on our own, we only need this for host accesses. Shouldn't be
1570	* too difficult for DevVGA, VMMDev might be doable, the planned
1571	* networking fun will be fun since it involves ring-0.
1572	*/
1573	typedef struct PGMLIVESAVEMMIO2PAGE
1574	{
1575	/** Set if the page is considered dirty. */
1576	bool fDirty;
1577	/** The number of scans this page has remained unchanged for.
1578	* Only updated for dirty pages. */
1579	uint8_t cUnchangedScans;
1580	/** Whether this page was zero at the last scan. */
1581	bool fZero;
1582	/** Alignment padding. */
1583	bool fReserved;
1584	/** CRC-32 for the first half of the page.
1585	* This is used together with u32CrcH2 to quickly detect changes in the page
1586	* during the non-final passes. */
1587	uint32_t u32CrcH1;
1588	/** CRC-32 for the second half of the page. */
1589	uint32_t u32CrcH2;
1590	/** SHA-1 for the saved page.
1591	* This is used in the final pass to skip pages without changes. */
1592	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1593	} PGMLIVESAVEMMIO2PAGE;
1594	/** Pointer to a live save status data for an MMIO2 page. */
1595	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1596
1597	/**
1598	* A registered MMIO2 (= Device RAM) range.
1599	*
1600	* There are a few reason why we need to keep track of these registrations. One
1601	* of them is the deregistration & cleanup stuff, while another is that the
1602	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1603	* range list.
1604	*
1605	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1606	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1607	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1608	* overlap we will free all the existing RAM pages and put in the ram range
1609	* pages instead.
1610	*/
1611	typedef struct PGMREGMMIO2RANGE
1612	{
1613	/** The owner of the range (a device). */
1614	PPDMDEVINSR3 pDevInsR3;
1615	/** Pointer to the ring-3 mapping of the allocation. */
1616	R3PTRTYPE(uint8_t *) pbR3;
1617	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1618	uint16_t fFlags;
1619	/** The sub device number (internal PCI config (CFGM) number). */
1620	uint8_t iSubDev;
1621	/** The PCI region number. */
1622	uint8_t iRegion;
1623	/** The saved state range ID. */
1624	uint8_t idSavedState;
1625	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1626	uint8_t idMmio2;
1627	/** The ID of the associated RAM range. */
1628	#ifdef IN_RING0
1629	volatile
1630	#endif
1631	uint16_t idRamRange;
1632	/** The mapping address if mapped, NIL_RTGCPHYS if not. */
1633	RTGCPHYS GCPhys;
1634	/** The real size.
1635	* This may be larger than indicated by RamRange.cb if the range has been
1636	* reduced during saved state loading. */
1637	RTGCPHYS cbReal;
1638	/** Pointer to the physical handler for MMIO.
1639	* If NEM is responsible for tracking dirty pages in simple memory mode, this
1640	* will be NULL. */
1641	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1642	/** Live save per page tracking data for MMIO2. */
1643	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1644	RTR3PTR R3PtrPadding;
1645	} PGMREGMMIO2RANGE;
1646	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1647	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1648
1649	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1650	* @{ */
1651	/** Set if this is the first chunk in the MMIO2 range. */
1652	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1653	/** Set if this is the last chunk in the MMIO2 range. */
1654	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1655	/** Set if the whole range is mapped. */
1656	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1657	/** Set if it's overlapping, clear if not. */
1658	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1659	/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1660	#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1661	/** Set if the access handler is registered. */
1662	#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1663	/** Set if dirty page tracking is currently enabled. */
1664	#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1665	/** Set if there are dirty pages in the range. */
1666	#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1667	/** @} */
1668
1669
1670	/** @name Internal MMIO2 macros.
1671	* @{ */
1672	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1673	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1674	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1675	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1676	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1677	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1678	/** @} */
1679
1680
1681
1682	/**
1683	* PGMPhysRead/Write cache entry
1684	*/
1685	typedef struct PGMPHYSCACHEENTRY
1686	{
1687	/** R3 pointer to physical page. */
1688	R3PTRTYPE(uint8_t *) pbR3;
1689	/** GC Physical address for cache entry */
1690	RTGCPHYS GCPhys;
1691	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1692	RTGCPHYS u32Padding0; /*< alignment padding. /
1693	#endif
1694	} PGMPHYSCACHEENTRY;
1695
1696	/**
1697	* PGMPhysRead/Write cache to reduce REM memory access overhead
1698	*/
1699	typedef struct PGMPHYSCACHE
1700	{
1701	/** Bitmap of valid cache entries */
1702	uint64_t aEntries;
1703	/** Cache entries */
1704	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1705	} PGMPHYSCACHE;
1706
1707
1708	/** @name Ring-3 page mapping TLBs
1709	* @{ */
1710
1711	/** Pointer to an allocation chunk ring-3 mapping. */
1712	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1713	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1714	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1715
1716	/**
1717	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1718	*
1719	* The primary tree (Core) uses the chunk id as key.
1720	*/
1721	typedef struct PGMCHUNKR3MAP
1722	{
1723	/** The key is the chunk id. */
1724	AVLU32NODECORE Core;
1725	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1726	* selection. */
1727	uint32_t iLastUsed;
1728	/** The current reference count. */
1729	uint32_t volatile cRefs;
1730	/** The current permanent reference count. */
1731	uint32_t volatile cPermRefs;
1732	/** The mapping address. */
1733	void *pv;
1734	} PGMCHUNKR3MAP;
1735
1736	/**
1737	* Allocation chunk ring-3 mapping TLB entry.
1738	*/
1739	typedef struct PGMCHUNKR3MAPTLBE
1740	{
1741	/** The chunk id. */
1742	uint32_t volatile idChunk;
1743	#if HC_ARCH_BITS == 64
1744	uint32_t u32Padding; /*< alignment padding. /
1745	#endif
1746	/** The chunk map. */
1747	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1748	} PGMCHUNKR3MAPTLBE;
1749	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1750	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1751
1752	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1753	* @remark Must be a power of two value. */
1754	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1755
1756	/**
1757	* Allocation chunk ring-3 mapping TLB.
1758	*
1759	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1760	* At first glance this might look kinda odd since AVL trees are
1761	* supposed to give the most optimal lookup times of all trees
1762	* due to their balancing. However, take a tree with 1023 nodes
1763	* in it, that's 10 levels, meaning that most searches has to go
1764	* down 9 levels before they find what they want. This isn't fast
1765	* compared to a TLB hit. There is the factor of cache misses,
1766	* and of course the problem with trees and branch prediction.
1767	* This is why we use TLBs in front of most of the trees.
1768	*
1769	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1770	* difficult when we switch to the new inlined AVL trees (from kStuff).
1771	*/
1772	typedef struct PGMCHUNKR3MAPTLB
1773	{
1774	/** The TLB entries. */
1775	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1776	} PGMCHUNKR3MAPTLB;
1777
1778	/**
1779	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1780	* @returns Chunk TLB index.
1781	* @param idChunk The Chunk ID.
1782	*/
1783	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1784
1785
1786	/**
1787	* Ring-3 guest page mapping TLB entry.
1788	* @remarks used in ring-0 as well at the moment.
1789	*/
1790	typedef struct PGMPAGER3MAPTLBE
1791	{
1792	/** Address of the page. */
1793	RTGCPHYS volatile GCPhys;
1794	/** The guest page. */
1795	R3PTRTYPE(PPGMPAGE) volatile pPage;
1796	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1797	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1798	/** The address */
1799	R3PTRTYPE(void *) volatile pv;
1800	#if HC_ARCH_BITS == 32
1801	uint32_t u32Padding; /*< alignment padding. /
1802	#endif
1803	} PGMPAGER3MAPTLBE;
1804	/** Pointer to an entry in the HC physical TLB. */
1805	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1806
1807
1808	/** The number of entries in the ring-3 guest page mapping TLB.
1809	* @remarks The value must be a power of two. */
1810	#define PGM_PAGER3MAPTLB_ENTRIES 256
1811
1812	/**
1813	* Ring-3 guest page mapping TLB.
1814	* @remarks used in ring-0 as well at the moment.
1815	*/
1816	typedef struct PGMPAGER3MAPTLB
1817	{
1818	/** The TLB entries. */
1819	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1820	} PGMPAGER3MAPTLB;
1821	/** Pointer to the ring-3 guest page mapping TLB. */
1822	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1823
1824	/**
1825	* Calculates the index of the TLB entry for the specified guest page.
1826	* @returns Physical TLB index.
1827	* @param GCPhys The guest physical address.
1828	*/
1829	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1830
1831	/** @} */
1832
1833
1834	/** @name Ring-0 page mapping TLB
1835	* @{ */
1836	/**
1837	* Ring-0 guest page mapping TLB entry.
1838	*/
1839	typedef struct PGMPAGER0MAPTLBE
1840	{
1841	/** Address of the page. */
1842	RTGCPHYS volatile GCPhys;
1843	/** The guest page. */
1844	R0PTRTYPE(PPGMPAGE) volatile pPage;
1845	/** The address */
1846	R0PTRTYPE(void *) volatile pv;
1847	} PGMPAGER0MAPTLBE;
1848	/** Pointer to an entry in the HC physical TLB. */
1849	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1850
1851
1852	/** The number of entries in the ring-0 guest page mapping TLB.
1853	* @remarks The value must be a power of two. */
1854	#define PGM_PAGER0MAPTLB_ENTRIES 256
1855
1856	/**
1857	* Ring-0 guest page mapping TLB.
1858	*/
1859	typedef struct PGMPAGER0MAPTLB
1860	{
1861	/** The TLB entries. */
1862	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1863	} PGMPAGER0MAPTLB;
1864	/** Pointer to the ring-3 guest page mapping TLB. */
1865	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1866
1867	/**
1868	* Calculates the index of the TLB entry for the specified guest page.
1869	* @returns Physical TLB index.
1870	* @param GCPhys The guest physical address.
1871	*/
1872	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1873	/** @} */
1874
1875
1876	/** @name Context neutral page mapper TLB.
1877	*
1878	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1879	* code is writting in a kind of context neutral way. Time will show whether
1880	* this actually makes sense or not...
1881	*
1882	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1883	* context ends up using a global mapping cache on some platforms
1884	* (darwin).
1885	*
1886	* @{ */
1887	/** @typedef PPGMPAGEMAPTLB
1888	* The page mapper TLB pointer type for the current context. */
1889	/** @typedef PPGMPAGEMAPTLB
1890	* The page mapper TLB entry pointer type for the current context. */
1891	/** @typedef PPGMPAGEMAPTLB
1892	* The page mapper TLB entry pointer pointer type for the current context. */
1893	/** @def PGM_PAGEMAPTLB_ENTRIES
1894	* The number of TLB entries in the page mapper TLB for the current context. */
1895	/** @def PGM_PAGEMAPTLB_IDX
1896	* Calculate the TLB index for a guest physical address.
1897	* @returns The TLB index.
1898	* @param GCPhys The guest physical address. */
1899	/** @typedef PPGMPAGEMAP
1900	* Pointer to a page mapper unit for current context. */
1901	/** @typedef PPPGMPAGEMAP
1902	* Pointer to a page mapper unit pointer for current context. */
1903	#if defined(IN_RING0)
1904	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1905	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1906	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1907	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1908	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1909	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1910	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1911	#else
1912	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1913	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1914	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1915	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1916	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1917	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1918	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1919	#endif
1920	/** @} */
1921
1922
1923	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE /* No pool in NEM-only mode! */
1924
1925	/** @name PGM Pool Indexes.
1926	* Aka. the unique shadow page identifier.
1927	* @{ */
1928	/** NIL page pool IDX. */
1929	#define NIL_PGMPOOL_IDX 0
1930	/** The first normal index. There used to be 5 fictive pages up front, now
1931	* there is only the NIL page. */
1932	#define PGMPOOL_IDX_FIRST 1
1933	/** The last valid index. (inclusive, 14 bits) */
1934	#define PGMPOOL_IDX_LAST 0x3fff
1935	/** @} */
1936
1937	/** The NIL index for the parent chain. */
1938	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1939	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1940
1941	/**
1942	* Node in the chain linking a shadowed page to it's parent (user).
1943	*/
1944	#pragma pack(1)
1945	typedef struct PGMPOOLUSER
1946	{
1947	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1948	uint16_t iNext;
1949	/** The user page index. */
1950	uint16_t iUser;
1951	/** Index into the user table. */
1952	uint32_t iUserTable;
1953	} PGMPOOLUSER, *PPGMPOOLUSER;
1954	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1955	#pragma pack()
1956
1957
1958	/** The NIL index for the phys ext chain. */
1959	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1960	/** The NIL pte index for a phys ext chain slot. */
1961	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1962
1963	/**
1964	* Node in the chain of physical cross reference extents.
1965	* @todo Calling this an 'extent' is not quite right, find a better name.
1966	* @todo find out the optimal size of the aidx array
1967	*/
1968	#pragma pack(1)
1969	typedef struct PGMPOOLPHYSEXT
1970	{
1971	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1972	uint16_t iNext;
1973	/** Alignment. */
1974	uint16_t u16Align;
1975	/** The user page index. */
1976	uint16_t aidx[3];
1977	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1978	uint16_t apte[3];
1979	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1980	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1981	#pragma pack()
1982
1983
1984	/**
1985	* The kind of page that's being shadowed.
1986	*/
1987	typedef enum PGMPOOLKIND
1988	{
1989	/** The virtual invalid 0 entry. */
1990	PGMPOOLKIND_INVALID = 0,
1991	/** The entry is free (=unused). */
1992	PGMPOOLKIND_FREE,
1993
1994	/** Shw: 32-bit page table; Gst: no paging. */
1995	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1996	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1997	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1998	/** Shw: 32-bit page table; Gst: 4MB page. */
1999	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2000	/** Shw: PAE page table; Gst: no paging. */
2001	PGMPOOLKIND_PAE_PT_FOR_PHYS,
2002	/** Shw: PAE page table; Gst: 32-bit page table. */
2003	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2004	/** Shw: PAE page table; Gst: Half of a 4MB page. */
2005	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2006	/** Shw: PAE page table; Gst: PAE page table. */
2007	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2008	/** Shw: PAE page table; Gst: 2MB page. */
2009	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2010
2011	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2012	PGMPOOLKIND_32BIT_PD,
2013	/** Shw: 32-bit page directory. Gst: no paging. */
2014	PGMPOOLKIND_32BIT_PD_PHYS,
2015	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2016	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2017	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2018	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2019	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2020	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2021	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2022	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2023	/** Shw: PAE page directory; Gst: PAE page directory. */
2024	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2025	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2026	PGMPOOLKIND_PAE_PD_PHYS,
2027
2028	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2029	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2030	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2031	PGMPOOLKIND_PAE_PDPT,
2032	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2033	PGMPOOLKIND_PAE_PDPT_PHYS,
2034
2035	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2036	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2037	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
2038	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2039	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2040	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2041	/** Shw: 64-bit page directory table; Gst: no paging. */
2042	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2043
2044	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2045	PGMPOOLKIND_64BIT_PML4,
2046
2047	/** Shw: EPT page directory pointer table; Gst: no paging. */
2048	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2049	/** Shw: EPT page directory table; Gst: no paging. */
2050	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2051	/** Shw: EPT page table; Gst: no paging. */
2052	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2053
2054	/** Shw: Root Nested paging table. */
2055	PGMPOOLKIND_ROOT_NESTED,
2056
2057	/** Shw: EPT page table; Gst: EPT page table. */
2058	PGMPOOLKIND_EPT_PT_FOR_EPT_PT,
2059	/** Shw: EPT page table; Gst: 2MB page. */
2060	PGMPOOLKIND_EPT_PT_FOR_EPT_2MB,
2061	/** Shw: EPT page directory table; Gst: EPT page directory. */
2062	PGMPOOLKIND_EPT_PD_FOR_EPT_PD,
2063	/** Shw: EPT page directory pointer table; Gst: EPT page directory pointer table. */
2064	PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT,
2065	/** Shw: EPT PML4; Gst: EPT PML4. */
2066	PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4,
2067
2068	/** The last valid entry. */
2069	PGMPOOLKIND_LAST = PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4
2070	} PGMPOOLKIND;
2071
2072	/**
2073	* The access attributes of the page; only applies to big pages.
2074	*/
2075	typedef enum
2076	{
2077	PGMPOOLACCESS_DONTCARE = 0,
2078	PGMPOOLACCESS_USER_RW,
2079	PGMPOOLACCESS_USER_R,
2080	PGMPOOLACCESS_USER_RW_NX,
2081	PGMPOOLACCESS_USER_R_NX,
2082	PGMPOOLACCESS_SUPERVISOR_RW,
2083	PGMPOOLACCESS_SUPERVISOR_R,
2084	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2085	PGMPOOLACCESS_SUPERVISOR_R_NX
2086	} PGMPOOLACCESS;
2087
2088	/**
2089	* The tracking data for a page in the pool.
2090	*/
2091	typedef struct PGMPOOLPAGE
2092	{
2093	/** AVL node code with the (HC) physical address of this page. */
2094	AVLOHCPHYSNODECORE Core;
2095	/** Pointer to the R3 mapping of the page. */
2096	R3PTRTYPE(void *) pvPageR3;
2097	/** Pointer to the R0 mapping of the page. */
2098	R0PTRTYPE(void *) pvPageR0;
2099	/** The guest physical address. */
2100	RTGCPHYS GCPhys;
2101	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2102	uint8_t enmKind;
2103	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2104	uint8_t enmAccess;
2105	/** This supplements enmKind and enmAccess */
2106	bool fA20Enabled : 1;
2107
2108	/** Used to indicate that the page is zeroed. */
2109	bool fZeroed : 1;
2110	/** Used to indicate that a PT has non-global entries. */
2111	bool fSeenNonGlobal : 1;
2112	/** Used to indicate that we're monitoring writes to the guest page. */
2113	bool fMonitored : 1;
2114	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2115	* (All pages are in the age list.) */
2116	bool fCached : 1;
2117	/** This is used by the R3 access handlers when invoked by an async thread.
2118	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2119	bool volatile fReusedFlushPending : 1;
2120	/** Used to mark the page as dirty (write monitoring is temporarily
2121	* off). */
2122	bool fDirty : 1;
2123	bool fPadding1 : 1;
2124	bool fPadding2;
2125
2126	/** The index of this page. */
2127	uint16_t idx;
2128	/** The next entry in the list this page currently resides in.
2129	* It's either in the free list or in the GCPhys hash. */
2130	uint16_t iNext;
2131	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2132	uint16_t iUserHead;
2133	/** The number of present entries. */
2134	uint16_t cPresent;
2135	/** The first entry in the table which is present. */
2136	uint16_t iFirstPresent;
2137	/** The number of modifications to the monitored page. */
2138	uint16_t cModifications;
2139	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2140	uint16_t iModifiedNext;
2141	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2142	uint16_t iModifiedPrev;
2143	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2144	uint16_t iMonitoredNext;
2145	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2146	uint16_t iMonitoredPrev;
2147	/** The next page in the age list. */
2148	uint16_t iAgeNext;
2149	/** The previous page in the age list. */
2150	uint16_t iAgePrev;
2151	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2152	uint8_t idxDirtyEntry;
2153
2154	/** @name Access handler statistics to determine whether the guest is
2155	* (re)initializing a page table.
2156	* @{ */
2157	RTGCPTR GCPtrLastAccessHandlerRip;
2158	RTGCPTR GCPtrLastAccessHandlerFault;
2159	uint64_t cLastAccessHandler;
2160	/** @} */
2161	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2162	uint32_t volatile cLocked;
2163	#if GC_ARCH_BITS == 64
2164	uint32_t u32Alignment3;
2165	#endif
2166	# ifdef VBOX_STRICT
2167	RTGCPTR GCPtrDirtyFault;
2168	# endif
2169	} PGMPOOLPAGE;
2170	/** Pointer to a pool page. */
2171	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2172	/** Pointer to a const pool page. */
2173	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2174	/** Pointer to a pool page pointer. */
2175	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2176
2177
2178	/** The hash table size. */
2179	# define PGMPOOL_HASH_SIZE 0x8000
2180	/** The hash function. */
2181	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2182
2183
2184	/**
2185	* The shadow page pool instance data.
2186	*
2187	* It's all one big allocation made at init time, except for the
2188	* pages that is. The user nodes follows immediately after the
2189	* page structures.
2190	*/
2191	typedef struct PGMPOOL
2192	{
2193	/** The VM handle - R3 Ptr. */
2194	PVMR3 pVMR3;
2195	/** The VM handle - R0 Ptr. */
2196	R0PTRTYPE(PVMCC) pVMR0;
2197	/** The ring-3 pointer to this structure. */
2198	R3PTRTYPE(struct PGMPOOL *) pPoolR3;
2199	/** The ring-0 pointer to this structure. */
2200	R0PTRTYPE(struct PGMPOOL *) pPoolR0;
2201	/** The max pool size. This includes the special IDs. */
2202	uint16_t cMaxPages;
2203	/** The current pool size. */
2204	uint16_t cCurPages;
2205	/** The head of the free page list. */
2206	uint16_t iFreeHead;
2207	/* Padding. */
2208	uint16_t u16Padding;
2209	/** Head of the chain of free user nodes. */
2210	uint16_t iUserFreeHead;
2211	/** The number of user nodes we've allocated. */
2212	uint16_t cMaxUsers;
2213	/** The number of present page table entries in the entire pool. */
2214	uint32_t cPresent;
2215	/** Pointer to the array of user nodes - R3 pointer. */
2216	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2217	/** Pointer to the array of user nodes - R0 pointer. */
2218	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2219	/** Head of the chain of free phys ext nodes. */
2220	uint16_t iPhysExtFreeHead;
2221	/** The number of user nodes we've allocated. */
2222	uint16_t cMaxPhysExts;
2223	uint32_t u32Padding0b;
2224	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2225	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2226	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2227	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2228	/** Hash table for GCPhys addresses. */
2229	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2230	/** The head of the age list. */
2231	uint16_t iAgeHead;
2232	/** The tail of the age list. */
2233	uint16_t iAgeTail;
2234	/** Set if the cache is enabled. */
2235	bool fCacheEnabled;
2236	/** Alignment padding. */
2237	bool afPadding1[3];
2238	/** Head of the list of modified pages. */
2239	uint16_t iModifiedHead;
2240	/** The current number of modified pages. */
2241	uint16_t cModifiedPages;
2242	/** Alignment padding. */
2243	uint32_t u32Padding2;
2244	/** Physical access handler type registration handle. */
2245	PGMPHYSHANDLERTYPE hAccessHandlerType;
2246	/** Next available slot (in aDirtyPages). */
2247	uint32_t idxFreeDirtyPage;
2248	/** Number of active dirty pages. */
2249	uint32_t cDirtyPages;
2250	/** Array of current dirty pgm pool page indices. */
2251	uint16_t aidxDirtyPages[16];
2252	/** Array running in parallel to aidxDirtyPages with the page data. */
2253	struct
2254	{
2255	uint64_t aPage[512];
2256	} aDirtyPages[16];
2257
2258	/** The number of pages currently in use. */
2259	uint16_t cUsedPages;
2260	#ifdef VBOX_WITH_STATISTICS
2261	/** The high water mark for cUsedPages. */
2262	uint16_t cUsedPagesHigh;
2263	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2264	/** Profiling pgmPoolAlloc(). */
2265	STAMPROFILEADV StatAlloc;
2266	/** Profiling pgmR3PoolClearDoIt(). */
2267	STAMPROFILE StatClearAll;
2268	/** Profiling pgmR3PoolReset(). */
2269	STAMPROFILE StatR3Reset;
2270	/** Profiling pgmPoolFlushPage(). */
2271	STAMPROFILE StatFlushPage;
2272	/** Profiling pgmPoolFree(). */
2273	STAMPROFILE StatFree;
2274	/** Counting explicit flushes by PGMPoolFlushPage(). */
2275	STAMCOUNTER StatForceFlushPage;
2276	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2277	STAMCOUNTER StatForceFlushDirtyPage;
2278	/** Counting flushes for reused pages. */
2279	STAMCOUNTER StatForceFlushReused;
2280	/** Profiling time spent zeroing pages. */
2281	STAMPROFILE StatZeroPage;
2282	/** Profiling of pgmPoolTrackDeref. */
2283	STAMPROFILE StatTrackDeref;
2284	/** Profiling pgmTrackFlushGCPhysPT. */
2285	STAMPROFILE StatTrackFlushGCPhysPT;
2286	/** Profiling pgmTrackFlushGCPhysPTs. */
2287	STAMPROFILE StatTrackFlushGCPhysPTs;
2288	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2289	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2290	/** Number of times we've been out of user records. */
2291	STAMCOUNTER StatTrackFreeUpOneUser;
2292	/** Nr of flushed entries. */
2293	STAMCOUNTER StatTrackFlushEntry;
2294	/** Nr of updated entries. */
2295	STAMCOUNTER StatTrackFlushEntryKeep;
2296	/** Profiling deref activity related tracking GC physical pages. */
2297	STAMPROFILE StatTrackDerefGCPhys;
2298	/** Number of linear searches for a HCPhys in the ram ranges. */
2299	STAMCOUNTER StatTrackLinearRamSearches;
2300	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2301	STAMCOUNTER StamTrackPhysExtAllocFailures;
2302
2303	/** Profiling the RC/R0 \#PF access handler. */
2304	STAMPROFILE StatMonitorPfRZ;
2305	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2306	STAMPROFILE StatMonitorPfRZHandled;
2307	/** Times we've failed interpreting the instruction. */
2308	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2309	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2310	STAMPROFILE StatMonitorPfRZFlushPage;
2311	/** Times we've detected a page table reinit. */
2312	STAMCOUNTER StatMonitorPfRZFlushReinit;
2313	/** Counting flushes for pages that are modified too often. */
2314	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2315	/** Times we've detected fork(). */
2316	STAMCOUNTER StatMonitorPfRZFork;
2317	/** Times we've failed interpreting a patch code instruction. */
2318	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2319	/** Times we've failed interpreting a patch code instruction during flushing. */
2320	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2321	/** The number of times we've seen rep prefixes we can't handle. */
2322	STAMCOUNTER StatMonitorPfRZRepPrefix;
2323	/** Profiling the REP STOSD cases we've handled. */
2324	STAMPROFILE StatMonitorPfRZRepStosd;
2325
2326	/** Profiling the R0/RC regular access handler. */
2327	STAMPROFILE StatMonitorRZ;
2328	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2329	STAMPROFILE StatMonitorRZFlushPage;
2330	/** Per access size counts indexed by size minus 1, last for larger. */
2331	STAMCOUNTER aStatMonitorRZSizes[16+3];
2332	/** Missaligned access counts indexed by offset - 1. */
2333	STAMCOUNTER aStatMonitorRZMisaligned[7];
2334
2335	/** Nr of handled PT faults. */
2336	STAMCOUNTER StatMonitorRZFaultPT;
2337	/** Nr of handled PD faults. */
2338	STAMCOUNTER StatMonitorRZFaultPD;
2339	/** Nr of handled PDPT faults. */
2340	STAMCOUNTER StatMonitorRZFaultPDPT;
2341	/** Nr of handled PML4 faults. */
2342	STAMCOUNTER StatMonitorRZFaultPML4;
2343
2344	/** Profiling the R3 access handler. */
2345	STAMPROFILE StatMonitorR3;
2346	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2347	STAMPROFILE StatMonitorR3FlushPage;
2348	/** Per access size counts indexed by size minus 1, last for larger. */
2349	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2350	/** Missaligned access counts indexed by offset - 1. */
2351	STAMCOUNTER aStatMonitorR3Misaligned[7];
2352	/** Nr of handled PT faults. */
2353	STAMCOUNTER StatMonitorR3FaultPT;
2354	/** Nr of handled PD faults. */
2355	STAMCOUNTER StatMonitorR3FaultPD;
2356	/** Nr of handled PDPT faults. */
2357	STAMCOUNTER StatMonitorR3FaultPDPT;
2358	/** Nr of handled PML4 faults. */
2359	STAMCOUNTER StatMonitorR3FaultPML4;
2360
2361	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2362	STAMCOUNTER StatResetDirtyPages;
2363	/** Times we've called pgmPoolAddDirtyPage. */
2364	STAMCOUNTER StatDirtyPage;
2365	/** Times we've had to flush duplicates for dirty page management. */
2366	STAMCOUNTER StatDirtyPageDupFlush;
2367	/** Times we've had to flush because of overflow. */
2368	STAMCOUNTER StatDirtyPageOverFlowFlush;
2369
2370	/** The high water mark for cModifiedPages. */
2371	uint16_t cModifiedPagesHigh;
2372	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2373
2374	/** The number of cache hits. */
2375	STAMCOUNTER StatCacheHits;
2376	/** The number of cache misses. */
2377	STAMCOUNTER StatCacheMisses;
2378	/** The number of times we've got a conflict of 'kind' in the cache. */
2379	STAMCOUNTER StatCacheKindMismatches;
2380	/** Number of times we've been out of pages. */
2381	STAMCOUNTER StatCacheFreeUpOne;
2382	/** The number of cacheable allocations. */
2383	STAMCOUNTER StatCacheCacheable;
2384	/** The number of uncacheable allocations. */
2385	STAMCOUNTER StatCacheUncacheable;
2386	#else
2387	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2388	#endif
2389	/** Profiling PGMR0PoolGrow(). */
2390	STAMPROFILE StatGrow;
2391	/** The AVL tree for looking up a page by its HC physical address. */
2392	AVLOHCPHYSTREE HCPhysTree;
2393	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2394	/** Array of pages. (cMaxPages in length)
2395	* The Id is the index into thist array.
2396	*/
2397	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2398	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2399	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2400	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2401	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2402	#ifdef VBOX_WITH_STATISTICS
2403	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2404	#endif
2405	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2406
2407
2408	/** @def PGMPOOL_PAGE_2_PTR
2409	* Maps a pool page pool into the current context.
2410	*
2411	* @returns VBox status code.
2412	* @param a_pVM Pointer to the VM.
2413	* @param a_pPage The pool page.
2414	*
2415	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2416	* small page window employeed by that function. Be careful.
2417	* @remark There is no need to assert on the result.
2418	*/
2419	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2420	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2421	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2422	{
2423	RT_NOREF(pszCaller);
2424	AssertPtr(a_pPage);
2425	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2426	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2427	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2428	return a_pPage->CTX_SUFF(pvPage);
2429	}
2430	#else
2431	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2432	#endif
2433
2434
2435	/** @def PGMPOOL_PAGE_2_PTR_V2
2436	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2437	*
2438	* @returns VBox status code.
2439	* @param a_pVM Pointer to the VM.
2440	* @param a_pVCpu The current CPU.
2441	* @param a_pPage The pool page.
2442	*
2443	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2444	* small page window employeed by that function. Be careful.
2445	* @remark There is no need to assert on the result.
2446	*/
2447	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2448
2449
2450	/** @def PGMPOOL_PAGE_IS_NESTED
2451	* Checks whether the given pool page is a nested-guest pool page.
2452	*
2453	* @returns @c true if a nested-guest pool page, @c false otherwise.
2454	* @param a_pPage The pool page.
2455	* @todo We can optimize the conditionals later.
2456	*/
2457	#define PGMPOOL_PAGE_IS_NESTED(a_pPage) PGMPOOL_PAGE_IS_KIND_NESTED((a_pPage)->enmKind)
2458	#define PGMPOOL_PAGE_IS_KIND_NESTED(a_enmKind) ( (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_PT \
2459	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_2MB \
2460	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PD_FOR_EPT_PD \
2461	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT \
2462	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4)
2463
2464	/** @name Per guest page tracking data.
2465	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2466	* is to use more bits for it and split it up later on. But for now we'll play
2467	* safe and change as little as possible.
2468	*
2469	* The 16-bit word has two parts:
2470	*
2471	* The first 14-bit forms the @a idx field. It is either the index of a page in
2472	* the shadow page pool, or and index into the extent list.
2473	*
2474	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2475	* shadow page pool references to the page. If cRefs equals
2476	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2477	* (misnomer) table and not the shadow page pool.
2478	*
2479	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2480	* the 16-bit word.
2481	*
2482	* @{ */
2483	/** The shift count for getting to the cRefs part. */
2484	#define PGMPOOL_TD_CREFS_SHIFT 14
2485	/** The mask applied after shifting the tracking data down by
2486	* PGMPOOL_TD_CREFS_SHIFT. */
2487	#define PGMPOOL_TD_CREFS_MASK 0x3
2488	/** The cRefs value used to indicate that the idx is the head of a
2489	* physical cross reference list. */
2490	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2491	/** The shift used to get idx. */
2492	#define PGMPOOL_TD_IDX_SHIFT 0
2493	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2494	#define PGMPOOL_TD_IDX_MASK 0x3fff
2495	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2496	* simply too many mappings of this page. */
2497	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2498
2499	/** @def PGMPOOL_TD_MAKE
2500	* Makes a 16-bit tracking data word.
2501	*
2502	* @returns tracking data.
2503	* @param cRefs The @a cRefs field. Must be within bounds!
2504	* @param idx The @a idx field. Must also be within bounds! */
2505	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2506
2507	/** @def PGMPOOL_TD_GET_CREFS
2508	* Get the @a cRefs field from a tracking data word.
2509	*
2510	* @returns The @a cRefs field
2511	* @param u16 The tracking data word.
2512	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2513	* non-zero @a u16. */
2514	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2515
2516	/** @def PGMPOOL_TD_GET_IDX
2517	* Get the @a idx field from a tracking data word.
2518	*
2519	* @returns The @a idx field
2520	* @param u16 The tracking data word. */
2521	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2522	/** @} */
2523
2524	#endif /* !VBOX_WITH_ONLY_PGM_NEM_MODE - No pool in NEM-only mode! */
2525
2526
2527
2528	/** @name A20 gate macros
2529	* @{ */
2530	#if defined(VBOX_VMM_TARGET_X86) \|\| defined(DOXYGEN_RUNNING)
2531	# define PGM_WITH_A20
2532	#elif !defined(VBOX_VMM_TARGET_ARMV8) && !defined(IN_TSTVMSTRUCT)
2533	# error "Misconfig"
2534	#endif
2535	#ifdef PGM_WITH_A20
2536	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2537	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2538	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2539	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2540	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2541	#else
2542	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2543	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2544	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2545	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2546	#endif
2547	/** @} */
2548
2549
2550	/**
2551	* Guest page table walk for the AMD64 mode.
2552	*/
2553	typedef struct PGMPTWALKGSTAMD64
2554	{
2555	PX86PML4 pPml4;
2556	PX86PML4E pPml4e;
2557	X86PML4E Pml4e;
2558
2559	PX86PDPT pPdpt;
2560	PX86PDPE pPdpe;
2561	X86PDPE Pdpe;
2562
2563	PX86PDPAE pPd;
2564	PX86PDEPAE pPde;
2565	X86PDEPAE Pde;
2566
2567	PX86PTPAE pPt;
2568	PX86PTEPAE pPte;
2569	X86PTEPAE Pte;
2570	} PGMPTWALKGSTAMD64;
2571	/** Pointer to a AMD64 guest page table walk. */
2572	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2573	/** Pointer to a const AMD64 guest page table walk. */
2574	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2575
2576	/**
2577	* Guest page table walk for the EPT mode.
2578	*/
2579	typedef struct PGMPTWALKGSTEPT
2580	{
2581	PEPTPML4 pPml4;
2582	PEPTPML4E pPml4e;
2583	EPTPML4E Pml4e;
2584
2585	PEPTPDPT pPdpt;
2586	PEPTPDPTE pPdpte;
2587	EPTPDPTE Pdpte;
2588
2589	PEPTPD pPd;
2590	PEPTPDE pPde;
2591	EPTPDE Pde;
2592
2593	PEPTPT pPt;
2594	PEPTPTE pPte;
2595	EPTPTE Pte;
2596	} PGMPTWALKGSTEPT;
2597	/** Pointer to an EPT guest page table walk. */
2598	typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2599	/** Pointer to a const EPT guest page table walk. */
2600	typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2601
2602	/**
2603	* Guest page table walk for the PAE mode.
2604	*/
2605	typedef struct PGMPTWALKGSTPAE
2606	{
2607	PX86PDPT pPdpt;
2608	PX86PDPE pPdpe;
2609	X86PDPE Pdpe;
2610
2611	PX86PDPAE pPd;
2612	PX86PDEPAE pPde;
2613	X86PDEPAE Pde;
2614
2615	PX86PTPAE pPt;
2616	PX86PTEPAE pPte;
2617	X86PTEPAE Pte;
2618	} PGMPTWALKGSTPAE;
2619	/** Pointer to a PAE guest page table walk. */
2620	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2621	/** Pointer to a const AMD64 guest page table walk. */
2622	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2623
2624	/**
2625	* Guest page table walk for the 32-bit mode.
2626	*/
2627	typedef struct PGMPTWALKGST32BIT
2628	{
2629	PX86PD pPd;
2630	PX86PDE pPde;
2631	X86PDE Pde;
2632
2633	PX86PT pPt;
2634	PX86PTE pPte;
2635	X86PTE Pte;
2636	} PGMPTWALKGST32BIT;
2637	/** Pointer to a 32-bit guest page table walk. */
2638	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2639	/** Pointer to a const 32-bit guest page table walk. */
2640	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2641
2642	/**
2643	* Which part of PGMPTWALKGST that is valid.
2644	*/
2645	typedef enum PGMPTWALKGSTTYPE
2646	{
2647	/** Customary invalid 0 value. */
2648	PGMPTWALKGSTTYPE_INVALID = 0,
2649	/** PGMPTWALKGST::u.Amd64 is valid. */
2650	PGMPTWALKGSTTYPE_AMD64,
2651	/** PGMPTWALKGST::u.Pae is valid. */
2652	PGMPTWALKGSTTYPE_PAE,
2653	/** PGMPTWALKGST::u.Legacy is valid. */
2654	PGMPTWALKGSTTYPE_32BIT,
2655	/** PGMPTWALKGST::u.Ept is valid. */
2656	PGMPTWALKGSTTYPE_EPT,
2657	/** Customary 32-bit type hack. */
2658	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2659	} PGMPTWALKGSTTYPE;
2660
2661	/**
2662	* Combined guest page table walk result.
2663	*/
2664	typedef struct PGMPTWALKGST
2665	{
2666	union
2667	{
2668	/** The page walker for AMD64. */
2669	PGMPTWALKGSTAMD64 Amd64;
2670	/** The page walker for PAE (32-bit). */
2671	PGMPTWALKGSTPAE Pae;
2672	/** The page walker for 32-bit paging (called legacy due to C naming
2673	* convension). */
2674	PGMPTWALKGST32BIT Legacy;
2675	/** The page walker for EPT (SLAT). */
2676	PGMPTWALKGSTEPT Ept;
2677	} u;
2678	/** Indicates which part of the union is valid. */
2679	PGMPTWALKGSTTYPE enmType;
2680	} PGMPTWALKGST;
2681	/** Pointer to a combined guest page table walk result. */
2682	typedef PGMPTWALKGST *PPGMPTWALKGST;
2683	/** Pointer to a read-only combined guest page table walk result. */
2684	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2685
2686
2687	/** @name Paging mode macros
2688	* @{
2689	*/
2690	#ifdef IN_RING3
2691	# define PGM_CTX(a,b) a##R3##b
2692	# define PGM_CTX_STR(a,b) a "R3" b
2693	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2694	#elif defined(IN_RING0)
2695	# define PGM_CTX(a,b) a##R0##b
2696	# define PGM_CTX_STR(a,b) a "R0" b
2697	# define PGM_CTX_DECL(type) VMMDECL(type)
2698	#else
2699	# error "Not IN_RING3 or IN_RING0!"
2700	#endif
2701
2702	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2703	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2704	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2705	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2706	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2707	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2708	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2709	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2710	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2711	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2712	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2713	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2714	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2715	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2716	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2717	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2718
2719	#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2720	#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2721	#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2722	#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2723
2724	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2725	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2726	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2727	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2728	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2729	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2730	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2731	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2732	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2733	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2734	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2735	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2736	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2737	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2738	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2739	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2740	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2741	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2742	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2743	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2744	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2745	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2746	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2747	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2748	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2749
2750	/* Shw_Gst */
2751	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2752	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2753	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2754	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2755	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2756	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2757	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2758	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2759	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2760	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2761	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2762	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2763	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2764	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2765	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2766	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2767	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2768	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2769	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2770	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2771	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2772	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2773	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2774	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2775	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2776	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2777	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2778	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2779	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2780	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2781	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2782	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2783	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2784	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2785
2786	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2787	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2788	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2789	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2790	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2791	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2792	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2793	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2794	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2795	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2796	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2797	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2798	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2799	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2800	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2801	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2802	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2803	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2804	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2805	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2806	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2807	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2808	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2809	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2810	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2811	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2812	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2813	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2814
2815	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2816	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2817	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2818	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2819	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2820	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2821	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2822	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2823	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2824	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2825	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2826	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2827	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2828	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2829	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2830	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2831	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2832	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2833	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2834	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2835	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2836	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2837	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2838	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2839	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2840	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2841	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2842	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2843	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2844
2845	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2846	/** @} */
2847
2848
2849	/**
2850	* Function pointers for guest paging.
2851	*/
2852	typedef struct PGMMODEDATAGST
2853	{
2854	/** The guest mode type. */
2855	uint32_t uType;
2856	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2857	DECLCALLBACKMEMBER(int, pfnQueryPageFast,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags, PPGMPTWALKFAST pWalk));
2858	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2859	#if defined(VBOX_VMM_TARGET_X86)
2860	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2861	#else
2862	DECLCALLBACKMEMBER(int, pfnWalk,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk));
2863	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu));
2864	#endif
2865	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2866	#if defined(VBOX_VMM_TARGET_X86) && defined(IN_RING3)
2867	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2868	#endif
2869	} PGMMODEDATAGST;
2870
2871	#if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
2872	/** The length of g_aPgmGuestModeData. */
2873	# if VBOX_WITH_64_BITS_GUESTS
2874	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2875	# else
2876	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2877	# endif
2878	#elif defined(VBOX_VMM_TARGET_ARMV8)
2879	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (128 + 2) /** @todo Find a better way to express that. */
2880	#else
2881	# error "Port me"
2882	#endif
2883	/** The guest mode data array. */
2884	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2885
2886
2887	#if defined(VBOX_VMM_TARGET_X86)
2888	/**
2889	* Function pointers for shadow paging.
2890	*/
2891	typedef struct PGMMODEDATASHW
2892	{
2893	/** The shadow mode type. */
2894	uint32_t uType;
2895	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2896	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2897	uint64_t fMask, uint32_t fOpFlags));
2898	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu));
2899	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2900	#ifdef IN_RING3
2901	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2902	#endif
2903	} PGMMODEDATASHW;
2904
2905	/** The length of g_aPgmShadowModeData. */
2906	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2907	/** The shadow mode data array. */
2908	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2909
2910
2911	/**
2912	* Function pointers for guest+shadow paging.
2913	*/
2914	typedef struct PGMMODEDATABTH
2915	{
2916	/** The shadow mode type. */
2917	uint32_t uShwType;
2918	/** The guest mode type. */
2919	uint32_t uGstType;
2920
2921	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2922	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2923	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2924	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2925	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2926	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2927	#ifndef IN_RING3
2928	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken));
2929	DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNested,
2930	bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
2931	bool *pfLockTaken));
2932	#endif
2933	#ifdef VBOX_STRICT
2934	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2935	#endif
2936	} PGMMODEDATABTH;
2937
2938	/** The length of g_aPgmBothModeData. */
2939	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2940	/** The guest+shadow mode data array. */
2941	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2942	#endif /* VBOX_VMM_TARGET_X86 */
2943
2944
2945	#ifdef VBOX_WITH_STATISTICS
2946	/**
2947	* PGM statistics.
2948	*/
2949	typedef struct PGMSTATS
2950	{
2951	/* R3 only: */
2952	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2953	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2954
2955	/* R3+RZ */
2956	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2957	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2958	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2959	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2960	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2961	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2962	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2963	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2964	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2965	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2966	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2967	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2968	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2969	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2970	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2971	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2972	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2973	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2974	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2975	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2976	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2977	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2978	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2979	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2980	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2981	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2982
2983	/* RC only: */
2984	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2985	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2986
2987	STAMCOUNTER StatRZPhysRead;
2988	STAMCOUNTER StatRZPhysReadBytes;
2989	STAMCOUNTER StatRZPhysWrite;
2990	STAMCOUNTER StatRZPhysWriteBytes;
2991	STAMCOUNTER StatR3PhysRead;
2992	STAMCOUNTER StatR3PhysReadBytes;
2993	STAMCOUNTER StatR3PhysWrite;
2994	STAMCOUNTER StatR3PhysWriteBytes;
2995	STAMCOUNTER StatRCPhysRead;
2996	STAMCOUNTER StatRCPhysReadBytes;
2997	STAMCOUNTER StatRCPhysWrite;
2998	STAMCOUNTER StatRCPhysWriteBytes;
2999
3000	STAMCOUNTER StatRZPhysSimpleRead;
3001	STAMCOUNTER StatRZPhysSimpleReadBytes;
3002	STAMCOUNTER StatRZPhysSimpleWrite;
3003	STAMCOUNTER StatRZPhysSimpleWriteBytes;
3004	STAMCOUNTER StatR3PhysSimpleRead;
3005	STAMCOUNTER StatR3PhysSimpleReadBytes;
3006	STAMCOUNTER StatR3PhysSimpleWrite;
3007	STAMCOUNTER StatR3PhysSimpleWriteBytes;
3008	STAMCOUNTER StatRCPhysSimpleRead;
3009	STAMCOUNTER StatRCPhysSimpleReadBytes;
3010	STAMCOUNTER StatRCPhysSimpleWrite;
3011	STAMCOUNTER StatRCPhysSimpleWriteBytes;
3012
3013	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
3014	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
3015	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
3016	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
3017	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
3018	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
3019	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
3020
3021	STAMPROFILE StatLargePageAlloc2; /*< Time spent setting up newly allocated large pages. /
3022	STAMPROFILE StatLargePageSetup; /*< Time spent setting up newly allocated large pages. /
3023	/** pgmPhysIsValidLargePage profiling - R3 */
3024	STAMPROFILE StatR3IsValidLargePage;
3025	/** pgmPhysIsValidLargePage profiling - RZ*/
3026	STAMPROFILE StatRZIsValidLargePage;
3027
3028	STAMPROFILE StatChunkAging;
3029	STAMPROFILE StatChunkFindCandidate;
3030	STAMPROFILE StatChunkUnmap;
3031	STAMPROFILE StatChunkMap;
3032	} PGMSTATS;
3033	#endif /* VBOX_WITH_STATISTICS */
3034
3035
3036	/**
3037	* PGM Data (part of VM)
3038	*/
3039	typedef struct PGM
3040	{
3041	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3042	/** The zero page. */
3043	uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
3044	/** The MMIO placeholder page. */
3045	uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
3046	#endif
3047
3048	/** @name RAM, MMIO2 and ROM ranges
3049	* @{ */
3050	/** The RAM range lookup table. */
3051	PGMRAMRANGELOOKUPENTRY aRamRangeLookup[PGM_MAX_RAM_RANGES];
3052	/** The ring-3 RAM range pointer table. */
3053	R3PTRTYPE(PPGMRAMRANGE) apRamRanges[PGM_MAX_RAM_RANGES];
3054	/** MMIO2 ranges. Indexed by idMmio2 minus 1. */
3055	PGMREGMMIO2RANGE aMmio2Ranges[PGM_MAX_MMIO2_RANGES];
3056	/** The ring-3 RAM range pointer table running parallel to aMmio2Ranges. */
3057	R3PTRTYPE(PPGMRAMRANGE) apMmio2RamRanges[PGM_MAX_MMIO2_RANGES];
3058	/** The ring-3 ROM range pointer table. */
3059	R3PTRTYPE(PPGMROMRANGE) apRomRanges[PGM_MAX_ROM_RANGES];
3060	/** Union of generation ID and lookup count. */
3061	union PGMRAMRANGEGENANDLOOKUPCOUNT
3062	{
3063	/* Combined view of both the generation ID and the count for atomic updating/reading. */
3064	uint64_t volatile u64Combined;
3065	RT_GCC_EXTENSION struct
3066	{
3067	/** Generation ID for the RAM ranges.
3068	* This member is incremented twice everytime a RAM range is mapped or
3069	* unmapped, so odd numbers means aRamRangeLookup is being modified and even
3070	* means the update has completed. */
3071	uint32_t volatile idGeneration;
3072	/** The number of active entries in aRamRangeLookup. */
3073	uint32_t volatile cLookupEntries;
3074	};
3075	} RamRangeUnion;
3076	/** The max RAM range ID (mirroring PGMR0PERVM::idRamRangeMax). */
3077	uint32_t idRamRangeMax;
3078	/** The number of MMIO2 ranges (serves as the next MMIO2 ID). */
3079	uint8_t cMmio2Ranges;
3080	/** The number of ROM ranges. */
3081	uint8_t cRomRanges;
3082	uint8_t abAlignment1[2];
3083	/** @} */
3084
3085	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3086	/** @name The zero page (abPagePg).
3087	* @{ */
3088	/** The host physical address of the zero page. */
3089	RTHCPHYS HCPhysZeroPg;
3090	/** @}*/
3091
3092	/** @name The Invalid MMIO page (abMmioPg).
3093	* This page is filled with 0xfeedface.
3094	* @{ */
3095	/** The host physical address of the invalid MMIO page. */
3096	RTHCPHYS HCPhysMmioPg;
3097	/** The host pysical address of the invalid MMIO page plus all invalid
3098	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3099	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3100	RTHCPHYS HCPhysInvMmioPg;
3101	/** @} */
3102	#endif
3103
3104	/** @cfgm{/RamPreAlloc, boolean, false}
3105	* Indicates whether the base RAM should all be allocated before starting
3106	* the VM (default), or if it should be allocated when first written to.
3107	* This has no effect in NEM-mode.
3108	*/
3109	bool fRamPreAlloc;
3110	#ifndef VBOX_WITH_PGM_NEM_MODE
3111	# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
3112	#elif defined(VBOX_WITH_ONLY_PGM_NEM_MODE)
3113	# define PGM_IS_IN_NEM_MODE(a_pVM) (true)
3114	#else
3115	/** Set if we're operating in NEM memory mode.
3116	*
3117	* NEM mode implies that memory is allocated in big chunks for each RAM range
3118	* rather than on demand page by page. Memory is also not locked and PGM has
3119	* therefore no physical addresses for them. Page sharing is out of the
3120	* question. Ballooning depends on the native execution engine, but probably
3121	* pointless as well. */
3122	bool fNemMode;
3123	# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
3124	#endif
3125	/** Indicates whether write monitoring is currently in use.
3126	* This is used to prevent conflicts between live saving and page sharing
3127	* detection. */
3128	bool fPhysWriteMonitoringEngaged;
3129	/** Set if the CPU has less than 52-bit physical address width.
3130	* This is used */
3131	bool fLessThan52PhysicalAddressBits;
3132	/** Set when nested paging is active.
3133	* This is meant to save calls to HMIsNestedPagingActive and let the
3134	* compilers optimize the code better. Whether we use nested paging or
3135	* not is something we find out during VMM initialization and we won't
3136	* change this later on. */
3137	bool fNestedPaging;
3138	/** We're not in a state which permits writes to guest memory.
3139	* (Only used in strict builds.) */
3140	bool fNoMorePhysWrites;
3141	/** @cfgm{/PageFusionAllowed, boolean, false}
3142	* Whether page fusion is allowed. */
3143	bool fPageFusionAllowed;
3144	/** @cfgm{/PGM/PciPassThrough, boolean, false}
3145	* Whether PCI passthrough is enabled. */
3146	bool fPciPassthrough;
3147	/** Restore original ROM page content when resetting after loading state.
3148	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3149	* enables the VM to start using an updated ROM without requiring powering
3150	* down the VM, just rebooting or resetting it. */
3151	bool fRestoreRomPagesOnReset;
3152	/** Whether to automatically clear all RAM pages on reset. */
3153	bool fZeroRamPagesOnReset;
3154	/** Large page enabled flag. */
3155	bool fUseLargePages;
3156	/** Alignment padding. */
3157	#if !defined(VBOX_WITH_PGM_NEM_MODE) \|\| defined(VBOX_WITH_ONLY_PGM_NEM_MODE)
3158	bool afAlignment2[2];
3159	#else
3160	bool afAlignment2[1];
3161	#endif
3162	/** The host paging mode. (This is what SUPLib reports.) */
3163	SUPPAGINGMODE enmHostMode;
3164
3165	/** Physical access handler type for ROM protection. */
3166	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3167	/** Physical access handler type for MMIO2 dirty page tracing. */
3168	PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
3169
3170	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3171	RTGCPHYS GCPhys4MBPSEMask;
3172	/** Mask containing the invalid bits of a guest physical address.
3173	* @remarks this does not stop at bit 52. */
3174	RTGCPHYS GCPhysInvAddrMask;
3175
3176
3177	/** RAM range TLB for R3. */
3178	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlb[PGM_RAMRANGE_TLB_ENTRIES];
3179	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3180	/** Shadow Page Pool - R3 Ptr. */
3181	R3PTRTYPE(PPGMPOOL) pPoolR3;
3182	#else
3183	RTR3PTR ReservedPoolR3;
3184	#endif
3185
3186	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3187	/** Shadow Page Pool - R0 Ptr. */
3188	R0PTRTYPE(PPGMPOOL) pPoolR0;
3189	#else
3190	RTR0PTR ReservedPoolR0;
3191	#endif
3192
3193	/** Hack: Number of deprecated page mapping locks taken by the current lock
3194	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3195	uint32_t cDeprecatedPageLocks;
3196
3197	/** Registered physical access handler types. */
3198	uint32_t cPhysHandlerTypes;
3199	/** Physical access handler types.
3200	* Initialized to callback causing guru meditations and invalid enmKind. */
3201	PGMPHYSHANDLERTYPEINTR3 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3202	/** Physical handler allocator, ring-3 edition. */
3203	#ifdef IN_RING3
3204	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3205	#else
3206	RTCHardAvlTreeSlabAllocatorR3_T PhysHandlerAllocator;
3207	#endif
3208	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3209	R3PTRTYPE(PPGMPHYSHANDLERTREE) pPhysHandlerTree;
3210	/** Caching the last physical handler we looked. */
3211	uint32_t idxLastPhysHandler;
3212
3213	uint32_t au32Padding3[9];
3214	#ifdef VBOX_WITH_ONLY_PGM_NEM_MODE
3215	uint64_t au64Padding4[3];
3216	#endif
3217
3218	/** PGM critical section.
3219	* This protects the physical, ram ranges, and the page flag updating (some of
3220	* it anyway).
3221	*/
3222	PDMCRITSECT CritSectX;
3223
3224	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3225	/**
3226	* Data associated with managing the ring-3 mappings of the allocation chunks.
3227	*/
3228	struct
3229	{
3230	/** The chunk mapping TLB. */
3231	PGMCHUNKR3MAPTLB Tlb;
3232	/** The chunk tree, ordered by chunk id. */
3233	R3PTRTYPE(PAVLU32NODECORE) pTree;
3234	# if HC_ARCH_BITS == 32
3235	uint32_t u32Alignment0;
3236	# endif
3237	/** The number of mapped chunks. */
3238	uint32_t c;
3239	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3240	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3241	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3242	uint32_t cMax;
3243	/** The current time. This is incremented whenever a chunk is inserted. */
3244	uint32_t iNow;
3245	/** Alignment padding. */
3246	uint32_t au32Alignment1[3];
3247	} ChunkR3Map;
3248	#endif
3249
3250	/** The page mapping TLB for ring-3. */
3251	PGMPAGER3MAPTLB PhysTlbR3;
3252	/** The page mapping TLB for ring-0. */
3253	PGMPAGER0MAPTLB PhysTlbR0;
3254
3255	/** The number of handy pages. */
3256	uint32_t cHandyPages;
3257
3258	/** The number of large handy pages. */
3259	uint32_t cLargeHandyPages;
3260
3261	/**
3262	* Array of handy pages.
3263	*
3264	* This array is used in a two way communication between pgmPhysAllocPage
3265	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3266	* an intermediary.
3267	*
3268	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3269	* (The current size of 32 pages, means 128 KB of handy memory.)
3270	*/
3271	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3272
3273	/**
3274	* Array of large handy pages. (currently size 1)
3275	*
3276	* This array is used in a two way communication between pgmPhysAllocLargePage
3277	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3278	* an intermediary.
3279	*/
3280	GMMPAGEDESC aLargeHandyPage[1];
3281	/** When to try allocate large pages again after a failure. */
3282	uint64_t nsLargePageRetry;
3283	/** Number of repeated long allocation times. */
3284	uint32_t cLargePageLongAllocRepeats;
3285	uint32_t uPadding4;
3286
3287	/**
3288	* Live save data.
3289	*/
3290	struct
3291	{
3292	/** Per type statistics. */
3293	struct
3294	{
3295	/** The number of ready pages. */
3296	uint32_t cReadyPages;
3297	/** The number of dirty pages. */
3298	uint32_t cDirtyPages;
3299	/** The number of ready zero pages. */
3300	uint32_t cZeroPages;
3301	/** The number of write monitored pages. */
3302	uint32_t cMonitoredPages;
3303	} Rom,
3304	Mmio2,
3305	Ram;
3306	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3307	uint32_t cIgnoredPages;
3308	/** Indicates that a live save operation is active. */
3309	bool fActive;
3310	/** Padding. */
3311	bool afReserved[2];
3312	/** The next history index. */
3313	uint8_t iDirtyPagesHistory;
3314	/** History of the total amount of dirty pages. */
3315	uint32_t acDirtyPagesHistory[64];
3316	/** Short term dirty page average. */
3317	uint32_t cDirtyPagesShort;
3318	/** Long term dirty page average. */
3319	uint32_t cDirtyPagesLong;
3320	/** The number of saved pages. This is used to get some kind of estimate of the
3321	* link speed so we can decide when we're done. It is reset after the first
3322	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3323	* zero pages. */
3324	uint64_t cSavedPages;
3325	/** The nanosecond timestamp when cSavedPages was 0. */
3326	uint64_t uSaveStartNS;
3327	/** Pages per second (for statistics). */
3328	uint32_t cPagesPerSecond;
3329	uint32_t cAlignment;
3330	} LiveSave;
3331
3332	/** @name Error injection.
3333	* @{ */
3334	/** Inject handy page allocation errors pretending we're completely out of
3335	* memory. */
3336	bool volatile fErrInjHandyPages;
3337	/** Padding. */
3338	bool afReserved[3];
3339	/** @} */
3340
3341	/** @name Release Statistics
3342	* @{ */
3343	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3344	uint32_t cPrivatePages; /*< The number of private pages. /
3345	uint32_t cSharedPages; /*< The number of shared pages. /
3346	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3347	uint32_t cZeroPages; /*< The number of zero backed pages. /
3348	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3349	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3350	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3351	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3352	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3353	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3354	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3355	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3356	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3357	#endif
3358	uint32_t cLargePages; /*< The number of large pages. /
3359	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3360	/* uint32_t aAlignment4[1]; */
3361
3362	STAMPROFILE StatLargePageAlloc; /*< Time spent by the host OS for large page allocation. /
3363	STAMCOUNTER StatLargePageAllocFailed; /*< Count allocation failures. /
3364	STAMCOUNTER StatLargePageOverflow; /*< The number of times allocating a large pages takes more than the allowed period. /
3365	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3366	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3367	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3368	STAMCOUNTER StatLargePageTlbFlush; /*< The number of a full VCPU TLB flush was required after allocation. /
3369	STAMCOUNTER StatLargePageZeroEvict; /*< The number of zero page mappings we had to evict when allocating a large page. /
3370
3371	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3372
3373	STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /*< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. /
3374	/** @} */
3375
3376	#ifdef VBOX_WITH_STATISTICS
3377	/** These are optional statistics that used to be on the hyper heap. */
3378	PGMSTATS Stats;
3379	#endif
3380	} PGM;
3381	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3382	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3383	AssertCompileMemberAlignment(PGM, CritSectX, 16);
3384	AssertCompileMemberAlignment(PGM, CritSectX, 32);
3385	AssertCompileMemberAlignment(PGM, CritSectX, 64);
3386	AssertCompileMemberAlignment(PGM, PhysTlbR3, 8);
3387	AssertCompileMemberAlignment(PGM, PhysTlbR3, 16);
3388	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32);
3389	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3390	# ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3391	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3392	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3393	# endif
3394	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3395	#endif /* !IN_TSTVMSTRUCTGC */
3396	/** Pointer to the PGM instance data. */
3397	typedef PGM *PPGM;
3398
3399
3400	#ifdef VBOX_WITH_STATISTICS
3401	/**
3402	* Per CPU statistis for PGM (used to be on the heap).
3403	*/
3404	typedef struct PGMCPUSTATS
3405	{
3406	/* Common */
3407	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3408	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3409
3410	/* R0 only: */
3411	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3412	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3413
3414	/* RZ only: */
3415	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3416	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3417	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3418	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3419	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3420	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3421	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3422	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3423	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3424	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3425	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3426	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3427	STAMPROFILE StatRZTrap0eTime2PageZeroing; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a zero page that is being zeroed. /
3428	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3429	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3430	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3431	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3432	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3433	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3434	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3435	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3436	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3437	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3438	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3439	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3440	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3441	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3442	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3443	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3444	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3445	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3446	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3447	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3448	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3449	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3450	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3451	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3452	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3453	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3454	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3455	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3456	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3457	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3458	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3459	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3460	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3461	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3462	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3463	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3464	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3465	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3466	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3467	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3468	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3469	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3470	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3471	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3472	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3473	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3474	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3475	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3476	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3477	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3478	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3479	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3480	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3481	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3482	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3483	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3484	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3485
3486	/* HC - R3 and (maybe) R0: */
3487
3488	/* RZ & R3: */
3489	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3490	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3491	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3492	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3493	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3494	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3495	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3496	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3497	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3498	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3499	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3500	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3501	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3502	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3503	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3504	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3505	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3506	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3507	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3508	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3509	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3510	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3511	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3512	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3513	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3514	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3515	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3516	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3517	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3518	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3519	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3520	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3521	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3522	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3523	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3524	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3525	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3526	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3527	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3528	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3529	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3530	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3531	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3532	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3533	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3534	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3535	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3536	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits (lockless). /
3537	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Page mapper TLB hits (lockless). /
3538
3539	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3540	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3541	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3542	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3543	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3544	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3545	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3546	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3547	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3548	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3549	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3550	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3551	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3552	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3553	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3554	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3555	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3556	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3557	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3558	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3559	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3560	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3561	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3562	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3563	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3564	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3565	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3566	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3567	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3568	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3569	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3570	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3571	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3572	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3573	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3574	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3575	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3576	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3577	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3578	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3579	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3580	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3581	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3582	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3583	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3584	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3585	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits (lockless). /
3586	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Page mapper TLB hits (lockless). /
3587	} PGMCPUSTATS;
3588	#endif /* VBOX_WITH_STATISTICS */
3589
3590
3591	/**
3592	* PGMCPU Data (part of VMCPU).
3593	*/
3594	typedef struct PGMCPU
3595	{
3596	#if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
3597	/** A20 gate mask.
3598	* Our current approach to A20 emulation is to let REM do it and don't bother
3599	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3600	* But whould need arrise, we'll subject physical addresses to this mask. */
3601	RTGCPHYS GCPhysA20Mask;
3602	/** A20 gate state - boolean! */
3603	bool fA20Enabled;
3604	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3605	bool fNoExecuteEnabled;
3606	/** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3607	* active. */
3608	bool fPaePdpesAndCr3MappedR3;
3609	bool fPaePdpesAndCr3MappedR0;
3610
3611	/** What needs syncing (PGM_SYNC_*).
3612	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3613	* PGMFlushTLB, and PGMR3Load. */
3614	uint32_t fSyncFlags;
3615
3616	/** The shadow paging mode. */
3617	PGMMODE enmShadowMode;
3618	/** The guest paging mode. */
3619	PGMMODE enmGuestMode;
3620	/** The guest second level address translation mode. */
3621	PGMSLAT enmGuestSlatMode;
3622	/** Guest mode data table index (PGM_TYPE_XXX). */
3623	uint8_t volatile idxGuestModeData;
3624	/** Shadow mode data table index (PGM_TYPE_XXX). */
3625	uint8_t volatile idxShadowModeData;
3626	/** Both mode data table index (complicated). */
3627	uint8_t volatile idxBothModeData;
3628	/** Alignment padding. */
3629	uint8_t abPadding[1];
3630
3631	/** The guest CR3.
3632	* When SLAT is active, this is the translated physical address.
3633	* When SLAT is inactive, this is the physical address in CR3. */
3634	RTGCPHYS GCPhysCR3;
3635
3636	/** The nested-guest CR3.
3637	* When SLAT is active, this is CR3 prior to translation.
3638	* When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3639	RTGCPHYS GCPhysNstGstCR3;
3640
3641	/** The cached guest CR3 when it has been mapped in PAE mode.
3642	* This allows us to skip remapping the CR3 and PAE PDPEs
3643	* (in PGMFlushTLB or similar) when it was already done as
3644	* part of MOV CRx instruction emulation.
3645	*/
3646	RTGCPHYS GCPhysPaeCR3;
3647
3648	/** @name 32-bit Guest Paging.
3649	* @{ */
3650	/** The guest's page directory, R3 pointer. */
3651	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3652	/** The guest's page directory, R0 pointer. */
3653	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3654	/** Mask containing the MBZ bits of a big page PDE. */
3655	uint32_t fGst32BitMbzBigPdeMask;
3656	/** Set if the page size extension (PSE) is enabled. */
3657	bool fGst32BitPageSizeExtension;
3658	/** Alignment padding. */
3659	bool afAlignment2[3];
3660	/** @} */
3661
3662	/** @name PAE Guest Paging.
3663	* @{ */
3664	/** The guest's page directory pointer table, R3 pointer. */
3665	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3666	/** The guest's page directory pointer table, R0 pointer. */
3667	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3668
3669	/** The guest's page directories, R3 pointers.
3670	* These are individual pointers and don't have to be adjacent.
3671	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3672	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3673	/** The guest's page directories, R0 pointers.
3674	* Same restrictions as apGstPaePDsR3. */
3675	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3676	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3677	RTGCPHYS aGCPhysGstPaePDs[4];
3678	/** Mask containing the MBZ PTE bits. */
3679	uint64_t fGstPaeMbzPteMask;
3680	/** Mask containing the MBZ PDE bits. */
3681	uint64_t fGstPaeMbzPdeMask;
3682	/** Mask containing the MBZ big page PDE bits. */
3683	uint64_t fGstPaeMbzBigPdeMask;
3684	/** Mask containing the MBZ PDPE bits. */
3685	uint64_t fGstPaeMbzPdpeMask;
3686	/** @} */
3687
3688	/** @name AMD64 Guest Paging.
3689	* @{ */
3690	/** The guest's page directory pointer table, R3 pointer. */
3691	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3692	/** The guest's page directory pointer table, R0 pointer. */
3693	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3694	/** Mask containing the MBZ PTE bits. */
3695	uint64_t fGstAmd64MbzPteMask;
3696	/** Mask containing the MBZ PDE bits. */
3697	uint64_t fGstAmd64MbzPdeMask;
3698	/** Mask containing the MBZ big page PDE bits. */
3699	uint64_t fGstAmd64MbzBigPdeMask;
3700	/** Mask containing the MBZ PDPE bits. */
3701	uint64_t fGstAmd64MbzPdpeMask;
3702	/** Mask containing the MBZ big page PDPE bits. */
3703	uint64_t fGstAmd64MbzBigPdpeMask;
3704	/** Mask containing the MBZ PML4E bits. */
3705	uint64_t fGstAmd64MbzPml4eMask;
3706	/** Mask containing the PDPE bits that we shadow. */
3707	uint64_t fGstAmd64ShadowedPdpeMask;
3708	/** Mask containing the PML4E bits that we shadow. */
3709	uint64_t fGstAmd64ShadowedPml4eMask;
3710	/** @} */
3711
3712	/** @name PAE and AMD64 Guest Paging.
3713	* @{ */
3714	/** Mask containing the PTE bits that we shadow. */
3715	uint64_t fGst64ShadowedPteMask;
3716	/** Mask containing the PDE bits that we shadow. */
3717	uint64_t fGst64ShadowedPdeMask;
3718	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3719	uint64_t fGst64ShadowedBigPdeMask;
3720	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3721	uint64_t fGst64ShadowedBigPde4PteMask;
3722	/** @} */
3723
3724	/** @name EPT Guest Paging.
3725	* @{ */
3726	/** The guest's EPT PML4 table, R3 pointer. */
3727	R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3728	/** The guest's EPT PML4 table, R0 pointer. */
3729	R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3730	/** The guest's EPT pointer (copy of virtual VMCS). */
3731	uint64_t uEptPtr;
3732	/** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3733	* change through the lifetime of the VM. */
3734	uint64_t uEptVpidCapMsr;
3735	/** Mask containing the MBZ PTE bits. */
3736	uint64_t fGstEptMbzPteMask;
3737	/** Mask containing the MBZ PDE bits. */
3738	uint64_t fGstEptMbzPdeMask;
3739	/** Mask containing the MBZ big page (2M) PDE bits. */
3740	uint64_t fGstEptMbzBigPdeMask;
3741	/** Mask containing the MBZ PDPTE bits. */
3742	uint64_t fGstEptMbzPdpteMask;
3743	/** Mask containing the MBZ big page (1G) PDPTE bits. */
3744	uint64_t fGstEptMbzBigPdpteMask;
3745	/** Mask containing the MBZ PML4E bits. */
3746	uint64_t fGstEptMbzPml4eMask;
3747	/** Mask to determine whether an entry is present. */
3748	uint64_t fGstEptPresentMask;
3749
3750	/** Mask containing the EPT PTE bits we shadow. */
3751	uint64_t fGstEptShadowedPteMask;
3752	/** Mask containing the EPT PDE bits we shadow. */
3753	uint64_t fGstEptShadowedPdeMask;
3754	/** Mask containing the EPT PDE (2M) bits we shadow. */
3755	uint64_t fGstEptShadowedBigPdeMask;
3756	/** Mask containing the EPT PDPTE bits we shadow. */
3757	uint64_t fGstEptShadowedPdpteMask;
3758	/** Mask containing the EPT PML4E bits we shadow. */
3759	uint64_t fGstEptShadowedPml4eMask;
3760	/** @} */
3761
3762	# ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3763	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3764	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3765	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3766	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3767	# endif
3768
3769	/** For saving stack space, the disassembler state is allocated here instead of
3770	* on the stack. */
3771	DISSTATE Dis;
3772
3773	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3774	uint64_t cNetwareWp0Hacks;
3775	#elif defined(VBOX_VMM_TARGET_ARMV8)
3776	/** What needs syncing (PGM_SYNC_*).
3777	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3778	* PGMFlushTLB, and PGMR3Load. */
3779	uint32_t fSyncFlags;
3780
3781	/** The guest paging mode, indexed by the exception level (EL0 isn't used). */
3782	PGMMODE aenmGuestMode[3]; /** @todo Really necessary? */
3783	/** The cached SCTLR_ELx register (EL0 isn't used). */
3784	uint64_t au64RegSctlrEl[3];
3785	/** The cached TCR_ELx register (EL0 isn't used). */
3786	uint64_t au64RegTcrEl[3];
3787	/** Guest mode data table index for a page translation going through TTBR0_ELx (PGM_TYPE_XXX). */
3788	uint8_t volatile aidxGuestModeDataTtbr0[4];
3789	/** Guest mode data table index for a page translation going through TTBR1_ELx (PGM_TYPE_XXX). */
3790	uint8_t volatile aidxGuestModeDataTtbr1[4];
3791	/** The initial lookup mask for translations going through TTBR0_ELx. */
3792	uint64_t afLookupMaskTtbr0[4];
3793	/** The initial lookup mask for translations going through TTBR1_ELx. */
3794	uint64_t afLookupMaskTtbr1[4];
3795	#endif
3796
3797	/** Count the number of pgm pool access handler calls. */
3798	uint64_t cPoolAccessHandler;
3799
3800	/** Lockless RAM range TLB for R3. */
3801	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlb[PGM_RAMRANGE_TLB_ENTRIES];
3802
3803	/** Lockless page mapping TLB for R3. */
3804	PGMPAGER3MAPTLB PhysTlb;
3805
3806	/** @name Release Statistics
3807	* @{ */
3808	/** The number of times the guest has switched mode since last reset or statistics reset. */
3809	STAMCOUNTER cGuestModeChanges;
3810	/** The number of times the guest has switched mode since last reset or statistics reset. */
3811	STAMCOUNTER cA20Changes;
3812
3813	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses (lockless). /
3814	STAMCOUNTER StatRZRamRangeTlbLocking; /*< RC/R0: RAM range TLB lookup redone with locking. /
3815	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Page mapper TLB misses (lockless -> locked). /
3816
3817	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses (lockless). /
3818	STAMCOUNTER StatR3RamRangeTlbLocking; /*< R3: RAM range TLB lookup redone with locking. /
3819	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Page mapper TLB misses (lockless -> locked). /
3820	/** @} */
3821
3822	#ifdef VBOX_WITH_STATISTICS
3823	/** These are statistics that used to be on the hyper heap. */
3824	PGMCPUSTATS Stats;
3825	#endif
3826	} PGMCPU;
3827	/** Pointer to the per-cpu PGM data. */
3828	typedef PGMCPU *PPGMCPU;
3829
3830
3831	/** @name PGM::fSyncFlags Flags
3832	* @note Was part of saved state a long time ago.
3833	* @{
3834	*/
3835	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3836	/** Always sync CR3. */
3837	#define PGM_SYNC_ALWAYS RT_BIT(1)
3838	/** Check guest mapping in SyncCR3. */
3839	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3840	/** Clear the page pool (a light weight flush). */
3841	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3842	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3843	/** @} */
3844
3845
3846	#if defined(IN_RING0) \|\| defined(DOXYGEN_RUNNING)
3847
3848	/**
3849	* PGM GVMCPU instance data.
3850	*/
3851	typedef struct PGMR0PERVCPU
3852	{
3853	/** Lockless RAM range TLB for R0. */
3854	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlb[PGM_RAMRANGE_TLB_ENTRIES];
3855
3856	# ifdef VBOX_WITH_STATISTICS
3857	/** R0: Which statistic this \#PF should be attributed to. */
3858	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3859	# endif
3860	} PGMR0PERVCPU;
3861
3862
3863	/**
3864	* PGM GVM instance data.
3865	*/
3866	typedef struct PGMR0PERVM
3867	{
3868	/** @name RAM ranges
3869	* @{ */
3870	/** The ring-0 RAM range pointer table. */
3871	R0PTRTYPE(PPGMRAMRANGE) apRamRanges[PGM_MAX_RAM_RANGES];
3872	/** Trusted RAM range page counts running parallel to apRamRanges.
3873	* This keeps the original page count when a range is reduced,
3874	* only the PGMRAMRANGE::cb member is changed then. */
3875	uint32_t acRamRangePages[PGM_MAX_RAM_RANGES];
3876	/** The memory objects for the RAM ranges (parallel to apRamRanges). */
3877	RTR0MEMOBJ ahRamRangeMemObjs[PGM_MAX_RAM_RANGES];
3878	/** The ring-3 mapping objects for the RAM ranges (parallel to apRamRanges). */
3879	RTR0MEMOBJ ahRamRangeMapObjs[PGM_MAX_RAM_RANGES];
3880	/** The max RAM range ID (safe). */
3881	uint32_t idRamRangeMax;
3882	uint8_t abAlignment1[64 - sizeof(uint32_t)];
3883	/** RAM range TLB for R0. */
3884	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlb[PGM_RAMRANGE_TLB_ENTRIES];
3885	/** @} */
3886
3887	/** @name MMIO2 ranges
3888	* @{ */
3889	/** The ring-0 RAM range pointer table running parallel to aMmio2Ranges. */
3890	R0PTRTYPE(PPGMRAMRANGE) apMmio2RamRanges[PGM_MAX_MMIO2_RANGES];
3891	/** The memory objects for the MMIO2 backing memory (parallel to
3892	* apMmio2RamRanges). */
3893	RTR0MEMOBJ ahMmio2MemObjs[PGM_MAX_MMIO2_RANGES];
3894	/** The ring-3 mapping objects for the MMIO2 backing memory (parallel
3895	* to apMmio2RamRanges & ahMmio2MemObjs). */
3896	RTR0MEMOBJ ahMmio2MapObjs[PGM_MAX_MMIO2_RANGES];
3897	/** Trusted MMIO2 range sizes (count of guest pages).
3898	* This keeps the original page count when a range is reduced,
3899	* only the PGMRAMRANGE::cb member is changed then. */
3900	uint32_t acMmio2RangePages[PGM_MAX_MMIO2_RANGES];
3901	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3902	/** Pointer to the ring-0 mapping of the MMIO2 backings (parallel to
3903	* apMmio2RamRanges). */
3904	R0PTRTYPE(uint8_t *) apbMmio2Backing[PGM_MAX_MMIO2_RANGES];
3905	#endif
3906	/** @} */
3907
3908	/** @name ROM ranges
3909	* @{ */
3910	/** The ring-0 ROM range pointer table. */
3911	R0PTRTYPE(PPGMROMRANGE) apRomRanges[PGM_MAX_ROM_RANGES];
3912	/** The memory objects for each ROM range (parallel to apRomRanges). */
3913	RTR0MEMOBJ ahRomRangeMemObjs[PGM_MAX_ROM_RANGES];
3914	/** The ring-3 mapping objects for each ROM range (parallel to apRomRanges
3915	* & ahRamRangeMemObjs). */
3916	RTR0MEMOBJ ahRomRangeMapObjs[PGM_MAX_ROM_RANGES];
3917	/** Trusted ROM range sizes (count of guest pages). */
3918	uint32_t acRomRangePages[PGM_MAX_ROM_RANGES];
3919	/** @} */
3920
3921	# ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3922	/** @name PGM Pool related stuff.
3923	* @{ */
3924	/** Critical section for serializing pool growth. */
3925	RTCRITSECT PoolGrowCritSect;
3926	/** The memory objects for the pool pages. */
3927	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3928	/** The ring-3 mapping objects for the pool pages. */
3929	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3930	/** @} */
3931	# endif
3932
3933	/** Physical access handler types for ring-0.
3934	* Initialized to callback causing return to ring-3 and invalid enmKind. */
3935	PGMPHYSHANDLERTYPEINTR0 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3936	/** Physical handler allocator, ring-3 edition. */
3937	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3938	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3939	PPGMPHYSHANDLERTREE pPhysHandlerTree;
3940	/** The allocation object for the physical access handler tree. */
3941	RTR0MEMOBJ hPhysHandlerMemObj;
3942	/** The ring-3 mapping object for the physicall access handler tree. */
3943	RTR0MEMOBJ hPhysHandlerMapObj;
3944	} PGMR0PERVM;
3945
3946	#endif /* IN_RING0 \|\| DOXYGEN_RUNNING */
3947
3948	RT_C_DECLS_BEGIN
3949
3950	#if defined(VBOX_STRICT)
3951	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3952	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3953	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3954	#else
3955	int pgmLock(PVMCC pVM, bool fVoid);
3956	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3957	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3958	#endif
3959	void pgmUnlock(PVMCC pVM);
3960	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3961	/**
3962	* Asserts that the caller owns the PDM lock.
3963	* This is the internal variant of PGMIsLockOwner.
3964	* @param a_pVM Pointer to the VM.
3965	*/
3966	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3967	/**
3968	* Asserts that the caller owns the PDM lock.
3969	* This is the internal variant of PGMIsLockOwner.
3970	* @param a_pVM Pointer to the VM.
3971	* @param a_pVCpu The current CPU handle.
3972	*/
3973	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3974
3975	uint32_t pgmHandlerPhysicalCalcTableSizes(uint32_t pcEntries, uint32_t pcbTreeAndBitmap);
3976	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3977	R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3978	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3979	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3980	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3981	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3982	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3983	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3984	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam,
3985	bool fDoAccounting, bool fFlushIemTlbs);
3986	DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3987	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3988	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR3HandlerPhysicalHandlerInvalid;
3989	#ifndef IN_RING3
3990	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR0HandlerPhysicalHandlerToRing3;
3991	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmR0HandlerPhysicalPfHandlerToRing3;
3992	#endif
3993
3994	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3995
3996	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3997	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3998	#ifdef IN_RING0
3999	int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
4000	int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
4001	#endif
4002	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4003	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
4004	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4005	#ifdef IN_RING3
4006	DECLHIDDEN(int) pgmPhysPageLoadIntoLocklessTlbWithPage(PVMCPUCC pVCpu, PPGMPAGE pPage, RTGCPHYS GCPhys);
4007	#endif
4008	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4009	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4010	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4011	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4012	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4013	#if 0 /* unused */
4014	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4015	#endif
4016	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4017	int pgmPhysGCPhys2CCPtrLockless(PVMCPUCC pVCpu, RTGCPHYS GCPhys, void **ppv);
4018	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4019	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4020	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4021	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4022	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
4023	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4024	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
4025	#ifndef IN_RING3
4026	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4027	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
4028	#endif
4029	DECLHIDDEN(uint16_t) pgmPhysMmio2CalcChunkCount(RTGCPHYS cb, uint32_t *pcPagesPerChunk);
4030	DECLHIDDEN(int) pgmPhysMmio2RegisterWorker(PVMCC pVM, uint32_t const cGuestPages, uint8_t const idMmio2,
4031	const uint8_t cChunks, PPDMDEVINSR3 const pDevIns, uint8_t
4032	const iSubDev, uint8_t const iRegion, uint32_t const fFlags);
4033	DECLHIDDEN(int) pgmPhysMmio2DeregisterWorker(PVMCC pVM, uint8_t idMmio2, uint8_t cChunks, PPDMDEVINSR3 pDevIns);
4034	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
4035	PGMPAGETYPE enmNewType);
4036	#ifdef VBOX_STRICT
4037	DECLHIDDEN(bool) pgmPhysAssertRamRangesLocked(PVMCC pVM, bool fInUpdate, bool fRamRelaxed);
4038	#endif
4039	DECLHIDDEN(void) pgmR3PhysChunkInvalidateTLB(PVM pVM, bool fInRendezvous);
4040	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
4041	void pgmPhysInvalidatePageMapTLB(PVMCC pVM, bool fInRendezvous);
4042	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
4043	DECLHIDDEN(PPGMRAMRANGE) pgmPhysGetRangeSlow(PVMCC pVM, RTGCPHYS GCPhys);
4044	DECLHIDDEN(PPGMRAMRANGE) pgmPhysGetRangeAtOrAboveSlow(PVMCC pVM, RTGCPHYS GCPhys);
4045	DECLHIDDEN(PPGMPAGE) pgmPhysGetPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
4046	DECLHIDDEN(int) pgmPhysGetPageExSlow(PVMCC pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4047	DECLHIDDEN(int) pgmPhysGetPageAndRangeExSlow(PVMCC pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4048	DECLHIDDEN(int) pgmPhysGetPageAndRangeExSlowLockless(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
4049	PGMPAGE volatile ppPage, PGMRAMRANGE volatile ppRam);
4050	DECLHIDDEN(int) pgmPhysRamRangeAllocCommon(PVMCC pVM, uint32_t cPages, uint32_t fFlags, uint32_t *pidNewRange);
4051	DECLHIDDEN(int) pgmPhysRomRangeAllocCommon(PVMCC pVM, uint32_t cPages, uint8_t idRomRange, uint32_t fFlags);
4052	#ifdef VBOX_WITH_NATIVE_NEM
4053	DECLHIDDEN(void) pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
4054	#endif
4055
4056	#ifdef IN_RING3
4057	# ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
4058	int pgmR3PhysRamPreAllocate(PVM pVM);
4059	# endif
4060	int pgmR3PhysRamReset(PVM pVM);
4061	int pgmR3PhysRomReset(PVM pVM);
4062	int pgmR3PhysRamZeroAll(PVM pVM);
4063	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4064	int pgmR3PhysRamTerm(PVM pVM);
4065	void pgmR3PhysRomTerm(PVM pVM);
4066	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4067
4068	# ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
4069	int pgmR3PoolInit(PVM pVM);
4070	void pgmR3PoolRelocate(PVM pVM);
4071	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4072	void pgmR3PoolReset(PVM pVM);
4073	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4074	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4075	void pgmR3PoolWriteProtectPages(PVM pVM);
4076	# endif
4077
4078	#endif /* IN_RING3 */
4079	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
4080	# ifdef IN_RING0
4081	int pgmR0PoolInitVM(PGVM pGVM);
4082	# endif
4083	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4084	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4085	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4086	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4087	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4088	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4089	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4090	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4091	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
4092	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
4093	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
4094	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
4095	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4096	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4097	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4098	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4099	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4100	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4101	FNPGMPHYSHANDLER pgmPoolAccessHandler;
4102	#ifndef IN_RING3
4103	FNPGMRZPHYSPFHANDLER pgmRZPoolAccessPfHandler;
4104	#endif
4105
4106	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4107	void pgmPoolResetDirtyPages(PVMCC pVM);
4108	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
4109
4110	/** Gets the ring-0 pointer for the given pool page. */
4111	DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4112	{
4113	#ifdef IN_RING3
4114	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
4115	# ifdef VBOX_STRICT
4116	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
4117	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
4118	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
4119	# endif
4120	return pPool->pPoolR0 + offPage;
4121	#else
4122	RT_NOREF(pPool);
4123	return pPage;
4124	#endif
4125	}
4126
4127	/** Gets the ring-3 pointer for the given pool page. */
4128	DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4129	{
4130	#ifdef IN_RING3
4131	RT_NOREF(pPool);
4132	return pPage;
4133	#else
4134	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
4135	# ifdef VBOX_STRICT
4136	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
4137	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
4138	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
4139	# endif
4140	return pPool->pPoolR3 + offPage;
4141	#endif
4142	}
4143
4144	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4145	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4146	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4147	#endif /* !VBOX_WITH_ONLY_PGM_NEM_MODE */
4148
4149	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4150	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4151	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4152
4153	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
4154	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
4155	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4156	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
4157	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
4158	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
4159	#endif
4160	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
4161	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
4162
4163	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4164	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4165	FNDBGCCMD pgmR3CmdShowSharedModules;
4166	# endif
4167
4168	void pgmLogState(PVM pVM);
4169
4170	RT_C_DECLS_END
4171
4172	/** @} */
4173
4174	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
4175

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 108843

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