PGMInternal.h@ 104859

Last change on this file since 104859 was 104859, checked in by vboxsync, 12 months ago
VMM/PGM: Moved the apRamRangesTlbR0 out of the shared PGM structure and into the ring-0 only one; double the RAM range TLB size (from 8 to 16 entries). bugref:10687 bugref:10093
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File size: 183.8 KB

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1	/* $Id: PGMInternal.h 104859 2024-06-05 20:33:10Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
29	#define VMM_INCLUDED_SRC_include_PGMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/cdefs.h>
35	#include <VBox/types.h>
36	#include <VBox/err.h>
37	#include <VBox/dbg.h>
38	#include <VBox/vmm/stam.h>
39	#include <VBox/param.h>
40	#include <VBox/vmm/vmm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmapi.h>
44	#include <VBox/dis.h>
45	#include <VBox/vmm/dbgf.h>
46	#include <VBox/log.h>
47	#include <VBox/vmm/gmm.h>
48	#include <VBox/vmm/hm.h>
49	#include <iprt/asm.h>
50	#include <iprt/assert.h>
51	#include <iprt/avl.h>
52	#include <iprt/critsect.h>
53	#include <iprt/list-off32.h>
54	#include <iprt/sha.h>
55	#include <iprt/cpp/hardavlrange.h>
56
57
58
59	/** @defgroup grp_pgm_int Internals
60	* @ingroup grp_pgm
61	* @internal
62	* @{
63	*/
64
65
66	/** @name PGM Compile Time Config
67	* @{
68	*/
69
70	/**
71	* Check and skip global PDEs for non-global flushes
72	*/
73	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
74
75	/**
76	* Optimization for PAE page tables that are modified often
77	*/
78	#ifndef VBOX_VMM_TARGET_ARMV8
79	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
80	#endif
81
82	/**
83	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
84	*/
85	#define PGM_WITH_LARGE_PAGES
86
87	/**
88	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
89	* VMX_EXIT_EPT_MISCONFIG.
90	*/
91	#define PGM_WITH_MMIO_OPTIMIZATIONS
92
93	/**
94	* Sync N pages instead of a whole page table
95	*/
96	#define PGM_SYNC_N_PAGES
97
98	/**
99	* Number of pages to sync during a page fault
100	*
101	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
102	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
103	*
104	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
105	* world switch overhead, so let's sync more.
106	*/
107	#ifdef IN_RING0
108	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
109	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
110	* but ~5% fewer faults.
111	*/
112	# define PGM_SYNC_NR_PAGES 32
113	#else
114	# define PGM_SYNC_NR_PAGES 8
115	#endif
116
117	/** Maximum number of RAM ranges.
118	* @note This can be increased to 4096 (at least when targeting x86). */
119	#define PGM_MAX_RAM_RANGES 3072
120
121	/** Maximum pages per RAM range.
122	*
123	* The PGMRAMRANGE structures for the high memory can get very big. There
124	* used to be some limitations on SUPR3PageAllocEx allocation sizes, so
125	* traditionally we limited this to 16MB chunks. These days we do ~64 MB
126	* chunks each covering 16GB of guest RAM, making sure each range is a
127	* multiple of 1GB to enable eager hosts to use 1GB pages for NEM mode.
128	*
129	* See also pgmPhysMmio2CalcChunkCount.
130	*/
131	#define PGM_MAX_PAGES_PER_RAM_RANGE _4M
132	#if defined(X86_PD_PAE_SHIFT) && defined(AssertCompile)
133	AssertCompile(RT_ALIGN_32(PGM_MAX_PAGES_PER_RAM_RANGE, X86_PD_PAE_SHIFT - X86_PAGE_SHIFT)); /* NEM large page requirement: 1GB pages. */
134	#endif
135
136	/** The maximum number of MMIO2 ranges. */
137	#define PGM_MAX_MMIO2_RANGES 32
138	/** The maximum number of pages in a MMIO2 PCI region.
139	*
140	* The memory for a MMIO2 PCI region is a single chunk of host virtual memory,
141	* but may be handled internally by PGM as a set of multiple MMIO2/RAM ranges,
142	* since PGM_MAX_PAGES_PER_RAM_RANGE is currently lower than this value (4 GiB
143	* vs 16 GiB).
144	*/
145	#define PGM_MAX_PAGES_PER_MMIO2_REGION _16M
146
147	/** Maximum number of ROM ranges. */
148	#define PGM_MAX_ROM_RANGES 16
149	/** The maximum pages per ROM range.
150	* Currently 512K pages, or 2GB with 4K pages. */
151	#define PGM_MAX_PAGES_PER_ROM_RANGE _512K
152	AssertCompile(PGM_MAX_PAGES_PER_ROM_RANGE <= PGM_MAX_PAGES_PER_RAM_RANGE);
153
154	/**
155	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
156	*/
157	#define PGM_MAX_PHYSCACHE_ENTRIES 64
158	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
159
160
161	/** @def PGMPOOL_CFG_MAX_GROW
162	* The maximum number of pages to add to the pool in one go.
163	*/
164	#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
165
166	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
167	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
168	*/
169	#ifdef VBOX_STRICT
170	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
171	#endif
172
173	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
174	* Enables the experimental lazy page allocation code.
175	* @todo Problems with zero page tracking, see \@bugref{10509}. */
176	#if defined(DOXYGEN_RUNNING)
177	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
178	#endif
179
180	/** @def PGM_WITH_PAGE_ZEROING_DETECTION
181	* Enables the code for detecting guest zeroing page in the ZERO state and
182	* tries to avoid allocating them in response.
183	* This kind of relies upon VBOX_WITH_NEW_LAZY_PAGE_ALLOC to work atm. */
184	#if defined(DOXYGEN_RUNNING)
185	# define PGM_WITH_PAGE_ZEROING_DETECTION
186	#endif
187
188	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
189	* Enables real write monitoring of pages, i.e. mapping them read-only and
190	* only making them writable when getting a write access \#PF. */
191	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
192
193	/** @def VBOX_WITH_PGM_NEM_MODE
194	* Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
195	* details. */
196	#ifdef DOXYGEN_RUNNING
197	# define VBOX_WITH_PGM_NEM_MODE
198	#endif
199
200	/** @} */
201
202
203	/** @name PDPT and PML4 flags.
204	* These are placed in the three bits available for system programs in
205	* the PDPT and PML4 entries.
206	* @{ */
207	/** The entry is a permanent one and it's must always be present.
208	* Never free such an entry. */
209	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
210	/** PGM specific bits in PML4 entries. */
211	#define PGM_PML4_FLAGS 0
212	/** PGM specific bits in PDPT entries. */
213	#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
214	/** @} */
215
216	/** @name Page directory flags.
217	* These are placed in the three bits available for system programs in
218	* the page directory entries.
219	* @{ */
220	/** Indicates the original entry was a big page.
221	* @remarks This is currently only used for statistics and can be recycled. */
222	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
223	/** Made read-only to facilitate dirty bit tracking. */
224	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
225	/** @} */
226
227	/** @name Page flags.
228	* These are placed in the three bits available for system programs in
229	* the page entries.
230	* @{ */
231	/** Made read-only to facilitate dirty bit tracking. */
232	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
233	/** @} */
234
235	/** @name Defines used to indicate the shadow and guest paging in the templates.
236	* @{ */
237	#define PGM_TYPE_REAL 1
238	#define PGM_TYPE_PROT 2
239	#define PGM_TYPE_32BIT 3
240	#define PGM_TYPE_PAE 4
241	#define PGM_TYPE_AMD64 5
242	#define PGM_TYPE_NESTED_32BIT 6
243	#define PGM_TYPE_NESTED_PAE 7
244	#define PGM_TYPE_NESTED_AMD64 8
245	#define PGM_TYPE_EPT 9
246	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
247	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
248	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
249	/** @} */
250
251	/** @name Defines used to indicate the second-level
252	* address translation (SLAT) modes in the templates.
253	* @{ */
254	#define PGM_SLAT_TYPE_DIRECT (PGM_TYPE_END + 1)
255	#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 2)
256	#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 3)
257	#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 4)
258	#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 5)
259	/** @} */
260
261	/** Macro for checking if the guest is using paging.
262	* @param uGstType PGM_TYPE_*
263	* @param uShwType PGM_TYPE_*
264	* @remark ASSUMES certain order of the PGM_TYPE_* values.
265	*/
266	#define PGM_WITH_PAGING(uGstType, uShwType) \
267	( (uGstType) >= PGM_TYPE_32BIT \
268	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
269
270	/** Macro for checking if the guest supports the NX bit.
271	* @param uGstType PGM_TYPE_*
272	* @param uShwType PGM_TYPE_*
273	* @remark ASSUMES certain order of the PGM_TYPE_* values.
274	*/
275	#define PGM_WITH_NX(uGstType, uShwType) \
276	( (uGstType) >= PGM_TYPE_PAE \
277	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
278
279	/** Macro for checking for nested.
280	* @param uType PGM_TYPE_*
281	*/
282	#define PGM_TYPE_IS_NESTED(uType) \
283	( (uType) == PGM_TYPE_NESTED_32BIT \
284	\|\| (uType) == PGM_TYPE_NESTED_PAE \
285	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
286
287	/** Macro for checking for nested or EPT.
288	* @param uType PGM_TYPE_*
289	*/
290	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
291	( (uType) == PGM_TYPE_NESTED_32BIT \
292	\|\| (uType) == PGM_TYPE_NESTED_PAE \
293	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
294	\|\| (uType) == PGM_TYPE_EPT)
295
296
297
298	/** @def PGM_HCPHYS_2_PTR
299	* Maps a HC physical page pool address to a virtual address.
300	*
301	* @returns VBox status code.
302	* @param pVM The cross context VM structure.
303	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
304	* @param HCPhys The HC physical address to map to a virtual one.
305	* @param ppv Where to store the virtual address. No need to cast
306	* this.
307	*
308	* @remark There is no need to assert on the result.
309	*/
310	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
311
312	/** @def PGM_GCPHYS_2_PTR_V2
313	* Maps a GC physical page address to a virtual address.
314	*
315	* @returns VBox status code.
316	* @param pVM The cross context VM structure.
317	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
318	* @param GCPhys The GC physical address to map to a virtual one.
319	* @param ppv Where to store the virtual address. No need to cast this.
320	*
321	* @remark Use with care as we don't have so much dynamic mapping space in
322	* ring-0 on 32-bit darwin and in RC.
323	* @remark There is no need to assert on the result.
324	*/
325	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
326	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
327
328	/** @def PGM_GCPHYS_2_PTR
329	* Maps a GC physical page address to a virtual address.
330	*
331	* @returns VBox status code.
332	* @param pVM The cross context VM structure.
333	* @param GCPhys The GC physical address to map to a virtual one.
334	* @param ppv Where to store the virtual address. No need to cast this.
335	*
336	* @remark Use with care as we don't have so much dynamic mapping space in
337	* ring-0 on 32-bit darwin and in RC.
338	* @remark There is no need to assert on the result.
339	*/
340	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
341
342	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
343	* Maps a GC physical page address to a virtual address.
344	*
345	* @returns VBox status code.
346	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
347	* @param GCPhys The GC physical address to map to a virtual one.
348	* @param ppv Where to store the virtual address. No need to cast this.
349	*
350	* @remark Use with care as we don't have so much dynamic mapping space in
351	* ring-0 on 32-bit darwin and in RC.
352	* @remark There is no need to assert on the result.
353	*/
354	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
355
356	/** @def PGM_GCPHYS_2_PTR_EX
357	* Maps a unaligned GC physical page address to a virtual address.
358	*
359	* @returns VBox status code.
360	* @param pVM The cross context VM structure.
361	* @param GCPhys The GC physical address to map to a virtual one.
362	* @param ppv Where to store the virtual address. No need to cast this.
363	*
364	* @remark Use with care as we don't have so much dynamic mapping space in
365	* ring-0 on 32-bit darwin and in RC.
366	* @remark There is no need to assert on the result.
367	*/
368	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
369	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
370
371	/** @def PGM_DYNMAP_UNUSED_HINT
372	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
373	* is no longer used.
374	*
375	* For best effect only apply this to the page that was mapped most recently.
376	*
377	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
378	* @param pvPage The pool page.
379	*/
380	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
381
382	/** @def PGM_DYNMAP_UNUSED_HINT_VM
383	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
384	* is no longer used.
385	*
386	* For best effect only apply this to the page that was mapped most recently.
387	*
388	* @param pVM The cross context VM structure.
389	* @param pvPage The pool page.
390	*/
391	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
392
393
394	/** @def PGM_INVL_PG
395	* Invalidates a page.
396	*
397	* @param pVCpu The cross context virtual CPU structure.
398	* @param GCVirt The virtual address of the page to invalidate.
399	*/
400	#ifdef IN_RING0
401	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
402	#elif defined(IN_RING3)
403	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
404	#else
405	# error "Not IN_RING0 or IN_RING3!"
406	#endif
407
408	/** @def PGM_INVL_PG_ALL_VCPU
409	* Invalidates a page on all VCPUs
410	*
411	* @param pVM The cross context VM structure.
412	* @param GCVirt The virtual address of the page to invalidate.
413	*/
414	#if defined(VBOX_VMM_TARGET_ARMV8)
415	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) do { } while(0)
416	#else
417	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
418	#endif
419
420	/** @def PGM_INVL_BIG_PG
421	* Invalidates a 4MB page directory entry.
422	*
423	* @param pVCpu The cross context virtual CPU structure.
424	* @param GCVirt The virtual address within the page directory to invalidate.
425	*/
426	#if defined(VBOX_VMM_TARGET_ARMV8)
427	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) do { } while(0)
428	#else
429	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
430	#endif
431
432	/** @def PGM_INVL_VCPU_TLBS()
433	* Invalidates the TLBs of the specified VCPU
434	*
435	* @param pVCpu The cross context virtual CPU structure.
436	*/
437	#if defined(VBOX_VMM_TARGET_ARMV8)
438	# define PGM_INVL_VCPU_TLBS(pVCpu) do { } while(0)
439	#else
440	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
441	#endif
442
443	/** @def PGM_INVL_ALL_VCPU_TLBS()
444	* Invalidates the TLBs of all VCPUs
445	*
446	* @param pVM The cross context VM structure.
447	*/
448	#if defined(VBOX_VMM_TARGET_ARMV8)
449	# define PGM_INVL_ALL_VCPU_TLBS(pVM) do { } while(0)
450	#else
451	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
452	#endif
453
454
455	/** @name Safer Shadow PAE PT/PTE
456	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
457	* present.
458	*
459	* @{
460	*/
461	#if 1
462	/**
463	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
464	* invalid entries for present.
465	* @sa X86PTEPAE.
466	*/
467	typedef union PGMSHWPTEPAE
468	{
469	/** Unsigned integer view */
470	X86PGPAEUINT uCareful;
471	/* Not other views. */
472	} PGMSHWPTEPAE;
473
474	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
475	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
476	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
477	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
478	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
479	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
480	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
481	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
482	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
483	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
484	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
485	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
486	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
487	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
488	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
489	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
490
491	/**
492	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
493	* invalid entries for present.
494	* @sa X86PTPAE.
495	*/
496	typedef struct PGMSHWPTPAE
497	{
498	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
499	} PGMSHWPTPAE;
500
501	#else
502	typedef X86PTEPAE PGMSHWPTEPAE;
503	typedef X86PTPAE PGMSHWPTPAE;
504	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
505	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
506	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
507	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
508	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
509	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
510	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
511	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
512	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
513	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
514	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
515	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
516	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
517	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
518	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
519	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
520
521	#endif
522
523	/** Pointer to a shadow PAE PTE. */
524	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
525	/** Pointer to a const shadow PAE PTE. */
526	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
527
528	/** Pointer to a shadow PAE page table. */
529	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
530	/** Pointer to a const shadow PAE page table. */
531	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
532	/** @} */
533
534
535	/** The physical access handler type handle count (power of two). */
536	#define PGMPHYSHANDLERTYPE_COUNT 0x20
537	/** Mask for getting the array index from an access handler type handle.
538	* The other handle bits are random and non-zero to avoid mixups due to zero
539	* initialized fields. */
540	#define PGMPHYSHANDLERTYPE_IDX_MASK 0x1f
541
542	/**
543	* Physical page access handler type registration, ring-0 part.
544	*/
545	typedef struct PGMPHYSHANDLERTYPEINTR0
546	{
547	/** The handle value for verfication. */
548	PGMPHYSHANDLERTYPE hType;
549	/** The kind of accesses we're handling. */
550	PGMPHYSHANDLERKIND enmKind;
551	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
552	uint8_t uState;
553	/** Whether to keep the PGM lock when calling the handler.
554	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
555	bool fKeepPgmLock;
556	/** Set if this is registered by a device instance and uUser should be
557	* translated from a device instance ID to a pointer.
558	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
559	bool fRing0DevInsIdx;
560	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
561	bool fNotInHm : 1;
562	/** Pointer to the ring-0 callback function. */
563	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
564	/** Pointer to the ring-0 callback function for \#PFs, can be NULL. */
565	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandler;
566	/** Description / Name. For easing debugging. */
567	R0PTRTYPE(const char *) pszDesc;
568	} PGMPHYSHANDLERTYPEINTR0;
569	/** Pointer to a physical access handler type registration. */
570	typedef PGMPHYSHANDLERTYPEINTR0 *PPGMPHYSHANDLERTYPEINTR0;
571
572	/**
573	* Physical page access handler type registration, shared/ring-3 part.
574	*/
575	typedef struct PGMPHYSHANDLERTYPEINTR3
576	{
577	/** The handle value for verfication. */
578	PGMPHYSHANDLERTYPE hType;
579	/** The kind of accesses we're handling. */
580	PGMPHYSHANDLERKIND enmKind;
581	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
582	uint8_t uState;
583	/** Whether to keep the PGM lock when calling the handler.
584	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
585	bool fKeepPgmLock;
586	/** Set if this is registered by a device instance and uUser should be
587	* translated from a device instance ID to a pointer.
588	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
589	bool fRing0DevInsIdx;
590	/** Set by ring-0 if the handler is ring-0 enabled (for debug). */
591	bool fRing0Enabled : 1;
592	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
593	bool fNotInHm : 1;
594	/** Pointer to the ring-3 callback function. */
595	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
596	/** Description / Name. For easing debugging. */
597	R3PTRTYPE(const char *) pszDesc;
598	} PGMPHYSHANDLERTYPEINTR3;
599	/** Pointer to a physical access handler type registration. */
600	typedef PGMPHYSHANDLERTYPEINTR3 *PPGMPHYSHANDLERTYPEINTR3;
601
602	/** Pointer to a physical access handler type record for the current context. */
603	typedef CTX_SUFF(PPGMPHYSHANDLERTYPEINT) PPGMPHYSHANDLERTYPEINT;
604	/** Pointer to a const physical access handler type record for the current context. */
605	typedef CTX_SUFF(PGMPHYSHANDLERTYPEINT) const *PCPGMPHYSHANDLERTYPEINT;
606	/** Dummy physical access handler type record. */
607	extern CTX_SUFF(PGMPHYSHANDLERTYPEINT) const g_pgmHandlerPhysicalDummyType;
608
609
610	/**
611	* Physical page access handler structure.
612	*
613	* This is used to keep track of physical address ranges
614	* which are being monitored in some kind of way.
615	*/
616	typedef struct PGMPHYSHANDLER
617	{
618	/** @name Tree stuff.
619	* @{ */
620	/** First address. */
621	RTGCPHYS Key;
622	/** Last address. */
623	RTGCPHYS KeyLast;
624	uint32_t idxLeft;
625	uint32_t idxRight;
626	uint8_t cHeight;
627	/** @} */
628	uint8_t abPadding[3];
629	/** Number of pages to update. */
630	uint32_t cPages;
631	/** Set if we have pages that have been aliased. */
632	uint32_t cAliasedPages;
633	/** Set if we have pages that have temporarily been disabled. */
634	uint32_t cTmpOffPages;
635	/** Registered handler type handle.
636	* @note Marked volatile to prevent re-reading after validation. */
637	PGMPHYSHANDLERTYPE volatile hType;
638	/** User argument for the handlers. */
639	uint64_t uUser;
640	/** Description / Name. For easing debugging. */
641	R3PTRTYPE(const char *) pszDesc;
642	/** Profiling of this handler.
643	* @note VBOX_WITH_STATISTICS only, but included to keep structure stable. */
644	STAMPROFILE Stat;
645	} PGMPHYSHANDLER;
646	AssertCompileSize(PGMPHYSHANDLER, 12*8);
647	/** Pointer to a physical page access handler structure. */
648	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
649
650	/**
651	* Gets the type record for a physical handler (no reference added).
652	* @returns PCPGMPHYSHANDLERTYPEINT, can be NULL
653	* @param a_pVM The cross context VM structure.
654	* @param a_pPhysHandler Pointer to the physical handler structure
655	* (PGMPHYSHANDLER).
656	*/
657	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) \
658	pgmHandlerPhysicalTypeHandleToPtr(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
659
660	/**
661	* Gets the type record for a physical handler, never returns NULL.
662	*
663	* @returns PCPGMPHYSHANDLERTYPEINT, never NULL.
664	* @param a_pVM The cross context VM structure.
665	* @param a_pPhysHandler Pointer to the physical handler structure
666	* (PGMPHYSHANDLER).
667	*/
668	#define PGMPHYSHANDLER_GET_TYPE_NO_NULL(a_pVM, a_pPhysHandler) \
669	pgmHandlerPhysicalTypeHandleToPtr2(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
670
671	/** Physical access handler allocator. */
672	typedef RTCHardAvlTreeSlabAllocator<PGMPHYSHANDLER> PGMPHYSHANDLERALLOCATOR;
673
674	/** Physical access handler tree. */
675	typedef RTCHardAvlRangeTree<PGMPHYSHANDLER, RTGCPHYS> PGMPHYSHANDLERTREE;
676	/** Pointer to a physical access handler tree. */
677	typedef PGMPHYSHANDLERTREE *PPGMPHYSHANDLERTREE;
678
679
680	/**
681	* A Physical Guest Page tracking structure.
682	*
683	* The format of this structure is complicated because we have to fit a lot
684	* of information into as few bits as possible. The format is also subject
685	* to change (there is one coming up soon). Which means that for we'll be
686	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
687	* accesses to the structure.
688	*/
689	typedef union PGMPAGE
690	{
691	/** Structured view. */
692	struct
693	{
694	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
695	uint64_t u2HandlerPhysStateY : 2;
696	/** 2 - Don't apply the physical handler in HM mode (nested APIC hack). */
697	uint64_t fHandlerPhysNotInHm : 1;
698	/** 3 - Flag indicating that a write monitored page was written to when set. */
699	uint64_t fWrittenToY : 1;
700	/** 4 - Set when the page is write monitored because it's an IEM TB code
701	* page. Save recompiled code the need to verify opcode bytes.
702	*
703	* IEM fetches this flag as part of the TLB queries. The flag is cleared when
704	* the page is made writable and IEM is informed and will invalidate its
705	* physical TLB layer.
706	*
707	* @note Can possibly be set on ROM pages that are not in the monitored state. */
708	uint64_t fCodePageY : 1;
709	/** 7:5 - Unused. */
710	uint64_t u2Unused0 : 3;
711	/** 9:8 - Paging structure needed to map the page
712	* (PGM_PAGE_PDE_TYPE_). /
713	uint64_t u2PDETypeY : 2;
714	/** 11:10 - NEM state bits. */
715	uint64_t u2NemStateY : 2;
716	/** 12:48 - The host physical frame number (shift left to get the
717	* address). */
718	uint64_t HCPhysFN : 36;
719	/** 50:48 - The page state. */
720	uint64_t uStateY : 3;
721	/** 51:53 - The page type (PGMPAGETYPE). */
722	uint64_t uTypeY : 3;
723	/** 63:54 - PTE index for usage tracking (page pool). */
724	uint64_t u10PteIdx : 10;
725
726	/** The GMM page ID.
727	* @remarks In the current implementation, MMIO2 and pages aliased to
728	* MMIO2 pages will be exploiting this field to calculate the
729	* ring-3 mapping address corresponding to the page.
730	* Later we may consider including MMIO2 management into GMM. */
731	uint32_t idPage;
732	/** Usage tracking (page pool). */
733	uint16_t u16TrackingY;
734	/** The number of read locks on this page. */
735	uint8_t cReadLocksY;
736	/** The number of write locks on this page. */
737	uint8_t cWriteLocksY;
738	} s;
739
740	/** 64-bit integer view. */
741	uint64_t au64[2];
742	/** 16-bit view. */
743	uint32_t au32[4];
744	/** 16-bit view. */
745	uint16_t au16[8];
746	/** 8-bit view. */
747	uint8_t au8[16];
748	} PGMPAGE;
749	AssertCompileSize(PGMPAGE, 16);
750	/** Pointer to a physical guest page. */
751	typedef PGMPAGE *PPGMPAGE;
752	/** Pointer to a const physical guest page. */
753	typedef const PGMPAGE *PCPGMPAGE;
754	/** Pointer to a physical guest page pointer. */
755	typedef PPGMPAGE *PPPGMPAGE;
756
757
758	/**
759	* Clears the page structure.
760	* @param a_pPage Pointer to the physical guest page tracking structure.
761	*/
762	#define PGM_PAGE_CLEAR(a_pPage) \
763	do { \
764	(a_pPage)->au64[0] = 0; \
765	(a_pPage)->au64[1] = 0; \
766	} while (0)
767
768	/**
769	* Initializes the page structure.
770	* @param a_pPage Pointer to the physical guest page tracking structure.
771	* @param a_HCPhys The host physical address of the page.
772	* @param a_idPage The (GMM) page ID of the page.
773	* @param a_uType The page type (PGMPAGETYPE).
774	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
775	*/
776	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
777	do { \
778	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
779	AssertFatalMsg(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000)), ("%RHp\n", SetHCPhysTmp)); \
780	(a_pPage)->au64[0] = SetHCPhysTmp; \
781	(a_pPage)->au64[1] = 0; \
782	(a_pPage)->s.idPage = (a_idPage); \
783	(a_pPage)->s.uStateY = (a_uState); \
784	(a_pPage)->s.uTypeY = (a_uType); \
785	} while (0)
786
787	/**
788	* Initializes the page structure of a ZERO page.
789	* @param a_pPage Pointer to the physical guest page tracking structure.
790	* @param a_pVM The VM handle (for getting the zero page address).
791	* @param a_uType The page type (PGMPAGETYPE).
792	*/
793	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
794	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
795
796
797	/** @name The Page state, PGMPAGE::uStateY.
798	* @{ */
799	/** The zero page.
800	* This is a per-VM page that's never ever mapped writable. */
801	#define PGM_PAGE_STATE_ZERO 0U
802	/** A allocated page.
803	* This is a per-VM page allocated from the page pool (or wherever
804	* we get MMIO2 pages from if the type is MMIO2).
805	*/
806	#define PGM_PAGE_STATE_ALLOCATED 1U
807	/** A allocated page that's being monitored for writes.
808	* The shadow page table mappings are read-only. When a write occurs, the
809	* fWrittenTo member is set, the page remapped as read-write and the state
810	* moved back to allocated. */
811	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
812	/** The page is shared, aka. copy-on-write.
813	* This is a page that's shared with other VMs. */
814	#define PGM_PAGE_STATE_SHARED 3U
815	/** The page is ballooned, so no longer available for this VM. */
816	#define PGM_PAGE_STATE_BALLOONED 4U
817	/** @} */
818
819
820	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
821	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
822	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
823	#else
824	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
825	#endif
826
827	/**
828	* Gets the page state.
829	* @returns page state (PGM_PAGE_STATE_*).
830	* @param a_pPage Pointer to the physical guest page tracking structure.
831	*
832	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
833	* builds.
834	*/
835	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
836	#if defined(__GNUC__) && defined(VBOX_STRICT)
837	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
838	#else
839	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
840	#endif
841
842	/**
843	* Sets the page state.
844	* @param a_pVM The VM handle, only used for lock ownership assertions.
845	* @param a_pPage Pointer to the physical guest page tracking structure.
846	* @param a_uState The new page state.
847	*/
848	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
849	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
850
851
852	/**
853	* Gets the host physical address of the guest page.
854	* @returns host physical address (RTHCPHYS).
855	* @param a_pPage Pointer to the physical guest page tracking structure.
856	*
857	* @remarks In strict builds on gcc platforms, this macro will make some ugly
858	* assumption about a valid pVM variable/parameter being in the
859	* current context. It will use this pVM variable to assert that the
860	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
861	* pVM is not around.
862	*/
863	#if 0
864	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
865	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
866	#else
867	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
868	# if defined(__GNUC__) && defined(VBOX_STRICT)
869	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
870	# else
871	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
872	# endif
873	#endif
874
875	/**
876	* Sets the host physical address of the guest page.
877	*
878	* @param a_pVM The VM handle, only used for lock ownership assertions.
879	* @param a_pPage Pointer to the physical guest page tracking structure.
880	* @param a_HCPhys The new host physical address.
881	*/
882	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
883	do { \
884	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
885	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
886	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
887	PGM_PAGE_ASSERT_LOCK(a_pVM); \
888	} while (0)
889
890	/**
891	* Get the Page ID.
892	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
893	* @param a_pPage Pointer to the physical guest page tracking structure.
894	*/
895	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
896
897	/**
898	* Sets the Page ID.
899	* @param a_pVM The VM handle, only used for lock ownership assertions.
900	* @param a_pPage Pointer to the physical guest page tracking structure.
901	* @param a_idPage The new page ID.
902	*/
903	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
904	do { \
905	(a_pPage)->s.idPage = (a_idPage); \
906	PGM_PAGE_ASSERT_LOCK(a_pVM); \
907	} while (0)
908
909	/**
910	* Get the Chunk ID.
911	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
912	* @param a_pPage Pointer to the physical guest page tracking structure.
913	*/
914	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
915
916	/**
917	* Get the index of the page within the allocation chunk.
918	* @returns The page index.
919	* @param a_pPage Pointer to the physical guest page tracking structure.
920	*/
921	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
922
923	/**
924	* Gets the page type.
925	* @returns The page type.
926	* @param a_pPage Pointer to the physical guest page tracking structure.
927	*
928	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
929	* builds.
930	*/
931	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
932	#if defined(__GNUC__) && defined(VBOX_STRICT)
933	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
934	#else
935	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
936	#endif
937
938	/**
939	* Sets the page type.
940	*
941	* @param a_pVM The VM handle, only used for lock ownership assertions.
942	* @param a_pPage Pointer to the physical guest page tracking structure.
943	* @param a_enmType The new page type (PGMPAGETYPE).
944	*/
945	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
946	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
947
948	/**
949	* Gets the page table index
950	* @returns The page table index.
951	* @param a_pPage Pointer to the physical guest page tracking structure.
952	*/
953	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
954
955	/**
956	* Sets the page table index.
957	* @param a_pVM The VM handle, only used for lock ownership assertions.
958	* @param a_pPage Pointer to the physical guest page tracking structure.
959	* @param a_iPte New page table index.
960	*/
961	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
962	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
963
964	/**
965	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
966	* @returns true/false.
967	* @param a_pPage Pointer to the physical guest page tracking structure.
968	*/
969	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
970
971	/**
972	* Checks if the page is marked for MMIO, including both aliases.
973	* @returns true/false.
974	* @param a_pPage Pointer to the physical guest page tracking structure.
975	*/
976	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
977	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
978	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
979	)
980
981	/**
982	* Checks if the page is marked for MMIO, including special aliases.
983	* @returns true/false.
984	* @param a_pPage Pointer to the physical guest page tracking structure.
985	*/
986	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
987	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
988
989	/**
990	* Checks if the page is a special aliased MMIO page.
991	* @returns true/false.
992	* @param a_pPage Pointer to the physical guest page tracking structure.
993	*/
994	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
995
996	/**
997	* Checks if the page is backed by the ZERO page.
998	* @returns true/false.
999	* @param a_pPage Pointer to the physical guest page tracking structure.
1000	*/
1001	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1002
1003	/**
1004	* Checks if the page is backed by a SHARED page.
1005	* @returns true/false.
1006	* @param a_pPage Pointer to the physical guest page tracking structure.
1007	*/
1008	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1009
1010	/**
1011	* Checks if the page is ballooned.
1012	* @returns true/false.
1013	* @param a_pPage Pointer to the physical guest page tracking structure.
1014	*/
1015	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1016
1017	/**
1018	* Checks if the page is allocated.
1019	* @returns true/false.
1020	* @param a_pPage Pointer to the physical guest page tracking structure.
1021	*/
1022	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1023
1024
1025	/**
1026	* Marks the page as written to (for GMM change monitoring).
1027	* @param a_pVM The VM handle, only used for lock ownership assertions.
1028	* @param a_pPage Pointer to the physical guest page tracking structure.
1029	*/
1030	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1031	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1032
1033	/**
1034	* Clears the written-to indicator.
1035	* @param a_pVM The VM handle, only used for lock ownership assertions.
1036	* @param a_pPage Pointer to the physical guest page tracking structure.
1037	*/
1038	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1039	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1040
1041	/**
1042	* Checks if the page was marked as written-to.
1043	* @returns true/false.
1044	* @param a_pPage Pointer to the physical guest page tracking structure.
1045	*/
1046	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1047
1048
1049	/**
1050	* Marks the page as an IEM code page (being write monitored or a ROM page).
1051	* @param a_pVM The VM handle, only used for lock ownership assertions.
1052	* @param a_pPage Pointer to the physical guest page tracking structure.
1053	*/
1054	#define PGM_PAGE_SET_CODE_PAGE(a_pVM, a_pPage) \
1055	do { (a_pPage)->s.fCodePageY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1056
1057	/**
1058	* Clears the code page indicator.
1059	* @param a_pVM The VM handle, only used for lock ownership assertions.
1060	* @param a_pPage Pointer to the physical guest page tracking structure.
1061	*/
1062	#define PGM_PAGE_CLEAR_CODE_PAGE(a_pVM, a_pPage) \
1063	do { (a_pPage)->s.fCodePageY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1064
1065	/**
1066	* Checks if the page is an IEM code page (implies write monitored or ROM page).
1067	* @returns true/false.
1068	* @param a_pPage Pointer to the physical guest page tracking structure.
1069	*/
1070	#define PGM_PAGE_IS_CODE_PAGE(a_pPage) ( (a_pPage)->s.fCodePageY )
1071
1072
1073	/** @name PT usage values (PGMPAGE::u2PDEType).
1074	*
1075	* @{ */
1076	/** Either as a PT or PDE. */
1077	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1078	/** Must use a page table to map the range. */
1079	#define PGM_PAGE_PDE_TYPE_PT 1
1080	/** Can use a page directory entry to map the continuous range. */
1081	#define PGM_PAGE_PDE_TYPE_PDE 2
1082	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1083	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1084	/** @} */
1085
1086	/**
1087	* Set the PDE type of the page
1088	* @param a_pVM The VM handle, only used for lock ownership assertions.
1089	* @param a_pPage Pointer to the physical guest page tracking structure.
1090	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1091	*/
1092	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1093	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1094
1095	/**
1096	* Checks if the page was marked being part of a large page
1097	* @returns true/false.
1098	* @param a_pPage Pointer to the physical guest page tracking structure.
1099	*/
1100	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1101
1102	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1103	*
1104	* @remarks The values are assigned in order of priority, so we can calculate
1105	* the correct state for a page with different handlers installed.
1106	* @{ */
1107	/** No handler installed. */
1108	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1109	/** Monitoring is temporarily disabled. */
1110	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1111	/** Write access is monitored. */
1112	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1113	/** All access is monitored. */
1114	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1115	/** @} */
1116
1117	/**
1118	* Gets the physical access handler state of a page.
1119	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1120	* @param a_pPage Pointer to the physical guest page tracking structure.
1121	*/
1122	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1123
1124	/**
1125	* Sets the physical access handler state of a page.
1126	* @param a_pPage Pointer to the physical guest page tracking structure.
1127	* @param a_uState The new state value.
1128	* @param a_fNotInHm The PGMPHYSHANDLER_F_NOT_HM bit.
1129	*/
1130	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState, a_fNotInHm) \
1131	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); (a_pPage)->s.fHandlerPhysNotInHm = (a_fNotInHm); } while (0)
1132
1133	/**
1134	* Sets the physical access handler state of a page.
1135	* @param a_pPage Pointer to the physical guest page tracking structure.
1136	* @param a_uState The new state value.
1137	*/
1138	#define PGM_PAGE_SET_HNDL_PHYS_STATE_ONLY(a_pPage, a_uState) \
1139	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1140
1141	/**
1142	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1143	* @returns true/false
1144	* @param a_pPage Pointer to the physical guest page tracking structure.
1145	*/
1146	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1147	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1148
1149	/**
1150	* Checks if the page has any active physical access handlers.
1151	* @returns true/false
1152	* @param a_pPage Pointer to the physical guest page tracking structure.
1153	*/
1154	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1155	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1156
1157	/**
1158	* Checks if the page has any access handlers, including temporarily disabled ones.
1159	* @returns true/false
1160	* @param a_pPage Pointer to the physical guest page tracking structure.
1161	*/
1162	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1163	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1164
1165	/**
1166	* Checks if the page has any active access handlers.
1167	* @returns true/false
1168	* @param a_pPage Pointer to the physical guest page tracking structure.
1169	*/
1170	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1171	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1172
1173	/**
1174	* Checks if the page has any active access handlers catching all accesses.
1175	* @returns true/false
1176	* @param a_pPage Pointer to the physical guest page tracking structure.
1177	*/
1178	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1179	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1180
1181	/** @def PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM
1182	* Checks if the physical handlers of the page should be ignored in shadow page
1183	* tables and such.
1184	* @returns true/false
1185	* @param a_pPage Pointer to the physical guest page tracking structure.
1186	*/
1187	#define PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(a_pPage) ((a_pPage)->s.fHandlerPhysNotInHm)
1188
1189	/** @def PGM_PAGE_GET_TRACKING
1190	* Gets the packed shadow page pool tracking data associated with a guest page.
1191	* @returns uint16_t containing the data.
1192	* @param a_pPage Pointer to the physical guest page tracking structure.
1193	*/
1194	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1195	#if defined(__GNUC__) && defined(VBOX_STRICT)
1196	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1197	#else
1198	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1199	#endif
1200
1201	/** @def PGM_PAGE_SET_TRACKING
1202	* Sets the packed shadow page pool tracking data associated with a guest page.
1203	* @param a_pVM The VM handle, only used for lock ownership assertions.
1204	* @param a_pPage Pointer to the physical guest page tracking structure.
1205	* @param a_u16TrackingData The tracking data to store.
1206	*/
1207	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1208	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1209
1210	/** @def PGM_PAGE_GET_TD_CREFS
1211	* Gets the @a cRefs tracking data member.
1212	* @returns cRefs.
1213	* @param a_pPage Pointer to the physical guest page tracking structure.
1214	*/
1215	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1216	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1217	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1218	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1219
1220	/** @def PGM_PAGE_GET_TD_IDX
1221	* Gets the @a idx tracking data member.
1222	* @returns idx.
1223	* @param a_pPage Pointer to the physical guest page tracking structure.
1224	*/
1225	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1226	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1227	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1228	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1229
1230
1231	/** Max number of locks on a page. */
1232	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1233
1234	/** Get the read lock count.
1235	* @returns count.
1236	* @param a_pPage Pointer to the physical guest page tracking structure.
1237	*/
1238	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1239
1240	/** Get the write lock count.
1241	* @returns count.
1242	* @param a_pPage Pointer to the physical guest page tracking structure.
1243	*/
1244	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1245
1246	/** Decrement the read lock counter.
1247	* @param a_pPage Pointer to the physical guest page tracking structure.
1248	*/
1249	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1250
1251	/** Decrement the write lock counter.
1252	* @param a_pPage Pointer to the physical guest page tracking structure.
1253	*/
1254	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1255
1256	/** Increment the read lock counter.
1257	* @param a_pPage Pointer to the physical guest page tracking structure.
1258	*/
1259	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1260
1261	/** Increment the write lock counter.
1262	* @param a_pPage Pointer to the physical guest page tracking structure.
1263	*/
1264	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1265
1266
1267	/** Gets the NEM state.
1268	* @returns NEM state value (two bits).
1269	* @param a_pPage Pointer to the physical guest page tracking structure.
1270	*/
1271	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1272
1273	/** Sets the NEM state.
1274	* @param a_pPage Pointer to the physical guest page tracking structure.
1275	* @param a_u2State The NEM state value (specific to NEM impl.).
1276	*/
1277	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1278	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1279
1280
1281	#if 0
1282	/** Enables sanity checking of write monitoring using CRC-32. */
1283	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1284	#endif
1285
1286	/**
1287	* Per page live save tracking data.
1288	*/
1289	typedef struct PGMLIVESAVERAMPAGE
1290	{
1291	/** Number of times it has been dirtied. */
1292	uint32_t cDirtied : 24;
1293	/** Whether it is currently dirty. */
1294	uint32_t fDirty : 1;
1295	/** Ignore the page.
1296	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1297	* deal with these after pausing the VM and DevPCI have said it bit about
1298	* remappings. */
1299	uint32_t fIgnore : 1;
1300	/** Was a ZERO page last time around. */
1301	uint32_t fZero : 1;
1302	/** Was a SHARED page last time around. */
1303	uint32_t fShared : 1;
1304	/** Whether the page is/was write monitored in a previous pass. */
1305	uint32_t fWriteMonitored : 1;
1306	/** Whether the page is/was write monitored earlier in this pass. */
1307	uint32_t fWriteMonitoredJustNow : 1;
1308	/** Bits reserved for future use. */
1309	uint32_t u2Reserved : 2;
1310	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1311	/** CRC-32 for the page. This is for internal consistency checks. */
1312	uint32_t u32Crc;
1313	#endif
1314	} PGMLIVESAVERAMPAGE;
1315	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1316	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1317	#else
1318	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1319	#endif
1320	/** Pointer to the per page live save tracking data. */
1321	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1322
1323	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1324	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1325
1326
1327	/**
1328	* RAM range lookup table entry.
1329	*/
1330	typedef union PGMRAMRANGELOOKUPENTRY
1331	{
1332	RT_GCC_EXTENSION struct
1333	{
1334	/** Page aligned start address of the range, with page offset holding the ID. */
1335	RTGCPHYS GCPhysFirstAndId;
1336	/** The last address in the range (inclusive). Page aligned (-1). */
1337	RTGCPHYS GCPhysLast;
1338	};
1339	/** Alternative 128-bit view for atomic updating. */
1340	RTUINT128U volatile u128Volatile;
1341	/** Alternative 128-bit view for atomic updating. */
1342	RTUINT128U u128Normal;
1343	} PGMRAMRANGELOOKUPENTRY;
1344	/** Pointer to a lookup table entry. */
1345	typedef PGMRAMRANGELOOKUPENTRY *PPGMRAMRANGELOOKUPENTRY;
1346
1347	/** Extracts the ID from PGMRAMRANGELOOKUPENTRY::GCPhysFirstAndId. */
1348	#define PGMRAMRANGELOOKUPENTRY_GET_ID(a_LookupEntry) ((uint32_t)((a_LookupEntry).GCPhysFirstAndId & GUEST_PAGE_OFFSET_MASK))
1349	/** Extracts the GCPhysFirst from PGMRAMRANGELOOKUPENTRY::GCPhysFirstAndId. */
1350	#define PGMRAMRANGELOOKUPENTRY_GET_FIRST(a_LookupEntry) (((a_LookupEntry).GCPhysFirstAndId) & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK)
1351
1352
1353	/**
1354	* RAM range for GC Phys to HC Phys & R3 Ptr conversion.
1355	*
1356	* This structure is addressed via context specific pointer tables. Lookup is
1357	* organized via the lookup table (PGMRAMRANGELOOKUPENTRY).
1358	*/
1359	typedef struct PGMRAMRANGE
1360	{
1361	/** Start of the range. Page aligned. */
1362	RTGCPHYS GCPhys;
1363	/** Size of the range. (Page aligned of course).
1364	* Ring-0 duplicates this in a PGMR0PERVM::acRamRangePages (shifted by
1365	* guest page size). */
1366	RTGCPHYS cb;
1367	/** PGM_RAM_RANGE_FLAGS_* flags. */
1368	uint32_t fFlags;
1369	/** NEM specific info, UINT32_MAX if not used. */
1370	uint32_t uNemRange;
1371	/** Last address in the range (inclusive). Page aligned (-1). */
1372	RTGCPHYS GCPhysLast;
1373	/** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1374	R3PTRTYPE(uint8_t *) pbR3;
1375	/** The RAM range identifier (index into the pointer table). */
1376	uint32_t idRange;
1377	#if HC_ARCH_BITS != 32
1378	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1379	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 0 : 1];
1380	#endif
1381	/** Live save per page tracking data. */
1382	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1383	/** The range description. */
1384	R3PTRTYPE(const char *) pszDesc;
1385
1386	/** Array of physical guest page tracking structures.
1387	* @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1388	PGMPAGE aPages[1];
1389	} PGMRAMRANGE;
1390	AssertCompileMemberAlignment(PGMRAMRANGE, aPages, 16);
1391	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1392	typedef PGMRAMRANGE *PPGMRAMRANGE;
1393
1394	/** @name PGMRAMRANGE::fFlags
1395	* @{ */
1396	/** Ad hoc RAM range for an ROM mapping. */
1397	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1398	/** Ad hoc RAM range for an MMIO mapping. */
1399	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1400	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1401	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1402	/** Valid RAM range flags. */
1403	#define PGM_RAM_RANGE_FLAGS_VALID_MASK (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX)
1404	/** @} */
1405
1406	/** Tests if a RAM range is an ad hoc one or not.
1407	* @returns true/false.
1408	* @param pRam The RAM range.
1409	*/
1410	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1411	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1412
1413	/** The number of entries in the RAM range TLBs (there is one for each
1414	* context). Must be a power of two. */
1415	#define PGM_RAMRANGE_TLB_ENTRIES 16
1416
1417	/**
1418	* Calculates the RAM range TLB index for the physical address.
1419	*
1420	* @returns RAM range TLB index.
1421	* @param a_GCPhys The guest physical address.
1422	*/
1423	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1424
1425	/**
1426	* Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1427	* mapping address.
1428	*/
1429	#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1430	( (a_pRam)->pbR3 ? (a_pRam)->pbR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1431
1432
1433	/**
1434	* Per page tracking structure for ROM image.
1435	*
1436	* A ROM image may have a shadow page, in which case we may have two pages
1437	* backing it. This structure contains the PGMPAGE for both while
1438	* PGMRAMRANGE have a copy of the active one. It is important that these
1439	* aren't out of sync in any regard other than page pool tracking data.
1440	*/
1441	typedef struct PGMROMPAGE
1442	{
1443	/** The page structure for the virgin ROM page. */
1444	PGMPAGE Virgin;
1445	/** The page structure for the shadow RAM page. */
1446	PGMPAGE Shadow;
1447	/** The current protection setting. */
1448	PGMROMPROT enmProt;
1449	/** Live save status information. Makes use of unused alignment space. */
1450	struct
1451	{
1452	/** The previous protection value. */
1453	uint8_t u8Prot;
1454	/** Written to flag set by the handler. */
1455	bool fWrittenTo;
1456	/** Whether the shadow page is dirty or not. */
1457	bool fDirty;
1458	/** Whether it was dirtied in the recently. */
1459	bool fDirtiedRecently;
1460	} LiveSave;
1461	} PGMROMPAGE;
1462	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1463	/** Pointer to a ROM page tracking structure. */
1464	typedef PGMROMPAGE *PPGMROMPAGE;
1465
1466
1467	/**
1468	* A registered ROM image.
1469	*
1470	* This is needed to keep track of ROM image since they generally intrude
1471	* into a PGMRAMRANGE. It also keeps track of additional info like the
1472	* two page sets (read-only virgin and read-write shadow), the current
1473	* state of each page.
1474	*
1475	* Because access handlers cannot easily be executed in a different
1476	* context, the ROM ranges needs to be accessible and in all contexts.
1477	*/
1478	typedef struct PGMROMRANGE
1479	{
1480	/** Address of the range. */
1481	RTGCPHYS GCPhys;
1482	/** Address of the last byte in the range. */
1483	RTGCPHYS GCPhysLast;
1484	/** Size of the range. */
1485	RTGCPHYS cb;
1486	/** The flags (PGMPHYS_ROM_FLAGS_). /
1487	uint8_t fFlags;
1488	/** The saved state range ID. */
1489	uint8_t idSavedState;
1490	/** The ID of the associated RAM range. */
1491	#ifdef IN_RING0
1492	volatile
1493	#endif
1494	uint16_t idRamRange;
1495	/** The size bits pvOriginal points to. */
1496	uint32_t cbOriginal;
1497	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1498	* This is used for strictness checks. */
1499	R3PTRTYPE(const void *) pvOriginal;
1500	/** The ROM description. */
1501	R3PTRTYPE(const char *) pszDesc;
1502	#ifdef VBOX_WITH_PGM_NEM_MODE
1503	/** In simplified memory mode this provides alternate backing for shadowed ROMs.
1504	* - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1505	* - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1506	* - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1507	* - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1508	R3PTRTYPE(uint8_t *) pbR3Alternate;
1509	RTR3PTR pvAlignment2;
1510	#else
1511	RTR3PTR apvUnused[2];
1512	#endif
1513	/** The per page tracking structures. */
1514	PGMROMPAGE aPages[1];
1515	} PGMROMRANGE;
1516	/** Pointer to a ROM range. */
1517	typedef PGMROMRANGE *PPGMROMRANGE;
1518
1519
1520	/**
1521	* Live save per page data for an MMIO2 page.
1522	*
1523	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1524	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1525	* CRC-32 for detecting changes as well as special handling of zero pages. This
1526	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1527	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1528	* because of speed (2.5x and 6x slower).)
1529	*
1530	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1531	* save but normally is disabled. Since we can write monitor guest
1532	* accesses on our own, we only need this for host accesses. Shouldn't be
1533	* too difficult for DevVGA, VMMDev might be doable, the planned
1534	* networking fun will be fun since it involves ring-0.
1535	*/
1536	typedef struct PGMLIVESAVEMMIO2PAGE
1537	{
1538	/** Set if the page is considered dirty. */
1539	bool fDirty;
1540	/** The number of scans this page has remained unchanged for.
1541	* Only updated for dirty pages. */
1542	uint8_t cUnchangedScans;
1543	/** Whether this page was zero at the last scan. */
1544	bool fZero;
1545	/** Alignment padding. */
1546	bool fReserved;
1547	/** CRC-32 for the first half of the page.
1548	* This is used together with u32CrcH2 to quickly detect changes in the page
1549	* during the non-final passes. */
1550	uint32_t u32CrcH1;
1551	/** CRC-32 for the second half of the page. */
1552	uint32_t u32CrcH2;
1553	/** SHA-1 for the saved page.
1554	* This is used in the final pass to skip pages without changes. */
1555	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1556	} PGMLIVESAVEMMIO2PAGE;
1557	/** Pointer to a live save status data for an MMIO2 page. */
1558	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1559
1560	/**
1561	* A registered MMIO2 (= Device RAM) range.
1562	*
1563	* There are a few reason why we need to keep track of these registrations. One
1564	* of them is the deregistration & cleanup stuff, while another is that the
1565	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1566	* range list.
1567	*
1568	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1569	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1570	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1571	* overlap we will free all the existing RAM pages and put in the ram range
1572	* pages instead.
1573	*/
1574	typedef struct PGMREGMMIO2RANGE
1575	{
1576	/** The owner of the range (a device). */
1577	PPDMDEVINSR3 pDevInsR3;
1578	/** Pointer to the ring-3 mapping of the allocation. */
1579	R3PTRTYPE(uint8_t *) pbR3;
1580	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1581	uint16_t fFlags;
1582	/** The sub device number (internal PCI config (CFGM) number). */
1583	uint8_t iSubDev;
1584	/** The PCI region number. */
1585	uint8_t iRegion;
1586	/** The saved state range ID. */
1587	uint8_t idSavedState;
1588	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1589	uint8_t idMmio2;
1590	/** The ID of the associated RAM range. */
1591	#ifdef IN_RING0
1592	volatile
1593	#endif
1594	uint16_t idRamRange;
1595	/** The mapping address if mapped, NIL_RTGCPHYS if not. */
1596	RTGCPHYS GCPhys;
1597	/** The real size.
1598	* This may be larger than indicated by RamRange.cb if the range has been
1599	* reduced during saved state loading. */
1600	RTGCPHYS cbReal;
1601	/** Pointer to the physical handler for MMIO.
1602	* If NEM is responsible for tracking dirty pages in simple memory mode, this
1603	* will be NULL. */
1604	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1605	/** Live save per page tracking data for MMIO2. */
1606	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1607	RTR3PTR R3PtrPadding;
1608	} PGMREGMMIO2RANGE;
1609	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1610	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1611
1612	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1613	* @{ */
1614	/** Set if this is the first chunk in the MMIO2 range. */
1615	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1616	/** Set if this is the last chunk in the MMIO2 range. */
1617	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1618	/** Set if the whole range is mapped. */
1619	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1620	/** Set if it's overlapping, clear if not. */
1621	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1622	/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1623	#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1624	/** Set if the access handler is registered. */
1625	#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1626	/** Set if dirty page tracking is currently enabled. */
1627	#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1628	/** Set if there are dirty pages in the range. */
1629	#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1630	/** @} */
1631
1632
1633	/** @name Internal MMIO2 macros.
1634	* @{ */
1635	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1636	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1637	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1638	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1639	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1640	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1641	/** @} */
1642
1643
1644
1645	/**
1646	* PGMPhysRead/Write cache entry
1647	*/
1648	typedef struct PGMPHYSCACHEENTRY
1649	{
1650	/** R3 pointer to physical page. */
1651	R3PTRTYPE(uint8_t *) pbR3;
1652	/** GC Physical address for cache entry */
1653	RTGCPHYS GCPhys;
1654	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1655	RTGCPHYS u32Padding0; /*< alignment padding. /
1656	#endif
1657	} PGMPHYSCACHEENTRY;
1658
1659	/**
1660	* PGMPhysRead/Write cache to reduce REM memory access overhead
1661	*/
1662	typedef struct PGMPHYSCACHE
1663	{
1664	/** Bitmap of valid cache entries */
1665	uint64_t aEntries;
1666	/** Cache entries */
1667	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1668	} PGMPHYSCACHE;
1669
1670
1671	/** @name Ring-3 page mapping TLBs
1672	* @{ */
1673
1674	/** Pointer to an allocation chunk ring-3 mapping. */
1675	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1676	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1677	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1678
1679	/**
1680	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1681	*
1682	* The primary tree (Core) uses the chunk id as key.
1683	*/
1684	typedef struct PGMCHUNKR3MAP
1685	{
1686	/** The key is the chunk id. */
1687	AVLU32NODECORE Core;
1688	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1689	* selection. */
1690	uint32_t iLastUsed;
1691	/** The current reference count. */
1692	uint32_t volatile cRefs;
1693	/** The current permanent reference count. */
1694	uint32_t volatile cPermRefs;
1695	/** The mapping address. */
1696	void *pv;
1697	} PGMCHUNKR3MAP;
1698
1699	/**
1700	* Allocation chunk ring-3 mapping TLB entry.
1701	*/
1702	typedef struct PGMCHUNKR3MAPTLBE
1703	{
1704	/** The chunk id. */
1705	uint32_t volatile idChunk;
1706	#if HC_ARCH_BITS == 64
1707	uint32_t u32Padding; /*< alignment padding. /
1708	#endif
1709	/** The chunk map. */
1710	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1711	} PGMCHUNKR3MAPTLBE;
1712	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1713	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1714
1715	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1716	* @remark Must be a power of two value. */
1717	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1718
1719	/**
1720	* Allocation chunk ring-3 mapping TLB.
1721	*
1722	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1723	* At first glance this might look kinda odd since AVL trees are
1724	* supposed to give the most optimal lookup times of all trees
1725	* due to their balancing. However, take a tree with 1023 nodes
1726	* in it, that's 10 levels, meaning that most searches has to go
1727	* down 9 levels before they find what they want. This isn't fast
1728	* compared to a TLB hit. There is the factor of cache misses,
1729	* and of course the problem with trees and branch prediction.
1730	* This is why we use TLBs in front of most of the trees.
1731	*
1732	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1733	* difficult when we switch to the new inlined AVL trees (from kStuff).
1734	*/
1735	typedef struct PGMCHUNKR3MAPTLB
1736	{
1737	/** The TLB entries. */
1738	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1739	} PGMCHUNKR3MAPTLB;
1740
1741	/**
1742	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1743	* @returns Chunk TLB index.
1744	* @param idChunk The Chunk ID.
1745	*/
1746	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1747
1748
1749	/**
1750	* Ring-3 guest page mapping TLB entry.
1751	* @remarks used in ring-0 as well at the moment.
1752	*/
1753	typedef struct PGMPAGER3MAPTLBE
1754	{
1755	/** Address of the page. */
1756	RTGCPHYS volatile GCPhys;
1757	/** The guest page. */
1758	R3PTRTYPE(PPGMPAGE) volatile pPage;
1759	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1760	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1761	/** The address */
1762	R3PTRTYPE(void *) volatile pv;
1763	#if HC_ARCH_BITS == 32
1764	uint32_t u32Padding; /*< alignment padding. /
1765	#endif
1766	} PGMPAGER3MAPTLBE;
1767	/** Pointer to an entry in the HC physical TLB. */
1768	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1769
1770
1771	/** The number of entries in the ring-3 guest page mapping TLB.
1772	* @remarks The value must be a power of two. */
1773	#define PGM_PAGER3MAPTLB_ENTRIES 256
1774
1775	/**
1776	* Ring-3 guest page mapping TLB.
1777	* @remarks used in ring-0 as well at the moment.
1778	*/
1779	typedef struct PGMPAGER3MAPTLB
1780	{
1781	/** The TLB entries. */
1782	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1783	} PGMPAGER3MAPTLB;
1784	/** Pointer to the ring-3 guest page mapping TLB. */
1785	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1786
1787	/**
1788	* Calculates the index of the TLB entry for the specified guest page.
1789	* @returns Physical TLB index.
1790	* @param GCPhys The guest physical address.
1791	*/
1792	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1793
1794	/** @} */
1795
1796
1797	/** @name Ring-0 page mapping TLB
1798	* @{ */
1799	/**
1800	* Ring-0 guest page mapping TLB entry.
1801	*/
1802	typedef struct PGMPAGER0MAPTLBE
1803	{
1804	/** Address of the page. */
1805	RTGCPHYS volatile GCPhys;
1806	/** The guest page. */
1807	R0PTRTYPE(PPGMPAGE) volatile pPage;
1808	/** The address */
1809	R0PTRTYPE(void *) volatile pv;
1810	} PGMPAGER0MAPTLBE;
1811	/** Pointer to an entry in the HC physical TLB. */
1812	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1813
1814
1815	/** The number of entries in the ring-3 guest page mapping TLB.
1816	* @remarks The value must be a power of two. */
1817	#define PGM_PAGER0MAPTLB_ENTRIES 256
1818
1819	/**
1820	* Ring-3 guest page mapping TLB.
1821	* @remarks used in ring-0 as well at the moment.
1822	*/
1823	typedef struct PGMPAGER0MAPTLB
1824	{
1825	/** The TLB entries. */
1826	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1827	} PGMPAGER0MAPTLB;
1828	/** Pointer to the ring-3 guest page mapping TLB. */
1829	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1830
1831	/**
1832	* Calculates the index of the TLB entry for the specified guest page.
1833	* @returns Physical TLB index.
1834	* @param GCPhys The guest physical address.
1835	*/
1836	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1837	/** @} */
1838
1839
1840	/** @name Context neutral page mapper TLB.
1841	*
1842	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1843	* code is writting in a kind of context neutral way. Time will show whether
1844	* this actually makes sense or not...
1845	*
1846	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1847	* context ends up using a global mapping cache on some platforms
1848	* (darwin).
1849	*
1850	* @{ */
1851	/** @typedef PPGMPAGEMAPTLB
1852	* The page mapper TLB pointer type for the current context. */
1853	/** @typedef PPGMPAGEMAPTLB
1854	* The page mapper TLB entry pointer type for the current context. */
1855	/** @typedef PPGMPAGEMAPTLB
1856	* The page mapper TLB entry pointer pointer type for the current context. */
1857	/** @def PGM_PAGEMAPTLB_ENTRIES
1858	* The number of TLB entries in the page mapper TLB for the current context. */
1859	/** @def PGM_PAGEMAPTLB_IDX
1860	* Calculate the TLB index for a guest physical address.
1861	* @returns The TLB index.
1862	* @param GCPhys The guest physical address. */
1863	/** @typedef PPGMPAGEMAP
1864	* Pointer to a page mapper unit for current context. */
1865	/** @typedef PPPGMPAGEMAP
1866	* Pointer to a page mapper unit pointer for current context. */
1867	#if defined(IN_RING0)
1868	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1869	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1870	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1871	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1872	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1873	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1874	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1875	#else
1876	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1877	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1878	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1879	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1880	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1881	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1882	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1883	#endif
1884	/** @} */
1885
1886
1887	/** @name PGM Pool Indexes.
1888	* Aka. the unique shadow page identifier.
1889	* @{ */
1890	/** NIL page pool IDX. */
1891	#define NIL_PGMPOOL_IDX 0
1892	/** The first normal index. There used to be 5 fictive pages up front, now
1893	* there is only the NIL page. */
1894	#define PGMPOOL_IDX_FIRST 1
1895	/** The last valid index. (inclusive, 14 bits) */
1896	#define PGMPOOL_IDX_LAST 0x3fff
1897	/** @} */
1898
1899	/** The NIL index for the parent chain. */
1900	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1901	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1902
1903	/**
1904	* Node in the chain linking a shadowed page to it's parent (user).
1905	*/
1906	#pragma pack(1)
1907	typedef struct PGMPOOLUSER
1908	{
1909	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1910	uint16_t iNext;
1911	/** The user page index. */
1912	uint16_t iUser;
1913	/** Index into the user table. */
1914	uint32_t iUserTable;
1915	} PGMPOOLUSER, *PPGMPOOLUSER;
1916	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1917	#pragma pack()
1918
1919
1920	/** The NIL index for the phys ext chain. */
1921	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1922	/** The NIL pte index for a phys ext chain slot. */
1923	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1924
1925	/**
1926	* Node in the chain of physical cross reference extents.
1927	* @todo Calling this an 'extent' is not quite right, find a better name.
1928	* @todo find out the optimal size of the aidx array
1929	*/
1930	#pragma pack(1)
1931	typedef struct PGMPOOLPHYSEXT
1932	{
1933	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1934	uint16_t iNext;
1935	/** Alignment. */
1936	uint16_t u16Align;
1937	/** The user page index. */
1938	uint16_t aidx[3];
1939	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1940	uint16_t apte[3];
1941	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1942	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1943	#pragma pack()
1944
1945
1946	/**
1947	* The kind of page that's being shadowed.
1948	*/
1949	typedef enum PGMPOOLKIND
1950	{
1951	/** The virtual invalid 0 entry. */
1952	PGMPOOLKIND_INVALID = 0,
1953	/** The entry is free (=unused). */
1954	PGMPOOLKIND_FREE,
1955
1956	/** Shw: 32-bit page table; Gst: no paging. */
1957	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1958	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1959	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1960	/** Shw: 32-bit page table; Gst: 4MB page. */
1961	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1962	/** Shw: PAE page table; Gst: no paging. */
1963	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1964	/** Shw: PAE page table; Gst: 32-bit page table. */
1965	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1966	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1967	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1968	/** Shw: PAE page table; Gst: PAE page table. */
1969	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1970	/** Shw: PAE page table; Gst: 2MB page. */
1971	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1972
1973	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1974	PGMPOOLKIND_32BIT_PD,
1975	/** Shw: 32-bit page directory. Gst: no paging. */
1976	PGMPOOLKIND_32BIT_PD_PHYS,
1977	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1978	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1979	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1980	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1981	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1982	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1983	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1984	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1985	/** Shw: PAE page directory; Gst: PAE page directory. */
1986	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1987	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1988	PGMPOOLKIND_PAE_PD_PHYS,
1989
1990	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1991	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1992	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1993	PGMPOOLKIND_PAE_PDPT,
1994	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1995	PGMPOOLKIND_PAE_PDPT_PHYS,
1996
1997	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1998	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1999	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
2000	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2001	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2002	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2003	/** Shw: 64-bit page directory table; Gst: no paging. */
2004	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2005
2006	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2007	PGMPOOLKIND_64BIT_PML4,
2008
2009	/** Shw: EPT page directory pointer table; Gst: no paging. */
2010	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2011	/** Shw: EPT page directory table; Gst: no paging. */
2012	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2013	/** Shw: EPT page table; Gst: no paging. */
2014	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2015
2016	/** Shw: Root Nested paging table. */
2017	PGMPOOLKIND_ROOT_NESTED,
2018
2019	/** Shw: EPT page table; Gst: EPT page table. */
2020	PGMPOOLKIND_EPT_PT_FOR_EPT_PT,
2021	/** Shw: EPT page table; Gst: 2MB page. */
2022	PGMPOOLKIND_EPT_PT_FOR_EPT_2MB,
2023	/** Shw: EPT page directory table; Gst: EPT page directory. */
2024	PGMPOOLKIND_EPT_PD_FOR_EPT_PD,
2025	/** Shw: EPT page directory pointer table; Gst: EPT page directory pointer table. */
2026	PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT,
2027	/** Shw: EPT PML4; Gst: EPT PML4. */
2028	PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4,
2029
2030	/** The last valid entry. */
2031	PGMPOOLKIND_LAST = PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4
2032	} PGMPOOLKIND;
2033
2034	/**
2035	* The access attributes of the page; only applies to big pages.
2036	*/
2037	typedef enum
2038	{
2039	PGMPOOLACCESS_DONTCARE = 0,
2040	PGMPOOLACCESS_USER_RW,
2041	PGMPOOLACCESS_USER_R,
2042	PGMPOOLACCESS_USER_RW_NX,
2043	PGMPOOLACCESS_USER_R_NX,
2044	PGMPOOLACCESS_SUPERVISOR_RW,
2045	PGMPOOLACCESS_SUPERVISOR_R,
2046	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2047	PGMPOOLACCESS_SUPERVISOR_R_NX
2048	} PGMPOOLACCESS;
2049
2050	/**
2051	* The tracking data for a page in the pool.
2052	*/
2053	typedef struct PGMPOOLPAGE
2054	{
2055	/** AVL node code with the (HC) physical address of this page. */
2056	AVLOHCPHYSNODECORE Core;
2057	/** Pointer to the R3 mapping of the page. */
2058	R3PTRTYPE(void *) pvPageR3;
2059	/** Pointer to the R0 mapping of the page. */
2060	R0PTRTYPE(void *) pvPageR0;
2061	/** The guest physical address. */
2062	RTGCPHYS GCPhys;
2063	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2064	uint8_t enmKind;
2065	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2066	uint8_t enmAccess;
2067	/** This supplements enmKind and enmAccess */
2068	bool fA20Enabled : 1;
2069
2070	/** Used to indicate that the page is zeroed. */
2071	bool fZeroed : 1;
2072	/** Used to indicate that a PT has non-global entries. */
2073	bool fSeenNonGlobal : 1;
2074	/** Used to indicate that we're monitoring writes to the guest page. */
2075	bool fMonitored : 1;
2076	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2077	* (All pages are in the age list.) */
2078	bool fCached : 1;
2079	/** This is used by the R3 access handlers when invoked by an async thread.
2080	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2081	bool volatile fReusedFlushPending : 1;
2082	/** Used to mark the page as dirty (write monitoring is temporarily
2083	* off). */
2084	bool fDirty : 1;
2085	bool fPadding1 : 1;
2086	bool fPadding2;
2087
2088	/** The index of this page. */
2089	uint16_t idx;
2090	/** The next entry in the list this page currently resides in.
2091	* It's either in the free list or in the GCPhys hash. */
2092	uint16_t iNext;
2093	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2094	uint16_t iUserHead;
2095	/** The number of present entries. */
2096	uint16_t cPresent;
2097	/** The first entry in the table which is present. */
2098	uint16_t iFirstPresent;
2099	/** The number of modifications to the monitored page. */
2100	uint16_t cModifications;
2101	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2102	uint16_t iModifiedNext;
2103	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2104	uint16_t iModifiedPrev;
2105	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2106	uint16_t iMonitoredNext;
2107	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2108	uint16_t iMonitoredPrev;
2109	/** The next page in the age list. */
2110	uint16_t iAgeNext;
2111	/** The previous page in the age list. */
2112	uint16_t iAgePrev;
2113	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2114	uint8_t idxDirtyEntry;
2115
2116	/** @name Access handler statistics to determine whether the guest is
2117	* (re)initializing a page table.
2118	* @{ */
2119	RTGCPTR GCPtrLastAccessHandlerRip;
2120	RTGCPTR GCPtrLastAccessHandlerFault;
2121	uint64_t cLastAccessHandler;
2122	/** @} */
2123	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2124	uint32_t volatile cLocked;
2125	#if GC_ARCH_BITS == 64
2126	uint32_t u32Alignment3;
2127	#endif
2128	# ifdef VBOX_STRICT
2129	RTGCPTR GCPtrDirtyFault;
2130	# endif
2131	} PGMPOOLPAGE;
2132	/** Pointer to a pool page. */
2133	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2134	/** Pointer to a const pool page. */
2135	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2136	/** Pointer to a pool page pointer. */
2137	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2138
2139
2140	/** The hash table size. */
2141	# define PGMPOOL_HASH_SIZE 0x8000
2142	/** The hash function. */
2143	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2144
2145
2146	/**
2147	* The shadow page pool instance data.
2148	*
2149	* It's all one big allocation made at init time, except for the
2150	* pages that is. The user nodes follows immediately after the
2151	* page structures.
2152	*/
2153	typedef struct PGMPOOL
2154	{
2155	/** The VM handle - R3 Ptr. */
2156	PVMR3 pVMR3;
2157	/** The VM handle - R0 Ptr. */
2158	R0PTRTYPE(PVMCC) pVMR0;
2159	/** The ring-3 pointer to this structure. */
2160	R3PTRTYPE(struct PGMPOOL *) pPoolR3;
2161	/** The ring-0 pointer to this structure. */
2162	R0PTRTYPE(struct PGMPOOL *) pPoolR0;
2163	/** The max pool size. This includes the special IDs. */
2164	uint16_t cMaxPages;
2165	/** The current pool size. */
2166	uint16_t cCurPages;
2167	/** The head of the free page list. */
2168	uint16_t iFreeHead;
2169	/* Padding. */
2170	uint16_t u16Padding;
2171	/** Head of the chain of free user nodes. */
2172	uint16_t iUserFreeHead;
2173	/** The number of user nodes we've allocated. */
2174	uint16_t cMaxUsers;
2175	/** The number of present page table entries in the entire pool. */
2176	uint32_t cPresent;
2177	/** Pointer to the array of user nodes - R3 pointer. */
2178	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2179	/** Pointer to the array of user nodes - R0 pointer. */
2180	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2181	/** Head of the chain of free phys ext nodes. */
2182	uint16_t iPhysExtFreeHead;
2183	/** The number of user nodes we've allocated. */
2184	uint16_t cMaxPhysExts;
2185	uint32_t u32Padding0b;
2186	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2187	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2188	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2189	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2190	/** Hash table for GCPhys addresses. */
2191	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2192	/** The head of the age list. */
2193	uint16_t iAgeHead;
2194	/** The tail of the age list. */
2195	uint16_t iAgeTail;
2196	/** Set if the cache is enabled. */
2197	bool fCacheEnabled;
2198	/** Alignment padding. */
2199	bool afPadding1[3];
2200	/** Head of the list of modified pages. */
2201	uint16_t iModifiedHead;
2202	/** The current number of modified pages. */
2203	uint16_t cModifiedPages;
2204	/** Alignment padding. */
2205	uint32_t u32Padding2;
2206	/** Physical access handler type registration handle. */
2207	PGMPHYSHANDLERTYPE hAccessHandlerType;
2208	/** Next available slot (in aDirtyPages). */
2209	uint32_t idxFreeDirtyPage;
2210	/** Number of active dirty pages. */
2211	uint32_t cDirtyPages;
2212	/** Array of current dirty pgm pool page indices. */
2213	uint16_t aidxDirtyPages[16];
2214	/** Array running in parallel to aidxDirtyPages with the page data. */
2215	struct
2216	{
2217	uint64_t aPage[512];
2218	} aDirtyPages[16];
2219
2220	/** The number of pages currently in use. */
2221	uint16_t cUsedPages;
2222	#ifdef VBOX_WITH_STATISTICS
2223	/** The high water mark for cUsedPages. */
2224	uint16_t cUsedPagesHigh;
2225	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2226	/** Profiling pgmPoolAlloc(). */
2227	STAMPROFILEADV StatAlloc;
2228	/** Profiling pgmR3PoolClearDoIt(). */
2229	STAMPROFILE StatClearAll;
2230	/** Profiling pgmR3PoolReset(). */
2231	STAMPROFILE StatR3Reset;
2232	/** Profiling pgmPoolFlushPage(). */
2233	STAMPROFILE StatFlushPage;
2234	/** Profiling pgmPoolFree(). */
2235	STAMPROFILE StatFree;
2236	/** Counting explicit flushes by PGMPoolFlushPage(). */
2237	STAMCOUNTER StatForceFlushPage;
2238	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2239	STAMCOUNTER StatForceFlushDirtyPage;
2240	/** Counting flushes for reused pages. */
2241	STAMCOUNTER StatForceFlushReused;
2242	/** Profiling time spent zeroing pages. */
2243	STAMPROFILE StatZeroPage;
2244	/** Profiling of pgmPoolTrackDeref. */
2245	STAMPROFILE StatTrackDeref;
2246	/** Profiling pgmTrackFlushGCPhysPT. */
2247	STAMPROFILE StatTrackFlushGCPhysPT;
2248	/** Profiling pgmTrackFlushGCPhysPTs. */
2249	STAMPROFILE StatTrackFlushGCPhysPTs;
2250	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2251	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2252	/** Number of times we've been out of user records. */
2253	STAMCOUNTER StatTrackFreeUpOneUser;
2254	/** Nr of flushed entries. */
2255	STAMCOUNTER StatTrackFlushEntry;
2256	/** Nr of updated entries. */
2257	STAMCOUNTER StatTrackFlushEntryKeep;
2258	/** Profiling deref activity related tracking GC physical pages. */
2259	STAMPROFILE StatTrackDerefGCPhys;
2260	/** Number of linear searches for a HCPhys in the ram ranges. */
2261	STAMCOUNTER StatTrackLinearRamSearches;
2262	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2263	STAMCOUNTER StamTrackPhysExtAllocFailures;
2264
2265	/** Profiling the RC/R0 \#PF access handler. */
2266	STAMPROFILE StatMonitorPfRZ;
2267	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2268	STAMPROFILE StatMonitorPfRZHandled;
2269	/** Times we've failed interpreting the instruction. */
2270	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2271	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2272	STAMPROFILE StatMonitorPfRZFlushPage;
2273	/** Times we've detected a page table reinit. */
2274	STAMCOUNTER StatMonitorPfRZFlushReinit;
2275	/** Counting flushes for pages that are modified too often. */
2276	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2277	/** Times we've detected fork(). */
2278	STAMCOUNTER StatMonitorPfRZFork;
2279	/** Times we've failed interpreting a patch code instruction. */
2280	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2281	/** Times we've failed interpreting a patch code instruction during flushing. */
2282	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2283	/** The number of times we've seen rep prefixes we can't handle. */
2284	STAMCOUNTER StatMonitorPfRZRepPrefix;
2285	/** Profiling the REP STOSD cases we've handled. */
2286	STAMPROFILE StatMonitorPfRZRepStosd;
2287
2288	/** Profiling the R0/RC regular access handler. */
2289	STAMPROFILE StatMonitorRZ;
2290	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2291	STAMPROFILE StatMonitorRZFlushPage;
2292	/** Per access size counts indexed by size minus 1, last for larger. */
2293	STAMCOUNTER aStatMonitorRZSizes[16+3];
2294	/** Missaligned access counts indexed by offset - 1. */
2295	STAMCOUNTER aStatMonitorRZMisaligned[7];
2296
2297	/** Nr of handled PT faults. */
2298	STAMCOUNTER StatMonitorRZFaultPT;
2299	/** Nr of handled PD faults. */
2300	STAMCOUNTER StatMonitorRZFaultPD;
2301	/** Nr of handled PDPT faults. */
2302	STAMCOUNTER StatMonitorRZFaultPDPT;
2303	/** Nr of handled PML4 faults. */
2304	STAMCOUNTER StatMonitorRZFaultPML4;
2305
2306	/** Profiling the R3 access handler. */
2307	STAMPROFILE StatMonitorR3;
2308	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2309	STAMPROFILE StatMonitorR3FlushPage;
2310	/** Per access size counts indexed by size minus 1, last for larger. */
2311	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2312	/** Missaligned access counts indexed by offset - 1. */
2313	STAMCOUNTER aStatMonitorR3Misaligned[7];
2314	/** Nr of handled PT faults. */
2315	STAMCOUNTER StatMonitorR3FaultPT;
2316	/** Nr of handled PD faults. */
2317	STAMCOUNTER StatMonitorR3FaultPD;
2318	/** Nr of handled PDPT faults. */
2319	STAMCOUNTER StatMonitorR3FaultPDPT;
2320	/** Nr of handled PML4 faults. */
2321	STAMCOUNTER StatMonitorR3FaultPML4;
2322
2323	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2324	STAMCOUNTER StatResetDirtyPages;
2325	/** Times we've called pgmPoolAddDirtyPage. */
2326	STAMCOUNTER StatDirtyPage;
2327	/** Times we've had to flush duplicates for dirty page management. */
2328	STAMCOUNTER StatDirtyPageDupFlush;
2329	/** Times we've had to flush because of overflow. */
2330	STAMCOUNTER StatDirtyPageOverFlowFlush;
2331
2332	/** The high water mark for cModifiedPages. */
2333	uint16_t cModifiedPagesHigh;
2334	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2335
2336	/** The number of cache hits. */
2337	STAMCOUNTER StatCacheHits;
2338	/** The number of cache misses. */
2339	STAMCOUNTER StatCacheMisses;
2340	/** The number of times we've got a conflict of 'kind' in the cache. */
2341	STAMCOUNTER StatCacheKindMismatches;
2342	/** Number of times we've been out of pages. */
2343	STAMCOUNTER StatCacheFreeUpOne;
2344	/** The number of cacheable allocations. */
2345	STAMCOUNTER StatCacheCacheable;
2346	/** The number of uncacheable allocations. */
2347	STAMCOUNTER StatCacheUncacheable;
2348	#else
2349	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2350	#endif
2351	/** Profiling PGMR0PoolGrow(). */
2352	STAMPROFILE StatGrow;
2353	/** The AVL tree for looking up a page by its HC physical address. */
2354	AVLOHCPHYSTREE HCPhysTree;
2355	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2356	/** Array of pages. (cMaxPages in length)
2357	* The Id is the index into thist array.
2358	*/
2359	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2360	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2361	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2362	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2363	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2364	#ifdef VBOX_WITH_STATISTICS
2365	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2366	#endif
2367	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2368
2369
2370	/** @def PGMPOOL_PAGE_2_PTR
2371	* Maps a pool page pool into the current context.
2372	*
2373	* @returns VBox status code.
2374	* @param a_pVM Pointer to the VM.
2375	* @param a_pPage The pool page.
2376	*
2377	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2378	* small page window employeed by that function. Be careful.
2379	* @remark There is no need to assert on the result.
2380	*/
2381	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2382	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2383	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2384	{
2385	RT_NOREF(pszCaller);
2386	AssertPtr(a_pPage);
2387	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2388	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2389	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2390	return a_pPage->CTX_SUFF(pvPage);
2391	}
2392	#else
2393	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2394	#endif
2395
2396
2397	/** @def PGMPOOL_PAGE_2_PTR_V2
2398	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2399	*
2400	* @returns VBox status code.
2401	* @param a_pVM Pointer to the VM.
2402	* @param a_pVCpu The current CPU.
2403	* @param a_pPage The pool page.
2404	*
2405	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2406	* small page window employeed by that function. Be careful.
2407	* @remark There is no need to assert on the result.
2408	*/
2409	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2410
2411
2412	/** @def PGMPOOL_PAGE_IS_NESTED
2413	* Checks whether the given pool page is a nested-guest pool page.
2414	*
2415	* @returns @c true if a nested-guest pool page, @c false otherwise.
2416	* @param a_pPage The pool page.
2417	* @todo We can optimize the conditionals later.
2418	*/
2419	#define PGMPOOL_PAGE_IS_NESTED(a_pPage) PGMPOOL_PAGE_IS_KIND_NESTED((a_pPage)->enmKind)
2420	#define PGMPOOL_PAGE_IS_KIND_NESTED(a_enmKind) ( (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_PT \
2421	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_2MB \
2422	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PD_FOR_EPT_PD \
2423	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT \
2424	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4)
2425
2426	/** @name Per guest page tracking data.
2427	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2428	* is to use more bits for it and split it up later on. But for now we'll play
2429	* safe and change as little as possible.
2430	*
2431	* The 16-bit word has two parts:
2432	*
2433	* The first 14-bit forms the @a idx field. It is either the index of a page in
2434	* the shadow page pool, or and index into the extent list.
2435	*
2436	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2437	* shadow page pool references to the page. If cRefs equals
2438	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2439	* (misnomer) table and not the shadow page pool.
2440	*
2441	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2442	* the 16-bit word.
2443	*
2444	* @{ */
2445	/** The shift count for getting to the cRefs part. */
2446	#define PGMPOOL_TD_CREFS_SHIFT 14
2447	/** The mask applied after shifting the tracking data down by
2448	* PGMPOOL_TD_CREFS_SHIFT. */
2449	#define PGMPOOL_TD_CREFS_MASK 0x3
2450	/** The cRefs value used to indicate that the idx is the head of a
2451	* physical cross reference list. */
2452	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2453	/** The shift used to get idx. */
2454	#define PGMPOOL_TD_IDX_SHIFT 0
2455	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2456	#define PGMPOOL_TD_IDX_MASK 0x3fff
2457	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2458	* simply too many mappings of this page. */
2459	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2460
2461	/** @def PGMPOOL_TD_MAKE
2462	* Makes a 16-bit tracking data word.
2463	*
2464	* @returns tracking data.
2465	* @param cRefs The @a cRefs field. Must be within bounds!
2466	* @param idx The @a idx field. Must also be within bounds! */
2467	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2468
2469	/** @def PGMPOOL_TD_GET_CREFS
2470	* Get the @a cRefs field from a tracking data word.
2471	*
2472	* @returns The @a cRefs field
2473	* @param u16 The tracking data word.
2474	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2475	* non-zero @a u16. */
2476	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2477
2478	/** @def PGMPOOL_TD_GET_IDX
2479	* Get the @a idx field from a tracking data word.
2480	*
2481	* @returns The @a idx field
2482	* @param u16 The tracking data word. */
2483	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2484	/** @} */
2485
2486
2487
2488	/** @name A20 gate macros
2489	* @{ */
2490	#define PGM_WITH_A20
2491	#ifdef PGM_WITH_A20
2492	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2493	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2494	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2495	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2496	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2497	#else
2498	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2499	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2500	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2501	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2502	#endif
2503	/** @} */
2504
2505
2506	/**
2507	* Guest page table walk for the AMD64 mode.
2508	*/
2509	typedef struct PGMPTWALKGSTAMD64
2510	{
2511	PX86PML4 pPml4;
2512	PX86PML4E pPml4e;
2513	X86PML4E Pml4e;
2514
2515	PX86PDPT pPdpt;
2516	PX86PDPE pPdpe;
2517	X86PDPE Pdpe;
2518
2519	PX86PDPAE pPd;
2520	PX86PDEPAE pPde;
2521	X86PDEPAE Pde;
2522
2523	PX86PTPAE pPt;
2524	PX86PTEPAE pPte;
2525	X86PTEPAE Pte;
2526	} PGMPTWALKGSTAMD64;
2527	/** Pointer to a AMD64 guest page table walk. */
2528	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2529	/** Pointer to a const AMD64 guest page table walk. */
2530	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2531
2532	/**
2533	* Guest page table walk for the EPT mode.
2534	*/
2535	typedef struct PGMPTWALKGSTEPT
2536	{
2537	PEPTPML4 pPml4;
2538	PEPTPML4E pPml4e;
2539	EPTPML4E Pml4e;
2540
2541	PEPTPDPT pPdpt;
2542	PEPTPDPTE pPdpte;
2543	EPTPDPTE Pdpte;
2544
2545	PEPTPD pPd;
2546	PEPTPDE pPde;
2547	EPTPDE Pde;
2548
2549	PEPTPT pPt;
2550	PEPTPTE pPte;
2551	EPTPTE Pte;
2552	} PGMPTWALKGSTEPT;
2553	/** Pointer to an EPT guest page table walk. */
2554	typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2555	/** Pointer to a const EPT guest page table walk. */
2556	typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2557
2558	/**
2559	* Guest page table walk for the PAE mode.
2560	*/
2561	typedef struct PGMPTWALKGSTPAE
2562	{
2563	PX86PDPT pPdpt;
2564	PX86PDPE pPdpe;
2565	X86PDPE Pdpe;
2566
2567	PX86PDPAE pPd;
2568	PX86PDEPAE pPde;
2569	X86PDEPAE Pde;
2570
2571	PX86PTPAE pPt;
2572	PX86PTEPAE pPte;
2573	X86PTEPAE Pte;
2574	} PGMPTWALKGSTPAE;
2575	/** Pointer to a PAE guest page table walk. */
2576	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2577	/** Pointer to a const AMD64 guest page table walk. */
2578	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2579
2580	/**
2581	* Guest page table walk for the 32-bit mode.
2582	*/
2583	typedef struct PGMPTWALKGST32BIT
2584	{
2585	PX86PD pPd;
2586	PX86PDE pPde;
2587	X86PDE Pde;
2588
2589	PX86PT pPt;
2590	PX86PTE pPte;
2591	X86PTE Pte;
2592	} PGMPTWALKGST32BIT;
2593	/** Pointer to a 32-bit guest page table walk. */
2594	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2595	/** Pointer to a const 32-bit guest page table walk. */
2596	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2597
2598	/**
2599	* Which part of PGMPTWALKGST that is valid.
2600	*/
2601	typedef enum PGMPTWALKGSTTYPE
2602	{
2603	/** Customary invalid 0 value. */
2604	PGMPTWALKGSTTYPE_INVALID = 0,
2605	/** PGMPTWALKGST::u.Amd64 is valid. */
2606	PGMPTWALKGSTTYPE_AMD64,
2607	/** PGMPTWALKGST::u.Pae is valid. */
2608	PGMPTWALKGSTTYPE_PAE,
2609	/** PGMPTWALKGST::u.Legacy is valid. */
2610	PGMPTWALKGSTTYPE_32BIT,
2611	/** PGMPTWALKGST::u.Ept is valid. */
2612	PGMPTWALKGSTTYPE_EPT,
2613	/** Customary 32-bit type hack. */
2614	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2615	} PGMPTWALKGSTTYPE;
2616
2617	/**
2618	* Combined guest page table walk result.
2619	*/
2620	typedef struct PGMPTWALKGST
2621	{
2622	union
2623	{
2624	/** The page walker for AMD64. */
2625	PGMPTWALKGSTAMD64 Amd64;
2626	/** The page walker for PAE (32-bit). */
2627	PGMPTWALKGSTPAE Pae;
2628	/** The page walker for 32-bit paging (called legacy due to C naming
2629	* convension). */
2630	PGMPTWALKGST32BIT Legacy;
2631	/** The page walker for EPT (SLAT). */
2632	PGMPTWALKGSTEPT Ept;
2633	} u;
2634	/** Indicates which part of the union is valid. */
2635	PGMPTWALKGSTTYPE enmType;
2636	} PGMPTWALKGST;
2637	/** Pointer to a combined guest page table walk result. */
2638	typedef PGMPTWALKGST *PPGMPTWALKGST;
2639	/** Pointer to a read-only combined guest page table walk result. */
2640	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2641
2642
2643	/** @name Paging mode macros
2644	* @{
2645	*/
2646	#ifdef IN_RING3
2647	# define PGM_CTX(a,b) a##R3##b
2648	# define PGM_CTX_STR(a,b) a "R3" b
2649	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2650	#elif defined(IN_RING0)
2651	# define PGM_CTX(a,b) a##R0##b
2652	# define PGM_CTX_STR(a,b) a "R0" b
2653	# define PGM_CTX_DECL(type) VMMDECL(type)
2654	#else
2655	# error "Not IN_RING3 or IN_RING0!"
2656	#endif
2657
2658	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2659	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2660	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2661	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2662	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2663	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2664	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2665	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2666	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2667	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2668	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2669	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2670	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2671	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2672	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2673	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2674
2675	#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2676	#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2677	#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2678	#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2679
2680	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2681	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2682	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2683	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2684	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2685	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2686	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2687	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2688	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2689	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2690	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2691	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2692	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2693	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2694	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2695	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2696	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2697	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2698	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2699	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2700	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2701	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2702	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2703	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2704	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2705
2706	/* Shw_Gst */
2707	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2708	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2709	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2710	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2711	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2712	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2713	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2714	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2715	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2716	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2717	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2718	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2719	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2720	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2721	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2722	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2723	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2724	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2725	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2726	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2727	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2728	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2729	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2730	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2731	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2732	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2733	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2734	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2735	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2736	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2737	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2738	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2739	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2740	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2741
2742	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2743	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2744	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2745	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2746	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2747	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2748	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2749	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2750	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2751	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2752	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2753	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2754	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2755	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2756	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2757	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2758	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2759	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2760	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2761	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2762	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2763	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2764	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2765	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2766	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2767	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2768	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2769	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2770
2771	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2772	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2773	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2774	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2775	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2776	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2777	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2778	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2779	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2780	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2781	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2782	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2783	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2784	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2785	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2786	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2787	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2788	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2789	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2790	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2791	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2792	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2793	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2794	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2795	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2796	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2797	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2798	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2799	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2800
2801	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2802	/** @} */
2803
2804
2805	/**
2806	* Function pointers for guest paging.
2807	*/
2808	typedef struct PGMMODEDATAGST
2809	{
2810	/** The guest mode type. */
2811	uint32_t uType;
2812	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2813	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2814	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2815	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2816	#ifdef IN_RING3
2817	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2818	#endif
2819	} PGMMODEDATAGST;
2820
2821	/** The length of g_aPgmGuestModeData. */
2822	#if VBOX_WITH_64_BITS_GUESTS
2823	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2824	#else
2825	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2826	#endif
2827	/** The guest mode data array. */
2828	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2829
2830
2831	/**
2832	* Function pointers for shadow paging.
2833	*/
2834	typedef struct PGMMODEDATASHW
2835	{
2836	/** The shadow mode type. */
2837	uint32_t uType;
2838	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2839	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2840	uint64_t fMask, uint32_t fOpFlags));
2841	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu));
2842	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2843	#ifdef IN_RING3
2844	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2845	#endif
2846	} PGMMODEDATASHW;
2847
2848	/** The length of g_aPgmShadowModeData. */
2849	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2850	/** The shadow mode data array. */
2851	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2852
2853
2854	/**
2855	* Function pointers for guest+shadow paging.
2856	*/
2857	typedef struct PGMMODEDATABTH
2858	{
2859	/** The shadow mode type. */
2860	uint32_t uShwType;
2861	/** The guest mode type. */
2862	uint32_t uGstType;
2863
2864	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2865	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2866	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2867	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2868	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2869	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2870	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2871	#ifndef IN_RING3
2872	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken));
2873	DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNested,
2874	bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
2875	bool *pfLockTaken));
2876	#endif
2877	#ifdef VBOX_STRICT
2878	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2879	#endif
2880	} PGMMODEDATABTH;
2881
2882	/** The length of g_aPgmBothModeData. */
2883	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2884	/** The guest+shadow mode data array. */
2885	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2886
2887
2888	#ifdef VBOX_WITH_STATISTICS
2889	/**
2890	* PGM statistics.
2891	*/
2892	typedef struct PGMSTATS
2893	{
2894	/* R3 only: */
2895	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2896	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2897
2898	/* R3+RZ */
2899	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2900	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2901	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2902	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2903	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2904	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2905	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2906	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2907	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2908	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2909	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2910	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2911	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2912	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2913	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2914	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2915	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2916	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2917	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2918	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2919	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2920	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2921	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2922	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2923	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2924	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2925
2926	/* RC only: */
2927	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2928	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2929
2930	STAMCOUNTER StatRZPhysRead;
2931	STAMCOUNTER StatRZPhysReadBytes;
2932	STAMCOUNTER StatRZPhysWrite;
2933	STAMCOUNTER StatRZPhysWriteBytes;
2934	STAMCOUNTER StatR3PhysRead;
2935	STAMCOUNTER StatR3PhysReadBytes;
2936	STAMCOUNTER StatR3PhysWrite;
2937	STAMCOUNTER StatR3PhysWriteBytes;
2938	STAMCOUNTER StatRCPhysRead;
2939	STAMCOUNTER StatRCPhysReadBytes;
2940	STAMCOUNTER StatRCPhysWrite;
2941	STAMCOUNTER StatRCPhysWriteBytes;
2942
2943	STAMCOUNTER StatRZPhysSimpleRead;
2944	STAMCOUNTER StatRZPhysSimpleReadBytes;
2945	STAMCOUNTER StatRZPhysSimpleWrite;
2946	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2947	STAMCOUNTER StatR3PhysSimpleRead;
2948	STAMCOUNTER StatR3PhysSimpleReadBytes;
2949	STAMCOUNTER StatR3PhysSimpleWrite;
2950	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2951	STAMCOUNTER StatRCPhysSimpleRead;
2952	STAMCOUNTER StatRCPhysSimpleReadBytes;
2953	STAMCOUNTER StatRCPhysSimpleWrite;
2954	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2955
2956	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2957	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2958	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2959	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2960	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2961	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2962	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2963
2964	STAMPROFILE StatLargePageAlloc2; /*< Time spent setting up newly allocated large pages. /
2965	STAMPROFILE StatLargePageSetup; /*< Time spent setting up newly allocated large pages. /
2966	/** pgmPhysIsValidLargePage profiling - R3 */
2967	STAMPROFILE StatR3IsValidLargePage;
2968	/** pgmPhysIsValidLargePage profiling - RZ*/
2969	STAMPROFILE StatRZIsValidLargePage;
2970
2971	STAMPROFILE StatChunkAging;
2972	STAMPROFILE StatChunkFindCandidate;
2973	STAMPROFILE StatChunkUnmap;
2974	STAMPROFILE StatChunkMap;
2975	} PGMSTATS;
2976	#endif /* VBOX_WITH_STATISTICS */
2977
2978
2979	/**
2980	* PGM Data (part of VM)
2981	*/
2982	typedef struct PGM
2983	{
2984	/** The zero page. */
2985	uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2986	/** The MMIO placeholder page. */
2987	uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2988
2989	/** @name RAM, MMIO2 and ROM ranges
2990	* @{ */
2991	/** The RAM range lookup table. */
2992	PGMRAMRANGELOOKUPENTRY aRamRangeLookup[PGM_MAX_RAM_RANGES];
2993	/** The ring-3 RAM range pointer table. */
2994	R3PTRTYPE(PPGMRAMRANGE) apRamRanges[PGM_MAX_RAM_RANGES];
2995	/** MMIO2 ranges. Indexed by idMmio2 minus 1. */
2996	PGMREGMMIO2RANGE aMmio2Ranges[PGM_MAX_MMIO2_RANGES];
2997	/** The ring-3 RAM range pointer table running parallel to aMmio2Ranges. */
2998	R3PTRTYPE(PPGMRAMRANGE) apMmio2RamRanges[PGM_MAX_MMIO2_RANGES];
2999	/** The ring-3 ROM range pointer table. */
3000	R3PTRTYPE(PPGMROMRANGE) apRomRanges[PGM_MAX_ROM_RANGES];
3001	/** Union of generation ID and lookup count. */
3002	union PGMRAMRANGEGENANDLOOKUPCOUNT
3003	{
3004	/* Combined view of both the generation ID and the count for atomic updating/reading. */
3005	uint64_t volatile u64Combined;
3006	RT_GCC_EXTENSION struct
3007	{
3008	/** Generation ID for the RAM ranges.
3009	* This member is incremented twice everytime a RAM range is mapped or
3010	* unmapped, so odd numbers means aRamRangeLookup is being modified and even
3011	* means the update has completed. */
3012	uint32_t volatile idGeneration;
3013	/** The number of active entries in aRamRangeLookup. */
3014	uint32_t volatile cLookupEntries;
3015	};
3016	} RamRangeUnion;
3017	/** The max RAM range ID (mirroring PGMR0PERVM::idRamRangeMax). */
3018	uint32_t idRamRangeMax;
3019	/** The number of MMIO2 ranges (serves as the next MMIO2 ID). */
3020	uint8_t cMmio2Ranges;
3021	/** The number of ROM ranges. */
3022	uint8_t cRomRanges;
3023	uint8_t abAlignment1[2];
3024	/** @} */
3025
3026	/** @name The zero page (abPagePg).
3027	* @{ */
3028	/** The host physical address of the zero page. */
3029	RTHCPHYS HCPhysZeroPg;
3030	/** @}*/
3031
3032	/** @name The Invalid MMIO page (abMmioPg).
3033	* This page is filled with 0xfeedface.
3034	* @{ */
3035	/** The host physical address of the invalid MMIO page. */
3036	RTHCPHYS HCPhysMmioPg;
3037	/** The host pysical address of the invalid MMIO page plus all invalid
3038	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3039	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3040	RTHCPHYS HCPhysInvMmioPg;
3041	/** @} */
3042
3043	/** @cfgm{/RamPreAlloc, boolean, false}
3044	* Indicates whether the base RAM should all be allocated before starting
3045	* the VM (default), or if it should be allocated when first written to.
3046	*/
3047	bool fRamPreAlloc;
3048	#ifdef VBOX_WITH_PGM_NEM_MODE
3049	/** Set if we're operating in NEM memory mode.
3050	*
3051	* NEM mode implies that memory is allocated in big chunks for each RAM range
3052	* rather than on demand page by page. Memory is also not locked and PGM has
3053	* therefore no physical addresses for them. Page sharing is out of the
3054	* question. Ballooning depends on the native execution engine, but probably
3055	* pointless as well. */
3056	bool fNemMode;
3057	# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
3058	#else
3059	# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
3060	#endif
3061	/** Indicates whether write monitoring is currently in use.
3062	* This is used to prevent conflicts between live saving and page sharing
3063	* detection. */
3064	bool fPhysWriteMonitoringEngaged;
3065	/** Set if the CPU has less than 52-bit physical address width.
3066	* This is used */
3067	bool fLessThan52PhysicalAddressBits;
3068	/** Set when nested paging is active.
3069	* This is meant to save calls to HMIsNestedPagingActive and let the
3070	* compilers optimize the code better. Whether we use nested paging or
3071	* not is something we find out during VMM initialization and we won't
3072	* change this later on. */
3073	bool fNestedPaging;
3074	/** We're not in a state which permits writes to guest memory.
3075	* (Only used in strict builds.) */
3076	bool fNoMorePhysWrites;
3077	/** @cfgm{/PageFusionAllowed, boolean, false}
3078	* Whether page fusion is allowed. */
3079	bool fPageFusionAllowed;
3080	/** @cfgm{/PGM/PciPassThrough, boolean, false}
3081	* Whether PCI passthrough is enabled. */
3082	bool fPciPassthrough;
3083	/** Restore original ROM page content when resetting after loading state.
3084	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3085	* enables the VM to start using an updated ROM without requiring powering
3086	* down the VM, just rebooting or resetting it. */
3087	bool fRestoreRomPagesOnReset;
3088	/** Whether to automatically clear all RAM pages on reset. */
3089	bool fZeroRamPagesOnReset;
3090	/** Large page enabled flag. */
3091	bool fUseLargePages;
3092	/** Alignment padding. */
3093	#ifndef VBOX_WITH_PGM_NEM_MODE
3094	bool afAlignment2[2];
3095	#else
3096	bool afAlignment2[1];
3097	#endif
3098	/** The host paging mode. (This is what SUPLib reports.) */
3099	SUPPAGINGMODE enmHostMode;
3100
3101	/** Physical access handler type for ROM protection. */
3102	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3103	/** Physical access handler type for MMIO2 dirty page tracing. */
3104	PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
3105
3106	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3107	RTGCPHYS GCPhys4MBPSEMask;
3108	/** Mask containing the invalid bits of a guest physical address.
3109	* @remarks this does not stop at bit 52. */
3110	RTGCPHYS GCPhysInvAddrMask;
3111
3112
3113	/** RAM range TLB for R3. */
3114	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlb[PGM_RAMRANGE_TLB_ENTRIES];
3115	/** Shadow Page Pool - R3 Ptr. */
3116	R3PTRTYPE(PPGMPOOL) pPoolR3;
3117
3118	/** Shadow Page Pool - R0 Ptr. */
3119	R0PTRTYPE(PPGMPOOL) pPoolR0;
3120
3121	/** Hack: Number of deprecated page mapping locks taken by the current lock
3122	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3123	uint32_t cDeprecatedPageLocks;
3124
3125	/** Registered physical access handler types. */
3126	uint32_t cPhysHandlerTypes;
3127	/** Physical access handler types.
3128	* Initialized to callback causing guru meditations and invalid enmKind. */
3129	PGMPHYSHANDLERTYPEINTR3 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3130	/** Physical handler allocator, ring-3 edition. */
3131	#ifdef IN_RING3
3132	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3133	#else
3134	RTCHardAvlTreeSlabAllocatorR3_T PhysHandlerAllocator;
3135	#endif
3136	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3137	R3PTRTYPE(PPGMPHYSHANDLERTREE) pPhysHandlerTree;
3138	/** Caching the last physical handler we looked. */
3139	uint32_t idxLastPhysHandler;
3140
3141	uint32_t au64Padding3[9];
3142
3143	/** PGM critical section.
3144	* This protects the physical, ram ranges, and the page flag updating (some of
3145	* it anyway).
3146	*/
3147	PDMCRITSECT CritSectX;
3148
3149	/**
3150	* Data associated with managing the ring-3 mappings of the allocation chunks.
3151	*/
3152	struct
3153	{
3154	/** The chunk mapping TLB. */
3155	PGMCHUNKR3MAPTLB Tlb;
3156	/** The chunk tree, ordered by chunk id. */
3157	R3PTRTYPE(PAVLU32NODECORE) pTree;
3158	#if HC_ARCH_BITS == 32
3159	uint32_t u32Alignment0;
3160	#endif
3161	/** The number of mapped chunks. */
3162	uint32_t c;
3163	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3164	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3165	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3166	uint32_t cMax;
3167	/** The current time. This is incremented whenever a chunk is inserted. */
3168	uint32_t iNow;
3169	/** Alignment padding. */
3170	uint32_t au32Alignment1[3];
3171	} ChunkR3Map;
3172
3173	/** The page mapping TLB for ring-3. */
3174	PGMPAGER3MAPTLB PhysTlbR3;
3175	/** The page mapping TLB for ring-0. */
3176	PGMPAGER0MAPTLB PhysTlbR0;
3177
3178	/** The number of handy pages. */
3179	uint32_t cHandyPages;
3180
3181	/** The number of large handy pages. */
3182	uint32_t cLargeHandyPages;
3183
3184	/**
3185	* Array of handy pages.
3186	*
3187	* This array is used in a two way communication between pgmPhysAllocPage
3188	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3189	* an intermediary.
3190	*
3191	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3192	* (The current size of 32 pages, means 128 KB of handy memory.)
3193	*/
3194	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3195
3196	/**
3197	* Array of large handy pages. (currently size 1)
3198	*
3199	* This array is used in a two way communication between pgmPhysAllocLargePage
3200	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3201	* an intermediary.
3202	*/
3203	GMMPAGEDESC aLargeHandyPage[1];
3204	/** When to try allocate large pages again after a failure. */
3205	uint64_t nsLargePageRetry;
3206	/** Number of repeated long allocation times. */
3207	uint32_t cLargePageLongAllocRepeats;
3208	uint32_t uPadding4;
3209
3210	/**
3211	* Live save data.
3212	*/
3213	struct
3214	{
3215	/** Per type statistics. */
3216	struct
3217	{
3218	/** The number of ready pages. */
3219	uint32_t cReadyPages;
3220	/** The number of dirty pages. */
3221	uint32_t cDirtyPages;
3222	/** The number of ready zero pages. */
3223	uint32_t cZeroPages;
3224	/** The number of write monitored pages. */
3225	uint32_t cMonitoredPages;
3226	} Rom,
3227	Mmio2,
3228	Ram;
3229	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3230	uint32_t cIgnoredPages;
3231	/** Indicates that a live save operation is active. */
3232	bool fActive;
3233	/** Padding. */
3234	bool afReserved[2];
3235	/** The next history index. */
3236	uint8_t iDirtyPagesHistory;
3237	/** History of the total amount of dirty pages. */
3238	uint32_t acDirtyPagesHistory[64];
3239	/** Short term dirty page average. */
3240	uint32_t cDirtyPagesShort;
3241	/** Long term dirty page average. */
3242	uint32_t cDirtyPagesLong;
3243	/** The number of saved pages. This is used to get some kind of estimate of the
3244	* link speed so we can decide when we're done. It is reset after the first
3245	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3246	* zero pages. */
3247	uint64_t cSavedPages;
3248	/** The nanosecond timestamp when cSavedPages was 0. */
3249	uint64_t uSaveStartNS;
3250	/** Pages per second (for statistics). */
3251	uint32_t cPagesPerSecond;
3252	uint32_t cAlignment;
3253	} LiveSave;
3254
3255	/** @name Error injection.
3256	* @{ */
3257	/** Inject handy page allocation errors pretending we're completely out of
3258	* memory. */
3259	bool volatile fErrInjHandyPages;
3260	/** Padding. */
3261	bool afReserved[3];
3262	/** @} */
3263
3264	/** @name Release Statistics
3265	* @{ */
3266	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3267	uint32_t cPrivatePages; /*< The number of private pages. /
3268	uint32_t cSharedPages; /*< The number of shared pages. /
3269	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3270	uint32_t cZeroPages; /*< The number of zero backed pages. /
3271	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3272	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3273	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3274	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3275	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3276	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3277	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3278	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3279	uint32_t cLargePages; /*< The number of large pages. /
3280	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3281	/* uint32_t aAlignment4[1]; */
3282
3283	STAMPROFILE StatLargePageAlloc; /*< Time spent by the host OS for large page allocation. /
3284	STAMCOUNTER StatLargePageAllocFailed; /*< Count allocation failures. /
3285	STAMCOUNTER StatLargePageOverflow; /*< The number of times allocating a large pages takes more than the allowed period. /
3286	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3287	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3288	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3289	STAMCOUNTER StatLargePageTlbFlush; /*< The number of a full VCPU TLB flush was required after allocation. /
3290	STAMCOUNTER StatLargePageZeroEvict; /*< The number of zero page mappings we had to evict when allocating a large page. /
3291
3292	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3293
3294	STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /*< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. /
3295	/** @} */
3296
3297	#ifdef VBOX_WITH_STATISTICS
3298	/** These are optional statistics that used to be on the hyper heap. */
3299	PGMSTATS Stats;
3300	#endif
3301	} PGM;
3302	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3303	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3304	AssertCompileMemberAlignment(PGM, CritSectX, 16);
3305	AssertCompileMemberAlignment(PGM, CritSectX, 32);
3306	AssertCompileMemberAlignment(PGM, CritSectX, 64);
3307	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3308	AssertCompileMemberAlignment(PGM, PhysTlbR3, 8);
3309	AssertCompileMemberAlignment(PGM, PhysTlbR3, 16);
3310	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32);
3311	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3312	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3313	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3314	#endif /* !IN_TSTVMSTRUCTGC */
3315	/** Pointer to the PGM instance data. */
3316	typedef PGM *PPGM;
3317
3318
3319	#ifdef VBOX_WITH_STATISTICS
3320	/**
3321	* Per CPU statistis for PGM (used to be on the heap).
3322	*/
3323	typedef struct PGMCPUSTATS
3324	{
3325	/* Common */
3326	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3327	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3328
3329	/* R0 only: */
3330	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3331	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3332
3333	/* RZ only: */
3334	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3335	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3336	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3337	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3338	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3339	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3340	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3341	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3342	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3343	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3344	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3345	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3346	STAMPROFILE StatRZTrap0eTime2PageZeroing; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a zero page that is being zeroed. /
3347	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3348	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3349	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3350	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3351	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3352	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3353	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3354	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3355	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3356	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3357	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3358	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3359	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3360	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3361	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3362	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3363	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3364	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3365	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3366	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3367	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3368	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3369	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3370	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3371	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3372	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3373	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3374	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3375	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3376	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3377	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3378	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3379	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3380	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3381	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3382	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3383	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3384	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3385	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3386	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3387	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3388	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3389	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3390	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3391	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3392	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3393	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3394	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3395	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3396	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3397	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3398	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3399	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3400	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3401	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3402	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3403	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3404
3405	/* HC - R3 and (maybe) R0: */
3406
3407	/* RZ & R3: */
3408	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3409	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3410	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3411	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3412	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3413	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3414	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3415	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3416	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3417	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3418	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3419	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3420	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3421	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3422	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3423	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3424	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3425	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3426	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3427	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3428	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3429	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3430	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3431	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3432	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3433	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3434	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3435	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3436	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3437	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3438	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3439	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3440	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3441	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3442	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3443	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3444	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3445	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3446	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3447	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3448	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3449	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3450	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3451	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3452	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3453	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3454	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3455
3456	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3457	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3458	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3459	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3460	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3461	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3462	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3463	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3464	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3465	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3466	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3467	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3468	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3469	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3470	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3471	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3472	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3473	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3474	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3475	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3476	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3477	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3478	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3479	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3480	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3481	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3482	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3483	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3484	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3485	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3486	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3487	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3488	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3489	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3490	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3491	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3492	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3493	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3494	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3495	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3496	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3497	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3498	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3499	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3500	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3501	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3502	} PGMCPUSTATS;
3503	#endif /* VBOX_WITH_STATISTICS */
3504
3505
3506	/**
3507	* PGMCPU Data (part of VMCPU).
3508	*/
3509	typedef struct PGMCPU
3510	{
3511	/** A20 gate mask.
3512	* Our current approach to A20 emulation is to let REM do it and don't bother
3513	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3514	* But whould need arrise, we'll subject physical addresses to this mask. */
3515	RTGCPHYS GCPhysA20Mask;
3516	/** A20 gate state - boolean! */
3517	bool fA20Enabled;
3518	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3519	bool fNoExecuteEnabled;
3520	/** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3521	* active. */
3522	bool fPaePdpesAndCr3MappedR3;
3523	bool fPaePdpesAndCr3MappedR0;
3524
3525	/** What needs syncing (PGM_SYNC_*).
3526	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3527	* PGMFlushTLB, and PGMR3Load. */
3528	uint32_t fSyncFlags;
3529
3530	/** The shadow paging mode. */
3531	PGMMODE enmShadowMode;
3532	/** The guest paging mode. */
3533	PGMMODE enmGuestMode;
3534	/** The guest second level address translation mode. */
3535	PGMSLAT enmGuestSlatMode;
3536	/** Guest mode data table index (PGM_TYPE_XXX). */
3537	uint8_t volatile idxGuestModeData;
3538	/** Shadow mode data table index (PGM_TYPE_XXX). */
3539	uint8_t volatile idxShadowModeData;
3540	/** Both mode data table index (complicated). */
3541	uint8_t volatile idxBothModeData;
3542	/** Alignment padding. */
3543	uint8_t abPadding[1];
3544
3545	/** The guest CR3.
3546	* When SLAT is active, this is the translated physical address.
3547	* When SLAT is inactive, this is the physical address in CR3. */
3548	RTGCPHYS GCPhysCR3;
3549
3550	/** The nested-guest CR3.
3551	* When SLAT is active, this is CR3 prior to translation.
3552	* When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3553	RTGCPHYS GCPhysNstGstCR3;
3554
3555	/** The cached guest CR3 when it has been mapped in PAE mode.
3556	* This allows us to skip remapping the CR3 and PAE PDPEs
3557	* (in PGMFlushTLB or similar) when it was already done as
3558	* part of MOV CRx instruction emulation.
3559	*/
3560	RTGCPHYS GCPhysPaeCR3;
3561
3562	/** @name 32-bit Guest Paging.
3563	* @{ */
3564	/** The guest's page directory, R3 pointer. */
3565	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3566	/** The guest's page directory, R0 pointer. */
3567	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3568	/** Mask containing the MBZ bits of a big page PDE. */
3569	uint32_t fGst32BitMbzBigPdeMask;
3570	/** Set if the page size extension (PSE) is enabled. */
3571	bool fGst32BitPageSizeExtension;
3572	/** Alignment padding. */
3573	bool afAlignment2[3];
3574	/** @} */
3575
3576	/** @name PAE Guest Paging.
3577	* @{ */
3578	/** The guest's page directory pointer table, R3 pointer. */
3579	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3580	/** The guest's page directory pointer table, R0 pointer. */
3581	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3582
3583	/** The guest's page directories, R3 pointers.
3584	* These are individual pointers and don't have to be adjacent.
3585	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3586	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3587	/** The guest's page directories, R0 pointers.
3588	* Same restrictions as apGstPaePDsR3. */
3589	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3590	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3591	RTGCPHYS aGCPhysGstPaePDs[4];
3592	/** Mask containing the MBZ PTE bits. */
3593	uint64_t fGstPaeMbzPteMask;
3594	/** Mask containing the MBZ PDE bits. */
3595	uint64_t fGstPaeMbzPdeMask;
3596	/** Mask containing the MBZ big page PDE bits. */
3597	uint64_t fGstPaeMbzBigPdeMask;
3598	/** Mask containing the MBZ PDPE bits. */
3599	uint64_t fGstPaeMbzPdpeMask;
3600	/** @} */
3601
3602	/** @name AMD64 Guest Paging.
3603	* @{ */
3604	/** The guest's page directory pointer table, R3 pointer. */
3605	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3606	/** The guest's page directory pointer table, R0 pointer. */
3607	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3608	/** Mask containing the MBZ PTE bits. */
3609	uint64_t fGstAmd64MbzPteMask;
3610	/** Mask containing the MBZ PDE bits. */
3611	uint64_t fGstAmd64MbzPdeMask;
3612	/** Mask containing the MBZ big page PDE bits. */
3613	uint64_t fGstAmd64MbzBigPdeMask;
3614	/** Mask containing the MBZ PDPE bits. */
3615	uint64_t fGstAmd64MbzPdpeMask;
3616	/** Mask containing the MBZ big page PDPE bits. */
3617	uint64_t fGstAmd64MbzBigPdpeMask;
3618	/** Mask containing the MBZ PML4E bits. */
3619	uint64_t fGstAmd64MbzPml4eMask;
3620	/** Mask containing the PDPE bits that we shadow. */
3621	uint64_t fGstAmd64ShadowedPdpeMask;
3622	/** Mask containing the PML4E bits that we shadow. */
3623	uint64_t fGstAmd64ShadowedPml4eMask;
3624	/** @} */
3625
3626	/** @name PAE and AMD64 Guest Paging.
3627	* @{ */
3628	/** Mask containing the PTE bits that we shadow. */
3629	uint64_t fGst64ShadowedPteMask;
3630	/** Mask containing the PDE bits that we shadow. */
3631	uint64_t fGst64ShadowedPdeMask;
3632	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3633	uint64_t fGst64ShadowedBigPdeMask;
3634	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3635	uint64_t fGst64ShadowedBigPde4PteMask;
3636	/** @} */
3637
3638	/** @name EPT Guest Paging.
3639	* @{ */
3640	/** The guest's EPT PML4 table, R3 pointer. */
3641	R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3642	/** The guest's EPT PML4 table, R0 pointer. */
3643	R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3644	/** The guest's EPT pointer (copy of virtual VMCS). */
3645	uint64_t uEptPtr;
3646	/** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3647	* change through the lifetime of the VM. */
3648	uint64_t uEptVpidCapMsr;
3649	/** Mask containing the MBZ PTE bits. */
3650	uint64_t fGstEptMbzPteMask;
3651	/** Mask containing the MBZ PDE bits. */
3652	uint64_t fGstEptMbzPdeMask;
3653	/** Mask containing the MBZ big page (2M) PDE bits. */
3654	uint64_t fGstEptMbzBigPdeMask;
3655	/** Mask containing the MBZ PDPTE bits. */
3656	uint64_t fGstEptMbzPdpteMask;
3657	/** Mask containing the MBZ big page (1G) PDPTE bits. */
3658	uint64_t fGstEptMbzBigPdpteMask;
3659	/** Mask containing the MBZ PML4E bits. */
3660	uint64_t fGstEptMbzPml4eMask;
3661	/** Mask to determine whether an entry is present. */
3662	uint64_t fGstEptPresentMask;
3663
3664	/** Mask containing the EPT PTE bits we shadow. */
3665	uint64_t fGstEptShadowedPteMask;
3666	/** Mask containing the EPT PDE bits we shadow. */
3667	uint64_t fGstEptShadowedPdeMask;
3668	/** Mask containing the EPT PDE (2M) bits we shadow. */
3669	uint64_t fGstEptShadowedBigPdeMask;
3670	/** Mask containing the EPT PDPTE bits we shadow. */
3671	uint64_t fGstEptShadowedPdpteMask;
3672	/** Mask containing the EPT PML4E bits we shadow. */
3673	uint64_t fGstEptShadowedPml4eMask;
3674	/** @} */
3675
3676	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3677	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3678	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3679	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3680
3681	/** For saving stack space, the disassembler state is allocated here instead of
3682	* on the stack. */
3683	DISSTATE Dis;
3684
3685	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3686	uint64_t cNetwareWp0Hacks;
3687
3688	/** Count the number of pgm pool access handler calls. */
3689	uint64_t cPoolAccessHandler;
3690
3691	/** @name Release Statistics
3692	* @{ */
3693	/** The number of times the guest has switched mode since last reset or statistics reset. */
3694	STAMCOUNTER cGuestModeChanges;
3695	/** The number of times the guest has switched mode since last reset or statistics reset. */
3696	STAMCOUNTER cA20Changes;
3697	/** @} */
3698
3699	#ifdef VBOX_WITH_STATISTICS
3700	/** These are statistics that used to be on the hyper heap. */
3701	PGMCPUSTATS Stats;
3702	#endif
3703	} PGMCPU;
3704	/** Pointer to the per-cpu PGM data. */
3705	typedef PGMCPU *PPGMCPU;
3706
3707
3708	/** @name PGM::fSyncFlags Flags
3709	* @note Was part of saved state a long time ago.
3710	* @{
3711	*/
3712	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3713	/** Always sync CR3. */
3714	#define PGM_SYNC_ALWAYS RT_BIT(1)
3715	/** Check guest mapping in SyncCR3. */
3716	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3717	/** Clear the page pool (a light weight flush). */
3718	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3719	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3720	/** @} */
3721
3722
3723	#if defined(IN_RING0) \|\| defined(DOXYGEN_RUNNING)
3724
3725	/**
3726	* PGM GVMCPU instance data.
3727	*/
3728	typedef struct PGMR0PERVCPU
3729	{
3730	# ifdef VBOX_WITH_STATISTICS
3731	/** R0: Which statistic this \#PF should be attributed to. */
3732	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3733	# endif
3734	uint64_t u64Dummy;
3735	} PGMR0PERVCPU;
3736
3737
3738	/**
3739	* PGM GVM instance data.
3740	*/
3741	typedef struct PGMR0PERVM
3742	{
3743	/** @name RAM ranges
3744	* @{ */
3745	/** The ring-0 RAM range pointer table. */
3746	R0PTRTYPE(PPGMRAMRANGE) apRamRanges[PGM_MAX_RAM_RANGES];
3747	/** Trusted RAM range page counts running parallel to apRamRanges.
3748	* This keeps the original page count when a range is reduced,
3749	* only the PGMRAMRANGE::cb member is changed then. */
3750	uint32_t acRamRangePages[PGM_MAX_RAM_RANGES];
3751	/** The memory objects for the RAM ranges (parallel to apRamRanges). */
3752	RTR0MEMOBJ ahRamRangeMemObjs[PGM_MAX_RAM_RANGES];
3753	/** The ring-3 mapping objects for the RAM ranges (parallel to apRamRanges). */
3754	RTR0MEMOBJ ahRamRangeMapObjs[PGM_MAX_RAM_RANGES];
3755	/** The max RAM range ID (safe). */
3756	uint32_t idRamRangeMax;
3757	uint8_t abAlignment1[64 - sizeof(uint32_t)];
3758	/** RAM range TLB for R0. */
3759	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlb[PGM_RAMRANGE_TLB_ENTRIES];
3760	/** @} */
3761
3762	/** @name MMIO2 ranges
3763	* @{ */
3764	/** The ring-0 RAM range pointer table running parallel to aMmio2Ranges. */
3765	R0PTRTYPE(PPGMRAMRANGE) apMmio2RamRanges[PGM_MAX_MMIO2_RANGES];
3766	/** The memory objects for the MMIO2 backing memory (parallel to
3767	* apMmio2RamRanges). */
3768	RTR0MEMOBJ ahMmio2MemObjs[PGM_MAX_MMIO2_RANGES];
3769	/** The ring-3 mapping objects for the MMIO2 backing memory (parallel
3770	* to apMmio2RamRanges & ahMmio2MemObjs). */
3771	RTR0MEMOBJ ahMmio2MapObjs[PGM_MAX_MMIO2_RANGES];
3772	/** Trusted MMIO2 range sizes (count of guest pages).
3773	* This keeps the original page count when a range is reduced,
3774	* only the PGMRAMRANGE::cb member is changed then. */
3775	uint32_t acMmio2RangePages[PGM_MAX_MMIO2_RANGES];
3776	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3777	/** Pointer to the ring-0 mapping of the MMIO2 backings (parallel to
3778	* apMmio2RamRanges). */
3779	R0PTRTYPE(uint8_t *) apbMmio2Backing[PGM_MAX_MMIO2_RANGES];
3780	#endif
3781	/** @} */
3782
3783	/** @name ROM ranges
3784	* @{ */
3785	/** The ring-0 ROM range pointer table. */
3786	R0PTRTYPE(PPGMROMRANGE) apRomRanges[PGM_MAX_ROM_RANGES];
3787	/** The memory objects for each ROM range (parallel to apRomRanges). */
3788	RTR0MEMOBJ ahRomRangeMemObjs[PGM_MAX_ROM_RANGES];
3789	/** The ring-3 mapping objects for each ROM range (parallel to apRomRanges
3790	* & ahRamRangeMemObjs). */
3791	RTR0MEMOBJ ahRomRangeMapObjs[PGM_MAX_ROM_RANGES];
3792	/** Trusted ROM range sizes (count of guest pages). */
3793	uint32_t acRomRangePages[PGM_MAX_ROM_RANGES];
3794	/** @} */
3795
3796	/** @name PGM Pool related stuff.
3797	* @{ */
3798	/** Critical section for serializing pool growth. */
3799	RTCRITSECT PoolGrowCritSect;
3800	/** The memory objects for the pool pages. */
3801	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3802	/** The ring-3 mapping objects for the pool pages. */
3803	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3804	/** @} */
3805
3806	/** Physical access handler types for ring-0.
3807	* Initialized to callback causing return to ring-3 and invalid enmKind. */
3808	PGMPHYSHANDLERTYPEINTR0 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3809	/** Physical handler allocator, ring-3 edition. */
3810	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3811	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3812	PPGMPHYSHANDLERTREE pPhysHandlerTree;
3813	/** The allocation object for the physical access handler tree. */
3814	RTR0MEMOBJ hPhysHandlerMemObj;
3815	/** The ring-3 mapping object for the physicall access handler tree. */
3816	RTR0MEMOBJ hPhysHandlerMapObj;
3817	} PGMR0PERVM;
3818
3819	#endif /* IN_RING0 \|\| DOXYGEN_RUNNING */
3820
3821	RT_C_DECLS_BEGIN
3822
3823	#if defined(VBOX_STRICT)
3824	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3825	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3826	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3827	#else
3828	int pgmLock(PVMCC pVM, bool fVoid);
3829	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3830	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3831	#endif
3832	void pgmUnlock(PVMCC pVM);
3833	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3834	/**
3835	* Asserts that the caller owns the PDM lock.
3836	* This is the internal variant of PGMIsLockOwner.
3837	* @param a_pVM Pointer to the VM.
3838	*/
3839	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3840	/**
3841	* Asserts that the caller owns the PDM lock.
3842	* This is the internal variant of PGMIsLockOwner.
3843	* @param a_pVM Pointer to the VM.
3844	* @param a_pVCpu The current CPU handle.
3845	*/
3846	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3847
3848	uint32_t pgmHandlerPhysicalCalcTableSizes(uint32_t pcEntries, uint32_t pcbTreeAndBitmap);
3849	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3850	R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3851	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3852	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3853	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3854	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3855	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3856	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3857	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam,
3858	bool fDoAccounting, bool fFlushIemTlbs);
3859	DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3860	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3861	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR3HandlerPhysicalHandlerInvalid;
3862	#ifndef IN_RING3
3863	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR0HandlerPhysicalHandlerToRing3;
3864	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmR0HandlerPhysicalPfHandlerToRing3;
3865	#endif
3866
3867	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3868
3869	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3870	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3871	#ifdef IN_RING0
3872	int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
3873	int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3874	#endif
3875	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3876	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3877	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3878	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3879	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3880	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3881	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3882	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3883	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3884	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3885	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3886	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3887	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3888	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3889	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3890	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3891	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3892	#ifndef IN_RING3
3893	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3894	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3895	#endif
3896	DECLHIDDEN(uint16_t) pgmPhysMmio2CalcChunkCount(RTGCPHYS cb, uint32_t *pcPagesPerChunk);
3897	DECLHIDDEN(int) pgmPhysMmio2RegisterWorker(PVMCC pVM, uint32_t const cGuestPages, uint8_t const idMmio2,
3898	const uint8_t cChunks, PPDMDEVINSR3 const pDevIns, uint8_t
3899	const iSubDev, uint8_t const iRegion, uint32_t const fFlags);
3900	DECLHIDDEN(int) pgmPhysMmio2DeregisterWorker(PVMCC pVM, uint8_t idMmio2, uint8_t cChunks, PPDMDEVINSR3 pDevIns);
3901	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3902	PGMPAGETYPE enmNewType);
3903	#ifdef VBOX_STRICT
3904	DECLHIDDEN(bool) pgmPhysAssertRamRangesLocked(PVMCC pVM, bool fInUpdate, bool fRamRelaxed);
3905	#endif
3906	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3907	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3908	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3909	PPGMRAMRANGE pgmPhysGetRangeSlow(PVMCC pVM, RTGCPHYS GCPhys);
3910	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVMCC pVM, RTGCPHYS GCPhys);
3911	PPGMPAGE pgmPhysGetPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3912	int pgmPhysGetPageExSlow(PVMCC pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3913	int pgmPhysGetPageAndRangeExSlow(PVMCC pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3914	DECLHIDDEN(int) pgmPhysRamRangeAllocCommon(PVMCC pVM, uint32_t cPages, uint32_t fFlags, uint32_t *pidNewRange);
3915	DECLHIDDEN(int) pgmPhysRomRangeAllocCommon(PVMCC pVM, uint32_t cPages, uint8_t idRomRange, uint32_t fFlags);
3916	#ifdef VBOX_WITH_NATIVE_NEM
3917	void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3918	#endif
3919
3920	#ifdef IN_RING3
3921	int pgmR3PhysRamPreAllocate(PVM pVM);
3922	int pgmR3PhysRamReset(PVM pVM);
3923	int pgmR3PhysRomReset(PVM pVM);
3924	int pgmR3PhysRamZeroAll(PVM pVM);
3925	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3926	int pgmR3PhysRamTerm(PVM pVM);
3927	void pgmR3PhysRomTerm(PVM pVM);
3928	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3929
3930	int pgmR3PoolInit(PVM pVM);
3931	void pgmR3PoolRelocate(PVM pVM);
3932	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3933	void pgmR3PoolReset(PVM pVM);
3934	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3935	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3936	void pgmR3PoolWriteProtectPages(PVM pVM);
3937
3938	#endif /* IN_RING3 */
3939	#ifdef IN_RING0
3940	int pgmR0PoolInitVM(PGVM pGVM);
3941	#endif
3942	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3943	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3944	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3945	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3946	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3947	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3948	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3949	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3950	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3951	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3952	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3953	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3954	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3955	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3956	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3957	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3958	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3959	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3960	FNPGMPHYSHANDLER pgmPoolAccessHandler;
3961	#ifndef IN_RING3
3962	FNPGMRZPHYSPFHANDLER pgmRZPoolAccessPfHandler;
3963	#endif
3964
3965	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3966	void pgmPoolResetDirtyPages(PVMCC pVM);
3967	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3968
3969	/** Gets the ring-0 pointer for the given pool page. */
3970	DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3971	{
3972	#ifdef IN_RING3
3973	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3974	# ifdef VBOX_STRICT
3975	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3976	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
3977	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
3978	# endif
3979	return pPool->pPoolR0 + offPage;
3980	#else
3981	RT_NOREF(pPool);
3982	return pPage;
3983	#endif
3984	}
3985
3986	/** Gets the ring-3 pointer for the given pool page. */
3987	DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3988	{
3989	#ifdef IN_RING3
3990	RT_NOREF(pPool);
3991	return pPage;
3992	#else
3993	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3994	# ifdef VBOX_STRICT
3995	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3996	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
3997	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
3998	# endif
3999	return pPool->pPoolR3 + offPage;
4000	#endif
4001	}
4002
4003	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4004	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4005	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4006
4007	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4008	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4009	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4010
4011	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
4012	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
4013	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4014	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
4015	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
4016	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
4017	#endif
4018	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
4019	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
4020
4021	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4022	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4023	FNDBGCCMD pgmR3CmdShowSharedModules;
4024	# endif
4025
4026	void pgmLogState(PVM pVM);
4027
4028	RT_C_DECLS_END
4029
4030	/** @} */
4031
4032	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
4033

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 104859

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