VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 84044

Last change on this file since 84044 was 83987, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Naming nit.
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1/* $Id: PDMInternal.h 83987 2020-04-27 08:40:42Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
19#define VMM_INCLUDED_SRC_include_PDMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/types.h>
25#include <VBox/param.h>
26#include <VBox/vmm/cfgm.h>
27#include <VBox/vmm/stam.h>
28#include <VBox/vusb.h>
29#include <VBox/vmm/pdmasynccompletion.h>
30#ifdef VBOX_WITH_NETSHAPER
31# include <VBox/vmm/pdmnetshaper.h>
32#endif
33#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
34# include <VBox/vmm/pdmasynccompletion.h>
35#endif
36#include <VBox/vmm/pdmblkcache.h>
37#include <VBox/vmm/pdmcommon.h>
38#include <VBox/vmm/pdmtask.h>
39#include <VBox/sup.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42#ifdef IN_RING3
43# include <iprt/thread.h>
44#endif
45
46RT_C_DECLS_BEGIN
47
48
49/** @defgroup grp_pdm_int Internal
50 * @ingroup grp_pdm
51 * @internal
52 * @{
53 */
54
55/** @def PDM_WITH_R3R0_CRIT_SECT
56 * Enables or disabled ring-3/ring-0 critical sections. */
57#if defined(DOXYGEN_RUNNING) || 1
58# define PDM_WITH_R3R0_CRIT_SECT
59#endif
60
61/** @def PDMCRITSECT_STRICT
62 * Enables/disables PDM critsect strictness like deadlock detection. */
63#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
64 || defined(DOXYGEN_RUNNING)
65# define PDMCRITSECT_STRICT
66#endif
67
68/** @def PDMCRITSECT_STRICT
69 * Enables/disables PDM read/write critsect strictness like deadlock
70 * detection. */
71#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
72 || defined(DOXYGEN_RUNNING)
73# define PDMCRITSECTRW_STRICT
74#endif
75
76/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
77#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
78/** The maximum device instance (total) size, ring-3 only devices. */
79#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
80
81
82
83/*******************************************************************************
84* Structures and Typedefs *
85*******************************************************************************/
86
87/** Pointer to a PDM Device. */
88typedef struct PDMDEV *PPDMDEV;
89/** Pointer to a pointer to a PDM Device. */
90typedef PPDMDEV *PPPDMDEV;
91
92/** Pointer to a PDM USB Device. */
93typedef struct PDMUSB *PPDMUSB;
94/** Pointer to a pointer to a PDM USB Device. */
95typedef PPDMUSB *PPPDMUSB;
96
97/** Pointer to a PDM Driver. */
98typedef struct PDMDRV *PPDMDRV;
99/** Pointer to a pointer to a PDM Driver. */
100typedef PPDMDRV *PPPDMDRV;
101
102/** Pointer to a PDM Logical Unit. */
103typedef struct PDMLUN *PPDMLUN;
104/** Pointer to a pointer to a PDM Logical Unit. */
105typedef PPDMLUN *PPPDMLUN;
106
107/** Pointer to a PDM PCI Bus instance. */
108typedef struct PDMPCIBUS *PPDMPCIBUS;
109/** Pointer to a PDM IOMMU instance. */
110typedef struct PDMIOMMU *PPDMIOMMU;
111/** Pointer to a DMAC instance. */
112typedef struct PDMDMAC *PPDMDMAC;
113/** Pointer to a RTC instance. */
114typedef struct PDMRTC *PPDMRTC;
115
116/** Pointer to an USB HUB registration record. */
117typedef struct PDMUSBHUB *PPDMUSBHUB;
118
119/**
120 * Supported asynchronous completion endpoint classes.
121 */
122typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
123{
124 /** File class. */
125 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
126 /** Number of supported classes. */
127 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
128 /** 32bit hack. */
129 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
130} PDMASYNCCOMPLETIONEPCLASSTYPE;
131
132/**
133 * Private device instance data, ring-3.
134 */
135typedef struct PDMDEVINSINTR3
136{
137 /** Pointer to the next instance.
138 * (Head is pointed to by PDM::pDevInstances.) */
139 R3PTRTYPE(PPDMDEVINS) pNextR3;
140 /** Pointer to the next per device instance.
141 * (Head is pointed to by PDMDEV::pInstances.) */
142 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
143 /** Pointer to device structure. */
144 R3PTRTYPE(PPDMDEV) pDevR3;
145 /** Pointer to the list of logical units associated with the device. (FIFO) */
146 R3PTRTYPE(PPDMLUN) pLunsR3;
147 /** Pointer to the asynchronous notification callback set while in
148 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
149 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
150 /** Configuration handle to the instance node. */
151 R3PTRTYPE(PCFGMNODE) pCfgHandle;
152
153 /** R3 pointer to the VM this instance was created for. */
154 PVMR3 pVMR3;
155
156 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
157 uint32_t fIntFlags;
158 /** The last IRQ tag (for tracing it thru clearing). */
159 uint32_t uLastIrqTag;
160 /** The ring-0 device index (for making ring-0 calls). */
161 uint32_t idxR0Device;
162} PDMDEVINSINTR3;
163
164
165/**
166 * Private device instance data, ring-0.
167 */
168typedef struct PDMDEVINSINTR0
169{
170 /** Pointer to the VM this instance was created for. */
171 R0PTRTYPE(PGVM) pGVM;
172 /** Pointer to device structure. */
173 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
174 /** The ring-0 module reference. */
175 RTR0PTR hMod;
176 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
177 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
178 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
179 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
180 /** The device instance memory. */
181 RTR0MEMOBJ hMemObj;
182 /** The ring-3 mapping object. */
183 RTR0MEMOBJ hMapObj;
184 /** Index into PDMR0PERVM::apDevInstances. */
185 uint32_t idxR0Device;
186} PDMDEVINSINTR0;
187
188
189/**
190 * Private device instance data, raw-mode
191 */
192typedef struct PDMDEVINSINTRC
193{
194 /** Pointer to the VM this instance was created for. */
195 RGPTRTYPE(PVM) pVMRC;
196} PDMDEVINSINTRC;
197
198
199/**
200 * Private device instance data.
201 */
202typedef struct PDMDEVINSINT
203{
204 /** Pointer to the next instance (HC Ptr).
205 * (Head is pointed to by PDM::pDevInstances.) */
206 R3PTRTYPE(PPDMDEVINS) pNextR3;
207 /** Pointer to the next per device instance (HC Ptr).
208 * (Head is pointed to by PDMDEV::pInstances.) */
209 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
210 /** Pointer to device structure - HC Ptr. */
211 R3PTRTYPE(PPDMDEV) pDevR3;
212 /** Pointer to the list of logical units associated with the device. (FIFO) */
213 R3PTRTYPE(PPDMLUN) pLunsR3;
214 /** Pointer to the asynchronous notification callback set while in
215 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
216 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
217 /** Configuration handle to the instance node. */
218 R3PTRTYPE(PCFGMNODE) pCfgHandle;
219
220 /** R3 pointer to the VM this instance was created for. */
221 PVMR3 pVMR3;
222
223 /** R0 pointer to the VM this instance was created for. */
224 R0PTRTYPE(PVMCC) pVMR0;
225
226 /** RC pointer to the VM this instance was created for. */
227 PVMRC pVMRC;
228
229 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
230 uint32_t fIntFlags;
231 /** The last IRQ tag (for tracing it thru clearing). */
232 uint32_t uLastIrqTag;
233} PDMDEVINSINT;
234
235/** @name PDMDEVINSINT::fIntFlags
236 * @{ */
237/** Used by pdmR3Load to mark device instances it found in the saved state. */
238#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
239/** Indicates that the device hasn't been powered on or resumed.
240 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
241 * to make sure each device gets exactly one notification for each of those
242 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
243 * a failure (already resumed/powered-on devices are suspended).
244 * PDMR3PowerOff resets this flag once before going through the devices to make sure
245 * every device gets the power off notification even if it was suspended before with
246 * PDMR3Suspend.
247 */
248#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
249/** Indicates that the device has been reset already. Used by PDMR3Reset. */
250#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
251#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
252#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
253/** Set if we've called the ring-0 constructor. */
254#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
255/** Set if using non-default critical section. */
256#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
257/** @} */
258
259
260/**
261 * Private USB device instance data.
262 */
263typedef struct PDMUSBINSINT
264{
265 /** The UUID of this instance. */
266 RTUUID Uuid;
267 /** Pointer to the next instance.
268 * (Head is pointed to by PDM::pUsbInstances.) */
269 R3PTRTYPE(PPDMUSBINS) pNext;
270 /** Pointer to the next per USB device instance.
271 * (Head is pointed to by PDMUSB::pInstances.) */
272 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
273
274 /** Pointer to device structure. */
275 R3PTRTYPE(PPDMUSB) pUsbDev;
276
277 /** Pointer to the VM this instance was created for. */
278 PVMR3 pVM;
279 /** Pointer to the list of logical units associated with the device. (FIFO) */
280 R3PTRTYPE(PPDMLUN) pLuns;
281 /** The per instance device configuration. */
282 R3PTRTYPE(PCFGMNODE) pCfg;
283 /** Same as pCfg if the configuration should be deleted when detaching the device. */
284 R3PTRTYPE(PCFGMNODE) pCfgDelete;
285 /** The global device configuration. */
286 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
287
288 /** Pointer to the USB hub this device is attached to.
289 * This is NULL if the device isn't connected to any HUB. */
290 R3PTRTYPE(PPDMUSBHUB) pHub;
291 /** The port number that we're connected to. */
292 uint32_t iPort;
293 /** Indicates that the USB device hasn't been powered on or resumed.
294 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
295 bool fVMSuspended;
296 /** Indicates that the USB device has been reset. */
297 bool fVMReset;
298 /** Pointer to the asynchronous notification callback set while in
299 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
300 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
301} PDMUSBINSINT;
302
303
304/**
305 * Private driver instance data.
306 */
307typedef struct PDMDRVINSINT
308{
309 /** Pointer to the driver instance above.
310 * This is NULL for the topmost drive. */
311 R3PTRTYPE(PPDMDRVINS) pUp;
312 /** Pointer to the driver instance below.
313 * This is NULL for the bottommost driver. */
314 R3PTRTYPE(PPDMDRVINS) pDown;
315 /** Pointer to the logical unit this driver chained on. */
316 R3PTRTYPE(PPDMLUN) pLun;
317 /** Pointer to driver structure from which this was instantiated. */
318 R3PTRTYPE(PPDMDRV) pDrv;
319 /** Pointer to the VM this instance was created for, ring-3 context. */
320 PVMR3 pVMR3;
321 /** Pointer to the VM this instance was created for, ring-0 context. */
322 R0PTRTYPE(PVMCC) pVMR0;
323 /** Pointer to the VM this instance was created for, raw-mode context. */
324 PVMRC pVMRC;
325 /** Flag indicating that the driver is being detached and destroyed.
326 * (Helps detect potential recursive detaching.) */
327 bool fDetaching;
328 /** Indicates that the driver hasn't been powered on or resumed.
329 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
330 bool fVMSuspended;
331 /** Indicates that the driver has been reset already. */
332 bool fVMReset;
333 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
334 bool fHyperHeap;
335 /** Pointer to the asynchronous notification callback set while in
336 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
337 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
338 /** Configuration handle to the instance node. */
339 R3PTRTYPE(PCFGMNODE) pCfgHandle;
340 /** Pointer to the ring-0 request handler function. */
341 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
342} PDMDRVINSINT;
343
344
345/**
346 * Private critical section data.
347 */
348typedef struct PDMCRITSECTINT
349{
350 /** The critical section core which is shared with IPRT.
351 * @note The semaphore is a SUPSEMEVENT. */
352 RTCRITSECT Core;
353 /** Pointer to the next critical section.
354 * This chain is used for relocating pVMRC and device cleanup. */
355 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
356 /** Owner identifier.
357 * This is pDevIns if the owner is a device. Similarly for a driver or service.
358 * PDMR3CritSectInit() sets this to point to the critsect itself. */
359 RTR3PTR pvKey;
360 /** Pointer to the VM - R3Ptr. */
361 PVMR3 pVMR3;
362 /** Pointer to the VM - R0Ptr. */
363 R0PTRTYPE(PVMCC) pVMR0;
364 /** Pointer to the VM - GCPtr. */
365 PVMRC pVMRC;
366 /** Set if this critical section is the automatically created default
367 * section of a device. */
368 bool fAutomaticDefaultCritsect;
369 /** Set if the critical section is used by a timer or similar.
370 * See PDMR3DevGetCritSect. */
371 bool fUsedByTimerOrSimilar;
372 /** Alignment padding. */
373 bool afPadding[2];
374 /** Support driver event semaphore that is scheduled to be signaled upon leaving
375 * the critical section. This is only for Ring-3 and Ring-0. */
376 SUPSEMEVENT hEventToSignal;
377 /** The lock name. */
378 R3PTRTYPE(const char *) pszName;
379 /** R0/RC lock contention. */
380 STAMCOUNTER StatContentionRZLock;
381 /** R0/RC unlock contention. */
382 STAMCOUNTER StatContentionRZUnlock;
383 /** R3 lock contention. */
384 STAMCOUNTER StatContentionR3;
385 /** Profiling the time the section is locked. */
386 STAMPROFILEADV StatLocked;
387} PDMCRITSECTINT;
388AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
389/** Pointer to private critical section data. */
390typedef PDMCRITSECTINT *PPDMCRITSECTINT;
391
392/** Indicates that the critical section is queued for unlock.
393 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
394#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
395
396
397/**
398 * Private critical section data.
399 */
400typedef struct PDMCRITSECTRWINT
401{
402 /** The read/write critical section core which is shared with IPRT.
403 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
404 RTCRITSECTRW Core;
405
406 /** Pointer to the next critical section.
407 * This chain is used for relocating pVMRC and device cleanup. */
408 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
409 /** Owner identifier.
410 * This is pDevIns if the owner is a device. Similarly for a driver or service.
411 * PDMR3CritSectInit() sets this to point to the critsect itself. */
412 RTR3PTR pvKey;
413 /** Pointer to the VM - R3Ptr. */
414 PVMR3 pVMR3;
415 /** Pointer to the VM - R0Ptr. */
416 R0PTRTYPE(PVMCC) pVMR0;
417 /** Pointer to the VM - GCPtr. */
418 PVMRC pVMRC;
419#if HC_ARCH_BITS == 64
420 /** Alignment padding. */
421 RTRCPTR RCPtrPadding;
422#endif
423 /** The lock name. */
424 R3PTRTYPE(const char *) pszName;
425 /** R0/RC write lock contention. */
426 STAMCOUNTER StatContentionRZEnterExcl;
427 /** R0/RC write unlock contention. */
428 STAMCOUNTER StatContentionRZLeaveExcl;
429 /** R0/RC read lock contention. */
430 STAMCOUNTER StatContentionRZEnterShared;
431 /** R0/RC read unlock contention. */
432 STAMCOUNTER StatContentionRZLeaveShared;
433 /** R0/RC writes. */
434 STAMCOUNTER StatRZEnterExcl;
435 /** R0/RC reads. */
436 STAMCOUNTER StatRZEnterShared;
437 /** R3 write lock contention. */
438 STAMCOUNTER StatContentionR3EnterExcl;
439 /** R3 read lock contention. */
440 STAMCOUNTER StatContentionR3EnterShared;
441 /** R3 writes. */
442 STAMCOUNTER StatR3EnterExcl;
443 /** R3 reads. */
444 STAMCOUNTER StatR3EnterShared;
445 /** Profiling the time the section is write locked. */
446 STAMPROFILEADV StatWriteLocked;
447} PDMCRITSECTRWINT;
448AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
449AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u64State, 8);
450/** Pointer to private critical section data. */
451typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
452
453
454
455/**
456 * The usual device/driver/internal/external stuff.
457 */
458typedef enum
459{
460 /** The usual invalid entry. */
461 PDMTHREADTYPE_INVALID = 0,
462 /** Device type. */
463 PDMTHREADTYPE_DEVICE,
464 /** USB Device type. */
465 PDMTHREADTYPE_USB,
466 /** Driver type. */
467 PDMTHREADTYPE_DRIVER,
468 /** Internal type. */
469 PDMTHREADTYPE_INTERNAL,
470 /** External type. */
471 PDMTHREADTYPE_EXTERNAL,
472 /** The usual 32-bit hack. */
473 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
474} PDMTHREADTYPE;
475
476
477/**
478 * The internal structure for the thread.
479 */
480typedef struct PDMTHREADINT
481{
482 /** The VM pointer. */
483 PVMR3 pVM;
484 /** The event semaphore the thread blocks on when not running. */
485 RTSEMEVENTMULTI BlockEvent;
486 /** The event semaphore the thread sleeps on while running. */
487 RTSEMEVENTMULTI SleepEvent;
488 /** Pointer to the next thread. */
489 R3PTRTYPE(struct PDMTHREAD *) pNext;
490 /** The thread type. */
491 PDMTHREADTYPE enmType;
492} PDMTHREADINT;
493
494
495
496/* Must be included after PDMDEVINSINT is defined. */
497#define PDMDEVINSINT_DECLARED
498#define PDMUSBINSINT_DECLARED
499#define PDMDRVINSINT_DECLARED
500#define PDMCRITSECTINT_DECLARED
501#define PDMCRITSECTRWINT_DECLARED
502#define PDMTHREADINT_DECLARED
503#ifdef ___VBox_pdm_h
504# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
505#endif
506RT_C_DECLS_END
507#include <VBox/vmm/pdm.h>
508RT_C_DECLS_BEGIN
509
510/**
511 * PDM Logical Unit.
512 *
513 * This typically the representation of a physical port on a
514 * device, like for instance the PS/2 keyboard port on the
515 * keyboard controller device. The LUNs are chained on the
516 * device they belong to (PDMDEVINSINT::pLunsR3).
517 */
518typedef struct PDMLUN
519{
520 /** The LUN - The Logical Unit Number. */
521 RTUINT iLun;
522 /** Pointer to the next LUN. */
523 PPDMLUN pNext;
524 /** Pointer to the top driver in the driver chain. */
525 PPDMDRVINS pTop;
526 /** Pointer to the bottom driver in the driver chain. */
527 PPDMDRVINS pBottom;
528 /** Pointer to the device instance which the LUN belongs to.
529 * Either this is set or pUsbIns is set. Both is never set at the same time. */
530 PPDMDEVINS pDevIns;
531 /** Pointer to the USB device instance which the LUN belongs to. */
532 PPDMUSBINS pUsbIns;
533 /** Pointer to the device base interface. */
534 PPDMIBASE pBase;
535 /** Description of this LUN. */
536 const char *pszDesc;
537} PDMLUN;
538
539
540/**
541 * PDM Device, ring-3.
542 */
543typedef struct PDMDEV
544{
545 /** Pointer to the next device (R3 Ptr). */
546 R3PTRTYPE(PPDMDEV) pNext;
547 /** Device name length. (search optimization) */
548 uint32_t cchName;
549 /** Registration structure. */
550 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
551 /** Number of instances. */
552 uint32_t cInstances;
553 /** Pointer to chain of instances (R3 Ptr). */
554 PPDMDEVINSR3 pInstances;
555 /** The search path for raw-mode context modules (';' as separator). */
556 char *pszRCSearchPath;
557 /** The search path for ring-0 context modules (';' as separator). */
558 char *pszR0SearchPath;
559} PDMDEV;
560
561
562#if 0
563/**
564 * PDM Device, ring-0.
565 */
566typedef struct PDMDEVR0
567{
568 /** Pointer to the next device. */
569 R0PTRTYPE(PPDMDEVR0) pNext;
570 /** Device name length. (search optimization) */
571 uint32_t cchName;
572 /** Registration structure. */
573 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
574 /** Number of instances. */
575 uint32_t cInstances;
576 /** Pointer to chain of instances. */
577 PPDMDEVINSR0 pInstances;
578} PDMDEVR0;
579#endif
580
581
582/**
583 * PDM USB Device.
584 */
585typedef struct PDMUSB
586{
587 /** Pointer to the next device (R3 Ptr). */
588 R3PTRTYPE(PPDMUSB) pNext;
589 /** Device name length. (search optimization) */
590 RTUINT cchName;
591 /** Registration structure. */
592 R3PTRTYPE(const struct PDMUSBREG *) pReg;
593 /** Next instance number. */
594 uint32_t iNextInstance;
595 /** Pointer to chain of instances (R3 Ptr). */
596 R3PTRTYPE(PPDMUSBINS) pInstances;
597} PDMUSB;
598
599
600/**
601 * PDM Driver.
602 */
603typedef struct PDMDRV
604{
605 /** Pointer to the next device. */
606 PPDMDRV pNext;
607 /** Registration structure. */
608 const struct PDMDRVREG * pReg;
609 /** Current number of instances. */
610 uint32_t cInstances;
611 /** The next instance number. */
612 uint32_t iNextInstance;
613 /** The search path for raw-mode context modules (';' as separator). */
614 char *pszRCSearchPath;
615 /** The search path for ring-0 context modules (';' as separator). */
616 char *pszR0SearchPath;
617} PDMDRV;
618
619
620/**
621 * PDM registered IOMMU device.
622 */
623typedef struct PDMIOMMU
624{
625 /** IOMMU index. */
626 uint32_t idxIommu;
627 uint32_t uPadding0; /**< Alignment padding.*/
628
629 /** Pointer to the IOMMU device instance - R3. */
630 PPDMDEVINSR3 pDevInsR3;
631 /** @copydoc PDMIOMMUREGR3::pfnMemRead */
632 DECLR3CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbRead,
633 PRTGCPHYS pGCPhysOut));
634 /** @copydoc PDMIOMMUREGR3::pfnMemWrite */
635 DECLR3CALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbWrite,
636 PRTGCPHYS pGCPhysOut));
637} PDMIOMMU;
638
639
640/**
641 * Ring-0 PDM IOMMU instance data.
642 */
643typedef struct PDMIOMMUR0
644{
645 /** IOMMU index. */
646 uint32_t idxIommu;
647 uint32_t uPadding0; /**< Alignment padding.*/
648
649 /** Pointer to IOMMU device instance. */
650 PPDMDEVINSR0 pDevInsR0;
651 /** @copydoc PDMIOMMUREGR0::pfnMemRead */
652 DECLR0CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbRead,
653 PRTGCPHYS pGCPhysOut));
654 /** @copydoc PDMIOMMUREGR3::pfnMemWrite */
655 DECLR0CALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbWrite,
656 PRTGCPHYS pGCPhysOut));
657} PDMIOMMUR0;
658/** Pointer to a ring-0 IOMMU data. */
659typedef PDMIOMMUR0 *PPDMIOMMUR0;
660/** Pointer to a const ring-0 IOMMU data. */
661typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
662
663
664/**
665 * PDM registered PIC device.
666 */
667typedef struct PDMPIC
668{
669 /** Pointer to the PIC device instance - R3. */
670 PPDMDEVINSR3 pDevInsR3;
671 /** @copydoc PDMPICREG::pfnSetIrq */
672 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
673 /** @copydoc PDMPICREG::pfnGetInterrupt */
674 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
675
676 /** Pointer to the PIC device instance - R0. */
677 PPDMDEVINSR0 pDevInsR0;
678 /** @copydoc PDMPICREG::pfnSetIrq */
679 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
680 /** @copydoc PDMPICREG::pfnGetInterrupt */
681 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
682
683 /** Pointer to the PIC device instance - RC. */
684 PPDMDEVINSRC pDevInsRC;
685 /** @copydoc PDMPICREG::pfnSetIrq */
686 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
687 /** @copydoc PDMPICREG::pfnGetInterrupt */
688 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
689 /** Alignment padding. */
690 RTRCPTR RCPtrPadding;
691} PDMPIC;
692
693
694/**
695 * PDM registered APIC device.
696 */
697typedef struct PDMAPIC
698{
699 /** Pointer to the APIC device instance - R3 Ptr. */
700 PPDMDEVINSR3 pDevInsR3;
701 /** Pointer to the APIC device instance - R0 Ptr. */
702 PPDMDEVINSR0 pDevInsR0;
703 /** Pointer to the APIC device instance - RC Ptr. */
704 PPDMDEVINSRC pDevInsRC;
705 uint8_t Alignment[4];
706} PDMAPIC;
707
708
709/**
710 * PDM registered I/O APIC device.
711 */
712typedef struct PDMIOAPIC
713{
714 /** Pointer to the APIC device instance - R3 Ptr. */
715 PPDMDEVINSR3 pDevInsR3;
716 /** @copydoc PDMIOAPICREG::pfnSetIrq */
717 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
718 /** @copydoc PDMIOAPICREG::pfnSendMsi */
719 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
720 /** @copydoc PDMIOAPICREG::pfnSetEoi */
721 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
722
723 /** Pointer to the PIC device instance - R0. */
724 PPDMDEVINSR0 pDevInsR0;
725 /** @copydoc PDMIOAPICREG::pfnSetIrq */
726 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
727 /** @copydoc PDMIOAPICREG::pfnSendMsi */
728 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
729 /** @copydoc PDMIOAPICREG::pfnSetEoi */
730 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
731
732 /** Pointer to the APIC device instance - RC Ptr. */
733 PPDMDEVINSRC pDevInsRC;
734 /** @copydoc PDMIOAPICREG::pfnSetIrq */
735 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
736 /** @copydoc PDMIOAPICREG::pfnSendMsi */
737 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
738 /** @copydoc PDMIOAPICREG::pfnSendMsi */
739 DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
740} PDMIOAPIC;
741
742/** Maximum number of PCI busses for a VM. */
743#define PDM_PCI_BUSSES_MAX 8
744/** Maximum number of IOMMUs (at most one per PCI bus). */
745#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
746
747
748#ifdef IN_RING3
749/**
750 * PDM registered firmware device.
751 */
752typedef struct PDMFW
753{
754 /** Pointer to the firmware device instance. */
755 PPDMDEVINSR3 pDevIns;
756 /** Copy of the registration structure. */
757 PDMFWREG Reg;
758} PDMFW;
759/** Pointer to a firmware instance. */
760typedef PDMFW *PPDMFW;
761#endif
762
763
764/**
765 * PDM PCI bus instance.
766 */
767typedef struct PDMPCIBUS
768{
769 /** PCI bus number. */
770 uint32_t iBus;
771 uint32_t uPadding0; /**< Alignment padding.*/
772
773 /** Pointer to PCI bus device instance. */
774 PPDMDEVINSR3 pDevInsR3;
775 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
776 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
777
778 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
779 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
780 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
781 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
782 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
783 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
784 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
785 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
786 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
787 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
788 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
789 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
790 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
791 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
792 uint32_t uAddress, unsigned cb, uint32_t u32Value));
793 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
794 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
795 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
796} PDMPCIBUS;
797
798
799/**
800 * Ring-0 PDM PCI bus instance data.
801 */
802typedef struct PDMPCIBUSR0
803{
804 /** PCI bus number. */
805 uint32_t iBus;
806 uint32_t uPadding0; /**< Alignment padding.*/
807 /** Pointer to PCI bus device instance. */
808 PPDMDEVINSR0 pDevInsR0;
809 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
810 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
811} PDMPCIBUSR0;
812/** Pointer to the ring-0 PCI bus data. */
813typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
814
815
816#ifdef IN_RING3
817/**
818 * PDM registered DMAC (DMA Controller) device.
819 */
820typedef struct PDMDMAC
821{
822 /** Pointer to the DMAC device instance. */
823 PPDMDEVINSR3 pDevIns;
824 /** Copy of the registration structure. */
825 PDMDMACREG Reg;
826} PDMDMAC;
827
828
829/**
830 * PDM registered RTC (Real Time Clock) device.
831 */
832typedef struct PDMRTC
833{
834 /** Pointer to the RTC device instance. */
835 PPDMDEVINSR3 pDevIns;
836 /** Copy of the registration structure. */
837 PDMRTCREG Reg;
838} PDMRTC;
839
840#endif /* IN_RING3 */
841
842/**
843 * Module type.
844 */
845typedef enum PDMMODTYPE
846{
847 /** Raw-mode (RC) context module. */
848 PDMMOD_TYPE_RC,
849 /** Ring-0 (host) context module. */
850 PDMMOD_TYPE_R0,
851 /** Ring-3 (host) context module. */
852 PDMMOD_TYPE_R3
853} PDMMODTYPE;
854
855
856/** The module name length including the terminator. */
857#define PDMMOD_NAME_LEN 32
858
859/**
860 * Loaded module instance.
861 */
862typedef struct PDMMOD
863{
864 /** Module name. This is used for referring to
865 * the module internally, sort of like a handle. */
866 char szName[PDMMOD_NAME_LEN];
867 /** Module type. */
868 PDMMODTYPE eType;
869 /** Loader module handle. Not used for R0 modules. */
870 RTLDRMOD hLdrMod;
871 /** Loaded address.
872 * This is the 'handle' for R0 modules. */
873 RTUINTPTR ImageBase;
874 /** Old loaded address.
875 * This is used during relocation of GC modules. Not used for R0 modules. */
876 RTUINTPTR OldImageBase;
877 /** Where the R3 HC bits are stored.
878 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
879 void *pvBits;
880
881 /** Pointer to next module. */
882 struct PDMMOD *pNext;
883 /** Module filename. */
884 char szFilename[1];
885} PDMMOD;
886/** Pointer to loaded module instance. */
887typedef PDMMOD *PPDMMOD;
888
889
890
891/** Extra space in the free array. */
892#define PDMQUEUE_FREE_SLACK 16
893
894/**
895 * Queue type.
896 */
897typedef enum PDMQUEUETYPE
898{
899 /** Device consumer. */
900 PDMQUEUETYPE_DEV = 1,
901 /** Driver consumer. */
902 PDMQUEUETYPE_DRV,
903 /** Internal consumer. */
904 PDMQUEUETYPE_INTERNAL,
905 /** External consumer. */
906 PDMQUEUETYPE_EXTERNAL
907} PDMQUEUETYPE;
908
909/** Pointer to a PDM Queue. */
910typedef struct PDMQUEUE *PPDMQUEUE;
911
912/**
913 * PDM Queue.
914 */
915typedef struct PDMQUEUE
916{
917 /** Pointer to the next queue in the list. */
918 R3PTRTYPE(PPDMQUEUE) pNext;
919 /** Type specific data. */
920 union
921 {
922 /** PDMQUEUETYPE_DEV */
923 struct
924 {
925 /** Pointer to consumer function. */
926 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
927 /** Pointer to the device instance owning the queue. */
928 R3PTRTYPE(PPDMDEVINS) pDevIns;
929 } Dev;
930 /** PDMQUEUETYPE_DRV */
931 struct
932 {
933 /** Pointer to consumer function. */
934 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
935 /** Pointer to the driver instance owning the queue. */
936 R3PTRTYPE(PPDMDRVINS) pDrvIns;
937 } Drv;
938 /** PDMQUEUETYPE_INTERNAL */
939 struct
940 {
941 /** Pointer to consumer function. */
942 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
943 } Int;
944 /** PDMQUEUETYPE_EXTERNAL */
945 struct
946 {
947 /** Pointer to consumer function. */
948 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
949 /** Pointer to user argument. */
950 R3PTRTYPE(void *) pvUser;
951 } Ext;
952 } u;
953 /** Queue type. */
954 PDMQUEUETYPE enmType;
955 /** The interval between checking the queue for events.
956 * The realtime timer below is used to do the waiting.
957 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
958 uint32_t cMilliesInterval;
959 /** Interval timer. Only used if cMilliesInterval is non-zero. */
960 PTMTIMERR3 pTimer;
961 /** Pointer to the VM - R3. */
962 PVMR3 pVMR3;
963 /** LIFO of pending items - R3. */
964 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR3;
965 /** Pointer to the VM - R0. */
966 PVMR0 pVMR0;
967 /** LIFO of pending items - R0. */
968 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR0;
969 /** Pointer to the GC VM and indicator for GC enabled queue.
970 * If this is NULL, the queue cannot be used in GC.
971 */
972 PVMRC pVMRC;
973 /** LIFO of pending items - GC. */
974 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingRC;
975
976 /** Item size (bytes). */
977 uint32_t cbItem;
978 /** Number of items in the queue. */
979 uint32_t cItems;
980 /** Index to the free head (where we insert). */
981 uint32_t volatile iFreeHead;
982 /** Index to the free tail (where we remove). */
983 uint32_t volatile iFreeTail;
984
985 /** Unique queue name. */
986 R3PTRTYPE(const char *) pszName;
987#if HC_ARCH_BITS == 32
988 RTR3PTR Alignment1;
989#endif
990 /** Stat: Times PDMQueueAlloc fails. */
991 STAMCOUNTER StatAllocFailures;
992 /** Stat: PDMQueueInsert calls. */
993 STAMCOUNTER StatInsert;
994 /** Stat: Queue flushes. */
995 STAMCOUNTER StatFlush;
996 /** Stat: Queue flushes with pending items left over. */
997 STAMCOUNTER StatFlushLeftovers;
998#ifdef VBOX_WITH_STATISTICS
999 /** State: Profiling the flushing. */
1000 STAMPROFILE StatFlushPrf;
1001 /** State: Pending items. */
1002 uint32_t volatile cStatPending;
1003 uint32_t volatile cAlignment;
1004#endif
1005
1006 /** Array of pointers to free items. Variable size. */
1007 struct PDMQUEUEFREEITEM
1008 {
1009 /** Pointer to the free item - HC Ptr. */
1010 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR3;
1011 /** Pointer to the free item - HC Ptr. */
1012 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR0;
1013 /** Pointer to the free item - GC Ptr. */
1014 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pItemRC;
1015#if HC_ARCH_BITS == 64
1016 RTRCPTR Alignment0;
1017#endif
1018 } aFreeItems[1];
1019} PDMQUEUE;
1020
1021/** @name PDM::fQueueFlushing
1022 * @{ */
1023/** Used to make sure only one EMT will flush the queues.
1024 * Set when an EMT is flushing queues, clear otherwise. */
1025#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1026/** Indicating there are queues with items pending.
1027 * This is make sure we don't miss inserts happening during flushing. The FF
1028 * cannot be used for this since it has to be cleared immediately to prevent
1029 * other EMTs from spinning. */
1030#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1031/** @} */
1032
1033
1034/** @name PDM task structures.
1035 * @{ */
1036
1037/**
1038 * A asynchronous user mode task.
1039 */
1040typedef struct PDMTASK
1041{
1042 /** Task owner type. */
1043 PDMTASKTYPE volatile enmType;
1044 /** Queue flags. */
1045 uint32_t volatile fFlags;
1046 /** User argument for the callback. */
1047 R3PTRTYPE(void *) volatile pvUser;
1048 /** The callback (will be cast according to enmType before callout). */
1049 R3PTRTYPE(PFNRT) volatile pfnCallback;
1050 /** The owner identifier. */
1051 R3PTRTYPE(void *) volatile pvOwner;
1052 /** Task name. */
1053 R3PTRTYPE(const char *) pszName;
1054 /** Number of times already triggered when PDMTaskTrigger was called. */
1055 uint32_t volatile cAlreadyTrigged;
1056 /** Number of runs. */
1057 uint32_t cRuns;
1058} PDMTASK;
1059/** Pointer to a PDM task. */
1060typedef PDMTASK *PPDMTASK;
1061
1062/**
1063 * A task set.
1064 *
1065 * This is served by one task executor thread.
1066 */
1067typedef struct PDMTASKSET
1068{
1069 /** Magic value (PDMTASKSET_MAGIC). */
1070 uint32_t u32Magic;
1071 /** Set if this task set works for ring-0 and raw-mode. */
1072 bool fRZEnabled;
1073 /** Number of allocated taks. */
1074 uint8_t volatile cAllocated;
1075 /** Base handle value for this set. */
1076 uint16_t uHandleBase;
1077 /** The task executor thread. */
1078 R3PTRTYPE(RTTHREAD) hThread;
1079 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1080 SUPSEMEVENT hEventR0;
1081 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1082 R3PTRTYPE(RTSEMEVENT) hEventR3;
1083 /** The VM pointer. */
1084 PVM pVM;
1085 /** Padding so fTriggered is in its own cacheline. */
1086 uint64_t au64Padding2[3];
1087
1088 /** Bitmask of triggered tasks. */
1089 uint64_t volatile fTriggered;
1090 /** Shutdown thread indicator. */
1091 bool volatile fShutdown;
1092 /** Padding. */
1093 bool volatile afPadding3[3];
1094 /** Task currently running, UINT32_MAX if idle. */
1095 uint32_t volatile idxRunning;
1096 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1097 uint64_t volatile au64Padding3[6];
1098
1099 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1100 PDMTASK aTasks[64];
1101} PDMTASKSET;
1102AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1103AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1104/** Magic value for PDMTASKSET::u32Magic. */
1105#define PDMTASKSET_MAGIC UINT32_C(0x19320314)
1106/** Pointer to a task set. */
1107typedef PDMTASKSET *PPDMTASKSET;
1108
1109/** @} */
1110
1111
1112/**
1113 * Queue device helper task operation.
1114 */
1115typedef enum PDMDEVHLPTASKOP
1116{
1117 /** The usual invalid 0 entry. */
1118 PDMDEVHLPTASKOP_INVALID = 0,
1119 /** ISASetIrq */
1120 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1121 /** PCISetIrq */
1122 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1123 /** PCISetIrq */
1124 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1125 /** The usual 32-bit hack. */
1126 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1127} PDMDEVHLPTASKOP;
1128
1129/**
1130 * Queued Device Helper Task.
1131 */
1132typedef struct PDMDEVHLPTASK
1133{
1134 /** The queue item core (don't touch). */
1135 PDMQUEUEITEMCORE Core;
1136 /** Pointer to the device instance (R3 Ptr). */
1137 PPDMDEVINSR3 pDevInsR3;
1138 /** This operation to perform. */
1139 PDMDEVHLPTASKOP enmOp;
1140#if HC_ARCH_BITS == 64
1141 uint32_t Alignment0;
1142#endif
1143 /** Parameters to the operation. */
1144 union PDMDEVHLPTASKPARAMS
1145 {
1146 /**
1147 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1148 */
1149 struct PDMDEVHLPTASKISASETIRQ
1150 {
1151 /** The IRQ */
1152 int iIrq;
1153 /** The new level. */
1154 int iLevel;
1155 /** The IRQ tag and source. */
1156 uint32_t uTagSrc;
1157 } IsaSetIRQ, IoApicSetIRQ;
1158
1159 /**
1160 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1161 */
1162 struct PDMDEVHLPTASKPCISETIRQ
1163 {
1164 /** Pointer to the PCI device (R3 Ptr). */
1165 R3PTRTYPE(PPDMPCIDEV) pPciDevR3;
1166 /** The IRQ */
1167 int iIrq;
1168 /** The new level. */
1169 int iLevel;
1170 /** The IRQ tag and source. */
1171 uint32_t uTagSrc;
1172 } PciSetIRQ;
1173
1174 /** Expanding the structure. */
1175 uint64_t au64[3];
1176 } u;
1177} PDMDEVHLPTASK;
1178/** Pointer to a queued Device Helper Task. */
1179typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1180/** Pointer to a const queued Device Helper Task. */
1181typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1182
1183
1184
1185/**
1186 * An USB hub registration record.
1187 */
1188typedef struct PDMUSBHUB
1189{
1190 /** The USB versions this hub support.
1191 * Note that 1.1 hubs can take on 2.0 devices. */
1192 uint32_t fVersions;
1193 /** The number of ports on the hub. */
1194 uint32_t cPorts;
1195 /** The number of available ports (0..cPorts). */
1196 uint32_t cAvailablePorts;
1197 /** The driver instance of the hub. */
1198 PPDMDRVINS pDrvIns;
1199 /** Copy of the to the registration structure. */
1200 PDMUSBHUBREG Reg;
1201
1202 /** Pointer to the next hub in the list. */
1203 struct PDMUSBHUB *pNext;
1204} PDMUSBHUB;
1205
1206/** Pointer to a const USB HUB registration record. */
1207typedef const PDMUSBHUB *PCPDMUSBHUB;
1208
1209/** Pointer to a PDM Async I/O template. */
1210typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1211
1212/** Pointer to the main PDM Async completion endpoint class. */
1213typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1214
1215/** Pointer to the global block cache structure. */
1216typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1217
1218/**
1219 * PDM VMCPU Instance data.
1220 * Changes to this must checked against the padding of the pdm union in VMCPU!
1221 */
1222typedef struct PDMCPU
1223{
1224 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1225 * in use. */
1226 uint32_t cQueuedCritSectLeaves;
1227 uint32_t uPadding0; /**< Alignment padding.*/
1228 /** Critical sections queued in RC/R0 because of contention preventing leave to
1229 * complete. (R3 Ptrs)
1230 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1231 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1232
1233 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1234 * currently in use. */
1235 uint32_t cQueuedCritSectRwExclLeaves;
1236 uint32_t uPadding1; /**< Alignment padding.*/
1237 /** Read/write critical sections queued in RC/R0 because of contention
1238 * preventing exclusive leave to complete. (R3 Ptrs)
1239 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1240 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1241
1242 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1243 * currently in use. */
1244 uint32_t cQueuedCritSectRwShrdLeaves;
1245 uint32_t uPadding2; /**< Alignment padding.*/
1246 /** Read/write critical sections queued in RC/R0 because of contention
1247 * preventing shared leave to complete. (R3 Ptrs)
1248 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1249 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1250} PDMCPU;
1251
1252
1253/**
1254 * PDM VM Instance data.
1255 * Changes to this must checked against the padding of the cfgm union in VM!
1256 */
1257typedef struct PDM
1258{
1259 /** The PDM lock.
1260 * This is used to protect everything that deals with interrupts, i.e.
1261 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1262 PDMCRITSECT CritSect;
1263 /** The NOP critical section.
1264 * This is a dummy critical section that will not do any thread
1265 * serialization but instead let all threads enter immediately and
1266 * concurrently. */
1267 PDMCRITSECT NopCritSect;
1268
1269 /** The ring-0 capable task sets (max 128). */
1270 PDMTASKSET aTaskSets[2];
1271 /** Pointer to task sets (max 512). */
1272 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1273
1274 /** PCI Buses. */
1275 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1276 /** IOMMU devices. */
1277 PDMIOMMU aIommus[PDM_IOMMUS_MAX];
1278 /** The register PIC device. */
1279 PDMPIC Pic;
1280 /** The registered APIC device. */
1281 PDMAPIC Apic;
1282 /** The registered I/O APIC device. */
1283 PDMIOAPIC IoApic;
1284 /** The registered HPET device. */
1285 PPDMDEVINSR3 pHpet;
1286
1287 /** List of registered devices. (FIFO) */
1288 R3PTRTYPE(PPDMDEV) pDevs;
1289 /** List of devices instances. (FIFO) */
1290 R3PTRTYPE(PPDMDEVINS) pDevInstances;
1291 /** List of registered USB devices. (FIFO) */
1292 R3PTRTYPE(PPDMUSB) pUsbDevs;
1293 /** List of USB devices instances. (FIFO) */
1294 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1295 /** List of registered drivers. (FIFO) */
1296 R3PTRTYPE(PPDMDRV) pDrvs;
1297 /** The registered firmware device (can be NULL). */
1298 R3PTRTYPE(PPDMFW) pFirmware;
1299 /** The registered DMAC device. */
1300 R3PTRTYPE(PPDMDMAC) pDmac;
1301 /** The registered RTC device. */
1302 R3PTRTYPE(PPDMRTC) pRtc;
1303 /** The registered USB HUBs. (FIFO) */
1304 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1305
1306 /** @name Queues
1307 * @{ */
1308 /** Queue in which devhlp tasks are queued for R3 execution - R3 Ptr. */
1309 R3PTRTYPE(PPDMQUEUE) pDevHlpQueueR3;
1310 /** Queue in which devhlp tasks are queued for R3 execution - R0 Ptr. */
1311 R0PTRTYPE(PPDMQUEUE) pDevHlpQueueR0;
1312 /** Queue in which devhlp tasks are queued for R3 execution - RC Ptr. */
1313 RCPTRTYPE(PPDMQUEUE) pDevHlpQueueRC;
1314 /** Pointer to the queue which should be manually flushed - RC Ptr.
1315 * Only touched by EMT. */
1316 RCPTRTYPE(struct PDMQUEUE *) pQueueFlushRC;
1317 /** Pointer to the queue which should be manually flushed - R0 Ptr.
1318 * Only touched by EMT. */
1319 R0PTRTYPE(struct PDMQUEUE *) pQueueFlushR0;
1320 /** Bitmask controlling the queue flushing.
1321 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1322 uint32_t volatile fQueueFlushing;
1323 /** @} */
1324
1325 /** The current IRQ tag (tracing purposes). */
1326 uint32_t volatile uIrqTag;
1327
1328 /** Pending reset flags (PDMVMRESET_F_XXX). */
1329 uint32_t volatile fResetFlags;
1330
1331 /** Set by pdmR3LoadExec for use in assertions. */
1332 bool fStateLoaded;
1333 /** Alignment padding. */
1334 bool afPadding[3];
1335
1336 /** The tracing ID of the next device instance.
1337 *
1338 * @remarks We keep the device tracing ID seperate from the rest as these are
1339 * then more likely to end up with the same ID from one run to
1340 * another, making analysis somewhat easier. Drivers and USB devices
1341 * are more volatile and can be changed at runtime, thus these are much
1342 * less likely to remain stable, so just heap them all together. */
1343 uint32_t idTracingDev;
1344 /** The tracing ID of the next driver instance, USB device instance or other
1345 * PDM entity requiring an ID. */
1346 uint32_t idTracingOther;
1347
1348 /** @name VMM device heap
1349 * @{ */
1350 /** The heap size. */
1351 uint32_t cbVMMDevHeap;
1352 /** Free space. */
1353 uint32_t cbVMMDevHeapLeft;
1354 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1355 RTR3PTR pvVMMDevHeap;
1356 /** Ring-3 mapping/unmapping notification callback for the user. */
1357 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1358 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1359 RTGCPHYS GCPhysVMMDevHeap;
1360 /** @} */
1361
1362 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1363 STAMCOUNTER StatQueuedCritSectLeaves;
1364} PDM;
1365AssertCompileMemberAlignment(PDM, CritSect, 8);
1366AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1367AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1368AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1369/** Pointer to PDM VM instance data. */
1370typedef PDM *PPDM;
1371
1372
1373/**
1374 * PDM data kept in the ring-0 GVM.
1375 */
1376typedef struct PDMR0PERVM
1377{
1378 /** PCI Buses, ring-0 data. */
1379 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1380 /** IOMMUs, ring-0 data. */
1381 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1382 /** Number of valid ring-0 device instances (apDevInstances). */
1383 uint32_t cDevInstances;
1384 uint32_t u32Padding;
1385 /** Pointer to ring-0 device instances. */
1386 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[190];
1387} PDMR0PERVM;
1388
1389
1390/**
1391 * PDM data kept in the UVM.
1392 */
1393typedef struct PDMUSERPERVM
1394{
1395 /** @todo move more stuff over here. */
1396
1397 /** Linked list of timer driven PDM queues.
1398 * Currently serialized by PDM::CritSect. */
1399 R3PTRTYPE(struct PDMQUEUE *) pQueuesTimer;
1400 /** Linked list of force action driven PDM queues.
1401 * Currently serialized by PDM::CritSect. */
1402 R3PTRTYPE(struct PDMQUEUE *) pQueuesForced;
1403
1404 /** Lock protecting the lists below it. */
1405 RTCRITSECT ListCritSect;
1406 /** Pointer to list of loaded modules. */
1407 PPDMMOD pModules;
1408 /** List of initialized critical sections. (LIFO) */
1409 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1410 /** List of initialized read/write critical sections. (LIFO) */
1411 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1412 /** Head of the PDM Thread list. (singly linked) */
1413 R3PTRTYPE(PPDMTHREAD) pThreads;
1414 /** Tail of the PDM Thread list. (singly linked) */
1415 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1416
1417 /** @name PDM Async Completion
1418 * @{ */
1419 /** Pointer to the array of supported endpoint classes. */
1420 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1421 /** Head of the templates. Singly linked, protected by ListCritSect. */
1422 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1423 /** @} */
1424
1425 /** Global block cache data. */
1426 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1427#ifdef VBOX_WITH_NETSHAPER
1428 /** Pointer to network shaper instance. */
1429 R3PTRTYPE(PPDMNETSHAPER) pNetShaper;
1430#endif /* VBOX_WITH_NETSHAPER */
1431
1432} PDMUSERPERVM;
1433/** Pointer to the PDM data kept in the UVM. */
1434typedef PDMUSERPERVM *PPDMUSERPERVM;
1435
1436
1437
1438/*******************************************************************************
1439* Global Variables *
1440*******************************************************************************/
1441#ifdef IN_RING3
1442extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1443extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1444extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1445extern const PDMPICHLP g_pdmR3DevPicHlp;
1446extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1447extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1448extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1449extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1450extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1451extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1452extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1453extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1454#endif
1455
1456
1457/*******************************************************************************
1458* Defined Constants And Macros *
1459*******************************************************************************/
1460/** @def PDMDEV_ASSERT_DEVINS
1461 * Asserts the validity of the device instance.
1462 */
1463#ifdef VBOX_STRICT
1464# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1465 do { \
1466 AssertPtr(pDevIns); \
1467 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1468 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1469 } while (0)
1470#else
1471# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1472#endif
1473
1474/** @def PDMDRV_ASSERT_DRVINS
1475 * Asserts the validity of the driver instance.
1476 */
1477#ifdef VBOX_STRICT
1478# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1479 do { \
1480 AssertPtr(pDrvIns); \
1481 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1482 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1483 } while (0)
1484#else
1485# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1486#endif
1487
1488
1489/*******************************************************************************
1490* Internal Functions *
1491*******************************************************************************/
1492#ifdef IN_RING3
1493bool pdmR3IsValidName(const char *pszName);
1494
1495int pdmR3CritSectBothInitStats(PVM pVM);
1496void pdmR3CritSectBothRelocate(PVM pVM);
1497int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1498int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1499int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1500 const char *pszNameFmt, va_list va);
1501int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1502 const char *pszNameFmt, ...);
1503int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1504 const char *pszNameFmt, ...);
1505int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1506 const char *pszNameFmt, va_list va);
1507int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1508 const char *pszNameFmt, ...);
1509int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1510 const char *pszNameFmt, ...);
1511
1512int pdmR3DevInit(PVM pVM);
1513int pdmR3DevInitComplete(PVM pVM);
1514PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1515int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1516DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1517
1518int pdmR3UsbLoadModules(PVM pVM);
1519int pdmR3UsbInstantiateDevices(PVM pVM);
1520PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1521int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1522int pdmR3UsbVMInitComplete(PVM pVM);
1523
1524int pdmR3DrvInit(PVM pVM);
1525int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1526 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1527int pdmR3DrvDetach(PPDMDRVINS pDrvIns, uint32_t fFlags);
1528void pdmR3DrvDestroyChain(PPDMDRVINS pDrvIns, uint32_t fFlags);
1529PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1530
1531int pdmR3LdrInitU(PUVM pUVM);
1532void pdmR3LdrTermU(PUVM pUVM);
1533char *pdmR3FileR3(const char *pszFile, bool fShared);
1534int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1535
1536void pdmR3QueueRelocate(PVM pVM, RTGCINTPTR offDelta);
1537
1538int pdmR3TaskInit(PVM pVM);
1539void pdmR3TaskTerm(PVM pVM);
1540
1541int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1542 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1543int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1544 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1545int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1546 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1547int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1548int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1549int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1550void pdmR3ThreadDestroyAll(PVM pVM);
1551int pdmR3ThreadResumeAll(PVM pVM);
1552int pdmR3ThreadSuspendAll(PVM pVM);
1553
1554#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1555int pdmR3AsyncCompletionInit(PVM pVM);
1556int pdmR3AsyncCompletionTerm(PVM pVM);
1557void pdmR3AsyncCompletionResume(PVM pVM);
1558int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1559int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1560 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1561int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1562int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1563int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1564int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1565#endif
1566
1567#ifdef VBOX_WITH_NETSHAPER
1568int pdmR3NetShaperInit(PVM pVM);
1569int pdmR3NetShaperTerm(PVM pVM);
1570#endif
1571
1572int pdmR3BlkCacheInit(PVM pVM);
1573void pdmR3BlkCacheTerm(PVM pVM);
1574int pdmR3BlkCacheResume(PVM pVM);
1575
1576#endif /* IN_RING3 */
1577
1578void pdmLock(PVMCC pVM);
1579int pdmLockEx(PVMCC pVM, int rc);
1580void pdmUnlock(PVMCC pVM);
1581
1582#if defined(IN_RING3) || defined(IN_RING0)
1583void pdmCritSectRwLeaveSharedQueued(PPDMCRITSECTRW pThis);
1584void pdmCritSectRwLeaveExclQueued(PPDMCRITSECTRW pThis);
1585#endif
1586
1587/** @} */
1588
1589RT_C_DECLS_END
1590
1591#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1592
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