VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMOpHlp.h@ 96860

Last change on this file since 96860 was 96438, checked in by vboxsync, 22 months ago

VMM/IEM: Implement [v]phminposuw instructions, bugref:9898
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1/* $Id: IEMOpHlp.h 96438 2022-08-23 13:16:15Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - Opcode Helpers.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMOpHlp_h
29#define VMM_INCLUDED_SRC_include_IEMOpHlp_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34/** @name Common opcode decoders.
35 * @{
36 */
37void iemOpStubMsg2(PVMCPUCC pVCpu) RT_NOEXCEPT;
38
39/**
40 * Complains about a stub.
41 *
42 * Providing two versions of this macro, one for daily use and one for use when
43 * working on IEM.
44 */
45#if 0
46# define IEMOP_BITCH_ABOUT_STUB() \
47 do { \
48 RTAssertMsg1(NULL, __LINE__, __FILE__, __FUNCTION__); \
49 iemOpStubMsg2(pVCpu); \
50 RTAssertPanic(); \
51 } while (0)
52#else
53# define IEMOP_BITCH_ABOUT_STUB() Log(("Stub: %s (line %d)\n", __FUNCTION__, __LINE__));
54#endif
55
56/** Stubs an opcode. */
57#define FNIEMOP_STUB(a_Name) \
58 FNIEMOP_DEF(a_Name) \
59 { \
60 RT_NOREF_PV(pVCpu); \
61 IEMOP_BITCH_ABOUT_STUB(); \
62 return VERR_IEM_INSTR_NOT_IMPLEMENTED; \
63 } \
64 typedef int ignore_semicolon
65
66/** Stubs an opcode. */
67#define FNIEMOP_STUB_1(a_Name, a_Type0, a_Name0) \
68 FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
69 { \
70 RT_NOREF_PV(pVCpu); \
71 RT_NOREF_PV(a_Name0); \
72 IEMOP_BITCH_ABOUT_STUB(); \
73 return VERR_IEM_INSTR_NOT_IMPLEMENTED; \
74 } \
75 typedef int ignore_semicolon
76
77/** Stubs an opcode which currently should raise \#UD. */
78#define FNIEMOP_UD_STUB(a_Name) \
79 FNIEMOP_DEF(a_Name) \
80 { \
81 Log(("Unsupported instruction %Rfn\n", __FUNCTION__)); \
82 return IEMOP_RAISE_INVALID_OPCODE(); \
83 } \
84 typedef int ignore_semicolon
85
86/** Stubs an opcode which currently should raise \#UD. */
87#define FNIEMOP_UD_STUB_1(a_Name, a_Type0, a_Name0) \
88 FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
89 { \
90 RT_NOREF_PV(pVCpu); \
91 RT_NOREF_PV(a_Name0); \
92 Log(("Unsupported instruction %Rfn\n", __FUNCTION__)); \
93 return IEMOP_RAISE_INVALID_OPCODE(); \
94 } \
95 typedef int ignore_semicolon
96
97/** @} */
98
99
100/** @name Opcode Debug Helpers.
101 * @{
102 */
103#ifdef VBOX_WITH_STATISTICS
104# ifdef IN_RING3
105# define IEMOP_INC_STATS(a_Stats) do { pVCpu->iem.s.StatsR3.a_Stats += 1; } while (0)
106# else
107# define IEMOP_INC_STATS(a_Stats) do { pVCpu->iem.s.StatsRZ.a_Stats += 1; } while (0)
108# endif
109#else
110# define IEMOP_INC_STATS(a_Stats) do { } while (0)
111#endif
112
113#ifdef DEBUG
114# define IEMOP_MNEMONIC(a_Stats, a_szMnemonic) \
115 do { \
116 IEMOP_INC_STATS(a_Stats); \
117 Log4(("decode - %04x:%RGv %s%s [#%u]\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, \
118 pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK ? "lock " : "", a_szMnemonic, pVCpu->iem.s.cInstructions)); \
119 } while (0)
120
121# define IEMOP_MNEMONIC0EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) \
122 do { \
123 IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
124 (void)RT_CONCAT(IEMOPFORM_, a_Form); \
125 (void)RT_CONCAT(OP_,a_Upper); \
126 (void)(a_fDisHints); \
127 (void)(a_fIemHints); \
128 } while (0)
129
130# define IEMOP_MNEMONIC1EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) \
131 do { \
132 IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
133 (void)RT_CONCAT(IEMOPFORM_, a_Form); \
134 (void)RT_CONCAT(OP_,a_Upper); \
135 (void)RT_CONCAT(OP_PARM_,a_Op1); \
136 (void)(a_fDisHints); \
137 (void)(a_fIemHints); \
138 } while (0)
139
140# define IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \
141 do { \
142 IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
143 (void)RT_CONCAT(IEMOPFORM_, a_Form); \
144 (void)RT_CONCAT(OP_,a_Upper); \
145 (void)RT_CONCAT(OP_PARM_,a_Op1); \
146 (void)RT_CONCAT(OP_PARM_,a_Op2); \
147 (void)(a_fDisHints); \
148 (void)(a_fIemHints); \
149 } while (0)
150
151# define IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \
152 do { \
153 IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
154 (void)RT_CONCAT(IEMOPFORM_, a_Form); \
155 (void)RT_CONCAT(OP_,a_Upper); \
156 (void)RT_CONCAT(OP_PARM_,a_Op1); \
157 (void)RT_CONCAT(OP_PARM_,a_Op2); \
158 (void)RT_CONCAT(OP_PARM_,a_Op3); \
159 (void)(a_fDisHints); \
160 (void)(a_fIemHints); \
161 } while (0)
162
163# define IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \
164 do { \
165 IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
166 (void)RT_CONCAT(IEMOPFORM_, a_Form); \
167 (void)RT_CONCAT(OP_,a_Upper); \
168 (void)RT_CONCAT(OP_PARM_,a_Op1); \
169 (void)RT_CONCAT(OP_PARM_,a_Op2); \
170 (void)RT_CONCAT(OP_PARM_,a_Op3); \
171 (void)RT_CONCAT(OP_PARM_,a_Op4); \
172 (void)(a_fDisHints); \
173 (void)(a_fIemHints); \
174 } while (0)
175
176#else
177# define IEMOP_MNEMONIC(a_Stats, a_szMnemonic) IEMOP_INC_STATS(a_Stats)
178
179# define IEMOP_MNEMONIC0EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) \
180 IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
181# define IEMOP_MNEMONIC1EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) \
182 IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
183# define IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \
184 IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
185# define IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \
186 IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
187# define IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \
188 IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
189
190#endif
191
192#define IEMOP_MNEMONIC0(a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) \
193 IEMOP_MNEMONIC0EX(a_Lower, \
194 #a_Lower, \
195 a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints)
196#define IEMOP_MNEMONIC1(a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) \
197 IEMOP_MNEMONIC1EX(RT_CONCAT3(a_Lower,_,a_Op1), \
198 #a_Lower " " #a_Op1, \
199 a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints)
200#define IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \
201 IEMOP_MNEMONIC2EX(RT_CONCAT5(a_Lower,_,a_Op1,_,a_Op2), \
202 #a_Lower " " #a_Op1 "," #a_Op2, \
203 a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints)
204#define IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \
205 IEMOP_MNEMONIC3EX(RT_CONCAT7(a_Lower,_,a_Op1,_,a_Op2,_,a_Op3), \
206 #a_Lower " " #a_Op1 "," #a_Op2 "," #a_Op3, \
207 a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints)
208#define IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \
209 IEMOP_MNEMONIC4EX(RT_CONCAT9(a_Lower,_,a_Op1,_,a_Op2,_,a_Op3,_,a_Op4), \
210 #a_Lower " " #a_Op1 "," #a_Op2 "," #a_Op3 "," #a_Op4, \
211 a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints)
212
213/** @} */
214
215
216/** @name Opcode Helpers.
217 * @{
218 */
219
220#ifdef IN_RING3
221# define IEMOP_HLP_MIN_CPU(a_uMinCpu, a_fOnlyIf) \
222 do { \
223 if (IEM_GET_TARGET_CPU(pVCpu) >= (a_uMinCpu) || !(a_fOnlyIf)) { } \
224 else \
225 { \
226 (void)DBGFSTOP(pVCpu->CTX_SUFF(pVM)); \
227 return IEMOP_RAISE_INVALID_OPCODE(); \
228 } \
229 } while (0)
230#else
231# define IEMOP_HLP_MIN_CPU(a_uMinCpu, a_fOnlyIf) \
232 do { \
233 if (IEM_GET_TARGET_CPU(pVCpu) >= (a_uMinCpu) || !(a_fOnlyIf)) { } \
234 else return IEMOP_RAISE_INVALID_OPCODE(); \
235 } while (0)
236#endif
237
238/** The instruction requires a 186 or later. */
239#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_186
240# define IEMOP_HLP_MIN_186() do { } while (0)
241#else
242# define IEMOP_HLP_MIN_186() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_186, true)
243#endif
244
245/** The instruction requires a 286 or later. */
246#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_286
247# define IEMOP_HLP_MIN_286() do { } while (0)
248#else
249# define IEMOP_HLP_MIN_286() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_286, true)
250#endif
251
252/** The instruction requires a 386 or later. */
253#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_386
254# define IEMOP_HLP_MIN_386() do { } while (0)
255#else
256# define IEMOP_HLP_MIN_386() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_386, true)
257#endif
258
259/** The instruction requires a 386 or later if the given expression is true. */
260#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_386
261# define IEMOP_HLP_MIN_386_EX(a_fOnlyIf) do { } while (0)
262#else
263# define IEMOP_HLP_MIN_386_EX(a_fOnlyIf) IEMOP_HLP_MIN_CPU(IEMTARGETCPU_386, a_fOnlyIf)
264#endif
265
266/** The instruction requires a 486 or later. */
267#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_486
268# define IEMOP_HLP_MIN_486() do { } while (0)
269#else
270# define IEMOP_HLP_MIN_486() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_486, true)
271#endif
272
273/** The instruction requires a Pentium (586) or later. */
274#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_PENTIUM
275# define IEMOP_HLP_MIN_586() do { } while (0)
276#else
277# define IEMOP_HLP_MIN_586() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_PENTIUM, true)
278#endif
279
280/** The instruction requires a PentiumPro (686) or later. */
281#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_PPRO
282# define IEMOP_HLP_MIN_686() do { } while (0)
283#else
284# define IEMOP_HLP_MIN_686() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_PPRO, true)
285#endif
286
287
288/** The instruction raises an \#UD in real and V8086 mode. */
289#define IEMOP_HLP_NO_REAL_OR_V86_MODE() \
290 do \
291 { \
292 if (!IEM_IS_REAL_OR_V86_MODE(pVCpu)) { /* likely */ } \
293 else return IEMOP_RAISE_INVALID_OPCODE(); \
294 } while (0)
295
296#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
297/** This instruction raises an \#UD in real and V8086 mode or when not using a
298 * 64-bit code segment when in long mode (applicable to all VMX instructions
299 * except VMCALL).
300 */
301#define IEMOP_HLP_VMX_INSTR(a_szInstr, a_InsDiagPrefix) \
302 do \
303 { \
304 if ( !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
305 && ( !IEM_IS_LONG_MODE(pVCpu) \
306 || IEM_IS_64BIT_CODE(pVCpu))) \
307 { /* likely */ } \
308 else \
309 { \
310 if (IEM_IS_REAL_OR_V86_MODE(pVCpu)) \
311 { \
312 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_RealOrV86Mode; \
313 Log5((a_szInstr ": Real or v8086 mode -> #UD\n")); \
314 return IEMOP_RAISE_INVALID_OPCODE(); \
315 } \
316 if (IEM_IS_LONG_MODE(pVCpu) && !IEM_IS_64BIT_CODE(pVCpu)) \
317 { \
318 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_LongModeCS; \
319 Log5((a_szInstr ": Long mode without 64-bit code segment -> #UD\n")); \
320 return IEMOP_RAISE_INVALID_OPCODE(); \
321 } \
322 } \
323 } while (0)
324
325/** The instruction can only be executed in VMX operation (VMX root mode and
326 * non-root mode).
327 *
328 * @note Update IEM_VMX_IN_VMX_OPERATION if changes are made here.
329 */
330# define IEMOP_HLP_IN_VMX_OPERATION(a_szInstr, a_InsDiagPrefix) \
331 do \
332 { \
333 if (IEM_VMX_IS_ROOT_MODE(pVCpu)) { /* likely */ } \
334 else \
335 { \
336 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
337 Log5((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
338 return IEMOP_RAISE_INVALID_OPCODE(); \
339 } \
340 } while (0)
341#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
342
343/** The instruction is not available in 64-bit mode, throw \#UD if we're in
344 * 64-bit mode. */
345#define IEMOP_HLP_NO_64BIT() \
346 do \
347 { \
348 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT) \
349 return IEMOP_RAISE_INVALID_OPCODE(); \
350 } while (0)
351
352/** The instruction is only available in 64-bit mode, throw \#UD if we're not in
353 * 64-bit mode. */
354#define IEMOP_HLP_ONLY_64BIT() \
355 do \
356 { \
357 if (pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT) \
358 return IEMOP_RAISE_INVALID_OPCODE(); \
359 } while (0)
360
361/** The instruction defaults to 64-bit operand size if 64-bit mode. */
362#define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE() \
363 do \
364 { \
365 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT) \
366 iemRecalEffOpSize64Default(pVCpu); \
367 } while (0)
368
369/** The instruction has 64-bit operand size if 64-bit mode. */
370#define IEMOP_HLP_64BIT_OP_SIZE() \
371 do \
372 { \
373 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT) \
374 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT; \
375 } while (0)
376
377/** Only a REX prefix immediately preceeding the first opcode byte takes
378 * effect. This macro helps ensuring this as well as logging bad guest code. */
379#define IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE(a_szPrf) \
380 do \
381 { \
382 if (RT_UNLIKELY(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX)) \
383 { \
384 Log5((a_szPrf ": Overriding REX prefix at %RX16! fPrefixes=%#x\n", pVCpu->cpum.GstCtx.rip, pVCpu->iem.s.fPrefixes)); \
385 pVCpu->iem.s.fPrefixes &= ~IEM_OP_PRF_REX_MASK; \
386 pVCpu->iem.s.uRexB = 0; \
387 pVCpu->iem.s.uRexIndex = 0; \
388 pVCpu->iem.s.uRexReg = 0; \
389 iemRecalEffOpSize(pVCpu); \
390 } \
391 } while (0)
392
393/**
394 * Done decoding.
395 */
396#define IEMOP_HLP_DONE_DECODING() \
397 do \
398 { \
399 /*nothing for now, maybe later... */ \
400 } while (0)
401
402/**
403 * Done decoding, raise \#UD exception if lock prefix present.
404 */
405#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() \
406 do \
407 { \
408 if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))) \
409 { /* likely */ } \
410 else \
411 return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \
412 } while (0)
413
414
415/**
416 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
417 * repnz or size prefixes are present, or if in real or v8086 mode.
418 */
419#define IEMOP_HLP_DONE_VEX_DECODING() \
420 do \
421 { \
422 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
423 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
424 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) )) \
425 { /* likely */ } \
426 else \
427 return IEMOP_RAISE_INVALID_OPCODE(); \
428 } while (0)
429
430/**
431 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
432 * repnz or size prefixes are present, if in real or v8086 mode, or if the
433 * a_fFeature is present in the guest CPU.
434 */
435#define IEMOP_HLP_DONE_VEX_DECODING_EX(a_fFeature) \
436 do \
437 { \
438 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
439 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
440 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
441 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
442 { /* likely */ } \
443 else \
444 return IEMOP_RAISE_INVALID_OPCODE(); \
445 } while (0)
446
447/**
448 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
449 * repnz or size prefixes are present, or if in real or v8086 mode.
450 */
451#define IEMOP_HLP_DONE_VEX_DECODING_L0() \
452 do \
453 { \
454 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
455 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
456 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
457 && pVCpu->iem.s.uVexLength == 0)) \
458 { /* likely */ } \
459 else \
460 return IEMOP_RAISE_INVALID_OPCODE(); \
461 } while (0)
462
463/**
464 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
465 * repnz or size prefixes are present, or if in real or v8086 mode.
466 */
467#define IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeature) \
468 do \
469 { \
470 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
471 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
472 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
473 && pVCpu->iem.s.uVexLength == 0 \
474 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
475 { /* likely */ } \
476 else \
477 return IEMOP_RAISE_INVALID_OPCODE(); \
478 } while (0)
479
480
481/**
482 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
483 * repnz or size prefixes are present, or if the VEX.VVVV field doesn't indicate
484 * register 0, or if in real or v8086 mode.
485 */
486#define IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV() \
487 do \
488 { \
489 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
490 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
491 && !pVCpu->iem.s.uVex3rdReg \
492 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) )) \
493 { /* likely */ } \
494 else \
495 return IEMOP_RAISE_INVALID_OPCODE(); \
496 } while (0)
497
498/**
499 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
500 * repnz or size prefixes are present, or if the VEX.VVVV field doesn't indicate
501 * register 0, if in real or v8086 mode, or if the a_fFeature is present in the
502 * guest CPU.
503 */
504#define IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(a_fFeature) \
505 do \
506 { \
507 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
508 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
509 && !pVCpu->iem.s.uVex3rdReg \
510 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
511 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature )) \
512 { /* likely */ } \
513 else \
514 return IEMOP_RAISE_INVALID_OPCODE(); \
515 } while (0)
516
517/**
518 * Done decoding VEX, no V, L=0.
519 * Raises \#UD exception if rex, rep, opsize or lock prefixes are present, if
520 * we're in real or v8086 mode, if VEX.V!=0xf, or if VEX.L!=0.
521 */
522#define IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV() \
523 do \
524 { \
525 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
526 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REX)) \
527 && pVCpu->iem.s.uVexLength == 0 \
528 && pVCpu->iem.s.uVex3rdReg == 0 \
529 && !IEM_IS_REAL_OR_V86_MODE(pVCpu))) \
530 { /* likely */ } \
531 else \
532 return IEMOP_RAISE_INVALID_OPCODE(); \
533 } while (0)
534
535#define IEMOP_HLP_DECODED_NL_1(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_fDisOpType) \
536 do \
537 { \
538 if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))) \
539 { /* likely */ } \
540 else \
541 { \
542 NOREF(a_uDisOpNo); NOREF(a_fIemOpFlags); NOREF(a_uDisParam0); NOREF(a_fDisOpType); \
543 return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \
544 } \
545 } while (0)
546#define IEMOP_HLP_DECODED_NL_2(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_uDisParam1, a_fDisOpType) \
547 do \
548 { \
549 if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))) \
550 { /* likely */ } \
551 else \
552 { \
553 NOREF(a_uDisOpNo); NOREF(a_fIemOpFlags); NOREF(a_uDisParam0); NOREF(a_uDisParam1); NOREF(a_fDisOpType); \
554 return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \
555 } \
556 } while (0)
557
558/**
559 * Done decoding, raise \#UD exception if any lock, repz or repnz prefixes
560 * are present.
561 */
562#define IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES() \
563 do \
564 { \
565 if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ)))) \
566 { /* likely */ } \
567 else \
568 return IEMOP_RAISE_INVALID_OPCODE(); \
569 } while (0)
570
571/**
572 * Done decoding, raise \#UD exception if any operand-size override, repz or repnz
573 * prefixes are present.
574 */
575#define IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES() \
576 do \
577 { \
578 if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ)))) \
579 { /* likely */ } \
580 else \
581 return IEMOP_RAISE_INVALID_OPCODE(); \
582 } while (0)
583
584VBOXSTRICTRC iemOpHlpCalcRmEffAddr(PVMCPUCC pVCpu, uint8_t bRm, uint8_t cbImm, PRTGCPTR pGCPtrEff) RT_NOEXCEPT;
585VBOXSTRICTRC iemOpHlpCalcRmEffAddrEx(PVMCPUCC pVCpu, uint8_t bRm, uint8_t cbImm, PRTGCPTR pGCPtrEff, int8_t offRsp) RT_NOEXCEPT;
586#ifdef IEM_WITH_SETJMP
587RTGCPTR iemOpHlpCalcRmEffAddrJmp(PVMCPUCC pVCpu, uint8_t bRm, uint8_t cbImm) RT_NOEXCEPT;
588#endif
589
590/** @} */
591
592#endif /* !VMM_INCLUDED_SRC_include_IEMOpHlp_h */
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