VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMOpHlp.h@ 100594

Last change on this file since 100594 was 100579, checked in by vboxsync, 17 months ago

VMM/IEM: Implement vinserti128/vinsertf128 instruction emulation, bugref:9898

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1/* $Id: IEMOpHlp.h 100579 2023-07-14 14:04:07Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - Opcode Helpers.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMOpHlp_h
29#define VMM_INCLUDED_SRC_include_IEMOpHlp_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34/** @name Common opcode decoders.
35 * @{
36 */
37void iemOpStubMsg2(PVMCPUCC pVCpu) RT_NOEXCEPT;
38
39/**
40 * Complains about a stub.
41 *
42 * Providing two versions of this macro, one for daily use and one for use when
43 * working on IEM.
44 */
45#if 0
46# define IEMOP_BITCH_ABOUT_STUB() \
47 do { \
48 RTAssertMsg1(NULL, __LINE__, __FILE__, __FUNCTION__); \
49 iemOpStubMsg2(pVCpu); \
50 RTAssertPanic(); \
51 } while (0)
52#else
53# define IEMOP_BITCH_ABOUT_STUB() Log(("Stub: %s (line %d)\n", __FUNCTION__, __LINE__));
54#endif
55
56/** Stubs an opcode. */
57#define FNIEMOP_STUB(a_Name) \
58 FNIEMOP_DEF(a_Name) \
59 { \
60 RT_NOREF_PV(pVCpu); \
61 IEMOP_BITCH_ABOUT_STUB(); \
62 return VERR_IEM_INSTR_NOT_IMPLEMENTED; \
63 } \
64 typedef int ignore_semicolon
65
66/** Stubs an opcode. */
67#define FNIEMOP_STUB_1(a_Name, a_Type0, a_Name0) \
68 FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
69 { \
70 RT_NOREF_PV(pVCpu); \
71 RT_NOREF_PV(a_Name0); \
72 IEMOP_BITCH_ABOUT_STUB(); \
73 return VERR_IEM_INSTR_NOT_IMPLEMENTED; \
74 } \
75 typedef int ignore_semicolon
76
77/** Stubs an opcode which currently should raise \#UD. */
78#define FNIEMOP_UD_STUB(a_Name) \
79 FNIEMOP_DEF(a_Name) \
80 { \
81 Log(("Unsupported instruction %Rfn\n", __FUNCTION__)); \
82 IEMOP_RAISE_INVALID_OPCODE_RET(); \
83 } \
84 typedef int ignore_semicolon
85
86/** Stubs an opcode which currently should raise \#UD. */
87#define FNIEMOP_UD_STUB_1(a_Name, a_Type0, a_Name0) \
88 FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
89 { \
90 RT_NOREF_PV(pVCpu); \
91 RT_NOREF_PV(a_Name0); \
92 Log(("Unsupported instruction %Rfn\n", __FUNCTION__)); \
93 IEMOP_RAISE_INVALID_OPCODE_RET(); \
94 } \
95 typedef int ignore_semicolon
96
97/** @} */
98
99
100/** @name Opcode Debug Helpers.
101 * @{
102 */
103#ifdef VBOX_WITH_STATISTICS
104# ifdef IN_RING3
105# define IEMOP_INC_STATS(a_Stats) do { pVCpu->iem.s.StatsR3.a_Stats += 1; } while (0)
106# else
107# define IEMOP_INC_STATS(a_Stats) do { pVCpu->iem.s.StatsRZ.a_Stats += 1; } while (0)
108# endif
109#else
110# define IEMOP_INC_STATS(a_Stats) do { } while (0)
111#endif
112
113#ifdef DEBUG
114# define IEMOP_MNEMONIC(a_Stats, a_szMnemonic) \
115 do { \
116 IEMOP_INC_STATS(a_Stats); \
117 Log4(("decode - %04x:%RGv %s%s [#%u]\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, \
118 pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK ? "lock " : "", a_szMnemonic, pVCpu->iem.s.cInstructions)); \
119 } while (0)
120
121# define IEMOP_MNEMONIC0EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) \
122 do { \
123 IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
124 (void)RT_CONCAT(IEMOPFORM_, a_Form); \
125 (void)RT_CONCAT(OP_,a_Upper); \
126 (void)(a_fDisHints); \
127 (void)(a_fIemHints); \
128 } while (0)
129
130# define IEMOP_MNEMONIC1EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) \
131 do { \
132 IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
133 (void)RT_CONCAT(IEMOPFORM_, a_Form); \
134 (void)RT_CONCAT(OP_,a_Upper); \
135 (void)RT_CONCAT(OP_PARM_,a_Op1); \
136 (void)(a_fDisHints); \
137 (void)(a_fIemHints); \
138 } while (0)
139
140# define IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \
141 do { \
142 IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
143 (void)RT_CONCAT(IEMOPFORM_, a_Form); \
144 (void)RT_CONCAT(OP_,a_Upper); \
145 (void)RT_CONCAT(OP_PARM_,a_Op1); \
146 (void)RT_CONCAT(OP_PARM_,a_Op2); \
147 (void)(a_fDisHints); \
148 (void)(a_fIemHints); \
149 } while (0)
150
151# define IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \
152 do { \
153 IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
154 (void)RT_CONCAT(IEMOPFORM_, a_Form); \
155 (void)RT_CONCAT(OP_,a_Upper); \
156 (void)RT_CONCAT(OP_PARM_,a_Op1); \
157 (void)RT_CONCAT(OP_PARM_,a_Op2); \
158 (void)RT_CONCAT(OP_PARM_,a_Op3); \
159 (void)(a_fDisHints); \
160 (void)(a_fIemHints); \
161 } while (0)
162
163# define IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \
164 do { \
165 IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
166 (void)RT_CONCAT(IEMOPFORM_, a_Form); \
167 (void)RT_CONCAT(OP_,a_Upper); \
168 (void)RT_CONCAT(OP_PARM_,a_Op1); \
169 (void)RT_CONCAT(OP_PARM_,a_Op2); \
170 (void)RT_CONCAT(OP_PARM_,a_Op3); \
171 (void)RT_CONCAT(OP_PARM_,a_Op4); \
172 (void)(a_fDisHints); \
173 (void)(a_fIemHints); \
174 } while (0)
175
176#else
177# define IEMOP_MNEMONIC(a_Stats, a_szMnemonic) IEMOP_INC_STATS(a_Stats)
178
179# define IEMOP_MNEMONIC0EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) \
180 IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
181# define IEMOP_MNEMONIC1EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) \
182 IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
183# define IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \
184 IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
185# define IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \
186 IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
187# define IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \
188 IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
189
190#endif
191
192#define IEMOP_MNEMONIC0(a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) \
193 IEMOP_MNEMONIC0EX(a_Lower, \
194 #a_Lower, \
195 a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints)
196#define IEMOP_MNEMONIC1(a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) \
197 IEMOP_MNEMONIC1EX(RT_CONCAT3(a_Lower,_,a_Op1), \
198 #a_Lower " " #a_Op1, \
199 a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints)
200#define IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \
201 IEMOP_MNEMONIC2EX(RT_CONCAT5(a_Lower,_,a_Op1,_,a_Op2), \
202 #a_Lower " " #a_Op1 "," #a_Op2, \
203 a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints)
204#define IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \
205 IEMOP_MNEMONIC3EX(RT_CONCAT7(a_Lower,_,a_Op1,_,a_Op2,_,a_Op3), \
206 #a_Lower " " #a_Op1 "," #a_Op2 "," #a_Op3, \
207 a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints)
208#define IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \
209 IEMOP_MNEMONIC4EX(RT_CONCAT9(a_Lower,_,a_Op1,_,a_Op2,_,a_Op3,_,a_Op4), \
210 #a_Lower " " #a_Op1 "," #a_Op2 "," #a_Op3 "," #a_Op4, \
211 a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints)
212
213/** @} */
214
215
216/** @name Opcode Helpers.
217 * @{
218 */
219
220#ifdef IN_RING3
221# define IEMOP_HLP_MIN_CPU(a_uMinCpu, a_fOnlyIf) \
222 do { \
223 if (IEM_GET_TARGET_CPU(pVCpu) >= (a_uMinCpu) || !(a_fOnlyIf)) { } \
224 else \
225 { \
226 (void)DBGFSTOP(pVCpu->CTX_SUFF(pVM)); \
227 IEMOP_RAISE_INVALID_OPCODE_RET(); \
228 } \
229 } while (0)
230#else
231# define IEMOP_HLP_MIN_CPU(a_uMinCpu, a_fOnlyIf) \
232 do { \
233 if (IEM_GET_TARGET_CPU(pVCpu) >= (a_uMinCpu) || !(a_fOnlyIf)) { } \
234 else IEMOP_RAISE_INVALID_OPCODE_RET(); \
235 } while (0)
236#endif
237
238/** The instruction requires a 186 or later. */
239#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_186
240# define IEMOP_HLP_MIN_186() do { } while (0)
241#else
242# define IEMOP_HLP_MIN_186() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_186, true)
243#endif
244
245/** The instruction requires a 286 or later. */
246#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_286
247# define IEMOP_HLP_MIN_286() do { } while (0)
248#else
249# define IEMOP_HLP_MIN_286() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_286, true)
250#endif
251
252/** The instruction requires a 386 or later. */
253#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_386
254# define IEMOP_HLP_MIN_386() do { } while (0)
255#else
256# define IEMOP_HLP_MIN_386() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_386, true)
257#endif
258
259/** The instruction requires a 386 or later if the given expression is true. */
260#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_386
261# define IEMOP_HLP_MIN_386_EX(a_fOnlyIf) do { } while (0)
262#else
263# define IEMOP_HLP_MIN_386_EX(a_fOnlyIf) IEMOP_HLP_MIN_CPU(IEMTARGETCPU_386, a_fOnlyIf)
264#endif
265
266/** The instruction requires a 486 or later. */
267#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_486
268# define IEMOP_HLP_MIN_486() do { } while (0)
269#else
270# define IEMOP_HLP_MIN_486() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_486, true)
271#endif
272
273/** The instruction requires a Pentium (586) or later. */
274#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_PENTIUM
275# define IEMOP_HLP_MIN_586() do { } while (0)
276#else
277# define IEMOP_HLP_MIN_586() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_PENTIUM, true)
278#endif
279
280/** The instruction requires a PentiumPro (686) or later. */
281#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_PPRO
282# define IEMOP_HLP_MIN_686() do { } while (0)
283#else
284# define IEMOP_HLP_MIN_686() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_PPRO, true)
285#endif
286
287
288/** The instruction raises an \#UD in real and V8086 mode. */
289#define IEMOP_HLP_NO_REAL_OR_V86_MODE() \
290 do \
291 { \
292 if (!IEM_IS_REAL_OR_V86_MODE(pVCpu)) { /* likely */ } \
293 else IEMOP_RAISE_INVALID_OPCODE_RET(); \
294 } while (0)
295
296#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
297/** This instruction raises an \#UD in real and V8086 mode or when not using a
298 * 64-bit code segment when in long mode (applicable to all VMX instructions
299 * except VMCALL).
300 */
301#define IEMOP_HLP_VMX_INSTR(a_szInstr, a_InsDiagPrefix) \
302 do \
303 { \
304 if ( !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
305 && ( !IEM_IS_LONG_MODE(pVCpu) \
306 || IEM_IS_64BIT_CODE(pVCpu))) \
307 { /* likely */ } \
308 else \
309 { \
310 if (IEM_IS_REAL_OR_V86_MODE(pVCpu)) \
311 { \
312 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_RealOrV86Mode; \
313 Log5((a_szInstr ": Real or v8086 mode -> #UD\n")); \
314 IEMOP_RAISE_INVALID_OPCODE_RET(); \
315 } \
316 if (IEM_IS_LONG_MODE(pVCpu) && !IEM_IS_64BIT_CODE(pVCpu)) \
317 { \
318 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_LongModeCS; \
319 Log5((a_szInstr ": Long mode without 64-bit code segment -> #UD\n")); \
320 IEMOP_RAISE_INVALID_OPCODE_RET(); \
321 } \
322 } \
323 } while (0)
324
325/** The instruction can only be executed in VMX operation (VMX root mode and
326 * non-root mode).
327 *
328 * @note Update IEM_VMX_IN_VMX_OPERATION if changes are made here.
329 */
330# define IEMOP_HLP_IN_VMX_OPERATION(a_szInstr, a_InsDiagPrefix) \
331 do \
332 { \
333 if (IEM_VMX_IS_ROOT_MODE(pVCpu)) { /* likely */ } \
334 else \
335 { \
336 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
337 Log5((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
338 IEMOP_RAISE_INVALID_OPCODE_RET(); \
339 } \
340 } while (0)
341#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
342
343/** The instruction is not available in 64-bit mode, throw \#UD if we're in
344 * 64-bit mode. */
345#define IEMOP_HLP_NO_64BIT() \
346 do \
347 { \
348 if (!IEM_IS_64BIT_CODE(pVCpu)) \
349 { /* likely */ } \
350 else \
351 IEMOP_RAISE_INVALID_OPCODE_RET(); \
352 } while (0)
353
354/** The instruction is only available in 64-bit mode, throw \#UD if we're not in
355 * 64-bit mode. */
356#define IEMOP_HLP_ONLY_64BIT() \
357 do \
358 { \
359 if (IEM_IS_64BIT_CODE(pVCpu)) \
360 { /* likely */ } \
361 else \
362 IEMOP_RAISE_INVALID_OPCODE_RET(); \
363 } while (0)
364
365/** The instruction defaults to 64-bit operand size if 64-bit mode. */
366#define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE() \
367 do \
368 { \
369 if (IEM_IS_64BIT_CODE(pVCpu)) \
370 iemRecalEffOpSize64Default(pVCpu); \
371 } while (0)
372
373/** The instruction defaults to 64-bit operand size if 64-bit mode and intel
374 * CPUs ignore the operand size prefix complete (e.g. relative jumps). */
375#define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX() \
376 do \
377 { \
378 if (IEM_IS_64BIT_CODE(pVCpu)) \
379 iemRecalEffOpSize64DefaultAndIntelIgnoresOpSizePrefix(pVCpu); \
380 } while (0)
381
382/** The instruction has 64-bit operand size if 64-bit mode. */
383#define IEMOP_HLP_64BIT_OP_SIZE() \
384 do \
385 { \
386 if (IEM_IS_64BIT_CODE(pVCpu)) \
387 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT; \
388 } while (0)
389
390/** Only a REX prefix immediately preceeding the first opcode byte takes
391 * effect. This macro helps ensuring this as well as logging bad guest code. */
392#define IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE(a_szPrf) \
393 do \
394 { \
395 if (RT_UNLIKELY(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX)) \
396 { \
397 Log5((a_szPrf ": Overriding REX prefix at %RX16! fPrefixes=%#x\n", pVCpu->cpum.GstCtx.rip, pVCpu->iem.s.fPrefixes)); \
398 pVCpu->iem.s.fPrefixes &= ~IEM_OP_PRF_REX_MASK; \
399 pVCpu->iem.s.uRexB = 0; \
400 pVCpu->iem.s.uRexIndex = 0; \
401 pVCpu->iem.s.uRexReg = 0; \
402 iemRecalEffOpSize(pVCpu); \
403 } \
404 } while (0)
405
406/**
407 * Done decoding.
408 */
409#define IEMOP_HLP_DONE_DECODING() \
410 do \
411 { \
412 /*nothing for now, maybe later... */ \
413 } while (0)
414
415/**
416 * Done decoding, raise \#UD exception if lock prefix present.
417 */
418#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() \
419 do \
420 { \
421 if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))) \
422 { /* likely */ } \
423 else \
424 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \
425 } while (0)
426
427/**
428 * Done decoding, raise \#UD exception if lock prefix present, or if the
429 * a_fFeature is present in the guest CPU.
430 */
431#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(a_fFeature) \
432 do \
433 { \
434 if (RT_LIKELY( !(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK) \
435 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
436 { /* likely */ } \
437 else \
438 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \
439 } while (0)
440
441/**
442 * Done decoding, raise \#UD exception if lock prefix present, or if the
443 * a_fFeature is present in the guest CPU.
444 */
445#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(a_fFeature1, a_fFeature2) \
446 do \
447 { \
448 if (RT_LIKELY( !(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK) \
449 && ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature1 \
450 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature2) )) \
451 { /* likely */ } \
452 else \
453 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \
454 } while (0)
455
456
457/**
458 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
459 * repnz or size prefixes are present, if in real or v8086 mode, or if the
460 * a_fFeature is not present in the guest CPU.
461 */
462#define IEMOP_HLP_DONE_VEX_DECODING_EX(a_fFeature) \
463 do \
464 { \
465 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
466 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
467 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
468 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
469 { /* likely */ } \
470 else \
471 IEMOP_RAISE_INVALID_OPCODE_RET(); \
472 } while (0)
473
474/**
475 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
476 * repnz or size prefixes are present, or if in real or v8086 mode, or if the
477 * a_fFeature is not present in the guest CPU.
478 */
479#define IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeature) \
480 do \
481 { \
482 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
483 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
484 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
485 && pVCpu->iem.s.uVexLength == 0 \
486 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
487 { /* likely */ } \
488 else \
489 IEMOP_RAISE_INVALID_OPCODE_RET(); \
490 } while (0)
491
492/**
493 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
494 * repnz or size prefixes are present, or if in real or v8086 mode, or if the
495 * a_fFeature is not present in the guest CPU.
496 */
497#define IEMOP_HLP_DONE_VEX_DECODING_L1_EX(a_fFeature) \
498 do \
499 { \
500 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
501 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
502 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
503 && pVCpu->iem.s.uVexLength == 1 \
504 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
505 { /* likely */ } \
506 else \
507 IEMOP_RAISE_INVALID_OPCODE_RET(); \
508 } while (0)
509
510/**
511 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
512 * repnz or size prefixes are present, or if the VEX.VVVV field doesn't indicate
513 * register 0, if in real or v8086 mode, or if the a_fFeature is not present in
514 * the guest CPU.
515 */
516#define IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(a_fFeature) \
517 do \
518 { \
519 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
520 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
521 && !pVCpu->iem.s.uVex3rdReg \
522 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
523 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature )) \
524 { /* likely */ } \
525 else \
526 IEMOP_RAISE_INVALID_OPCODE_RET(); \
527 } while (0)
528
529/**
530 * Done decoding VEX, no V, L=0.
531 * Raises \#UD exception if rex, rep, opsize or lock prefixes are present, if
532 * we're in real or v8086 mode, if VEX.V!=0xf, if VEX.L!=0, or if the a_fFeature
533 * is not present in the guest CPU.
534 */
535#define IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(a_fFeature) \
536 do \
537 { \
538 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
539 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REX)) \
540 && pVCpu->iem.s.uVexLength == 0 \
541 && pVCpu->iem.s.uVex3rdReg == 0 \
542 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
543 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature )) \
544 { /* likely */ } \
545 else \
546 IEMOP_RAISE_INVALID_OPCODE_RET(); \
547 } while (0)
548
549/**
550 * Done decoding VEX, no V, L=1.
551 * Raises \#UD exception if rex, rep, opsize or lock prefixes are present, if
552 * we're in real or v8086 mode, if VEX.V!=0xf, if VEX.L!=1, or if the a_fFeature
553 * is not present in the guest CPU.
554 */
555#define IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(a_fFeature) \
556 do \
557 { \
558 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
559 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REX)) \
560 && pVCpu->iem.s.uVexLength == 1 \
561 && pVCpu->iem.s.uVex3rdReg == 0 \
562 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
563 && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature )) \
564 { /* likely */ } \
565 else \
566 IEMOP_RAISE_INVALID_OPCODE_RET(); \
567 } while (0)
568
569#define IEMOP_HLP_DECODED_NL_1(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_fDisOpType) \
570 do \
571 { \
572 if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))) \
573 { /* likely */ } \
574 else \
575 { \
576 NOREF(a_uDisOpNo); NOREF(a_fIemOpFlags); NOREF(a_uDisParam0); NOREF(a_fDisOpType); \
577 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \
578 } \
579 } while (0)
580#define IEMOP_HLP_DECODED_NL_2(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_uDisParam1, a_fDisOpType) \
581 do \
582 { \
583 if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))) \
584 { /* likely */ } \
585 else \
586 { \
587 NOREF(a_uDisOpNo); NOREF(a_fIemOpFlags); NOREF(a_uDisParam0); NOREF(a_uDisParam1); NOREF(a_fDisOpType); \
588 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \
589 } \
590 } while (0)
591
592/**
593 * Done decoding, raise \#UD exception if any lock, repz or repnz prefixes
594 * are present.
595 */
596#define IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES() \
597 do \
598 { \
599 if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ)))) \
600 { /* likely */ } \
601 else \
602 IEMOP_RAISE_INVALID_OPCODE_RET(); \
603 } while (0)
604
605/**
606 * Done decoding, raise \#UD exception if any operand-size override, repz or repnz
607 * prefixes are present.
608 */
609#define IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES() \
610 do \
611 { \
612 if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ)))) \
613 { /* likely */ } \
614 else \
615 IEMOP_RAISE_INVALID_OPCODE_RET(); \
616 } while (0)
617
618/**
619 * Check for a CPUMFEATURES member to be true, raise \#UD if clear.
620 */
621#define IEMOP_HLP_RAISE_UD_IF_MISSING_GUEST_FEATURE(pVCpu, a_fFeature) \
622 do \
623 { \
624 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature) \
625 { /* likely */ } \
626 else \
627 IEMOP_RAISE_INVALID_OPCODE_RET(); \
628 } while (0)
629
630VBOXSTRICTRC iemOpHlpCalcRmEffAddr(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, PRTGCPTR pGCPtrEff) RT_NOEXCEPT;
631VBOXSTRICTRC iemOpHlpCalcRmEffAddrEx(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, PRTGCPTR pGCPtrEff, uint64_t *puInfo) RT_NOEXCEPT;
632#ifdef IEM_WITH_SETJMP
633RTGCPTR iemOpHlpCalcRmEffAddrJmp(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset) IEM_NOEXCEPT_MAY_LONGJMP;
634RTGCPTR iemOpHlpCalcRmEffAddrJmpEx(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, uint64_t *puInfo) IEM_NOEXCEPT_MAY_LONGJMP;
635#endif
636
637/** @} */
638
639#endif /* !VMM_INCLUDED_SRC_include_IEMOpHlp_h */
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