VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 99330

Last change on this file since 99330 was 99330, checked in by vboxsync, 2 years ago

VMM/IEM: Use IEMOP_HLP_DONE_DECODING_*EX*() rather than IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT and firends to do the CPUID check. bugref:10369
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1/* $Id: IEMMc.h 99330 2023-04-07 00:23:11Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))) \
79 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
80 } while (0)
81#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
82 do { \
83 if (!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS))) \
84 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
85 } while (0)
86#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
87 do { \
88 if (!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)) \
89 { } else return iemRaiseMathFault(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
92 do { \
93 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
94 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
95 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
96 return iemRaiseUndefinedOpcode(pVCpu); \
97 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
98 return iemRaiseDeviceNotAvailable(pVCpu); \
99 } while (0)
100#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
101 do { \
102 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
103 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
104 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
105 return iemRaiseUndefinedOpcode(pVCpu); \
106 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
107 return iemRaiseDeviceNotAvailable(pVCpu); \
108 } while (0)
109#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
110 do { \
111 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
112 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
113 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAesNi) \
114 return iemRaiseUndefinedOpcode(pVCpu); \
115 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
116 return iemRaiseDeviceNotAvailable(pVCpu); \
117 } while (0)
118#define IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT() \
119 do { \
120 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
121 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
122 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha) \
123 return iemRaiseUndefinedOpcode(pVCpu); \
124 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
125 return iemRaiseDeviceNotAvailable(pVCpu); \
126 } while (0)
127#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
128 do { \
129 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
130 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
131 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
132 return iemRaiseUndefinedOpcode(pVCpu); \
133 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
134 return iemRaiseDeviceNotAvailable(pVCpu); \
135 } while (0)
136#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
137 do { \
138 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
139 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
140 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
141 return iemRaiseUndefinedOpcode(pVCpu); \
142 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
143 return iemRaiseDeviceNotAvailable(pVCpu); \
144 } while (0)
145#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
146 do { \
147 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
148 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
149 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
150 return iemRaiseUndefinedOpcode(pVCpu); \
151 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
152 return iemRaiseDeviceNotAvailable(pVCpu); \
153 } while (0)
154#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
155 do { \
156 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
157 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
158 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
159 return iemRaiseUndefinedOpcode(pVCpu); \
160 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
161 return iemRaiseDeviceNotAvailable(pVCpu); \
162 } while (0)
163#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
164 do { \
165 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
166 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
167 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
168 return iemRaiseUndefinedOpcode(pVCpu); \
169 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
170 return iemRaiseDeviceNotAvailable(pVCpu); \
171 } while (0)
172#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
173 do { \
174 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
175 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
176 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
177 return iemRaiseUndefinedOpcode(pVCpu); \
178 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
179 return iemRaiseDeviceNotAvailable(pVCpu); \
180 } while (0)
181#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
182 do { \
183 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
184 return iemRaiseUndefinedOpcode(pVCpu); \
185 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
186 return iemRaiseDeviceNotAvailable(pVCpu); \
187 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
188 return iemRaiseMathFault(pVCpu); \
189 } while (0)
190#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
191 do { \
192 if (pVCpu->iem.s.uCpl != 0) \
193 return iemRaiseGeneralProtectionFault0(pVCpu); \
194 } while (0)
195#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
196 do { \
197 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
198 else return iemRaiseGeneralProtectionFault0(pVCpu); \
199 } while (0)
200#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
201 do { \
202 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
203 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
204 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
205 return iemRaiseUndefinedOpcode(pVCpu); \
206 } while (0)
207#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
208 do { \
209 if (!IEM_IS_CANONICAL(a_u64Addr)) \
210 return iemRaiseGeneralProtectionFault0(pVCpu); \
211 } while (0)
212#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
213 do { \
214 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
215 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
216 { \
217 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
218 return iemRaiseSimdFpException(pVCpu); \
219 else \
220 return iemRaiseUndefinedOpcode(pVCpu); \
221 } \
222 } while (0)
223#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
224 do { \
225 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
226 return iemRaiseSimdFpException(pVCpu); \
227 else \
228 return iemRaiseUndefinedOpcode(pVCpu); \
229 } while (0)
230#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
231 do { \
232 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
233 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
234 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
235 return iemRaiseUndefinedOpcode(pVCpu); \
236 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
237 return iemRaiseDeviceNotAvailable(pVCpu); \
238 } while (0)
239
240
241#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
242#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
243#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
244#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
245#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
246#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
247#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
248 uint32_t a_Name; \
249 uint32_t *a_pName = &a_Name
250#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
251 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
252
253#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
254#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
255#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
256 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
257#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
258 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
259
260#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
261#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
262#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
263#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
264#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
265#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
266#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
267#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
268#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
269#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
270#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
271#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
272#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
273#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
274#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
275#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
276#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
277#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
278 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
279 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
280 } while (0)
281#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
282 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
283 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
284 } while (0)
285#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
286 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
287 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
288 } while (0)
289/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
290#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
291 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
292 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
293 } while (0)
294#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
295 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
296 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
297 } while (0)
298/** @note Not for IOPL or IF testing or modification. */
299#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
300#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
301#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
302#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
303
304#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
305#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
306#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
307#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
308#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
309#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
310#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
311#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
312#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
313#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
314#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
315/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
316#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
317 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
318 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
319 } while (0)
320#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
321 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
322 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
323 } while (0)
324#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
325 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
326
327
328#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
329#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
330/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
331 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
332#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
333#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
334#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
335#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
336#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
337#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
338/** @note Not for IOPL or IF testing or modification.
339 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
340#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
341#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
342
343#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
344#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
345#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
346 do { \
347 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
348 *pu32Reg += (a_u32Value); \
349 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
350 } while (0)
351#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
352
353#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
354#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
355#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
356 do { \
357 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
358 *pu32Reg -= (a_u32Value); \
359 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
360 } while (0)
361#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
362#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
363
364#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
365#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
366#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
367#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
368#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
369#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
370#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
371
372#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
373#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
374#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
375#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
376
377#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
378#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
379#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
380
381#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
382#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
383#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
384
385#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
386#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
387#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
388
389#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
390
391#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
392#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
393#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
394
395#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
396
397#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
398
399#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
400#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
401#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
402 do { \
403 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
404 *pu32Reg &= (a_u32Value); \
405 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
406 } while (0)
407#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
408
409#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
410#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
411#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
412 do { \
413 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
414 *pu32Reg |= (a_u32Value); \
415 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
416 } while (0)
417#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
418
419#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
420#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
421#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
422
423/** @note Not for IOPL or IF modification. */
424#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
425/** @note Not for IOPL or IF modification. */
426#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
427/** @note Not for IOPL or IF modification. */
428#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
429
430#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
431
432/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
433#define IEM_MC_FPU_TO_MMX_MODE() do { \
434 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
435 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
436 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
437 } while (0)
438
439/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
440#define IEM_MC_FPU_FROM_MMX_MODE() do { \
441 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
442 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
443 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
444 } while (0)
445
446#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
447 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
448#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
449 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
450#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
451 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
452 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
453 } while (0)
454#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
455 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
456 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
457 } while (0)
458#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
459 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
460#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
461 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
462#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
463 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
464#define IEM_MC_MODIFIED_MREG(a_iMReg) \
465 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
466#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
467 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
468
469#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
470 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
471 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
472 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
473 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
474 } while (0)
475#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
476 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
477 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
478 } while (0)
479#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
480 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
481 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
482 } while (0)
483#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
484 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
485#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
486 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
487#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
488 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
489#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
490 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
491#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
492 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
493 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
494 } while (0)
495#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
496 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
497 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
498 } while (0)
499#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
500 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
501#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
502 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
503#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
504 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
505#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
506 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
507#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
508 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
509#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
510 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
511
512#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
513 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
514 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
515 } while (0)
516
517#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
518 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
519#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
520 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
521#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
522 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
523#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
524 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
525 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
526 } while (0)
527#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
528 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
529#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
530 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
531#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
532 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
533#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
534 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
535#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
536 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
537#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
538 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
539#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
540 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
541#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
542 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
543#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
544 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
545 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
546 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
547 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
548 } while (0)
549
550#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
551 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
552 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
553 } while (0)
554#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
555 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
556 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
557 } while (0)
558#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
559 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
560 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
561 } while (0)
562#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
563 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
564 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
565 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
566 } while (0)
567#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
568 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
569 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
570 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
571 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
572 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
573 } while (0)
574
575#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
576#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
577 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
578 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
579 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
580 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
581 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
582 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
583 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
584 } while (0)
585#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
586 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
587 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
588 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
589 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
590 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
591 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
592 } while (0)
593#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
594 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
595 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
596 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
597 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
598 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
599 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
600 } while (0)
601#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
602 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
603 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
604 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
605 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
606 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
607 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
608 } while (0)
609
610#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
611 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
612#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
613 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
614#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
615 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
616#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
617 do { uintptr_t const iYRegTmp = (a_iYReg); \
618 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
619 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
620 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
621 } while (0)
622
623#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
624 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
625 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
626 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
627 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
628 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
629 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
630 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
631 } while (0)
632#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
633 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
634 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
635 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
636 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
637 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
638 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
639 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
640 } while (0)
641#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
642 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
643 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
644 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
645 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
646 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
647 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
648 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
649 } while (0)
650
651#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
652 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
653 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
654 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
655 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
656 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
657 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
658 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
659 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
660 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
661 } while (0)
662#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
663 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
664 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
665 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
666 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
667 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
668 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
669 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
670 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
671 } while (0)
672#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
673 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
674 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
675 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
676 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
677 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
678 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
679 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
680 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
681 } while (0)
682#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
683 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
684 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
685 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
686 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
687 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
688 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
689 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
690 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
691 } while (0)
692#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
693 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
694 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
695 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
696 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
697 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
698 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
699 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
700 } while (0)
701#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
702 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
703 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
704 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
705 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
706 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
707 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
708 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
709 } while (0)
710
711#ifndef IEM_WITH_SETJMP
712# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
713 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
714# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
715 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
716# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
717 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
718#else
719# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
720 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
721# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
722 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
723# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
724 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
725#endif
726
727#ifndef IEM_WITH_SETJMP
728# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
729 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
730# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
731 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
732# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
733 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
734#else
735# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
736 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
737# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
738 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
739# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
740 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
741#endif
742
743#ifndef IEM_WITH_SETJMP
744# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
745 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
746# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
747 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
748# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
749 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
750#else
751# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
752 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
753# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
754 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
755# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
756 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
757#endif
758
759#ifdef SOME_UNUSED_FUNCTION
760# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
761 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
762#endif
763
764#ifndef IEM_WITH_SETJMP
765# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
766 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
767# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
768 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
769# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
770 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
771# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
772 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
773#else
774# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
775 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
776# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
777 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
778# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
779 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
780# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
781 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
782#endif
783
784#ifndef IEM_WITH_SETJMP
785# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
786 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
787# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
788 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
789# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
790 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
791# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
792 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
793#else
794# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
795 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
796# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
797 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
798# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
799 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
800# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
801 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
802#endif
803
804#ifndef IEM_WITH_SETJMP
805# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
806 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
807# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
808 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
809# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
810 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
811
812# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
813 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
814# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
815 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
816# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
817 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
818# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
819 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
820# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
821 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
822#else
823# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
824 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
825# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
826 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
827# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
828 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
829
830# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
831 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
832# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
833 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
834# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
835 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
836# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
837 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
838# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
839 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
840#endif
841
842#ifndef IEM_WITH_SETJMP
843# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
844 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
845# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
846 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
847# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
848 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
849
850# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
851 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
852# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
853 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
854# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
855 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
856#else
857# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
858 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
859# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
860 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
861# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
862 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
863
864# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
865 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
866# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
867 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
868# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
869 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
870#endif
871
872
873
874#ifndef IEM_WITH_SETJMP
875# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
876 do { \
877 uint8_t u8Tmp; \
878 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
879 (a_u16Dst) = u8Tmp; \
880 } while (0)
881# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
882 do { \
883 uint8_t u8Tmp; \
884 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
885 (a_u32Dst) = u8Tmp; \
886 } while (0)
887# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
888 do { \
889 uint8_t u8Tmp; \
890 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
891 (a_u64Dst) = u8Tmp; \
892 } while (0)
893# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
894 do { \
895 uint16_t u16Tmp; \
896 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
897 (a_u32Dst) = u16Tmp; \
898 } while (0)
899# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
900 do { \
901 uint16_t u16Tmp; \
902 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
903 (a_u64Dst) = u16Tmp; \
904 } while (0)
905# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
906 do { \
907 uint32_t u32Tmp; \
908 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
909 (a_u64Dst) = u32Tmp; \
910 } while (0)
911#else /* IEM_WITH_SETJMP */
912# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
913 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
914# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
915 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
916# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
917 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
918# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
919 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
920# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
921 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
922# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
923 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
924#endif /* IEM_WITH_SETJMP */
925
926#ifndef IEM_WITH_SETJMP
927# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
928 do { \
929 uint8_t u8Tmp; \
930 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
931 (a_u16Dst) = (int8_t)u8Tmp; \
932 } while (0)
933# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
934 do { \
935 uint8_t u8Tmp; \
936 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
937 (a_u32Dst) = (int8_t)u8Tmp; \
938 } while (0)
939# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
940 do { \
941 uint8_t u8Tmp; \
942 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
943 (a_u64Dst) = (int8_t)u8Tmp; \
944 } while (0)
945# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
946 do { \
947 uint16_t u16Tmp; \
948 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
949 (a_u32Dst) = (int16_t)u16Tmp; \
950 } while (0)
951# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
952 do { \
953 uint16_t u16Tmp; \
954 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
955 (a_u64Dst) = (int16_t)u16Tmp; \
956 } while (0)
957# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
958 do { \
959 uint32_t u32Tmp; \
960 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
961 (a_u64Dst) = (int32_t)u32Tmp; \
962 } while (0)
963#else /* IEM_WITH_SETJMP */
964# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
965 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
966# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
967 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
968# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
969 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
970# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
971 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
972# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
973 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
974# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
975 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
976#endif /* IEM_WITH_SETJMP */
977
978#ifndef IEM_WITH_SETJMP
979# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
980 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
981# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
982 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
983# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
984 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
985# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
986 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
987#else
988# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
989 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
990# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
991 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
992# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
993 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
994# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
995 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
996#endif
997
998#ifndef IEM_WITH_SETJMP
999# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1000 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
1001# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1002 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
1003# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1004 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
1005# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1006 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
1007#else
1008# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1009 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
1010# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1011 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
1012# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1013 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
1014# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1015 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1016#endif
1017
1018#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1019#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1020#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1021#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1022#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1023#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1024#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1025 do { \
1026 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1027 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1028 } while (0)
1029#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1030 do { \
1031 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1032 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1033 } while (0)
1034
1035#ifndef IEM_WITH_SETJMP
1036# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1037 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1038# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1039 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1040#else
1041# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1042 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1043# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1044 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1045#endif
1046
1047#ifndef IEM_WITH_SETJMP
1048# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1049 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1050# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1051 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1052#else
1053# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1054 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1055# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1056 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1057#endif
1058
1059
1060#define IEM_MC_PUSH_U16(a_u16Value) \
1061 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1062#define IEM_MC_PUSH_U32(a_u32Value) \
1063 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1064#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1065 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1066#define IEM_MC_PUSH_U64(a_u64Value) \
1067 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1068
1069#define IEM_MC_POP_U16(a_pu16Value) \
1070 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1071#define IEM_MC_POP_U32(a_pu32Value) \
1072 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1073#define IEM_MC_POP_U64(a_pu64Value) \
1074 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1075
1076/** Maps guest memory for direct or bounce buffered access.
1077 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1078 * @remarks May return.
1079 */
1080#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1081 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1082 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1083
1084/** Maps guest memory for direct or bounce buffered access.
1085 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1086 * @remarks May return.
1087 */
1088#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1089 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1090 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1091
1092/** Commits the memory and unmaps the guest memory.
1093 * @remarks May return.
1094 */
1095#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1096 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1097
1098/** Commits the memory and unmaps the guest memory unless the FPU status word
1099 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1100 * that would cause FLD not to store.
1101 *
1102 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1103 * store, while \#P will not.
1104 *
1105 * @remarks May in theory return - for now.
1106 */
1107#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1108 do { \
1109 if ( !(a_u16FSW & X86_FSW_ES) \
1110 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1111 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1112 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1113 } while (0)
1114
1115/** Calculate efficient address from R/M. */
1116#ifndef IEM_WITH_SETJMP
1117# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1118 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1119#else
1120# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1121 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1122#endif
1123
1124#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1125#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1126#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1127#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1128#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1129#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1130#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1131
1132/**
1133 * Defers the rest of the instruction emulation to a C implementation routine
1134 * and returns, only taking the standard parameters.
1135 *
1136 * @param a_pfnCImpl The pointer to the C routine.
1137 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1138 */
1139#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1140
1141/**
1142 * Defers the rest of instruction emulation to a C implementation routine and
1143 * returns, taking one argument in addition to the standard ones.
1144 *
1145 * @param a_pfnCImpl The pointer to the C routine.
1146 * @param a0 The argument.
1147 */
1148#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1149
1150/**
1151 * Defers the rest of the instruction emulation to a C implementation routine
1152 * and returns, taking two arguments in addition to the standard ones.
1153 *
1154 * @param a_pfnCImpl The pointer to the C routine.
1155 * @param a0 The first extra argument.
1156 * @param a1 The second extra argument.
1157 */
1158#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1159
1160/**
1161 * Defers the rest of the instruction emulation to a C implementation routine
1162 * and returns, taking three arguments in addition to the standard ones.
1163 *
1164 * @param a_pfnCImpl The pointer to the C routine.
1165 * @param a0 The first extra argument.
1166 * @param a1 The second extra argument.
1167 * @param a2 The third extra argument.
1168 */
1169#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1170
1171/**
1172 * Defers the rest of the instruction emulation to a C implementation routine
1173 * and returns, taking four arguments in addition to the standard ones.
1174 *
1175 * @param a_pfnCImpl The pointer to the C routine.
1176 * @param a0 The first extra argument.
1177 * @param a1 The second extra argument.
1178 * @param a2 The third extra argument.
1179 * @param a3 The fourth extra argument.
1180 */
1181#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1182
1183/**
1184 * Defers the rest of the instruction emulation to a C implementation routine
1185 * and returns, taking two arguments in addition to the standard ones.
1186 *
1187 * @param a_pfnCImpl The pointer to the C routine.
1188 * @param a0 The first extra argument.
1189 * @param a1 The second extra argument.
1190 * @param a2 The third extra argument.
1191 * @param a3 The fourth extra argument.
1192 * @param a4 The fifth extra argument.
1193 */
1194#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1195
1196/**
1197 * Defers the entire instruction emulation to a C implementation routine and
1198 * returns, only taking the standard parameters.
1199 *
1200 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1201 *
1202 * @param a_pfnCImpl The pointer to the C routine.
1203 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1204 */
1205#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1206
1207/**
1208 * Defers the entire instruction emulation to a C implementation routine and
1209 * returns, taking one argument in addition to the standard ones.
1210 *
1211 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1212 *
1213 * @param a_pfnCImpl The pointer to the C routine.
1214 * @param a0 The argument.
1215 */
1216#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1217
1218/**
1219 * Defers the entire instruction emulation to a C implementation routine and
1220 * returns, taking two arguments in addition to the standard ones.
1221 *
1222 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1223 *
1224 * @param a_pfnCImpl The pointer to the C routine.
1225 * @param a0 The first extra argument.
1226 * @param a1 The second extra argument.
1227 */
1228#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1229
1230/**
1231 * Defers the entire instruction emulation to a C implementation routine and
1232 * returns, taking three arguments in addition to the standard ones.
1233 *
1234 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1235 *
1236 * @param a_pfnCImpl The pointer to the C routine.
1237 * @param a0 The first extra argument.
1238 * @param a1 The second extra argument.
1239 * @param a2 The third extra argument.
1240 */
1241#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1242
1243/**
1244 * Calls a FPU assembly implementation taking one visible argument.
1245 *
1246 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1247 * @param a0 The first extra argument.
1248 */
1249#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1250 do { \
1251 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1252 } while (0)
1253
1254/**
1255 * Calls a FPU assembly implementation taking two visible arguments.
1256 *
1257 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1258 * @param a0 The first extra argument.
1259 * @param a1 The second extra argument.
1260 */
1261#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1262 do { \
1263 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1264 } while (0)
1265
1266/**
1267 * Calls a FPU assembly implementation taking three visible arguments.
1268 *
1269 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1270 * @param a0 The first extra argument.
1271 * @param a1 The second extra argument.
1272 * @param a2 The third extra argument.
1273 */
1274#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1275 do { \
1276 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1277 } while (0)
1278
1279#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1280 do { \
1281 (a_FpuData).FSW = (a_FSW); \
1282 (a_FpuData).r80Result = *(a_pr80Value); \
1283 } while (0)
1284
1285/** Pushes FPU result onto the stack. */
1286#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1287 iemFpuPushResult(pVCpu, &a_FpuData)
1288/** Pushes FPU result onto the stack and sets the FPUDP. */
1289#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1290 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1291
1292/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1293#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1294 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1295
1296/** Stores FPU result in a stack register. */
1297#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1298 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1299/** Stores FPU result in a stack register and pops the stack. */
1300#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1301 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1302/** Stores FPU result in a stack register and sets the FPUDP. */
1303#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1304 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1305/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1306 * stack. */
1307#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1308 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1309
1310/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1311#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1312 iemFpuUpdateOpcodeAndIp(pVCpu)
1313/** Free a stack register (for FFREE and FFREEP). */
1314#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1315 iemFpuStackFree(pVCpu, a_iStReg)
1316/** Increment the FPU stack pointer. */
1317#define IEM_MC_FPU_STACK_INC_TOP() \
1318 iemFpuStackIncTop(pVCpu)
1319/** Decrement the FPU stack pointer. */
1320#define IEM_MC_FPU_STACK_DEC_TOP() \
1321 iemFpuStackDecTop(pVCpu)
1322
1323/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1324#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1325 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1326/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1327#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1328 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1329/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1330#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1331 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1332/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1333#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1334 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1335/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1336 * stack. */
1337#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1338 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1339/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1340#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1341 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1342
1343/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1344#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1345 iemFpuStackUnderflow(pVCpu, a_iStDst)
1346/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1347 * stack. */
1348#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1349 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1350/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1351 * FPUDS. */
1352#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1353 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1354/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1355 * FPUDS. Pops stack. */
1356#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1357 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1358/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1359 * stack twice. */
1360#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1361 iemFpuStackUnderflowThenPopPop(pVCpu)
1362/** Raises a FPU stack underflow exception for an instruction pushing a result
1363 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1364#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1365 iemFpuStackPushUnderflow(pVCpu)
1366/** Raises a FPU stack underflow exception for an instruction pushing a result
1367 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1368#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1369 iemFpuStackPushUnderflowTwo(pVCpu)
1370
1371/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1372 * FPUIP, FPUCS and FOP. */
1373#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1374 iemFpuStackPushOverflow(pVCpu)
1375/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1376 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1377#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1378 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1379/** Prepares for using the FPU state.
1380 * Ensures that we can use the host FPU in the current context (RC+R0.
1381 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1382#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1383/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1384#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1385/** Actualizes the guest FPU state so it can be accessed and modified. */
1386#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1387
1388/** Stores SSE SIMD result updating MXCSR. */
1389#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1390 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1391/** Updates MXCSR. */
1392#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1393 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1394
1395/** Prepares for using the SSE state.
1396 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1397 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1398#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1399/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1400#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1401/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1402#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1403
1404/** Prepares for using the AVX state.
1405 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1406 * Ensures the guest AVX state in the CPUMCTX is up to date.
1407 * @note This will include the AVX512 state too when support for it is added
1408 * due to the zero extending feature of VEX instruction. */
1409#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1410/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1411#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1412/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1413#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1414
1415/**
1416 * Calls a MMX assembly implementation taking two visible arguments.
1417 *
1418 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1419 * @param a0 The first extra argument.
1420 * @param a1 The second extra argument.
1421 */
1422#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1423 do { \
1424 IEM_MC_PREPARE_FPU_USAGE(); \
1425 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1426 } while (0)
1427
1428/**
1429 * Calls a MMX assembly implementation taking three visible arguments.
1430 *
1431 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1432 * @param a0 The first extra argument.
1433 * @param a1 The second extra argument.
1434 * @param a2 The third extra argument.
1435 */
1436#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1437 do { \
1438 IEM_MC_PREPARE_FPU_USAGE(); \
1439 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1440 } while (0)
1441
1442
1443/**
1444 * Calls a SSE assembly implementation taking two visible arguments.
1445 *
1446 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1447 * @param a0 The first extra argument.
1448 * @param a1 The second extra argument.
1449 */
1450#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1451 do { \
1452 IEM_MC_PREPARE_SSE_USAGE(); \
1453 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1454 } while (0)
1455
1456/**
1457 * Calls a SSE assembly implementation taking three visible arguments.
1458 *
1459 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1460 * @param a0 The first extra argument.
1461 * @param a1 The second extra argument.
1462 * @param a2 The third extra argument.
1463 */
1464#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1465 do { \
1466 IEM_MC_PREPARE_SSE_USAGE(); \
1467 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1468 } while (0)
1469
1470
1471/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1472 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1473#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1474 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1475
1476/**
1477 * Calls a AVX assembly implementation taking two visible arguments.
1478 *
1479 * There is one implicit zero'th argument, a pointer to the extended state.
1480 *
1481 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1482 * @param a1 The first extra argument.
1483 * @param a2 The second extra argument.
1484 */
1485#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1486 do { \
1487 IEM_MC_PREPARE_AVX_USAGE(); \
1488 a_pfnAImpl(pXState, (a1), (a2)); \
1489 } while (0)
1490
1491/**
1492 * Calls a AVX assembly implementation taking three visible arguments.
1493 *
1494 * There is one implicit zero'th argument, a pointer to the extended state.
1495 *
1496 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1497 * @param a1 The first extra argument.
1498 * @param a2 The second extra argument.
1499 * @param a3 The third extra argument.
1500 */
1501#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1502 do { \
1503 IEM_MC_PREPARE_AVX_USAGE(); \
1504 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1505 } while (0)
1506
1507/** @note Not for IOPL or IF testing. */
1508#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1509/** @note Not for IOPL or IF testing. */
1510#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1511/** @note Not for IOPL or IF testing. */
1512#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1513/** @note Not for IOPL or IF testing. */
1514#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1515/** @note Not for IOPL or IF testing. */
1516#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1517 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1518 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1519/** @note Not for IOPL or IF testing. */
1520#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1521 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1522 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1523/** @note Not for IOPL or IF testing. */
1524#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1525 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1526 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1527 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1528/** @note Not for IOPL or IF testing. */
1529#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1530 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1531 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1532 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1533#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1534#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1535#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1536/** @note Not for IOPL or IF testing. */
1537#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1538 if ( pVCpu->cpum.GstCtx.cx != 0 \
1539 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1540/** @note Not for IOPL or IF testing. */
1541#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1542 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1543 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1544/** @note Not for IOPL or IF testing. */
1545#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1546 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1547 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1548/** @note Not for IOPL or IF testing. */
1549#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1550 if ( pVCpu->cpum.GstCtx.cx != 0 \
1551 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1552/** @note Not for IOPL or IF testing. */
1553#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1554 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1555 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1556/** @note Not for IOPL or IF testing. */
1557#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1558 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1559 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1560#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1561#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1562
1563#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1564 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1565#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1566 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1567#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1568 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1569#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1570 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1571#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1572 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1573#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1574 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1575#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1576 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1577#define IEM_MC_IF_FCW_IM() \
1578 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1579#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1580 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1581 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1582
1583#define IEM_MC_ELSE() } else {
1584#define IEM_MC_ENDIF() } do {} while (0)
1585
1586/** @} */
1587
1588#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1589
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