VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 96860

Last change on this file since 96860 was 96852, checked in by vboxsync, 21 months ago

IEM: Rotate the FPU stack when changing the FP TOS. Make sure stack adjustment is done before MMX instructions execute, not after.
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  • Property svn:keywords set to Author Date Id Revision
File size: 83.4 KB
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1/* $Id: IEMMc.h 96852 2022-09-26 06:06:05Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44#define IEM_MC_PAUSE() do {} while (0)
45#define IEM_MC_CONTINUE() do {} while (0)
46
47/** Internal macro. */
48#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
49 do \
50 { \
51 VBOXSTRICTRC rcStrict2 = a_Expr; \
52 if (rcStrict2 != VINF_SUCCESS) \
53 return rcStrict2; \
54 } while (0)
55
56
57#define IEM_MC_ADVANCE_RIP() iemRegUpdateRipAndClearRF(pVCpu)
58#define IEM_MC_REL_JMP_S8(a_i8) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pVCpu, a_i8))
59#define IEM_MC_REL_JMP_S16(a_i16) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pVCpu, a_i16))
60#define IEM_MC_REL_JMP_S32(a_i32) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pVCpu, a_i32))
61#define IEM_MC_SET_RIP_U16(a_u16NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u16NewIP)))
62#define IEM_MC_SET_RIP_U32(a_u32NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u32NewIP)))
63#define IEM_MC_SET_RIP_U64(a_u64NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u64NewIP)))
64#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
65#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
66 do { \
67 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
68 return iemRaiseDeviceNotAvailable(pVCpu); \
69 } while (0)
70#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
71 do { \
72 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
73 return iemRaiseDeviceNotAvailable(pVCpu); \
74 } while (0)
75#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
76 do { \
77 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
78 return iemRaiseMathFault(pVCpu); \
79 } while (0)
80#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
81 do { \
82 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
83 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
84 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
85 return iemRaiseUndefinedOpcode(pVCpu); \
86 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
87 return iemRaiseDeviceNotAvailable(pVCpu); \
88 } while (0)
89#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
90 do { \
91 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
92 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
93 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
94 return iemRaiseUndefinedOpcode(pVCpu); \
95 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
96 return iemRaiseDeviceNotAvailable(pVCpu); \
97 } while (0)
98#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
99 do { \
100 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
101 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
102 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
103 return iemRaiseUndefinedOpcode(pVCpu); \
104 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
105 return iemRaiseDeviceNotAvailable(pVCpu); \
106 } while (0)
107#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
108 do { \
109 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
110 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
111 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
112 return iemRaiseUndefinedOpcode(pVCpu); \
113 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
114 return iemRaiseDeviceNotAvailable(pVCpu); \
115 } while (0)
116#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
117 do { \
118 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
119 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
120 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
121 return iemRaiseUndefinedOpcode(pVCpu); \
122 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
123 return iemRaiseDeviceNotAvailable(pVCpu); \
124 } while (0)
125#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
126 do { \
127 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
128 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
129 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
130 return iemRaiseUndefinedOpcode(pVCpu); \
131 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
132 return iemRaiseDeviceNotAvailable(pVCpu); \
133 } while (0)
134#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
135 do { \
136 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
137 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
138 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
139 return iemRaiseUndefinedOpcode(pVCpu); \
140 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
141 return iemRaiseDeviceNotAvailable(pVCpu); \
142 } while (0)
143#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
144 do { \
145 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
146 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
147 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
148 return iemRaiseUndefinedOpcode(pVCpu); \
149 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
150 return iemRaiseDeviceNotAvailable(pVCpu); \
151 } while (0)
152#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
153 do { \
154 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
155 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
156 return iemRaiseUndefinedOpcode(pVCpu); \
157 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
158 return iemRaiseDeviceNotAvailable(pVCpu); \
159 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
160 return iemRaiseMathFault(pVCpu); \
161 } while (0)
162#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
163 do { \
164 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
165 || !(a_fSupported)) \
166 return iemRaiseUndefinedOpcode(pVCpu); \
167 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
168 return iemRaiseDeviceNotAvailable(pVCpu); \
169 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
170 return iemRaiseMathFault(pVCpu); \
171 } while (0)
172#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
173 do { \
174 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
175 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
176 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
177 return iemRaiseUndefinedOpcode(pVCpu); \
178 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
179 return iemRaiseDeviceNotAvailable(pVCpu); \
180 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
181 return iemRaiseMathFault(pVCpu); \
182 } while (0)
183#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
184 do { \
185 if (pVCpu->iem.s.uCpl != 0) \
186 return iemRaiseGeneralProtectionFault0(pVCpu); \
187 } while (0)
188#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
189 do { \
190 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
191 else return iemRaiseGeneralProtectionFault0(pVCpu); \
192 } while (0)
193#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
194 do { \
195 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
196 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
197 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
198 return iemRaiseUndefinedOpcode(pVCpu); \
199 } while (0)
200#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
201 do { \
202 if (!IEM_IS_CANONICAL(a_u64Addr)) \
203 return iemRaiseGeneralProtectionFault0(pVCpu); \
204 } while (0)
205#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
206 do { \
207 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
208 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
209 { \
210 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
211 return iemRaiseSimdFpException(pVCpu); \
212 else \
213 return iemRaiseUndefinedOpcode(pVCpu); \
214 } \
215 } while (0)
216#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
217 do { \
218 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
219 return iemRaiseSimdFpException(pVCpu); \
220 else \
221 return iemRaiseUndefinedOpcode(pVCpu); \
222 } while (0)
223#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
224 do { \
225 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
226 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
227 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
228 return iemRaiseUndefinedOpcode(pVCpu); \
229 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
230 return iemRaiseDeviceNotAvailable(pVCpu); \
231 } while (0)
232
233
234#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
235#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
236#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
237#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
238#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
239#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
240#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
241 uint32_t a_Name; \
242 uint32_t *a_pName = &a_Name
243#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
244 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
245
246#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
247#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
248
249#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
250#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
251#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
252#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
253#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
254#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
255#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
256#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
257#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
258#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
259#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
260#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
261#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
262#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
263#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
264#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
265#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
266#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
267 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
268 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
269 } while (0)
270#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
271 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
272 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
273 } while (0)
274#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
275 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
276 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
277 } while (0)
278/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
279#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
280 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
281 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
282 } while (0)
283#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
284 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
285 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
286 } while (0)
287/** @note Not for IOPL or IF testing or modification. */
288#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
289#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
290#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
291#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
292
293#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
294#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
295#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
296#define IEM_MC_STORE_GREG_I32(a_iGReg, a_i32Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (int64_t)(a_i32Value) /* Sign extension. */
297#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
298#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
299#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
300#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
301#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
302#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
303#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
304#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
305/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
306#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
307 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
308 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
309 } while (0)
310#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
311 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
312 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
313 } while (0)
314#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
315 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
316
317
318#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
319#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
320/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
321 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
322#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
323#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
324#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
325#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
326#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
327#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
328/** @note Not for IOPL or IF testing or modification. */
329#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.u
330#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
331
332#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
333#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
334#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
335 do { \
336 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
337 *pu32Reg += (a_u32Value); \
338 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
339 } while (0)
340#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
341
342#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
343#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
344#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
345 do { \
346 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
347 *pu32Reg -= (a_u32Value); \
348 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
349 } while (0)
350#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
351#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
352
353#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
354#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
355#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
356#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
357#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
358#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
359#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
360
361#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
362#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
363#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
364#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
365
366#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
367#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
368#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
369
370#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
371#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
372#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
373
374#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
375#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
376#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
377
378#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
379#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
380#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
381
382#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
383
384#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
385
386#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
387#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
388#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
389 do { \
390 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
391 *pu32Reg &= (a_u32Value); \
392 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
393 } while (0)
394#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
395
396#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
397#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
398#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
399 do { \
400 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
401 *pu32Reg |= (a_u32Value); \
402 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
403 } while (0)
404#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
405
406
407/** @note Not for IOPL or IF modification. */
408#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
409/** @note Not for IOPL or IF modification. */
410#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
411/** @note Not for IOPL or IF modification. */
412#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
413
414#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
415
416/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
417#define IEM_MC_FPU_TO_MMX_MODE() do { \
418 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
419 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
420 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
421 } while (0)
422
423/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
424#define IEM_MC_FPU_FROM_MMX_MODE() do { \
425 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
426 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
427 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
428 } while (0)
429
430#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
431 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
432#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
433 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
434#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
435 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
436 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
437 } while (0)
438#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
439 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
440 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
441 } while (0)
442#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
443 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
444#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
445 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
446#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
447 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
448#define IEM_MC_MODIFIED_MREG(a_iMReg) \
449 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
450#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
451 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
452
453#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
454 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
455 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
456 } while (0)
457#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
458 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
459 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
460 } while (0)
461#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
462 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
463#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
464 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
465#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
466 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
467#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
468 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
469 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
470 } while (0)
471#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
472 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
473 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
474 } while (0)
475#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
476 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
477#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
478 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
479#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \
480 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0)
481#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
482 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
483 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
484 } while (0)
485#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \
486 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0)
487#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
488 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
489#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
490 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
491#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
492 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
493 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
494 } while (0)
495#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
496 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
497#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
498 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
499#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
500 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
501#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
502 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
503#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
504 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
505#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
506 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
507#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
508 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
509#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
510 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
511#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
512 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
513 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
514 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
515 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
516 } while (0)
517
518#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
519 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
520 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
521 } while (0)
522#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
523 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
524 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
525 } while (0)
526#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
527 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
528 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
529 } while (0)
530#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
531 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
532 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
533 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
534 } while (0)
535#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
536 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
537 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
538 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
539 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
540 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
541 } while (0)
542
543#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
544#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
545 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
546 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
547 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
548 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
549 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
550 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
551 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
552 } while (0)
553#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
554 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
555 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
556 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
557 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
558 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
559 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
560 } while (0)
561#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
562 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
563 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
564 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
565 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
566 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
567 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
568 } while (0)
569#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
570 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
571 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
572 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
573 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
574 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
575 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
576 } while (0)
577
578#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
579 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
580#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
581 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
582#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
583 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
584#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
585 do { uintptr_t const iYRegTmp = (a_iYReg); \
586 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
587 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
588 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
589 } while (0)
590
591#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
592 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
593 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
594 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
595 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
596 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
597 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
598 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
599 } while (0)
600#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
601 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
602 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
603 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
604 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
605 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
606 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
607 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
608 } while (0)
609#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
610 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
611 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
612 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
613 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
614 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
615 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
616 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
617 } while (0)
618
619#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
620 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
621 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
622 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
623 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
624 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
625 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
626 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
627 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
628 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
629 } while (0)
630#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
631 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
632 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
633 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
634 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
635 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
636 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
637 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
638 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
639 } while (0)
640#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
641 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
642 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
643 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
644 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
645 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
646 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
647 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
648 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
649 } while (0)
650#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
651 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
652 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
653 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
654 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
655 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
656 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
657 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
658 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
659 } while (0)
660#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
661 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
662 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
663 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
664 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
665 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
666 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
667 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
668 } while (0)
669#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
670 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
671 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
672 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
673 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
674 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
675 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
676 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
677 } while (0)
678
679#ifndef IEM_WITH_SETJMP
680# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
681 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
682# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
683 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
684# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
685 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
686#else
687# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
688 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
689# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
690 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
691# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
692 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
693#endif
694
695#ifndef IEM_WITH_SETJMP
696# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
697 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
698# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
699 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
700# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
701 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
702#else
703# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
704 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
705# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
706 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
707# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
708 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
709#endif
710
711#ifndef IEM_WITH_SETJMP
712# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
713 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
714# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
715 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
716# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
717 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
718#else
719# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
720 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
721# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
722 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
723# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
724 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
725#endif
726
727#ifdef SOME_UNUSED_FUNCTION
728# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
729 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
730#endif
731
732#ifndef IEM_WITH_SETJMP
733# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
734 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
735# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
736 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
737# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
738 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
739# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
740 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
741#else
742# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
743 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
744# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
745 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
746# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
747 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
748# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
749 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
750#endif
751
752#ifndef IEM_WITH_SETJMP
753# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
754 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
755# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
756 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
757# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
758 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
759# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
760 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
761#else
762# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
763 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
764# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
765 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
766# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
767 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
768# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
769 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
770#endif
771
772#ifndef IEM_WITH_SETJMP
773# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
774 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
775# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
776 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
777# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
778 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
779
780# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
781 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
782# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
783 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
784# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
785 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
786# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
787 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
788# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
789 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
790#else
791# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
792 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
793# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
794 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
795# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
796 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
797
798# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
799 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
800# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
801 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
802# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
803 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
804# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
805 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
806# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
807 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
808#endif
809
810#ifndef IEM_WITH_SETJMP
811# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
812 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
813# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
814 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
815# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
816 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
817
818# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
819 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
820# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
821 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
822# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
823 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
824#else
825# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
826 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
827# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
828 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
829# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
830 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
831
832# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
833 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
834# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
835 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
836# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
837 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
838#endif
839
840
841
842#ifndef IEM_WITH_SETJMP
843# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
844 do { \
845 uint8_t u8Tmp; \
846 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
847 (a_u16Dst) = u8Tmp; \
848 } while (0)
849# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
850 do { \
851 uint8_t u8Tmp; \
852 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
853 (a_u32Dst) = u8Tmp; \
854 } while (0)
855# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
856 do { \
857 uint8_t u8Tmp; \
858 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
859 (a_u64Dst) = u8Tmp; \
860 } while (0)
861# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
862 do { \
863 uint16_t u16Tmp; \
864 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
865 (a_u32Dst) = u16Tmp; \
866 } while (0)
867# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
868 do { \
869 uint16_t u16Tmp; \
870 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
871 (a_u64Dst) = u16Tmp; \
872 } while (0)
873# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
874 do { \
875 uint32_t u32Tmp; \
876 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
877 (a_u64Dst) = u32Tmp; \
878 } while (0)
879#else /* IEM_WITH_SETJMP */
880# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
881 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
882# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
883 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
884# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
885 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
886# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
887 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
888# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
889 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
890# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
891 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
892#endif /* IEM_WITH_SETJMP */
893
894#ifndef IEM_WITH_SETJMP
895# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
896 do { \
897 uint8_t u8Tmp; \
898 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
899 (a_u16Dst) = (int8_t)u8Tmp; \
900 } while (0)
901# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
902 do { \
903 uint8_t u8Tmp; \
904 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
905 (a_u32Dst) = (int8_t)u8Tmp; \
906 } while (0)
907# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
908 do { \
909 uint8_t u8Tmp; \
910 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
911 (a_u64Dst) = (int8_t)u8Tmp; \
912 } while (0)
913# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
914 do { \
915 uint16_t u16Tmp; \
916 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
917 (a_u32Dst) = (int16_t)u16Tmp; \
918 } while (0)
919# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
920 do { \
921 uint16_t u16Tmp; \
922 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
923 (a_u64Dst) = (int16_t)u16Tmp; \
924 } while (0)
925# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
926 do { \
927 uint32_t u32Tmp; \
928 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
929 (a_u64Dst) = (int32_t)u32Tmp; \
930 } while (0)
931#else /* IEM_WITH_SETJMP */
932# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
933 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
934# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
935 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
936# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
937 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
938# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
939 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
940# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
941 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
942# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
943 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
944#endif /* IEM_WITH_SETJMP */
945
946#ifndef IEM_WITH_SETJMP
947# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
948 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
949# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
950 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
951# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
952 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
953# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
954 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
955#else
956# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
957 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
958# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
959 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
960# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
961 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
962# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
963 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
964#endif
965
966#ifndef IEM_WITH_SETJMP
967# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
968 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
969# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
970 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
971# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
972 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
973# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
974 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
975#else
976# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
977 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
978# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
979 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
980# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
981 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
982# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
983 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
984#endif
985
986#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
987#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
988#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
989#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
990#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
991#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
992#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
993 do { \
994 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
995 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
996 } while (0)
997#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
998 do { \
999 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1000 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1001 } while (0)
1002
1003#ifndef IEM_WITH_SETJMP
1004# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1005 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1006# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1007 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1008#else
1009# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1010 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1011# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1012 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1013#endif
1014
1015#ifndef IEM_WITH_SETJMP
1016# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1017 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1018# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1019 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1020#else
1021# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1022 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1023# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1024 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1025#endif
1026
1027
1028#define IEM_MC_PUSH_U16(a_u16Value) \
1029 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1030#define IEM_MC_PUSH_U32(a_u32Value) \
1031 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1032#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1033 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1034#define IEM_MC_PUSH_U64(a_u64Value) \
1035 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1036
1037#define IEM_MC_POP_U16(a_pu16Value) \
1038 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1039#define IEM_MC_POP_U32(a_pu32Value) \
1040 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1041#define IEM_MC_POP_U64(a_pu64Value) \
1042 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1043
1044/** Maps guest memory for direct or bounce buffered access.
1045 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1046 * @remarks May return.
1047 */
1048#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1049 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1050 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1051
1052/** Maps guest memory for direct or bounce buffered access.
1053 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1054 * @remarks May return.
1055 */
1056#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1057 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1058 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1059
1060/** Commits the memory and unmaps the guest memory.
1061 * @remarks May return.
1062 */
1063#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1064 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1065
1066/** Commits the memory and unmaps the guest memory unless the FPU status word
1067 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1068 * that would cause FLD not to store.
1069 *
1070 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1071 * store, while \#P will not.
1072 *
1073 * @remarks May in theory return - for now.
1074 */
1075#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1076 do { \
1077 if ( !(a_u16FSW & X86_FSW_ES) \
1078 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1079 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1080 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1081 } while (0)
1082
1083/** Calculate efficient address from R/M. */
1084#ifndef IEM_WITH_SETJMP
1085# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1086 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1087#else
1088# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1089 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1090#endif
1091
1092#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1093#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1094#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1095#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1096#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1097#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1098#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1099
1100/**
1101 * Defers the rest of the instruction emulation to a C implementation routine
1102 * and returns, only taking the standard parameters.
1103 *
1104 * @param a_pfnCImpl The pointer to the C routine.
1105 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1106 */
1107#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1108
1109/**
1110 * Defers the rest of instruction emulation to a C implementation routine and
1111 * returns, taking one argument in addition to the standard ones.
1112 *
1113 * @param a_pfnCImpl The pointer to the C routine.
1114 * @param a0 The argument.
1115 */
1116#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1117
1118/**
1119 * Defers the rest of the instruction emulation to a C implementation routine
1120 * and returns, taking two arguments in addition to the standard ones.
1121 *
1122 * @param a_pfnCImpl The pointer to the C routine.
1123 * @param a0 The first extra argument.
1124 * @param a1 The second extra argument.
1125 */
1126#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1127
1128/**
1129 * Defers the rest of the instruction emulation to a C implementation routine
1130 * and returns, taking three arguments in addition to the standard ones.
1131 *
1132 * @param a_pfnCImpl The pointer to the C routine.
1133 * @param a0 The first extra argument.
1134 * @param a1 The second extra argument.
1135 * @param a2 The third extra argument.
1136 */
1137#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1138
1139/**
1140 * Defers the rest of the instruction emulation to a C implementation routine
1141 * and returns, taking four arguments in addition to the standard ones.
1142 *
1143 * @param a_pfnCImpl The pointer to the C routine.
1144 * @param a0 The first extra argument.
1145 * @param a1 The second extra argument.
1146 * @param a2 The third extra argument.
1147 * @param a3 The fourth extra argument.
1148 */
1149#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1150
1151/**
1152 * Defers the rest of the instruction emulation to a C implementation routine
1153 * and returns, taking two arguments in addition to the standard ones.
1154 *
1155 * @param a_pfnCImpl The pointer to the C routine.
1156 * @param a0 The first extra argument.
1157 * @param a1 The second extra argument.
1158 * @param a2 The third extra argument.
1159 * @param a3 The fourth extra argument.
1160 * @param a4 The fifth extra argument.
1161 */
1162#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1163
1164/**
1165 * Defers the entire instruction emulation to a C implementation routine and
1166 * returns, only taking the standard parameters.
1167 *
1168 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1169 *
1170 * @param a_pfnCImpl The pointer to the C routine.
1171 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1172 */
1173#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1174
1175/**
1176 * Defers the entire instruction emulation to a C implementation routine and
1177 * returns, taking one argument in addition to the standard ones.
1178 *
1179 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1180 *
1181 * @param a_pfnCImpl The pointer to the C routine.
1182 * @param a0 The argument.
1183 */
1184#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1185
1186/**
1187 * Defers the entire instruction emulation to a C implementation routine and
1188 * returns, taking two arguments in addition to the standard ones.
1189 *
1190 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1191 *
1192 * @param a_pfnCImpl The pointer to the C routine.
1193 * @param a0 The first extra argument.
1194 * @param a1 The second extra argument.
1195 */
1196#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1197
1198/**
1199 * Defers the entire instruction emulation to a C implementation routine and
1200 * returns, taking three arguments in addition to the standard ones.
1201 *
1202 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1203 *
1204 * @param a_pfnCImpl The pointer to the C routine.
1205 * @param a0 The first extra argument.
1206 * @param a1 The second extra argument.
1207 * @param a2 The third extra argument.
1208 */
1209#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1210
1211/**
1212 * Calls a FPU assembly implementation taking one visible argument.
1213 *
1214 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1215 * @param a0 The first extra argument.
1216 */
1217#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1218 do { \
1219 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1220 } while (0)
1221
1222/**
1223 * Calls a FPU assembly implementation taking two visible arguments.
1224 *
1225 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1226 * @param a0 The first extra argument.
1227 * @param a1 The second extra argument.
1228 */
1229#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1230 do { \
1231 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1232 } while (0)
1233
1234/**
1235 * Calls a FPU assembly implementation taking three visible arguments.
1236 *
1237 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1238 * @param a0 The first extra argument.
1239 * @param a1 The second extra argument.
1240 * @param a2 The third extra argument.
1241 */
1242#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1243 do { \
1244 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1245 } while (0)
1246
1247#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1248 do { \
1249 (a_FpuData).FSW = (a_FSW); \
1250 (a_FpuData).r80Result = *(a_pr80Value); \
1251 } while (0)
1252
1253/** Pushes FPU result onto the stack. */
1254#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1255 iemFpuPushResult(pVCpu, &a_FpuData)
1256/** Pushes FPU result onto the stack and sets the FPUDP. */
1257#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1258 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1259
1260/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1261#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1262 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1263
1264/** Stores FPU result in a stack register. */
1265#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1266 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1267/** Stores FPU result in a stack register and pops the stack. */
1268#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1269 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1270/** Stores FPU result in a stack register and sets the FPUDP. */
1271#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1272 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1273/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1274 * stack. */
1275#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1276 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1277
1278/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1279#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1280 iemFpuUpdateOpcodeAndIp(pVCpu)
1281/** Free a stack register (for FFREE and FFREEP). */
1282#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1283 iemFpuStackFree(pVCpu, a_iStReg)
1284/** Increment the FPU stack pointer. */
1285#define IEM_MC_FPU_STACK_INC_TOP() \
1286 iemFpuStackIncTop(pVCpu)
1287/** Decrement the FPU stack pointer. */
1288#define IEM_MC_FPU_STACK_DEC_TOP() \
1289 iemFpuStackDecTop(pVCpu)
1290
1291/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1292#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1293 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1294/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1295#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1296 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1297/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1298#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1299 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1300/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1301#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1302 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1303/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1304 * stack. */
1305#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1306 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1307/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1308#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1309 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1310
1311/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1312#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1313 iemFpuStackUnderflow(pVCpu, a_iStDst)
1314/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1315 * stack. */
1316#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1317 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1318/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1319 * FPUDS. */
1320#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1321 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1322/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1323 * FPUDS. Pops stack. */
1324#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1325 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1326/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1327 * stack twice. */
1328#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1329 iemFpuStackUnderflowThenPopPop(pVCpu)
1330/** Raises a FPU stack underflow exception for an instruction pushing a result
1331 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1332#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1333 iemFpuStackPushUnderflow(pVCpu)
1334/** Raises a FPU stack underflow exception for an instruction pushing a result
1335 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1336#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1337 iemFpuStackPushUnderflowTwo(pVCpu)
1338
1339/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1340 * FPUIP, FPUCS and FOP. */
1341#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1342 iemFpuStackPushOverflow(pVCpu)
1343/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1344 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1345#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1346 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1347/** Prepares for using the FPU state.
1348 * Ensures that we can use the host FPU in the current context (RC+R0.
1349 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1350#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1351/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1352#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1353/** Actualizes the guest FPU state so it can be accessed and modified. */
1354#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1355
1356/** Stores SSE SIMD result updating MXCSR. */
1357#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1358 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1359/** Updates MXCSR. */
1360#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1361 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1362
1363/** Prepares for using the SSE state.
1364 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1365 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1366#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1367/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1368#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1369/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1370#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1371
1372/** Prepares for using the AVX state.
1373 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1374 * Ensures the guest AVX state in the CPUMCTX is up to date.
1375 * @note This will include the AVX512 state too when support for it is added
1376 * due to the zero extending feature of VEX instruction. */
1377#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1378/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1379#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1380/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1381#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1382
1383/**
1384 * Calls a MMX assembly implementation taking two visible arguments.
1385 *
1386 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1387 * @param a0 The first extra argument.
1388 * @param a1 The second extra argument.
1389 */
1390#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1391 do { \
1392 IEM_MC_PREPARE_FPU_USAGE(); \
1393 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1394 } while (0)
1395
1396/**
1397 * Calls a MMX assembly implementation taking three visible arguments.
1398 *
1399 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1400 * @param a0 The first extra argument.
1401 * @param a1 The second extra argument.
1402 * @param a2 The third extra argument.
1403 */
1404#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1405 do { \
1406 IEM_MC_PREPARE_FPU_USAGE(); \
1407 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1408 } while (0)
1409
1410
1411/**
1412 * Calls a SSE assembly implementation taking two visible arguments.
1413 *
1414 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1415 * @param a0 The first extra argument.
1416 * @param a1 The second extra argument.
1417 */
1418#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1419 do { \
1420 IEM_MC_PREPARE_SSE_USAGE(); \
1421 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1422 } while (0)
1423
1424/**
1425 * Calls a SSE assembly implementation taking three visible arguments.
1426 *
1427 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1428 * @param a0 The first extra argument.
1429 * @param a1 The second extra argument.
1430 * @param a2 The third extra argument.
1431 */
1432#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1433 do { \
1434 IEM_MC_PREPARE_SSE_USAGE(); \
1435 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1436 } while (0)
1437
1438
1439/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1440 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1441#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1442 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1443
1444/**
1445 * Calls a AVX assembly implementation taking two visible arguments.
1446 *
1447 * There is one implicit zero'th argument, a pointer to the extended state.
1448 *
1449 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1450 * @param a1 The first extra argument.
1451 * @param a2 The second extra argument.
1452 */
1453#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1454 do { \
1455 IEM_MC_PREPARE_AVX_USAGE(); \
1456 a_pfnAImpl(pXState, (a1), (a2)); \
1457 } while (0)
1458
1459/**
1460 * Calls a AVX assembly implementation taking three visible arguments.
1461 *
1462 * There is one implicit zero'th argument, a pointer to the extended state.
1463 *
1464 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1465 * @param a1 The first extra argument.
1466 * @param a2 The second extra argument.
1467 * @param a3 The third extra argument.
1468 */
1469#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1470 do { \
1471 IEM_MC_PREPARE_AVX_USAGE(); \
1472 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1473 } while (0)
1474
1475/** @note Not for IOPL or IF testing. */
1476#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1477/** @note Not for IOPL or IF testing. */
1478#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1479/** @note Not for IOPL or IF testing. */
1480#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1481/** @note Not for IOPL or IF testing. */
1482#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1483/** @note Not for IOPL or IF testing. */
1484#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1485 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1486 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1487/** @note Not for IOPL or IF testing. */
1488#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1489 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1490 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1491/** @note Not for IOPL or IF testing. */
1492#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1493 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1494 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1495 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1496/** @note Not for IOPL or IF testing. */
1497#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1498 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1499 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1500 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1501#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1502#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1503#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1504/** @note Not for IOPL or IF testing. */
1505#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1506 if ( pVCpu->cpum.GstCtx.cx != 0 \
1507 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1508/** @note Not for IOPL or IF testing. */
1509#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1510 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1511 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1512/** @note Not for IOPL or IF testing. */
1513#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1514 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1515 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1516/** @note Not for IOPL or IF testing. */
1517#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1518 if ( pVCpu->cpum.GstCtx.cx != 0 \
1519 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1520/** @note Not for IOPL or IF testing. */
1521#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1522 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1523 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1524/** @note Not for IOPL or IF testing. */
1525#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1526 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1527 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1528#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1529#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1530
1531#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1532 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1533#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1534 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1535#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1536 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1537#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1538 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1539#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1540 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1541#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1542 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1543#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1544 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1545#define IEM_MC_IF_FCW_IM() \
1546 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1547#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1548 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1549 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1550
1551#define IEM_MC_ELSE() } else {
1552#define IEM_MC_ENDIF() } do {} while (0)
1553
1554/** @} */
1555
1556#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1557
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