IEMInternal.h@ 104932

Last change on this file since 104932 was 104932, checked in by vboxsync, 11 months ago
VMM/PGM,IEM: Refactored+copied PGMGstGetPage into PGMGstQueryPage that takes care of table walking, setting A & D bits and validating the access. Use new function in IEM. bugref:10687
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 325.0 KB

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1	/* $Id: IEMInternal.h 104932 2024-06-15 00:29:39Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
116	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
117	* executing native translation blocks.
118	*
119	* This exploits the fact that we save all non-volatile registers in the TB
120	* prologue and thus just need to do the same as the TB epilogue to get the
121	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
122	* non-volatile (and does something even more crazy for ARM), this probably
123	* won't work reliably on Windows. */
124	#ifdef RT_ARCH_ARM64
125	# ifndef RT_OS_WINDOWS
126	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
127	# endif
128	#endif
129	/* ASM-NOINC-START */
130	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
131	# if !defined(IN_RING3) \
132	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
133	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
134	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
135	# elif defined(RT_OS_WINDOWS)
136	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
137	# endif
138	#endif
139
140
141	/** @def IEM_DO_LONGJMP
142	*
143	* Wrapper around longjmp / throw.
144	*
145	* @param a_pVCpu The CPU handle.
146	* @param a_rc The status code jump back with / throw.
147	*/
148	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
149	# ifdef IEM_WITH_THROW_CATCH
150	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
151	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
152	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
153	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
154	throw int(a_rc); \
155	} while (0)
156	# else
157	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
158	# endif
159	# else
160	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
161	# endif
162	#endif
163
164	/** For use with IEM function that may do a longjmp (when enabled).
165	*
166	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
167	* attribute. So, we indicate that function that may be part of a longjmp may
168	* throw "exceptions" and that the compiler should definitely not generate and
169	* std::terminate calling unwind code.
170	*
171	* Here is one example of this ending in std::terminate:
172	* @code{.txt}
173	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
174	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
175	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
176	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
177	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
178	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
179	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
180	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
181	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
182	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
183	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
184	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
185	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
186	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
187	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
188	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
189	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
190	@endcode
191	*
192	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
193	*/
194	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
195	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
196	#else
197	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
198	#endif
199	/* ASM-NOINC-END */
200
201	#define IEM_IMPLEMENTS_TASKSWITCH
202
203	/** @def IEM_WITH_3DNOW
204	* Includes the 3DNow decoding. */
205	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
206	# ifndef IEM_WITHOUT_3DNOW
207	# define IEM_WITH_3DNOW
208	# endif
209	#endif
210
211	/** @def IEM_WITH_THREE_0F_38
212	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
213	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
214	# ifndef IEM_WITHOUT_THREE_0F_38
215	# define IEM_WITH_THREE_0F_38
216	# endif
217	#endif
218
219	/** @def IEM_WITH_THREE_0F_3A
220	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
221	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
222	# ifndef IEM_WITHOUT_THREE_0F_3A
223	# define IEM_WITH_THREE_0F_3A
224	# endif
225	#endif
226
227	/** @def IEM_WITH_VEX
228	* Includes the VEX decoding. */
229	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
230	# ifndef IEM_WITHOUT_VEX
231	# define IEM_WITH_VEX
232	# endif
233	#endif
234
235	/** @def IEM_CFG_TARGET_CPU
236	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
237	*
238	* By default we allow this to be configured by the user via the
239	* CPUM/GuestCpuName config string, but this comes at a slight cost during
240	* decoding. So, for applications of this code where there is no need to
241	* be dynamic wrt target CPU, just modify this define.
242	*/
243	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
244	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
245	#endif
246
247	//#define IEM_WITH_CODE_TLB // - work in progress
248	//#define IEM_WITH_DATA_TLB // - work in progress
249
250
251	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
252	* Use unaligned accesses instead of elaborate byte assembly. */
253	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
254	# define IEM_USE_UNALIGNED_DATA_ACCESS
255	#endif /ASM-NOINC/
256
257	//#define IEM_LOG_MEMORY_WRITES
258
259
260
261	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
262
263	# if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
264	/** Instruction statistics. */
265	typedef struct IEMINSTRSTATS
266	{
267	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
268	# include "IEMInstructionStatisticsTmpl.h"
269	# undef IEM_DO_INSTR_STAT
270	} IEMINSTRSTATS;
271	#else
272	struct IEMINSTRSTATS;
273	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
274	#endif
275	/** Pointer to IEM instruction statistics. */
276	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
277
278
279	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
280	* @{ */
281	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
282	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
283	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
284	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
285	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
286	/** Selects the right variant from a_aArray.
287	* pVCpu is implicit in the caller context. */
288	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
289	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
290	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
291	* be used because the host CPU does not support the operation. */
292	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
293	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
294	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
295	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
296	* into the two.
297	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
298	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
299	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
300	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
301	#else
302	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
303	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
304	#endif
305	/** @} */
306
307	/**
308	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
309	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
310	*
311	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
312	* indicator.
313	*
314	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
315	*/
316	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
317	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
318	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
319	#else
320	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
321	#endif
322
323
324	/**
325	* Branch types.
326	*/
327	typedef enum IEMBRANCH
328	{
329	IEMBRANCH_JUMP = 1,
330	IEMBRANCH_CALL,
331	IEMBRANCH_TRAP,
332	IEMBRANCH_SOFTWARE_INT,
333	IEMBRANCH_HARDWARE_INT
334	} IEMBRANCH;
335	AssertCompileSize(IEMBRANCH, 4);
336
337
338	/**
339	* INT instruction types.
340	*/
341	typedef enum IEMINT
342	{
343	/** INT n instruction (opcode 0xcd imm). */
344	IEMINT_INTN = 0,
345	/** Single byte INT3 instruction (opcode 0xcc). */
346	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
347	/** Single byte INTO instruction (opcode 0xce). */
348	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
349	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
350	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
351	} IEMINT;
352	AssertCompileSize(IEMINT, 4);
353
354
355	/**
356	* A FPU result.
357	*/
358	typedef struct IEMFPURESULT
359	{
360	/** The output value. */
361	RTFLOAT80U r80Result;
362	/** The output status. */
363	uint16_t FSW;
364	} IEMFPURESULT;
365	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
366	/** Pointer to a FPU result. */
367	typedef IEMFPURESULT *PIEMFPURESULT;
368	/** Pointer to a const FPU result. */
369	typedef IEMFPURESULT const *PCIEMFPURESULT;
370
371
372	/**
373	* A FPU result consisting of two output values and FSW.
374	*/
375	typedef struct IEMFPURESULTTWO
376	{
377	/** The first output value. */
378	RTFLOAT80U r80Result1;
379	/** The output status. */
380	uint16_t FSW;
381	/** The second output value. */
382	RTFLOAT80U r80Result2;
383	} IEMFPURESULTTWO;
384	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
385	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
386	/** Pointer to a FPU result consisting of two output values and FSW. */
387	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
388	/** Pointer to a const FPU result consisting of two output values and FSW. */
389	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
390
391
392	/**
393	* IEM TLB entry.
394	*
395	* Lookup assembly:
396	* @code{.asm}
397	; Calculate tag.
398	mov rax, [VA]
399	shl rax, 16
400	shr rax, 16 + X86_PAGE_SHIFT
401	or rax, [uTlbRevision]
402
403	; Do indexing.
404	movzx ecx, al
405	lea rcx, [pTlbEntries + rcx]
406
407	; Check tag.
408	cmp [rcx + IEMTLBENTRY.uTag], rax
409	jne .TlbMiss
410
411	; Check access.
412	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
413	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
414	cmp rax, [uTlbPhysRev]
415	jne .TlbMiss
416
417	; Calc address and we're done.
418	mov eax, X86_PAGE_OFFSET_MASK
419	and eax, [VA]
420	or rax, [rcx + IEMTLBENTRY.pMappingR3]
421	%ifdef VBOX_WITH_STATISTICS
422	inc qword [cTlbHits]
423	%endif
424	jmp .Done
425
426	.TlbMiss:
427	mov r8d, ACCESS_FLAGS
428	mov rdx, [VA]
429	mov rcx, [pVCpu]
430	call iemTlbTypeMiss
431	.Done:
432
433	@endcode
434	*
435	*/
436	typedef struct IEMTLBENTRY
437	{
438	/** The TLB entry tag.
439	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
440	* is ASSUMING a virtual address width of 48 bits.
441	*
442	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
443	*
444	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
445	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
446	* revision wraps around though, the tags needs to be zeroed.
447	*
448	* @note Try use SHRD instruction? After seeing
449	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
450	*
451	* @todo This will need to be reorganized for 57-bit wide virtual address and
452	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
453	* have to move the TLB entry versioning entirely to the
454	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
455	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
456	* consumed by PCID and ASID (12 + 6 = 18).
457	*/
458	uint64_t uTag;
459	/** Access flags and physical TLB revision.
460	*
461	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
462	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
463	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
464	* - Bit 3 - pgm phys/virt - not directly writable.
465	* - Bit 4 - pgm phys page - not directly readable.
466	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
467	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
468	* - Bit 7 - tlb entry - pMappingR3 member not valid.
469	* - Bits 63 thru 8 are used for the physical TLB revision number.
470	*
471	* We're using complemented bit meanings here because it makes it easy to check
472	* whether special action is required. For instance a user mode write access
473	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
474	* non-zero result would mean special handling needed because either it wasn't
475	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
476	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
477	* need to check any PTE flag.
478	*/
479	uint64_t fFlagsAndPhysRev;
480	/** The guest physical page address. */
481	uint64_t GCPhys;
482	/** Pointer to the ring-3 mapping. */
483	R3PTRTYPE(uint8_t *) pbMappingR3;
484	#if HC_ARCH_BITS == 32
485	uint32_t u32Padding1;
486	#endif
487	} IEMTLBENTRY;
488	AssertCompileSize(IEMTLBENTRY, 32);
489	/** Pointer to an IEM TLB entry. */
490	typedef IEMTLBENTRY *PIEMTLBENTRY;
491
492	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
493	* @{ */
494	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
495	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
496	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
497	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
498	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
499	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
500	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
501	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
502	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
503	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
504	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
505	/** @} */
506	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
507	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
508	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
509	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
510	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
511	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
512	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
513	\| PGMIEMGCPHYS2PTR_F_NO_READ \
514	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
515	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
516	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
517	\| IEMTLBE_F_PHYS_REV )
518
519
520	/**
521	* An IEM TLB.
522	*
523	* We've got two of these, one for data and one for instructions.
524	*/
525	typedef struct IEMTLB
526	{
527	/** The TLB revision.
528	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
529	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
530	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
531	* (The revision zero indicates an invalid TLB entry.)
532	*
533	* The initial value is choosen to cause an early wraparound. */
534	uint64_t uTlbRevision;
535	/** The TLB physical address revision - shadow of PGM variable.
536	*
537	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
538	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
539	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
540	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
541	*
542	* The initial value is choosen to cause an early wraparound. */
543	uint64_t volatile uTlbPhysRev;
544
545	/* Statistics: */
546
547	/** TLB hits (VBOX_WITH_STATISTICS only). */
548	uint64_t cTlbHits;
549	/** TLB misses. */
550	uint32_t cTlbMisses;
551	/** Slow read path. */
552	uint32_t cTlbSlowReadPath;
553	/** Safe read path. */
554	uint32_t cTlbSafeReadPath;
555	/** Safe write path. */
556	uint32_t cTlbSafeWritePath;
557	#if 0
558	/** TLB misses because of tag mismatch. */
559	uint32_t cTlbMissesTag;
560	/** TLB misses because of virtual access violation. */
561	uint32_t cTlbMissesVirtAccess;
562	/** TLB misses because of dirty bit. */
563	uint32_t cTlbMissesDirty;
564	/** TLB misses because of MMIO */
565	uint32_t cTlbMissesMmio;
566	/** TLB misses because of write access handlers. */
567	uint32_t cTlbMissesWriteHandler;
568	/** TLB misses because no r3(/r0) mapping. */
569	uint32_t cTlbMissesMapping;
570	#endif
571	/** Alignment padding. */
572	uint32_t au32Padding[6];
573
574	/** The TLB entries.
575	* We've choosen 256 because that way we can obtain the result directly from a
576	* 8-bit register without an additional AND instruction. */
577	IEMTLBENTRY aEntries[256];
578	} IEMTLB;
579	AssertCompileSizeAlignment(IEMTLB, 64);
580	/** IEMTLB::uTlbRevision increment. */
581	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
582	/** IEMTLB::uTlbRevision mask. */
583	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
584	/** IEMTLB::uTlbPhysRev increment.
585	* @sa IEMTLBE_F_PHYS_REV */
586	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
587	/**
588	* Calculates the TLB tag for a virtual address.
589	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
590	* @param a_pTlb The TLB.
591	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
592	* the clearing of the top 16 bits won't work (if 32-bit
593	* we'll end up with mostly zeros).
594	*/
595	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
596	/**
597	* Calculates the TLB tag for a virtual address but without TLB revision.
598	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
599	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
600	* the clearing of the top 16 bits won't work (if 32-bit
601	* we'll end up with mostly zeros).
602	*/
603	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
604	/**
605	* Converts a TLB tag value into a TLB index.
606	* @returns Index into IEMTLB::aEntries.
607	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
608	*/
609	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
610	/**
611	* Converts a TLB tag value into a TLB index.
612	* @returns Index into IEMTLB::aEntries.
613	* @param a_pTlb The TLB.
614	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
615	*/
616	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
617
618
619	/** @name IEM_MC_F_XXX - MC block flags/clues.
620	* @todo Merge with IEM_CIMPL_F_XXX
621	* @{ */
622	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
623	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
624	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
625	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
626	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
627	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
628	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
629	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
630	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
631	#define IEM_MC_F_64BIT RT_BIT_32(6)
632	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
633	/** This is set by IEMAllN8vePython.py to indicate a variation without the
634	* flags-clearing-and-checking, when there is also a variation with that.
635	* @note Do not use this manully, it's only for python and for testing in
636	* the native recompiler! */
637	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
638	/** @} */
639
640	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
641	*
642	* These clues are mainly for the recompiler, so that it can emit correct code.
643	*
644	* They are processed by the python script and which also automatically
645	* calculates flags for MC blocks based on the statements, extending the use of
646	* these flags to describe MC block behavior to the recompiler core. The python
647	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
648	* error checking purposes. The script emits the necessary fEndTb = true and
649	* similar statements as this reduces compile time a tiny bit.
650	*
651	* @{ */
652	/** Flag set if direct branch, clear if absolute or indirect. */
653	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
654	/** Flag set if indirect branch, clear if direct or relative.
655	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
656	* as well as for return instructions (RET, IRET, RETF). */
657	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
658	/** Flag set if relative branch, clear if absolute or indirect. */
659	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
660	/** Flag set if conditional branch, clear if unconditional. */
661	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
662	/** Flag set if it's a far branch (changes CS). */
663	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
664	/** Convenience: Testing any kind of branch. */
665	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
666
667	/** Execution flags may change (IEMCPU::fExec). */
668	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
669	/** May change significant portions of RFLAGS. */
670	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
671	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
672	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
673	/** May trigger interrupt shadowing. */
674	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
675	/** May enable interrupts, so recheck IRQ immediately afterwards executing
676	* the instruction. */
677	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
678	/** May disable interrupts, so recheck IRQ immediately before executing the
679	* instruction. */
680	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
681	/** Convenience: Check for IRQ both before and after an instruction. */
682	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
683	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
684	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
685	/** May modify FPU state.
686	* @todo Not sure if this is useful yet. */
687	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
688	/** REP prefixed instruction which may yield before updating PC.
689	* @todo Not sure if this is useful, REP functions now return non-zero
690	* status if they don't update the PC. */
691	#define IEM_CIMPL_F_REP RT_BIT_32(13)
692	/** I/O instruction.
693	* @todo Not sure if this is useful yet. */
694	#define IEM_CIMPL_F_IO RT_BIT_32(14)
695	/** Force end of TB after the instruction. */
696	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
697	/** Flag set if a branch may also modify the stack (push/pop return address). */
698	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
699	/** Flag set if a branch may also modify the stack (push/pop return address)
700	* and switch it (load/restore SS:RSP). */
701	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
702	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
703	#define IEM_CIMPL_F_XCPT \
704	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
705	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
706
707	/** The block calls a C-implementation instruction function with two implicit arguments.
708	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
709	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
710	* @note The python scripts will add this if missing. */
711	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
712	/** The block calls an ASM-implementation instruction function.
713	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
714	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
715	* @note The python scripts will add this if missing. */
716	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
717	/** The block calls an ASM-implementation instruction function with an implicit
718	* X86FXSTATE pointer argument.
719	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
720	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
721	* @note The python scripts will add this if missing. */
722	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
723	/** The block calls an ASM-implementation instruction function with an implicit
724	* X86XSAVEAREA pointer argument.
725	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
726	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
727	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
728	* @note The python scripts will add this if missing. */
729	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
730	/** @} */
731
732
733	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
734	*
735	* These flags are set when entering IEM and adjusted as code is executed, such
736	* that they will always contain the current values as instructions are
737	* finished.
738	*
739	* In recompiled execution mode, (most of) these flags are included in the
740	* translation block selection key and stored in IEMTB::fFlags alongside the
741	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
742	* in IEMCPU::fExec.
743	*
744	* @{ */
745	/** Mode: The block target mode mask. */
746	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
747	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
748	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
749	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
750	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
751	* 32-bit mode (for simplifying most memory accesses). */
752	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
753	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
754	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
755	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
756	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
757
758	/** X86 Mode: 16-bit on 386 or later. */
759	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
760	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
761	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
762	/** X86 Mode: 16-bit protected mode on 386 or later. */
763	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
764	/** X86 Mode: 16-bit protected mode on 386 or later. */
765	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
766	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
767	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
768
769	/** X86 Mode: 32-bit on 386 or later. */
770	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
771	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
772	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
773	/** X86 Mode: 32-bit protected mode. */
774	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
775	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
776	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
777
778	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
779	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
780
781	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
782	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
783	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
784	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
785
786	/** Bypass access handlers when set. */
787	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
788	/** Have pending hardware instruction breakpoints. */
789	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
790	/** Have pending hardware data breakpoints. */
791	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
792
793	/** X86: Have pending hardware I/O breakpoints. */
794	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
795	/** X86: Disregard the lock prefix (implied or not) when set. */
796	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
797
798	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
799	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
800
801	/** Caller configurable options. */
802	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
803
804	/** X86: The current protection level (CPL) shift factor. */
805	#define IEM_F_X86_CPL_SHIFT 8
806	/** X86: The current protection level (CPL) mask. */
807	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
808	/** X86: The current protection level (CPL) shifted mask. */
809	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
810
811	/** X86 execution context.
812	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
813	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
814	* mode. */
815	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
816	/** X86 context: Plain regular execution context. */
817	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
818	/** X86 context: VT-x enabled. */
819	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
820	/** X86 context: AMD-V enabled. */
821	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
822	/** X86 context: In AMD-V or VT-x guest mode. */
823	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
824	/** X86 context: System management mode (SMM). */
825	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
826
827	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
828	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
829	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
830	* alread). */
831
832	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
833	* iemRegFinishClearingRF() most for most situations
834	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
835	* the IEM_F_PENDING_BRK_XXX bits alread). */
836
837	/** @} */
838
839
840	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
841	*
842	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
843	* translation block flags. The combined flag mask (subject to
844	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
845	*
846	* @{ */
847	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
848	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
849
850	/** Type: The block type mask. */
851	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
852	/** Type: Purly threaded recompiler (via tables). */
853	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
854	/** Type: Native recompilation. */
855	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
856
857	/** Set when we're starting the block in an "interrupt shadow".
858	* We don't need to distingish between the two types of this mask, thus the one.
859	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
860	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
861	/** Set when we're currently inhibiting NMIs
862	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
863	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
864
865	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
866	* we're close the limit before starting a TB, as determined by
867	* iemGetTbFlagsForCurrentPc(). */
868	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
869
870	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
871	*
872	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
873	* don't implement), because we don't currently generate any context
874	* specific code - that's all handled in CIMPL functions.
875	*
876	* For the threaded recompiler we don't generate any CPL specific code
877	* either, but the native recompiler does for memory access (saves getting
878	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
879	* Since most OSes will not share code between rings, this shouldn't
880	* have any real effect on TB/memory/recompiling load.
881	*/
882	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
883	/** @} */
884
885	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
886	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
887	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
888	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
889	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
890	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
891	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
892	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
893	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
894	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
895	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
896	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
897	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
898	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
899	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
900	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
901	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
902	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
903	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
904
905	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
906	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
907	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
908	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
909	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
910	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
911	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
912	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
913	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
914	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
915	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
916	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
917
918	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
919	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
920	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
921
922	/** Native instruction type for use with the native code generator.
923	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
924	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
925	typedef uint8_t IEMNATIVEINSTR;
926	#else
927	typedef uint32_t IEMNATIVEINSTR;
928	#endif
929	/** Pointer to a native instruction unit. */
930	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
931	/** Pointer to a const native instruction unit. */
932	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
933
934	/**
935	* A call for the threaded call table.
936	*/
937	typedef struct IEMTHRDEDCALLENTRY
938	{
939	/** The function to call (IEMTHREADEDFUNCS). */
940	uint16_t enmFunction;
941
942	/** Instruction number in the TB (for statistics). */
943	uint8_t idxInstr;
944	/** The opcode length. */
945	uint8_t cbOpcode;
946	/** Offset into IEMTB::pabOpcodes. */
947	uint16_t offOpcode;
948
949	/** TB lookup table index (7 bits) and large size (1 bits).
950	*
951	* The default size is 1 entry, but for indirect calls and returns we set the
952	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
953	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
954	* lookup isn't that slow compared to sequentially trying out 4 TBs.
955	*
956	* By default lookup table entry 0 for a TB is reserved as a fallback for
957	* calltable entries w/o explicit entreis, so this member will be non-zero if
958	* there is a lookup entry associated with this call.
959	*
960	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
961	*/
962	uint8_t uTbLookup;
963
964	/** Unused atm. */
965	uint8_t uUnused0;
966
967	/** Generic parameters. */
968	uint64_t auParams[3];
969	} IEMTHRDEDCALLENTRY;
970	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
971	/** Pointer to a threaded call entry. */
972	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
973	/** Pointer to a const threaded call entry. */
974	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
975
976	/** The number of TB lookup table entries for a large allocation
977	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
978	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
979	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
980	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
981	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
982	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
983	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
984	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
985	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
986
987	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
988	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
989
990	/**
991	* Native IEM TB 'function' typedef.
992	*
993	* This will throw/longjmp on occation.
994	*
995	* @note AMD64 doesn't have that many non-volatile registers and does sport
996	* 32-bit address displacments, so we don't need pCtx.
997	*
998	* On ARM64 pCtx allows us to directly address the whole register
999	* context without requiring a separate indexing register holding the
1000	* offset. This saves an instruction loading the offset for each guest
1001	* CPU context access, at the cost of a non-volatile register.
1002	* Fortunately, ARM64 has quite a lot more registers.
1003	*/
1004	typedef
1005	#ifdef RT_ARCH_AMD64
1006	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1007	#else
1008	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1009	#endif
1010	#if RT_CPLUSPLUS_PREREQ(201700)
1011	IEM_NOEXCEPT_MAY_LONGJMP
1012	#endif
1013	;
1014	/** Pointer to a native IEM TB entry point function.
1015	* This will throw/longjmp on occation. */
1016	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1017
1018
1019	/**
1020	* Translation block debug info entry type.
1021	*/
1022	typedef enum IEMTBDBGENTRYTYPE
1023	{
1024	kIemTbDbgEntryType_Invalid = 0,
1025	/** The entry is for marking a native code position.
1026	* Entries following this all apply to this position. */
1027	kIemTbDbgEntryType_NativeOffset,
1028	/** The entry is for a new guest instruction. */
1029	kIemTbDbgEntryType_GuestInstruction,
1030	/** Marks the start of a threaded call. */
1031	kIemTbDbgEntryType_ThreadedCall,
1032	/** Marks the location of a label. */
1033	kIemTbDbgEntryType_Label,
1034	/** Info about a host register shadowing a guest register. */
1035	kIemTbDbgEntryType_GuestRegShadowing,
1036	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1037	/** Info about a host SIMD register shadowing a guest SIMD register. */
1038	kIemTbDbgEntryType_GuestSimdRegShadowing,
1039	#endif
1040	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1041	/** Info about a delayed RIP update. */
1042	kIemTbDbgEntryType_DelayedPcUpdate,
1043	#endif
1044	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1045	/** Info about a shadowed guest register becoming dirty. */
1046	kIemTbDbgEntryType_GuestRegDirty,
1047	/** Info about register writeback/flush oepration. */
1048	kIemTbDbgEntryType_GuestRegWriteback,
1049	#endif
1050	kIemTbDbgEntryType_End
1051	} IEMTBDBGENTRYTYPE;
1052
1053	/**
1054	* Translation block debug info entry.
1055	*/
1056	typedef union IEMTBDBGENTRY
1057	{
1058	/** Plain 32-bit view. */
1059	uint32_t u;
1060
1061	/** Generic view for getting at the type field. */
1062	struct
1063	{
1064	/** IEMTBDBGENTRYTYPE */
1065	uint32_t uType : 4;
1066	uint32_t uTypeSpecific : 28;
1067	} Gen;
1068
1069	struct
1070	{
1071	/** kIemTbDbgEntryType_ThreadedCall1. */
1072	uint32_t uType : 4;
1073	/** Native code offset. */
1074	uint32_t offNative : 28;
1075	} NativeOffset;
1076
1077	struct
1078	{
1079	/** kIemTbDbgEntryType_GuestInstruction. */
1080	uint32_t uType : 4;
1081	uint32_t uUnused : 4;
1082	/** The IEM_F_XXX flags. */
1083	uint32_t fExec : 24;
1084	} GuestInstruction;
1085
1086	struct
1087	{
1088	/* kIemTbDbgEntryType_ThreadedCall. */
1089	uint32_t uType : 4;
1090	/** Set if the call was recompiled to native code, clear if just calling
1091	* threaded function. */
1092	uint32_t fRecompiled : 1;
1093	uint32_t uUnused : 11;
1094	/** The threaded call number (IEMTHREADEDFUNCS). */
1095	uint32_t enmCall : 16;
1096	} ThreadedCall;
1097
1098	struct
1099	{
1100	/* kIemTbDbgEntryType_Label. */
1101	uint32_t uType : 4;
1102	uint32_t uUnused : 4;
1103	/** The label type (IEMNATIVELABELTYPE). */
1104	uint32_t enmLabel : 8;
1105	/** The label data. */
1106	uint32_t uData : 16;
1107	} Label;
1108
1109	struct
1110	{
1111	/* kIemTbDbgEntryType_GuestRegShadowing. */
1112	uint32_t uType : 4;
1113	uint32_t uUnused : 4;
1114	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1115	uint32_t idxGstReg : 8;
1116	/** The host new register number, UINT8_MAX if dropped. */
1117	uint32_t idxHstReg : 8;
1118	/** The previous host register number, UINT8_MAX if new. */
1119	uint32_t idxHstRegPrev : 8;
1120	} GuestRegShadowing;
1121
1122	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1123	struct
1124	{
1125	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1126	uint32_t uType : 4;
1127	uint32_t uUnused : 4;
1128	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1129	uint32_t idxGstSimdReg : 8;
1130	/** The host new register number, UINT8_MAX if dropped. */
1131	uint32_t idxHstSimdReg : 8;
1132	/** The previous host register number, UINT8_MAX if new. */
1133	uint32_t idxHstSimdRegPrev : 8;
1134	} GuestSimdRegShadowing;
1135	#endif
1136
1137	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1138	struct
1139	{
1140	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1141	uint32_t uType : 4;
1142	/* The instruction offset added to the program counter. */
1143	uint32_t offPc : 14;
1144	/** Number of instructions skipped. */
1145	uint32_t cInstrSkipped : 14;
1146	} DelayedPcUpdate;
1147	#endif
1148
1149	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1150	struct
1151	{
1152	/* kIemTbDbgEntryType_GuestRegDirty. */
1153	uint32_t uType : 4;
1154	uint32_t uUnused : 11;
1155	/** Flag whether this is about a SIMD (true) or general (false) register. */
1156	uint32_t fSimdReg : 1;
1157	/** The guest register index being marked as dirty. */
1158	uint32_t idxGstReg : 8;
1159	/** The host register number this register is shadowed in .*/
1160	uint32_t idxHstReg : 8;
1161	} GuestRegDirty;
1162
1163	struct
1164	{
1165	/* kIemTbDbgEntryType_GuestRegWriteback. */
1166	uint32_t uType : 4;
1167	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1168	uint32_t fSimdReg : 1;
1169	/** The mask shift. */
1170	uint32_t cShift : 2;
1171	/** The guest register mask being written back. */
1172	uint32_t fGstReg : 25;
1173	} GuestRegWriteback;
1174	#endif
1175
1176	} IEMTBDBGENTRY;
1177	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1178	/** Pointer to a debug info entry. */
1179	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1180	/** Pointer to a const debug info entry. */
1181	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1182
1183	/**
1184	* Translation block debug info.
1185	*/
1186	typedef struct IEMTBDBG
1187	{
1188	/** Number of entries in aEntries. */
1189	uint32_t cEntries;
1190	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1191	uint32_t offNativeLast;
1192	/** Debug info entries. */
1193	RT_FLEXIBLE_ARRAY_EXTENSION
1194	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1195	} IEMTBDBG;
1196	/** Pointer to TB debug info. */
1197	typedef IEMTBDBG *PIEMTBDBG;
1198	/** Pointer to const TB debug info. */
1199	typedef IEMTBDBG const *PCIEMTBDBG;
1200
1201
1202	/**
1203	* Translation block.
1204	*
1205	* The current plan is to just keep TBs and associated lookup hash table private
1206	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1207	* avoids using expensive atomic primitives for updating lists and stuff.
1208	*/
1209	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1210	typedef struct IEMTB
1211	{
1212	/** Next block with the same hash table entry. */
1213	struct IEMTB *pNext;
1214	/** Usage counter. */
1215	uint32_t cUsed;
1216	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1217	uint32_t msLastUsed;
1218
1219	/** @name What uniquely identifies the block.
1220	* @{ */
1221	RTGCPHYS GCPhysPc;
1222	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1223	uint32_t fFlags;
1224	union
1225	{
1226	struct
1227	{
1228	/*< Relevant CS X86DESCATTR_XXX bits. /
1229	uint16_t fAttr;
1230	} x86;
1231	};
1232	/** @} */
1233
1234	/** Number of opcode ranges. */
1235	uint8_t cRanges;
1236	/** Statistics: Number of instructions in the block. */
1237	uint8_t cInstructions;
1238
1239	/** Type specific info. */
1240	union
1241	{
1242	struct
1243	{
1244	/** The call sequence table. */
1245	PIEMTHRDEDCALLENTRY paCalls;
1246	/** Number of calls in paCalls. */
1247	uint16_t cCalls;
1248	/** Number of calls allocated. */
1249	uint16_t cAllocated;
1250	} Thrd;
1251	struct
1252	{
1253	/** The native instructions (PFNIEMTBNATIVE). */
1254	PIEMNATIVEINSTR paInstructions;
1255	/** Number of instructions pointed to by paInstructions. */
1256	uint32_t cInstructions;
1257	} Native;
1258	/** Generic view for zeroing when freeing. */
1259	struct
1260	{
1261	uintptr_t uPtr;
1262	uint32_t uData;
1263	} Gen;
1264	};
1265
1266	/** The allocation chunk this TB belongs to. */
1267	uint8_t idxAllocChunk;
1268	/** The number of entries in the lookup table.
1269	* Because we're out of space, the TB lookup table is located before the
1270	* opcodes pointed to by pabOpcodes. */
1271	uint8_t cTbLookupEntries;
1272
1273	/** Number of bytes of opcodes stored in pabOpcodes.
1274	* @todo this field isn't really needed, aRanges keeps the actual info. */
1275	uint16_t cbOpcodes;
1276	/** Pointer to the opcode bytes this block was recompiled from.
1277	* This also points to the TB lookup table, which starts cTbLookupEntries
1278	* entries before the opcodes (we don't have room atm for another point). */
1279	uint8_t *pabOpcodes;
1280
1281	/** Debug info if enabled.
1282	* This is only generated by the native recompiler. */
1283	PIEMTBDBG pDbgInfo;
1284
1285	/* --- 64 byte cache line end --- */
1286
1287	/** Opcode ranges.
1288	*
1289	* The opcode checkers and maybe TLB loading functions will use this to figure
1290	* out what to do. The parameter will specify an entry and the opcode offset to
1291	* start at and the minimum number of bytes to verify (instruction length).
1292	*
1293	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1294	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1295	* code TLB (must have a valid entry for that address) and scan the ranges to
1296	* locate the corresponding opcodes. Probably.
1297	*/
1298	struct IEMTBOPCODERANGE
1299	{
1300	/** Offset within pabOpcodes. */
1301	uint16_t offOpcodes;
1302	/** Number of bytes. */
1303	uint16_t cbOpcodes;
1304	/** The page offset. */
1305	RT_GCC_EXTENSION
1306	uint16_t offPhysPage : 12;
1307	/** Unused bits. */
1308	RT_GCC_EXTENSION
1309	uint16_t u2Unused : 2;
1310	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1311	RT_GCC_EXTENSION
1312	uint16_t idxPhysPage : 2;
1313	} aRanges[8];
1314
1315	/** Physical pages that this TB covers.
1316	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1317	RTGCPHYS aGCPhysPages[2];
1318	} IEMTB;
1319	#pragma pack()
1320	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1321	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1322	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1323	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1324	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1325	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1326	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1327	#if 1
1328	AssertCompileSize(IEMTB, 128);
1329	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1330	#else
1331	AssertCompileSize(IEMTB, 168);
1332	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1333	#endif
1334
1335	/** Pointer to a translation block. */
1336	typedef IEMTB *PIEMTB;
1337	/** Pointer to a const translation block. */
1338	typedef IEMTB const *PCIEMTB;
1339
1340	/** Gets address of the given TB lookup table entry. */
1341	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1342	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1343
1344	/**
1345	* Gets the physical address for a TB opcode range.
1346	*/
1347	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1348	{
1349	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1350	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1351	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1352	if (idxPage == 0)
1353	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1354	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1355	return pTb->aGCPhysPages[idxPage - 1];
1356	}
1357
1358
1359	/**
1360	* A chunk of memory in the TB allocator.
1361	*/
1362	typedef struct IEMTBCHUNK
1363	{
1364	/** Pointer to the translation blocks in this chunk. */
1365	PIEMTB paTbs;
1366	#ifdef IN_RING0
1367	/** Allocation handle. */
1368	RTR0MEMOBJ hMemObj;
1369	#endif
1370	} IEMTBCHUNK;
1371
1372	/**
1373	* A per-CPU translation block allocator.
1374	*
1375	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1376	* the length of the collision list, and of course also for cache line alignment
1377	* reasons, the TBs must be allocated with at least 64-byte alignment.
1378	* Memory is there therefore allocated using one of the page aligned allocators.
1379	*
1380	*
1381	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1382	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1383	* that enables us to quickly calculate the allocation bitmap position when
1384	* freeing the translation block.
1385	*/
1386	typedef struct IEMTBALLOCATOR
1387	{
1388	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1389	uint32_t uMagic;
1390
1391	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1392	/** Mask corresponding to cTbsPerChunk - 1. */
1393	uint32_t fChunkMask;
1394	/** Shift count corresponding to cTbsPerChunk. */
1395	uint8_t cChunkShift;
1396	#else
1397	uint32_t uUnused;
1398	uint8_t bUnused;
1399	#endif
1400	/** Number of chunks we're allowed to allocate. */
1401	uint8_t cMaxChunks;
1402	/** Number of chunks currently populated. */
1403	uint16_t cAllocatedChunks;
1404	/** Number of translation blocks per chunk. */
1405	uint32_t cTbsPerChunk;
1406	/** Chunk size. */
1407	uint32_t cbPerChunk;
1408
1409	/** The maximum number of TBs. */
1410	uint32_t cMaxTbs;
1411	/** Total number of TBs in the populated chunks.
1412	* (cAllocatedChunks * cTbsPerChunk) */
1413	uint32_t cTotalTbs;
1414	/** The current number of TBs in use.
1415	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1416	uint32_t cInUseTbs;
1417	/** Statistics: Number of the cInUseTbs that are native ones. */
1418	uint32_t cNativeTbs;
1419	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1420	uint32_t cThreadedTbs;
1421
1422	/** Where to start pruning TBs from when we're out.
1423	* See iemTbAllocatorAllocSlow for details. */
1424	uint32_t iPruneFrom;
1425	/** Hint about which bit to start scanning the bitmap from. */
1426	uint32_t iStartHint;
1427	/** Where to start pruning native TBs from when we're out of executable memory.
1428	* See iemTbAllocatorFreeupNativeSpace for details. */
1429	uint32_t iPruneNativeFrom;
1430	uint32_t uPadding;
1431
1432	/** Statistics: Number of TB allocation calls. */
1433	STAMCOUNTER StatAllocs;
1434	/** Statistics: Number of TB free calls. */
1435	STAMCOUNTER StatFrees;
1436	/** Statistics: Time spend pruning. */
1437	STAMPROFILE StatPrune;
1438	/** Statistics: Time spend pruning native TBs. */
1439	STAMPROFILE StatPruneNative;
1440
1441	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1442	PIEMTB pDelayedFreeHead;
1443
1444	/** Allocation chunks. */
1445	IEMTBCHUNK aChunks[256];
1446
1447	/** Allocation bitmap for all possible chunk chunks. */
1448	RT_FLEXIBLE_ARRAY_EXTENSION
1449	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1450	} IEMTBALLOCATOR;
1451	/** Pointer to a TB allocator. */
1452	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1453
1454	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1455	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1456
1457
1458	/**
1459	* A per-CPU translation block cache (hash table).
1460	*
1461	* The hash table is allocated once during IEM initialization and size double
1462	* the max TB count, rounded up to the nearest power of two (so we can use and
1463	* AND mask rather than a rest division when hashing).
1464	*/
1465	typedef struct IEMTBCACHE
1466	{
1467	/** Magic value (IEMTBCACHE_MAGIC). */
1468	uint32_t uMagic;
1469	/** Size of the hash table. This is a power of two. */
1470	uint32_t cHash;
1471	/** The mask corresponding to cHash. */
1472	uint32_t uHashMask;
1473	uint32_t uPadding;
1474
1475	/** @name Statistics
1476	* @{ */
1477	/** Number of collisions ever. */
1478	STAMCOUNTER cCollisions;
1479
1480	/** Statistics: Number of TB lookup misses. */
1481	STAMCOUNTER cLookupMisses;
1482	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1483	STAMCOUNTER cLookupHits;
1484	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1485	STAMCOUNTER cLookupHitsViaTbLookupTable;
1486	STAMCOUNTER auPadding2[2];
1487	/** Statistics: Collision list length pruning. */
1488	STAMPROFILE StatPrune;
1489	/** @} */
1490
1491	/** The hash table itself.
1492	* @note The lower 6 bits of the pointer is used for keeping the collision
1493	* list length, so we can take action when it grows too long.
1494	* This works because TBs are allocated using a 64 byte (or
1495	* higher) alignment from page aligned chunks of memory, so the lower
1496	* 6 bits of the address will always be zero.
1497	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1498	*/
1499	RT_FLEXIBLE_ARRAY_EXTENSION
1500	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1501	} IEMTBCACHE;
1502	/** Pointer to a per-CPU translation block cahce. */
1503	typedef IEMTBCACHE *PIEMTBCACHE;
1504
1505	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1506	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1507
1508	/** The collision count mask for IEMTBCACHE::apHash entries. */
1509	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1510	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1511	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1512	/** Combine a TB pointer and a collision list length into a value for an
1513	* IEMTBCACHE::apHash entry. */
1514	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1515	/** Combine a TB pointer and a collision list length into a value for an
1516	* IEMTBCACHE::apHash entry. */
1517	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1518	/** Combine a TB pointer and a collision list length into a value for an
1519	* IEMTBCACHE::apHash entry. */
1520	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1521
1522	/**
1523	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1524	*/
1525	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1526	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1527
1528	/**
1529	* Calculates the hash table slot for a TB from physical PC address and TB
1530	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1531	*/
1532	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1533	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1534
1535
1536	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1537	*
1538	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1539	*
1540	* @{ */
1541	/** Value if no branching happened recently. */
1542	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1543	/** Flag set if direct branch, clear if absolute or indirect. */
1544	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1545	/** Flag set if indirect branch, clear if direct or relative. */
1546	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1547	/** Flag set if relative branch, clear if absolute or indirect. */
1548	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1549	/** Flag set if conditional branch, clear if unconditional. */
1550	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1551	/** Flag set if it's a far branch. */
1552	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1553	/** Flag set if the stack pointer is modified. */
1554	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1555	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1556	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1557	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1558	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1559	/** @} */
1560
1561
1562	/**
1563	* The per-CPU IEM state.
1564	*/
1565	typedef struct IEMCPU
1566	{
1567	/** Info status code that needs to be propagated to the IEM caller.
1568	* This cannot be passed internally, as it would complicate all success
1569	* checks within the interpreter making the code larger and almost impossible
1570	* to get right. Instead, we'll store status codes to pass on here. Each
1571	* source of these codes will perform appropriate sanity checks. */
1572	int32_t rcPassUp; /* 0x00 */
1573	/** Execution flag, IEM_F_XXX. */
1574	uint32_t fExec; /* 0x04 */
1575
1576	/** @name Decoder state.
1577	* @{ */
1578	#ifdef IEM_WITH_CODE_TLB
1579	/** The offset of the next instruction byte. */
1580	uint32_t offInstrNextByte; /* 0x08 */
1581	/** The number of bytes available at pbInstrBuf for the current instruction.
1582	* This takes the max opcode length into account so that doesn't need to be
1583	* checked separately. */
1584	uint32_t cbInstrBuf; /* 0x0c */
1585	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1586	* This can be NULL if the page isn't mappable for some reason, in which
1587	* case we'll do fallback stuff.
1588	*
1589	* If we're executing an instruction from a user specified buffer,
1590	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1591	* aligned pointer but pointer to the user data.
1592	*
1593	* For instructions crossing pages, this will start on the first page and be
1594	* advanced to the next page by the time we've decoded the instruction. This
1595	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1596	*/
1597	uint8_t const pbInstrBuf; / 0x10 */
1598	# if ARCH_BITS == 32
1599	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1600	# endif
1601	/** The program counter corresponding to pbInstrBuf.
1602	* This is set to a non-canonical address when we need to invalidate it. */
1603	uint64_t uInstrBufPc; /* 0x18 */
1604	/** The guest physical address corresponding to pbInstrBuf. */
1605	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1606	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1607	* This takes the CS segment limit into account.
1608	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1609	uint16_t cbInstrBufTotal; /* 0x28 */
1610	/** Offset into pbInstrBuf of the first byte of the current instruction.
1611	* Can be negative to efficiently handle cross page instructions. */
1612	int16_t offCurInstrStart; /* 0x2a */
1613
1614	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1615	/** The prefix mask (IEM_OP_PRF_XXX). */
1616	uint32_t fPrefixes; /* 0x2c */
1617	/** The extra REX ModR/M register field bit (REX.R << 3). */
1618	uint8_t uRexReg; /* 0x30 */
1619	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1620	* (REX.B << 3). */
1621	uint8_t uRexB; /* 0x31 */
1622	/** The extra REX SIB index field bit (REX.X << 3). */
1623	uint8_t uRexIndex; /* 0x32 */
1624
1625	/** The effective segment register (X86_SREG_XXX). */
1626	uint8_t iEffSeg; /* 0x33 */
1627
1628	/** The offset of the ModR/M byte relative to the start of the instruction. */
1629	uint8_t offModRm; /* 0x34 */
1630
1631	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1632	/** The current offset into abOpcode. */
1633	uint8_t offOpcode; /* 0x35 */
1634	# else
1635	uint8_t bUnused; /* 0x35 */
1636	# endif
1637	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1638	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1639	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1640
1641	#else /* !IEM_WITH_CODE_TLB */
1642	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1643	/** The size of what has currently been fetched into abOpcode. */
1644	uint8_t cbOpcode; /* 0x08 */
1645	/** The current offset into abOpcode. */
1646	uint8_t offOpcode; /* 0x09 */
1647	/** The offset of the ModR/M byte relative to the start of the instruction. */
1648	uint8_t offModRm; /* 0x0a */
1649
1650	/** The effective segment register (X86_SREG_XXX). */
1651	uint8_t iEffSeg; /* 0x0b */
1652
1653	/** The prefix mask (IEM_OP_PRF_XXX). */
1654	uint32_t fPrefixes; /* 0x0c */
1655	/** The extra REX ModR/M register field bit (REX.R << 3). */
1656	uint8_t uRexReg; /* 0x10 */
1657	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1658	* (REX.B << 3). */
1659	uint8_t uRexB; /* 0x11 */
1660	/** The extra REX SIB index field bit (REX.X << 3). */
1661	uint8_t uRexIndex; /* 0x12 */
1662
1663	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1664	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1665	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1666	#endif /* !IEM_WITH_CODE_TLB */
1667
1668	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1669	/** The effective operand mode. */
1670	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1671	/** The default addressing mode. */
1672	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1673	/** The effective addressing mode. */
1674	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1675	/** The default operand mode. */
1676	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1677
1678	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1679	uint8_t idxPrefix; /* 0x3a, 0x17 */
1680	/** 3rd VEX/EVEX/XOP register.
1681	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1682	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1683	/** The VEX/EVEX/XOP length field. */
1684	uint8_t uVexLength; /* 0x3c, 0x19 */
1685	/** Additional EVEX stuff. */
1686	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1687
1688	# ifndef IEM_WITH_CODE_TLB
1689	/** Explicit alignment padding. */
1690	uint8_t abAlignment2a[1]; /* 0x1b */
1691	# endif
1692	/** The FPU opcode (FOP). */
1693	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1694	# ifndef IEM_WITH_CODE_TLB
1695	/** Explicit alignment padding. */
1696	uint8_t abAlignment2b[2]; /* 0x1e */
1697	# endif
1698
1699	/** The opcode bytes. */
1700	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1701	/** Explicit alignment padding. */
1702	# ifdef IEM_WITH_CODE_TLB
1703	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1704	# else
1705	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1706	# endif
1707
1708	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1709	# ifdef IEM_WITH_CODE_TLB
1710	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1711	# else
1712	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1713	# endif
1714	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1715	/** @} */
1716
1717
1718	/** The number of active guest memory mappings. */
1719	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1720
1721	/** Records for tracking guest memory mappings. */
1722	struct
1723	{
1724	/** The address of the mapped bytes. */
1725	R3R0PTRTYPE(void *) pv;
1726	/** The access flags (IEM_ACCESS_XXX).
1727	* IEM_ACCESS_INVALID if the entry is unused. */
1728	uint32_t fAccess;
1729	#if HC_ARCH_BITS == 64
1730	uint32_t u32Alignment4; /*< Alignment padding. /
1731	#endif
1732	} aMemMappings[3]; /* 0x50 LB 0x30 */
1733
1734	/** Locking records for the mapped memory. */
1735	union
1736	{
1737	PGMPAGEMAPLOCK Lock;
1738	uint64_t au64Padding[2];
1739	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1740
1741	/** Bounce buffer info.
1742	* This runs in parallel to aMemMappings. */
1743	struct
1744	{
1745	/** The physical address of the first byte. */
1746	RTGCPHYS GCPhysFirst;
1747	/** The physical address of the second page. */
1748	RTGCPHYS GCPhysSecond;
1749	/** The number of bytes in the first page. */
1750	uint16_t cbFirst;
1751	/** The number of bytes in the second page. */
1752	uint16_t cbSecond;
1753	/** Whether it's unassigned memory. */
1754	bool fUnassigned;
1755	/** Explicit alignment padding. */
1756	bool afAlignment5[3];
1757	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1758
1759	/** The flags of the current exception / interrupt. */
1760	uint32_t fCurXcpt; /* 0xf8 */
1761	/** The current exception / interrupt. */
1762	uint8_t uCurXcpt; /* 0xfc */
1763	/** Exception / interrupt recursion depth. */
1764	int8_t cXcptRecursions; /* 0xfb */
1765
1766	/** The next unused mapping index.
1767	* @todo try find room for this up with cActiveMappings. */
1768	uint8_t iNextMapping; /* 0xfd */
1769	uint8_t abAlignment7[1];
1770
1771	/** Bounce buffer storage.
1772	* This runs in parallel to aMemMappings and aMemBbMappings. */
1773	struct
1774	{
1775	uint8_t ab[512];
1776	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1777
1778
1779	/** Pointer set jump buffer - ring-3 context. */
1780	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1781	/** Pointer set jump buffer - ring-0 context. */
1782	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1783
1784	/** @todo Should move this near @a fCurXcpt later. */
1785	/** The CR2 for the current exception / interrupt. */
1786	uint64_t uCurXcptCr2;
1787	/** The error code for the current exception / interrupt. */
1788	uint32_t uCurXcptErr;
1789
1790	/** @name Statistics
1791	* @{ */
1792	/** The number of instructions we've executed. */
1793	uint32_t cInstructions;
1794	/** The number of potential exits. */
1795	uint32_t cPotentialExits;
1796	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1797	* This may contain uncommitted writes. */
1798	uint32_t cbWritten;
1799	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1800	uint32_t cRetInstrNotImplemented;
1801	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1802	uint32_t cRetAspectNotImplemented;
1803	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1804	uint32_t cRetInfStatuses;
1805	/** Counts other error statuses returned. */
1806	uint32_t cRetErrStatuses;
1807	/** Number of times rcPassUp has been used. */
1808	uint32_t cRetPassUpStatus;
1809	/** Number of times RZ left with instruction commit pending for ring-3. */
1810	uint32_t cPendingCommit;
1811	/** Number of misaligned (host sense) atomic instruction accesses. */
1812	uint32_t cMisalignedAtomics;
1813	/** Number of long jumps. */
1814	uint32_t cLongJumps;
1815	/** @} */
1816
1817	/** @name Target CPU information.
1818	* @{ */
1819	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1820	/** The target CPU. */
1821	uint8_t uTargetCpu;
1822	#else
1823	uint8_t bTargetCpuPadding;
1824	#endif
1825	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1826	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1827	* native host support and the 2nd for when there is.
1828	*
1829	* The two values are typically indexed by a g_CpumHostFeatures bit.
1830	*
1831	* This is for instance used for the BSF & BSR instructions where AMD and
1832	* Intel CPUs produce different EFLAGS. */
1833	uint8_t aidxTargetCpuEflFlavour[2];
1834
1835	/** The CPU vendor. */
1836	CPUMCPUVENDOR enmCpuVendor;
1837	/** @} */
1838
1839	/** @name Host CPU information.
1840	* @{ */
1841	/** The CPU vendor. */
1842	CPUMCPUVENDOR enmHostCpuVendor;
1843	/** @} */
1844
1845	/** Counts RDMSR \#GP(0) LogRel(). */
1846	uint8_t cLogRelRdMsr;
1847	/** Counts WRMSR \#GP(0) LogRel(). */
1848	uint8_t cLogRelWrMsr;
1849	/** Alignment padding. */
1850	uint8_t abAlignment9[42];
1851
1852	/** @name Recompilation
1853	* @{ */
1854	/** Pointer to the current translation block.
1855	* This can either be one being executed or one being compiled. */
1856	R3PTRTYPE(PIEMTB) pCurTbR3;
1857	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1858	/** Frame pointer for the last native TB to execute. */
1859	R3PTRTYPE(void *) pvTbFramePointerR3;
1860	#else
1861	R3PTRTYPE(void *) pvUnusedR3;
1862	#endif
1863	/** Fixed TB used for threaded recompilation.
1864	* This is allocated once with maxed-out sizes and re-used afterwards. */
1865	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1866	/** Pointer to the ring-3 TB cache for this EMT. */
1867	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1868	/** Pointer to the ring-3 TB lookup entry.
1869	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
1870	* entry, thus it can always safely be used w/o NULL checking. */
1871	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
1872	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1873	* The TBs are based on physical addresses, so this is needed to correleated
1874	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1875	uint64_t uCurTbStartPc;
1876	/** Number of threaded TBs executed. */
1877	uint64_t cTbExecThreaded;
1878	/** Number of native TBs executed. */
1879	uint64_t cTbExecNative;
1880	/** Whether we need to check the opcode bytes for the current instruction.
1881	* This is set by a previous instruction if it modified memory or similar. */
1882	bool fTbCheckOpcodes;
1883	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1884	uint8_t fTbBranched;
1885	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1886	bool fTbCrossedPage;
1887	/** Whether to end the current TB. */
1888	bool fEndTb;
1889	/** Number of instructions before we need emit an IRQ check call again.
1890	* This helps making sure we don't execute too long w/o checking for
1891	* interrupts and immediately following instructions that may enable
1892	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1893	* required to make sure we check following the next instruction as well, see
1894	* fTbCurInstrIsSti. */
1895	uint8_t cInstrTillIrqCheck;
1896	/** Indicates that the current instruction is an STI. This is set by the
1897	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1898	bool fTbCurInstrIsSti;
1899	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1900	uint16_t cbOpcodesAllocated;
1901	/** The current instruction number in a native TB.
1902	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1903	* and will be picked up by the TB execution loop. Only used when
1904	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1905	uint8_t idxTbCurInstr;
1906	/** Spaced reserved for recompiler data / alignment. */
1907	bool afRecompilerStuff1[3];
1908	/** The virtual sync time at the last timer poll call. */
1909	uint32_t msRecompilerPollNow;
1910	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
1911	uint32_t uTbNativeRecompileAtUsedCount;
1912	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1913	uint32_t fTbCurInstr;
1914	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1915	uint32_t fTbPrevInstr;
1916	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
1917	* currently not up to date in EFLAGS. */
1918	uint32_t fSkippingEFlags;
1919	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1920	RTGCPHYS GCPhysInstrBufPrev;
1921	/** Pointer to the ring-3 TB allocator for this EMT. */
1922	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1923	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1924	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1925	/** Pointer to the native recompiler state for ring-3. */
1926	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1927	/** Dummy entry for ppTbLookupEntryR3. */
1928	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
1929
1930	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
1931	STAMCOUNTER StatTbThreadedExecBreaks;
1932	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1933	STAMCOUNTER StatCheckIrqBreaks;
1934	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1935	STAMCOUNTER StatCheckModeBreaks;
1936	/** Threaded TB statistics: Times execution break on call with lookup entries. */
1937	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
1938	/** Threaded TB statistics: Times execution break on call without lookup entries. */
1939	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
1940	/** Statistics: Times a post jump target check missed and had to find new TB. */
1941	STAMCOUNTER StatCheckBranchMisses;
1942	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1943	STAMCOUNTER StatCheckNeedCsLimChecking;
1944	/** Statistics: Times a loop was detected within a TB.. */
1945	STAMCOUNTER StatTbLoopInTbDetected;
1946	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
1947	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
1948	/** Native TB statistics: Number of fully recompiled TBs. */
1949	STAMCOUNTER StatNativeFullyRecompiledTbs;
1950	/** TB statistics: Number of instructions per TB. */
1951	STAMPROFILE StatTbInstr;
1952	/** TB statistics: Number of TB lookup table entries per TB. */
1953	STAMPROFILE StatTbLookupEntries;
1954	/** Threaded TB statistics: Number of calls per TB. */
1955	STAMPROFILE StatTbThreadedCalls;
1956	/** Native TB statistics: Native code size per TB. */
1957	STAMPROFILE StatTbNativeCode;
1958	/** Native TB statistics: Profiling native recompilation. */
1959	STAMPROFILE StatNativeRecompilation;
1960	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
1961	STAMPROFILE StatNativeCallsRecompiled;
1962	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
1963	STAMPROFILE StatNativeCallsThreaded;
1964	/** Native recompiled execution: TLB hits for data fetches. */
1965	STAMCOUNTER StatNativeTlbHitsForFetch;
1966	/** Native recompiled execution: TLB hits for data stores. */
1967	STAMCOUNTER StatNativeTlbHitsForStore;
1968	/** Native recompiled execution: TLB hits for stack accesses. */
1969	STAMCOUNTER StatNativeTlbHitsForStack;
1970	/** Native recompiled execution: TLB hits for mapped accesses. */
1971	STAMCOUNTER StatNativeTlbHitsForMapped;
1972	/** Native recompiled execution: Code TLB misses for new page. */
1973	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
1974	/** Native recompiled execution: Code TLB hits for new page. */
1975	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
1976	/** Native recompiled execution: Code TLB misses for new page with offset. */
1977	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
1978	/** Native recompiled execution: Code TLB hits for new page with offset. */
1979	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
1980
1981	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
1982	STAMCOUNTER StatNativeRegFindFree;
1983	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
1984	* to free a variable. */
1985	STAMCOUNTER StatNativeRegFindFreeVar;
1986	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
1987	* not need to free any variables. */
1988	STAMCOUNTER StatNativeRegFindFreeNoVar;
1989	/** Native recompiler: Liveness info freed shadowed guest registers in
1990	* iemNativeRegAllocFindFree. */
1991	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
1992	/** Native recompiler: Liveness info helped with the allocation in
1993	* iemNativeRegAllocFindFree. */
1994	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
1995
1996	/** Native recompiler: Number of times status flags calc has been skipped. */
1997	STAMCOUNTER StatNativeEflSkippedArithmetic;
1998	/** Native recompiler: Number of times status flags calc has been skipped. */
1999	STAMCOUNTER StatNativeEflSkippedLogical;
2000
2001	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2002	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2003	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2004	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2005	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2006	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2007	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2008	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2009	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2010	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2011	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2012	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2013	/** Native recompiler: Number of required EFLAGS.CF updates. */
2014	STAMCOUNTER StatNativeLivenessEflCfRequired;
2015	/** Native recompiler: Number of required EFLAGS.PF updates. */
2016	STAMCOUNTER StatNativeLivenessEflPfRequired;
2017	/** Native recompiler: Number of required EFLAGS.AF updates. */
2018	STAMCOUNTER StatNativeLivenessEflAfRequired;
2019	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2020	STAMCOUNTER StatNativeLivenessEflZfRequired;
2021	/** Native recompiler: Number of required EFLAGS.SF updates. */
2022	STAMCOUNTER StatNativeLivenessEflSfRequired;
2023	/** Native recompiler: Number of required EFLAGS.OF updates. */
2024	STAMCOUNTER StatNativeLivenessEflOfRequired;
2025	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2026	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2027	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2028	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2029	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2030	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2031	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2032	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2033	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2034	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2035	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2036	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2037
2038	/** Native recompiler: Number of potential PC updates in total. */
2039	STAMCOUNTER StatNativePcUpdateTotal;
2040	/** Native recompiler: Number of PC updates which could be delayed. */
2041	STAMCOUNTER StatNativePcUpdateDelayed;
2042
2043	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2044	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2045	STAMCOUNTER StatNativeSimdRegFindFree;
2046	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2047	* to free a variable. */
2048	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2049	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2050	* not need to free any variables. */
2051	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2052	/** Native recompiler: Liveness info freed shadowed guest registers in
2053	* iemNativeSimdRegAllocFindFree. */
2054	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2055	/** Native recompiler: Liveness info helped with the allocation in
2056	* iemNativeSimdRegAllocFindFree. */
2057	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2058
2059	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2060	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2061	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2062	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2063	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2064	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2065	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2066	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2067
2068	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2069	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2070	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2071	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2072	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2073	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2074	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2075	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2076	//#endif
2077
2078	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2079	* Not availabe in release builds. */
2080	STAMCOUNTER StatNativeTbFinished;
2081	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2082	STAMCOUNTER StatNativeTbExitReturnBreak;
2083	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2084	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2085	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2086	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2087	/** Native recompiler: The TB finished executing with other non-zero status. */
2088	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2089	/** Native recompiler: The TB finished executing via throw / long jump. */
2090	STAMCOUNTER StatNativeTbExitLongJump;
2091	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2092	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2093	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2094	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2095	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2096	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2097	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2098	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2099	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2100	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2101	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2102	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2103
2104	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2105	STAMCOUNTER StatNativeTbExitRaiseDe;
2106	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2107	STAMCOUNTER StatNativeTbExitRaiseUd;
2108	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2109	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2110	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2111	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2112	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2113	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2114	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2115	STAMCOUNTER StatNativeTbExitRaiseNm;
2116	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2117	STAMCOUNTER StatNativeTbExitRaiseGp0;
2118	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2119	STAMCOUNTER StatNativeTbExitRaiseMf;
2120	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2121	STAMCOUNTER StatNativeTbExitRaiseXf;
2122	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2123	STAMCOUNTER StatNativeTbExitObsoleteTb;
2124
2125	/** Native recompiler: Failure situations with direct linking scenario \#1.
2126	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2127	* @{ */
2128	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2129	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2130	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2131	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2132	/** @} */
2133
2134	/** Native recompiler: Failure situations with direct linking scenario \#2.
2135	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2136	* @{ */
2137	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2138	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2139	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2140	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2141	/** @} */
2142
2143	uint64_t au64Padding[5];
2144	/** @} */
2145
2146	/** Data TLB.
2147	* @remarks Must be 64-byte aligned. */
2148	IEMTLB DataTlb;
2149	/** Instruction TLB.
2150	* @remarks Must be 64-byte aligned. */
2151	IEMTLB CodeTlb;
2152
2153	/** Exception statistics. */
2154	STAMCOUNTER aStatXcpts[32];
2155	/** Interrupt statistics. */
2156	uint32_t aStatInts[256];
2157
2158	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
2159	/** Instruction statistics for ring-0/raw-mode. */
2160	IEMINSTRSTATS StatsRZ;
2161	/** Instruction statistics for ring-3. */
2162	IEMINSTRSTATS StatsR3;
2163	# ifdef VBOX_WITH_IEM_RECOMPILER
2164	/** Statistics per threaded function call.
2165	* Updated by both the threaded and native recompilers. */
2166	uint32_t acThreadedFuncStats[0x6000 /24576/];
2167	# endif
2168	#endif
2169	} IEMCPU;
2170	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2171	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2172	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2173	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2174	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2175	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2176
2177	/** Pointer to the per-CPU IEM state. */
2178	typedef IEMCPU *PIEMCPU;
2179	/** Pointer to the const per-CPU IEM state. */
2180	typedef IEMCPU const *PCIEMCPU;
2181
2182
2183	/** @def IEM_GET_CTX
2184	* Gets the guest CPU context for the calling EMT.
2185	* @returns PCPUMCTX
2186	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2187	*/
2188	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2189
2190	/** @def IEM_CTX_ASSERT
2191	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2192	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2193	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2194	*/
2195	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2196	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2197	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2198	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2199
2200	/** @def IEM_CTX_IMPORT_RET
2201	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2202	*
2203	* Will call the keep to import the bits as needed.
2204	*
2205	* Returns on import failure.
2206	*
2207	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2208	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2209	*/
2210	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2211	do { \
2212	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2213	{ /* likely */ } \
2214	else \
2215	{ \
2216	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2217	AssertRCReturn(rcCtxImport, rcCtxImport); \
2218	} \
2219	} while (0)
2220
2221	/** @def IEM_CTX_IMPORT_NORET
2222	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2223	*
2224	* Will call the keep to import the bits as needed.
2225	*
2226	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2227	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2228	*/
2229	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2230	do { \
2231	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2232	{ /* likely */ } \
2233	else \
2234	{ \
2235	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2236	AssertLogRelRC(rcCtxImport); \
2237	} \
2238	} while (0)
2239
2240	/** @def IEM_CTX_IMPORT_JMP
2241	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2242	*
2243	* Will call the keep to import the bits as needed.
2244	*
2245	* Jumps on import failure.
2246	*
2247	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2248	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2249	*/
2250	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2251	do { \
2252	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2253	{ /* likely */ } \
2254	else \
2255	{ \
2256	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2257	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2258	} \
2259	} while (0)
2260
2261
2262
2263	/** @def IEM_GET_TARGET_CPU
2264	* Gets the current IEMTARGETCPU value.
2265	* @returns IEMTARGETCPU value.
2266	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2267	*/
2268	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2269	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2270	#else
2271	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2272	#endif
2273
2274	/** @def IEM_GET_INSTR_LEN
2275	* Gets the instruction length. */
2276	#ifdef IEM_WITH_CODE_TLB
2277	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2278	#else
2279	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2280	#endif
2281
2282	/** @def IEM_TRY_SETJMP
2283	* Wrapper around setjmp / try, hiding all the ugly differences.
2284	*
2285	* @note Use with extreme care as this is a fragile macro.
2286	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2287	* @param a_rcTarget The variable that should receive the status code in case
2288	* of a longjmp/throw.
2289	*/
2290	/** @def IEM_TRY_SETJMP_AGAIN
2291	* For when setjmp / try is used again in the same variable scope as a previous
2292	* IEM_TRY_SETJMP invocation.
2293	*/
2294	/** @def IEM_CATCH_LONGJMP_BEGIN
2295	* Start wrapper for catch / setjmp-else.
2296	*
2297	* This will set up a scope.
2298	*
2299	* @note Use with extreme care as this is a fragile macro.
2300	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2301	* @param a_rcTarget The variable that should receive the status code in case
2302	* of a longjmp/throw.
2303	*/
2304	/** @def IEM_CATCH_LONGJMP_END
2305	* End wrapper for catch / setjmp-else.
2306	*
2307	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2308	* state.
2309	*
2310	* @note Use with extreme care as this is a fragile macro.
2311	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2312	*/
2313	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2314	# ifdef IEM_WITH_THROW_CATCH
2315	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2316	a_rcTarget = VINF_SUCCESS; \
2317	try
2318	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2319	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2320	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2321	catch (int rcThrown) \
2322	{ \
2323	a_rcTarget = rcThrown
2324	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2325	} \
2326	((void)0)
2327	# else /* !IEM_WITH_THROW_CATCH */
2328	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2329	jmp_buf JmpBuf; \
2330	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2331	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2332	if ((rcStrict = setjmp(JmpBuf)) == 0)
2333	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2334	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2335	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2336	if ((rcStrict = setjmp(JmpBuf)) == 0)
2337	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2338	else \
2339	{ \
2340	((void)0)
2341	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2342	} \
2343	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2344	# endif /* !IEM_WITH_THROW_CATCH */
2345	#endif /* IEM_WITH_SETJMP */
2346
2347
2348	/**
2349	* Shared per-VM IEM data.
2350	*/
2351	typedef struct IEM
2352	{
2353	/** The VMX APIC-access page handler type. */
2354	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2355	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2356	/** Set if the CPUID host call functionality is enabled. */
2357	bool fCpuIdHostCall;
2358	#endif
2359	} IEM;
2360
2361
2362
2363	/** @name IEM_ACCESS_XXX - Access details.
2364	* @{ */
2365	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2366	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2367	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2368	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2369	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2370	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2371	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2372	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2373	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2374	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2375	/** The writes are partial, so if initialize the bounce buffer with the
2376	* orignal RAM content. */
2377	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2378	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2379	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2380	/** Bounce buffer with ring-3 write pending, first page. */
2381	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2382	/** Bounce buffer with ring-3 write pending, second page. */
2383	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2384	/** Not locked, accessed via the TLB. */
2385	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2386	/** Atomic access.
2387	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2388	* fallback for misaligned stuff. See @bugref{10547}. */
2389	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2390	/** Valid bit mask. */
2391	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2392	/** Shift count for the TLB flags (upper word). */
2393	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2394
2395	/** Atomic read+write data alias. */
2396	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2397	/** Read+write data alias. */
2398	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2399	/** Write data alias. */
2400	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2401	/** Read data alias. */
2402	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2403	/** Instruction fetch alias. */
2404	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2405	/** Stack write alias. */
2406	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2407	/** Stack read alias. */
2408	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2409	/** Stack read+write alias. */
2410	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2411	/** Read system table alias. */
2412	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2413	/** Read+write system table alias. */
2414	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2415	/** @} */
2416
2417	/** @name Prefix constants (IEMCPU::fPrefixes)
2418	* @{ */
2419	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2420	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2421	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2422	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2423	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2424	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2425	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2426
2427	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2428	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2429	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2430
2431	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2432	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2433	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2434
2435	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2436	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2437	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2438	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2439	/** Mask with all the REX prefix flags.
2440	* This is generally for use when needing to undo the REX prefixes when they
2441	* are followed legacy prefixes and therefore does not immediately preceed
2442	* the first opcode byte.
2443	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2444	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2445
2446	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2447	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2448	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2449	/** @} */
2450
2451	/** @name IEMOPFORM_XXX - Opcode forms
2452	* @note These are ORed together with IEMOPHINT_XXX.
2453	* @{ */
2454	/** ModR/M: reg, r/m */
2455	#define IEMOPFORM_RM 0
2456	/** ModR/M: reg, r/m (register) */
2457	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2458	/** ModR/M: reg, r/m (memory) */
2459	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2460	/** ModR/M: reg, r/m, imm */
2461	#define IEMOPFORM_RMI 1
2462	/** ModR/M: reg, r/m (register), imm */
2463	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2464	/** ModR/M: reg, r/m (memory), imm */
2465	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2466	/** ModR/M: reg, r/m, xmm0 */
2467	#define IEMOPFORM_RM0 2
2468	/** ModR/M: reg, r/m (register), xmm0 */
2469	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2470	/** ModR/M: reg, r/m (memory), xmm0 */
2471	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2472	/** ModR/M: r/m, reg */
2473	#define IEMOPFORM_MR 3
2474	/** ModR/M: r/m (register), reg */
2475	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2476	/** ModR/M: r/m (memory), reg */
2477	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2478	/** ModR/M: r/m, reg, imm */
2479	#define IEMOPFORM_MRI 4
2480	/** ModR/M: r/m (register), reg, imm */
2481	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2482	/** ModR/M: r/m (memory), reg, imm */
2483	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2484	/** ModR/M: r/m only */
2485	#define IEMOPFORM_M 5
2486	/** ModR/M: r/m only (register). */
2487	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2488	/** ModR/M: r/m only (memory). */
2489	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2490	/** ModR/M: r/m, imm */
2491	#define IEMOPFORM_MI 6
2492	/** ModR/M: r/m (register), imm */
2493	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2494	/** ModR/M: r/m (memory), imm */
2495	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2496	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2497	#define IEMOPFORM_M1 7
2498	/** ModR/M: r/m (register), 1. */
2499	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2500	/** ModR/M: r/m (memory), 1. */
2501	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2502	/** ModR/M: r/m, CL (shift and rotate instructions)
2503	* @todo This should just've been a generic fixed register. But the python
2504	* code doesn't needs more convincing. */
2505	#define IEMOPFORM_M_CL 8
2506	/** ModR/M: r/m (register), CL. */
2507	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2508	/** ModR/M: r/m (memory), CL. */
2509	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2510	/** ModR/M: reg only */
2511	#define IEMOPFORM_R 9
2512
2513	/** VEX+ModR/M: reg, r/m */
2514	#define IEMOPFORM_VEX_RM 16
2515	/** VEX+ModR/M: reg, r/m (register) */
2516	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2517	/** VEX+ModR/M: reg, r/m (memory) */
2518	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2519	/** VEX+ModR/M: r/m, reg */
2520	#define IEMOPFORM_VEX_MR 17
2521	/** VEX+ModR/M: r/m (register), reg */
2522	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2523	/** VEX+ModR/M: r/m (memory), reg */
2524	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2525	/** VEX+ModR/M: r/m, reg, imm8 */
2526	#define IEMOPFORM_VEX_MRI 18
2527	/** VEX+ModR/M: r/m (register), reg, imm8 */
2528	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2529	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2530	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2531	/** VEX+ModR/M: r/m only */
2532	#define IEMOPFORM_VEX_M 19
2533	/** VEX+ModR/M: r/m only (register). */
2534	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2535	/** VEX+ModR/M: r/m only (memory). */
2536	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2537	/** VEX+ModR/M: reg only */
2538	#define IEMOPFORM_VEX_R 20
2539	/** VEX+ModR/M: reg, vvvv, r/m */
2540	#define IEMOPFORM_VEX_RVM 21
2541	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2542	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2543	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2544	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2545	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2546	#define IEMOPFORM_VEX_RVMI 22
2547	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2548	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2549	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2550	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2551	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2552	#define IEMOPFORM_VEX_RVMR 23
2553	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2554	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2555	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2556	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2557	/** VEX+ModR/M: reg, r/m, vvvv */
2558	#define IEMOPFORM_VEX_RMV 24
2559	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2560	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2561	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2562	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2563	/** VEX+ModR/M: reg, r/m, imm8 */
2564	#define IEMOPFORM_VEX_RMI 25
2565	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2566	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2567	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2568	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2569	/** VEX+ModR/M: r/m, vvvv, reg */
2570	#define IEMOPFORM_VEX_MVR 26
2571	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2572	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2573	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2574	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2575	/** VEX+ModR/M+/n: vvvv, r/m */
2576	#define IEMOPFORM_VEX_VM 27
2577	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2578	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2579	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2580	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2581	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2582	#define IEMOPFORM_VEX_VMI 28
2583	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2584	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2585	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2586	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2587
2588	/** Fixed register instruction, no R/M. */
2589	#define IEMOPFORM_FIXED 32
2590
2591	/** The r/m is a register. */
2592	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2593	/** The r/m is a memory access. */
2594	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2595	/** @} */
2596
2597	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2598	* @note These are ORed together with IEMOPFORM_XXX.
2599	* @{ */
2600	/** Ignores the operand size prefix (66h). */
2601	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2602	/** Ignores REX.W (aka WIG). */
2603	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2604	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2605	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2606	/** Allowed with the lock prefix. */
2607	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2608	/** The VEX.L value is ignored (aka LIG). */
2609	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2610	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2611	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2612	/** The VEX.L value must be one (i.e. 256-bit width only). */
2613	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2614	/** The VEX.V value must be zero. */
2615	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2616	/** The REX.W/VEX.V value must be zero. */
2617	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2618	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2619	/** The REX.W/VEX.V value must be one. */
2620	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2621	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2622
2623	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2624	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2625	/** @} */
2626
2627	/**
2628	* Possible hardware task switch sources.
2629	*/
2630	typedef enum IEMTASKSWITCH
2631	{
2632	/** Task switch caused by an interrupt/exception. */
2633	IEMTASKSWITCH_INT_XCPT = 1,
2634	/** Task switch caused by a far CALL. */
2635	IEMTASKSWITCH_CALL,
2636	/** Task switch caused by a far JMP. */
2637	IEMTASKSWITCH_JUMP,
2638	/** Task switch caused by an IRET. */
2639	IEMTASKSWITCH_IRET
2640	} IEMTASKSWITCH;
2641	AssertCompileSize(IEMTASKSWITCH, 4);
2642
2643	/**
2644	* Possible CrX load (write) sources.
2645	*/
2646	typedef enum IEMACCESSCRX
2647	{
2648	/** CrX access caused by 'mov crX' instruction. */
2649	IEMACCESSCRX_MOV_CRX,
2650	/** CrX (CR0) write caused by 'lmsw' instruction. */
2651	IEMACCESSCRX_LMSW,
2652	/** CrX (CR0) write caused by 'clts' instruction. */
2653	IEMACCESSCRX_CLTS,
2654	/** CrX (CR0) read caused by 'smsw' instruction. */
2655	IEMACCESSCRX_SMSW
2656	} IEMACCESSCRX;
2657
2658	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2659	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2660	*
2661	* These flags provide further context to SLAT page-walk failures that could not be
2662	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2663	*
2664	* @{
2665	*/
2666	/** Translating a nested-guest linear address failed accessing a nested-guest
2667	* physical address. */
2668	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2669	/** Translating a nested-guest linear address failed accessing a
2670	* paging-structure entry or updating accessed/dirty bits. */
2671	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2672	/** @} */
2673
2674	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2675	# ifndef IN_RING3
2676	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2677	# endif
2678	#endif
2679
2680	/**
2681	* Indicates to the verifier that the given flag set is undefined.
2682	*
2683	* Can be invoked again to add more flags.
2684	*
2685	* This is a NOOP if the verifier isn't compiled in.
2686	*
2687	* @note We're temporarily keeping this until code is converted to new
2688	* disassembler style opcode handling.
2689	*/
2690	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2691
2692
2693	/** @def IEM_DECL_IMPL_TYPE
2694	* For typedef'ing an instruction implementation function.
2695	*
2696	* @param a_RetType The return type.
2697	* @param a_Name The name of the type.
2698	* @param a_ArgList The argument list enclosed in parentheses.
2699	*/
2700
2701	/** @def IEM_DECL_IMPL_DEF
2702	* For defining an instruction implementation function.
2703	*
2704	* @param a_RetType The return type.
2705	* @param a_Name The name of the type.
2706	* @param a_ArgList The argument list enclosed in parentheses.
2707	*/
2708
2709	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2710	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2711	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2712	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2713	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2714	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2715	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2716
2717	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2718	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2719	a_RetType (__fastcall a_Name) a_ArgList
2720	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2721	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2722	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2723	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2724
2725	#elif __cplusplus >= 201700 /* P0012R1 support */
2726	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2727	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2728	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2729	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2730	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2731	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2732
2733	#else
2734	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2735	a_RetType (VBOXCALL a_Name) a_ArgList
2736	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2737	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2738	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2739	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2740
2741	#endif
2742
2743	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2744	RT_C_DECLS_BEGIN
2745	extern uint8_t const g_afParity[256];
2746	RT_C_DECLS_END
2747
2748
2749	/** @name Arithmetic assignment operations on bytes (binary).
2750	* @{ */
2751	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
2752	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2753	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2754	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2755	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2756	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2757	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2758	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2759	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2760	/** @} */
2761
2762	/** @name Arithmetic assignment operations on words (binary).
2763	* @{ */
2764	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
2765	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2766	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2767	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2768	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2769	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2770	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2771	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2772	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2773	/** @} */
2774
2775
2776	/** @name Arithmetic assignment operations on double words (binary).
2777	* @{ */
2778	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
2779	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2780	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2781	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2782	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2783	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2784	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2785	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2786	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2787	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2788	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2789	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2790	/** @} */
2791
2792	/** @name Arithmetic assignment operations on quad words (binary).
2793	* @{ */
2794	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
2795	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2796	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2797	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2798	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2799	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2800	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2801	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2802	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2803	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2804	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2805	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2806	/** @} */
2807
2808	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
2809	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2810	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
2811	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2812	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
2813	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2814	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
2815	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2816
2817	/** @name Compare operations (thrown in with the binary ops).
2818	* @{ */
2819	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2820	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2821	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2822	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2823	/** @} */
2824
2825	/** @name Test operations (thrown in with the binary ops).
2826	* @{ */
2827	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2828	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2829	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2830	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2831	/** @} */
2832
2833	/** @name Bit operations operations (thrown in with the binary ops).
2834	* @{ */
2835	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2836	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2837	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2838	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2839	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2840	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2841	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2842	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2843	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2844	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2845	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2846	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2847	/** @} */
2848
2849	/** @name Arithmetic three operand operations on double words (binary).
2850	* @{ */
2851	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2852	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2853	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2854	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2855	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2856	/** @} */
2857
2858	/** @name Arithmetic three operand operations on quad words (binary).
2859	* @{ */
2860	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2861	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2862	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2863	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2864	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2865	/** @} */
2866
2867	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2868	* @{ */
2869	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2870	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2871	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2872	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2873	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2874	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2875	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2876	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2877	/** @} */
2878
2879	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2880	* @{ */
2881	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2882	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2883	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2884	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2885	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2886	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2887	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2888	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2889	/** @} */
2890
2891	/** @name MULX 32-bit and 64-bit.
2892	* @{ */
2893	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2894	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2895	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2896
2897	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2898	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2899	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2900	/** @} */
2901
2902
2903	/** @name Exchange memory with register operations.
2904	* @{ */
2905	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2906	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2907	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2908	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2909	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2910	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2911	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2912	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2913	/** @} */
2914
2915	/** @name Exchange and add operations.
2916	* @{ */
2917	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2918	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2919	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2920	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2921	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2922	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2923	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2924	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2925	/** @} */
2926
2927	/** @name Compare and exchange.
2928	* @{ */
2929	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2930	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2931	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2932	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2933	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2934	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2935	#if ARCH_BITS == 32
2936	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2937	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2938	#else
2939	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2940	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2941	#endif
2942	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2943	uint32_t *pEFlags));
2944	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2945	uint32_t *pEFlags));
2946	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2947	uint32_t *pEFlags));
2948	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2949	uint32_t *pEFlags));
2950	#ifndef RT_ARCH_ARM64
2951	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2952	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2953	#endif
2954	/** @} */
2955
2956	/** @name Memory ordering
2957	* @{ */
2958	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2959	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2960	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2961	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2962	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2963	#ifndef RT_ARCH_ARM64
2964	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2965	#endif
2966	/** @} */
2967
2968	/** @name Double precision shifts
2969	* @{ */
2970	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2971	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2972	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2973	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2974	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2975	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2976	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2977	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2978	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2979	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2980	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2981	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2982	/** @} */
2983
2984
2985	/** @name Bit search operations (thrown in with the binary ops).
2986	* @{ */
2987	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2988	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2989	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2990	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2991	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2992	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2993	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2994	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2995	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2996	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2997	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2998	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2999	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3000	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3001	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3002	/** @} */
3003
3004	/** @name Signed multiplication operations (thrown in with the binary ops).
3005	* @{ */
3006	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3007	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3008	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3009	/** @} */
3010
3011	/** @name Arithmetic assignment operations on bytes (unary).
3012	* @{ */
3013	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3014	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3015	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3016	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3017	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3018	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3019	/** @} */
3020
3021	/** @name Arithmetic assignment operations on words (unary).
3022	* @{ */
3023	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3024	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3025	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3026	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3027	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3028	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3029	/** @} */
3030
3031	/** @name Arithmetic assignment operations on double words (unary).
3032	* @{ */
3033	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3034	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3035	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3036	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3037	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3038	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3039	/** @} */
3040
3041	/** @name Arithmetic assignment operations on quad words (unary).
3042	* @{ */
3043	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3044	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3045	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3046	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3047	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3048	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3049	/** @} */
3050
3051
3052	/** @name Shift operations on bytes (Group 2).
3053	* @{ */
3054	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3055	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3056	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3057	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3058	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3059	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3060	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3061	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3062	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3063	/** @} */
3064
3065	/** @name Shift operations on words (Group 2).
3066	* @{ */
3067	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3068	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3069	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3070	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3071	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3072	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3073	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3074	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3075	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3076	/** @} */
3077
3078	/** @name Shift operations on double words (Group 2).
3079	* @{ */
3080	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3081	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3082	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3083	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3084	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3085	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3086	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3087	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3088	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3089	/** @} */
3090
3091	/** @name Shift operations on words (Group 2).
3092	* @{ */
3093	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3094	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3095	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3096	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3097	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3098	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3099	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3100	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3101	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3102	/** @} */
3103
3104	/** @name Multiplication and division operations.
3105	* @{ */
3106	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3107	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3108	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3109	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3110	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3111	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3112
3113	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3114	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3115	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3116	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3117	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3118	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3119
3120	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3121	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3122	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3123	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3124	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3125	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3126
3127	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3128	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3129	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3130	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3131	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3132	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3133	/** @} */
3134
3135	/** @name Byte Swap.
3136	* @{ */
3137	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3138	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3139	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3140	/** @} */
3141
3142	/** @name Misc.
3143	* @{ */
3144	FNIEMAIMPLBINU16 iemAImpl_arpl;
3145	/** @} */
3146
3147	/** @name RDRAND and RDSEED
3148	* @{ */
3149	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3150	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3151	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3152	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3153	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3154	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3155
3156	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3157	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3158	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3159	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3160	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3161	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3162	/** @} */
3163
3164	/** @name ADOX and ADCX
3165	* @{ */
3166	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3167	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3168	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3169	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3170	/** @} */
3171
3172	/** @name FPU operations taking a 32-bit float argument
3173	* @{ */
3174	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3175	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3176	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3177
3178	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3179	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3180	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3181
3182	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3183	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3184	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3185	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3186	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3187	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3188	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3189
3190	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3191	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3192	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3193	/** @} */
3194
3195	/** @name FPU operations taking a 64-bit float argument
3196	* @{ */
3197	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3198	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3199	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3200
3201	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3202	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3203	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3204
3205	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3206	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3207	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3208	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3209	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3210	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3211	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3212
3213	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3214	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3215	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3216	/** @} */
3217
3218	/** @name FPU operations taking a 80-bit float argument
3219	* @{ */
3220	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3221	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3222	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3223	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3224	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3225	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3226	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3227	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3228	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3229	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3230	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3231	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3232
3233	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3234	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3235	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3236
3237	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3238	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3239	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3240	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3241	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3242
3243	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3244	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3245	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3246	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3247	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3248
3249	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3250	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3251	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3252	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3253	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3254	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3255	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3256	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3257	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3258
3259	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3260	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3261	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3262	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3263
3264	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3265	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3266	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3267	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3268	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3269	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3270	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3271	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3272	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3273
3274	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3275	PCRTFLOAT80U pr80Val));
3276	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3277	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3278	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3279	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3280
3281	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3282	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3283	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3284
3285	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3286	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3287	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3288
3289	/** @} */
3290
3291	/** @name FPU operations taking a 16-bit signed integer argument
3292	* @{ */
3293	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3294	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3295	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3296	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3297	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3298	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3299
3300	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3301	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3302	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3303	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3304	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3305	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3306
3307	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3308	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3309	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3310	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3311
3312	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3313	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3314	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3315	/** @} */
3316
3317	/** @name FPU operations taking a 32-bit signed integer argument
3318	* @{ */
3319	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3320	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3321	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3322	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3323	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3324	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3325
3326	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3327	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3328	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3329	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3330	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3331	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3332
3333	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3334	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3335	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3336	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3337
3338	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3339	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3340	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3341	/** @} */
3342
3343	/** @name FPU operations taking a 64-bit signed integer argument
3344	* @{ */
3345	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3346	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3347	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3348
3349	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3350	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3351	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3352	/** @} */
3353
3354
3355	/** Temporary type representing a 256-bit vector register. */
3356	typedef struct { uint64_t au64[4]; } IEMVMM256;
3357	/** Temporary type pointing to a 256-bit vector register. */
3358	typedef IEMVMM256 *PIEMVMM256;
3359	/** Temporary type pointing to a const 256-bit vector register. */
3360	typedef IEMVMM256 *PCIEMVMM256;
3361
3362
3363	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3364	* @{ */
3365	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3366	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3367	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
3368	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3369	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3370	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3371	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3372	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3373	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3374	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3376	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3377	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3378	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3379	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3380	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3381	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3382	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3383	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3384	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3385	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3386	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3387	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3388	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3389	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3390	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3391	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3392	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3393	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3394	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3395	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3396	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3397	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3398	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3399	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3400	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3401	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3402	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3403	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3404	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3405	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3406	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3407	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3408	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3409	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3410	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3411	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3412	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3413	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3414	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3415	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3416	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3417	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3418	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3419	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3420	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3421	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3422
3423	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3424	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3425	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3426	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3427	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3428	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3429	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3430	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3431	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3432	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3433	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3434	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3435	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3436	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3437	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3438	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3439	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3440	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3441	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3442	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3443	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3444	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3445	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3446	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3447	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3448	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3449	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3450	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3451	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3452	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3453	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3454	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3455	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3456	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3457	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3458	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3459	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3460	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3461	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3462	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3463	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3464	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3465	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3466	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3467	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3468	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3469	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3470	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3471	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3472	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3473	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3474	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3475	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3476	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3477	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3478	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3479	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3480	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3481
3482	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3483	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3484	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3485	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3486	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3487	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3488	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3489	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3490	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3491	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3492	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3493	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3494	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3495	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3496	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3497	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3498	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3499	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3500	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3501	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3502	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3503	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3504	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3505	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3506	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3507	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3508	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3509	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3510	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3511	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3512	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3513	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3514	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3515	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3516	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3517	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3518	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3519	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3520	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3521	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3522	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3523	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3524	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3525	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3526	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3527	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3528	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3529	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3530	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3531	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3532	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3533	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3534	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3535	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3536	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3537	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3538	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3539	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3540	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3541	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3542	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3543	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3544	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3545	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3546	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3547	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3548	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3549	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3550	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3551	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3552	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3553	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3554	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3555	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3556
3557	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3558	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3559	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3560	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3561
3562	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3563	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3564	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3565	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3566	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3567	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3568	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3569	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3570	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3571	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3572	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3573	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3574	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3575	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3576	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3577	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3578	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3579	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3580	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3581	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3582	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3583	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3584	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3585	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3586	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3587	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3588	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3589	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3590	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3591	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3592	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3593	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3594	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3595	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3596	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3597	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3598	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3599	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3600	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3601	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3602	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3603	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3604	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3605	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3606	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3607	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3608	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3609	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3610	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3611	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3612	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3613	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3614	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3615	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3616	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3617	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3618	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3619	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3620	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3621	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3622	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3623	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3624	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3625	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3626	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3627	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3628	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3629	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3630	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3631	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3632	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3633	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3634	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3635	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3636
3637	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3638	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3639	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3640	/** @} */
3641
3642	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3643	* @{ */
3644	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3645	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3646	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3647	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3648	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3649	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3650	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3651	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3652	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3653	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3654
3655	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3656	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3657	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3658	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3659	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3660	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3661	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3662	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3663	/** @} */
3664
3665	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3666	* @{ */
3667	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3668	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3669	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3670	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3671	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3672	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3673	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3674	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3675	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3676	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3677	/** @} */
3678
3679	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3680	* @{ */
3681	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3682	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3683	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3684	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3685	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3686	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3687	#ifndef IEM_WITHOUT_ASSEMBLY
3688	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3689	#endif
3690	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3691	/** @} */
3692
3693	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3694	* @{ */
3695	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3696	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3697	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3698	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3699	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3700	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3701	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3702	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3703	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3704	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3705	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3706	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3707	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3708	/** @} */
3709
3710	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3711	* @{ */
3712	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
3713	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
3714	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3715	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3716	#ifndef IEM_WITHOUT_ASSEMBLY
3717	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3718	#endif
3719	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3720	/** @} */
3721
3722	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3723	* @{ */
3724	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3725	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3726	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3727	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3728	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3729	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3730
3731	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3732	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3733	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3734	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3735	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3736	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3737
3738	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3739	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3740	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3741	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3742	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3743	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3744
3745	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3746	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3747	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3748	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3749	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3750	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3751	/** @} */
3752
3753
3754	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3755	* @{ */
3756	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3757	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3758	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3759	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3760	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3761
3762	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3763	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3764	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3765	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3766	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3767
3768	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3769	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3770	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3771	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3772	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3773
3774	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3775	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3776	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3777	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3778	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3779
3780	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3781	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3782	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3783	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3784	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3785
3786	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3787	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3788	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3789	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3790	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3791
3792	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3793	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3794	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3795	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3796	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3797
3798	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3799	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3800	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3801	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3802	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3803
3804	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3805	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3806	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3807	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3808	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3809
3810	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3811	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3812	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3813	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3814	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3815
3816	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3817	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3818	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3819	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3820	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3821
3822	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3823	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3824	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3825	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3826	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3827
3828	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3829	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3830	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3831	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3832	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3833
3834	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3835	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3836	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3837	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3838	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3839
3840	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3841	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3842
3843	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3844	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3845	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3846	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3847	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3848
3849	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3850	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3851	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3852	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3853	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3854
3855
3856	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3857	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3858	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3859	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
3860	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3861	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3862	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3863	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3864
3865	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3866	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3867	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3868	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3869
3870	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3871	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3872	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
3873	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3874	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3875
3876	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3877	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3878	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
3879	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3880	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3881	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3882	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3883
3884	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3885	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3886	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3887	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3888	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3889
3890	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3891	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3892	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3893	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3894	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3895
3896	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3897
3898	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3899
3900	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3901	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3902	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3903	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3904	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3905	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3906	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3907	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3908
3909	typedef struct IEMPCMPISTRXSRC
3910	{
3911	RTUINT128U uSrc1;
3912	RTUINT128U uSrc2;
3913	} IEMPCMPISTRXSRC;
3914	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3915	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3916
3917	typedef struct IEMPCMPESTRXSRC
3918	{
3919	RTUINT128U uSrc1;
3920	RTUINT128U uSrc2;
3921	uint64_t u64Rax;
3922	uint64_t u64Rdx;
3923	} IEMPCMPESTRXSRC;
3924	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3925	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3926
3927	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
3928	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3929	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3930	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3931
3932	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3933	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3934	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3935	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3936
3937	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3938	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3939	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3940	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3941
3942	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3943	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3944
3945	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3946	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3947	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3948
3949	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
3950	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
3951	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
3952	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
3953	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
3954	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
3955	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3956	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3957	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3958	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3959
3960	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
3961	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
3962	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
3963	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
3964
3965	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
3966	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
3967	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
3968	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
3969	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
3970	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
3971	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3972	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3973	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3974	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3975
3976	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
3977	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
3978	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
3979	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
3980
3981	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
3982	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
3983	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
3984	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
3985
3986	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
3987	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
3988	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
3989	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
3990	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
3991	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
3992	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
3993	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
3994	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
3995	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
3996	/** @} */
3997
3998	/** @name Media Odds and Ends
3999	* @{ */
4000	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4001	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4002	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4003	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4004	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4005	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4006	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4007	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4008
4009	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4010	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4011	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4012	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4013	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4014	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4015	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4016	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4017	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4018	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4019
4020	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4021	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4022	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4023	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4024	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4025	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4026	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4027	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4028
4029	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4030	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4031
4032	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4033	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4034
4035	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4036	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4037
4038	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4039	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4040
4041	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4042	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4043	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4044	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4045
4046	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4047	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4048
4049	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4050	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4051	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4052	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4053
4054	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4055	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4056
4057
4058	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4059	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4060
4061	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4062	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4063
4064	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4065	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4066
4067	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4068	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4069
4070	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4071	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4072
4073	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4074	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4075
4076
4077	typedef struct IEMMEDIAF2XMMSRC
4078	{
4079	X86XMMREG uSrc1;
4080	X86XMMREG uSrc2;
4081	} IEMMEDIAF2XMMSRC;
4082	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4083	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4084
4085	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4086	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
4087
4088	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
4089	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
4090	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
4091	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
4092	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
4093	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
4094
4095	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4096	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4097
4098	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4099	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4100
4101	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4102	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4103
4104	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4105	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4106
4107	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4108	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4109
4110	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4111	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4112
4113	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4114	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4115
4116	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4117	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4118
4119	/** @} */
4120
4121
4122	/** @name Function tables.
4123	* @{
4124	*/
4125
4126	/**
4127	* Function table for a binary operator providing implementation based on
4128	* operand size.
4129	*/
4130	typedef struct IEMOPBINSIZES
4131	{
4132	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4133	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4134	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4135	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4136	} IEMOPBINSIZES;
4137	/** Pointer to a binary operator function table. */
4138	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4139
4140
4141	/**
4142	* Function table for a unary operator providing implementation based on
4143	* operand size.
4144	*/
4145	typedef struct IEMOPUNARYSIZES
4146	{
4147	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4148	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4149	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4150	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4151	} IEMOPUNARYSIZES;
4152	/** Pointer to a unary operator function table. */
4153	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4154
4155
4156	/**
4157	* Function table for a shift operator providing implementation based on
4158	* operand size.
4159	*/
4160	typedef struct IEMOPSHIFTSIZES
4161	{
4162	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4163	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4164	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4165	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4166	} IEMOPSHIFTSIZES;
4167	/** Pointer to a shift operator function table. */
4168	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4169
4170
4171	/**
4172	* Function table for a multiplication or division operation.
4173	*/
4174	typedef struct IEMOPMULDIVSIZES
4175	{
4176	PFNIEMAIMPLMULDIVU8 pfnU8;
4177	PFNIEMAIMPLMULDIVU16 pfnU16;
4178	PFNIEMAIMPLMULDIVU32 pfnU32;
4179	PFNIEMAIMPLMULDIVU64 pfnU64;
4180	} IEMOPMULDIVSIZES;
4181	/** Pointer to a multiplication or division operation function table. */
4182	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4183
4184
4185	/**
4186	* Function table for a double precision shift operator providing implementation
4187	* based on operand size.
4188	*/
4189	typedef struct IEMOPSHIFTDBLSIZES
4190	{
4191	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4192	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4193	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4194	} IEMOPSHIFTDBLSIZES;
4195	/** Pointer to a double precision shift function table. */
4196	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4197
4198
4199	/**
4200	* Function table for media instruction taking two full sized media source
4201	* registers and one full sized destination register (AVX).
4202	*/
4203	typedef struct IEMOPMEDIAF3
4204	{
4205	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4206	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4207	} IEMOPMEDIAF3;
4208	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4209	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4210
4211	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4212	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4213	* given functions as initializers. For use in AVX functions where a pair of
4214	* functions are only used once and the function table need not be public. */
4215	#ifndef TST_IEM_CHECK_MC
4216	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4217	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4218	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4219	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4220	# else
4221	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4222	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4223	# endif
4224	#else
4225	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4226	#endif
4227	/** @def IEMOPMEDIAF3_INIT_VARS
4228	* Generate AVX function tables for the @a a_InstrNm instruction.
4229	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4230	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4231	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4232	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4233
4234	/**
4235	* Function table for media instruction taking two full sized media source
4236	* registers and one full sized destination register, but no additional state
4237	* (AVX).
4238	*/
4239	typedef struct IEMOPMEDIAOPTF3
4240	{
4241	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4242	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4243	} IEMOPMEDIAOPTF3;
4244	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4245	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4246
4247	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4248	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4249	* given functions as initializers. For use in AVX functions where a pair of
4250	* functions are only used once and the function table need not be public. */
4251	#ifndef TST_IEM_CHECK_MC
4252	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4253	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4254	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4255	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4256	# else
4257	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4258	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4259	# endif
4260	#else
4261	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4262	#endif
4263	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4264	* Generate AVX function tables for the @a a_InstrNm instruction.
4265	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4266	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4267	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4268	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4269
4270	/**
4271	* Function table for media instruction taking one full sized media source
4272	* registers and one full sized destination register, but no additional state
4273	* (AVX).
4274	*/
4275	typedef struct IEMOPMEDIAOPTF2
4276	{
4277	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4278	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4279	} IEMOPMEDIAOPTF2;
4280	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4281	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4282
4283	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4284	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4285	* given functions as initializers. For use in AVX functions where a pair of
4286	* functions are only used once and the function table need not be public. */
4287	#ifndef TST_IEM_CHECK_MC
4288	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4289	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4290	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4291	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4292	# else
4293	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4294	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4295	# endif
4296	#else
4297	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4298	#endif
4299	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4300	* Generate AVX function tables for the @a a_InstrNm instruction.
4301	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4302	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4303	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4304	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4305
4306	/**
4307	* Function table for media instruction taking one full sized media source
4308	* register and one full sized destination register and an 8-bit immediate, but no additional state
4309	* (AVX).
4310	*/
4311	typedef struct IEMOPMEDIAOPTF2IMM8
4312	{
4313	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4314	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4315	} IEMOPMEDIAOPTF2IMM8;
4316	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4317	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4318
4319	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4320	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4321	* given functions as initializers. For use in AVX functions where a pair of
4322	* functions are only used once and the function table need not be public. */
4323	#ifndef TST_IEM_CHECK_MC
4324	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4325	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4326	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4327	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4328	# else
4329	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4330	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4331	# endif
4332	#else
4333	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4334	#endif
4335	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4336	* Generate AVX function tables for the @a a_InstrNm instruction.
4337	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4338	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4339	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4340	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4341
4342	/**
4343	* Function table for media instruction taking two full sized media source
4344	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4345	* (AVX).
4346	*/
4347	typedef struct IEMOPMEDIAOPTF3IMM8
4348	{
4349	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4350	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4351	} IEMOPMEDIAOPTF3IMM8;
4352	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4353	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4354
4355	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4356	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4357	* given functions as initializers. For use in AVX functions where a pair of
4358	* functions are only used once and the function table need not be public. */
4359	#ifndef TST_IEM_CHECK_MC
4360	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4361	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4362	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4363	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4364	# else
4365	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4366	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4367	# endif
4368	#else
4369	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4370	#endif
4371	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4372	* Generate AVX function tables for the @a a_InstrNm instruction.
4373	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4374	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4375	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4376	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4377	/** @} */
4378
4379
4380	/**
4381	* Function table for blend type instruction taking three full sized media source
4382	* registers and one full sized destination register, but no additional state
4383	* (AVX).
4384	*/
4385	typedef struct IEMOPBLENDOP
4386	{
4387	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4388	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4389	} IEMOPBLENDOP;
4390	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4391	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4392
4393	/** @def IEMOPBLENDOP_INIT_VARS_EX
4394	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4395	* given functions as initializers. For use in AVX functions where a pair of
4396	* functions are only used once and the function table need not be public. */
4397	#ifndef TST_IEM_CHECK_MC
4398	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4399	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4400	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4401	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4402	# else
4403	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4404	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4405	# endif
4406	#else
4407	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4408	#endif
4409	/** @def IEMOPBLENDOP_INIT_VARS
4410	* Generate AVX function tables for the @a a_InstrNm instruction.
4411	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4412	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4413	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4414	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4415
4416
4417	/** @name SSE/AVX single/double precision floating point operations.
4418	* @{ */
4419	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4420	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4421	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4422	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4423	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4424	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4425
4426	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4427	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4428	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4429	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4430	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4431	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4432
4433	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4434	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4435
4436	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4437	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4438	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4439	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4440	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4441	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4442	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4443	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4444	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4445	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4446	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4447	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4448	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4449	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4450	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4451	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4452	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4453	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4454	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4455	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4456	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4457	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4458
4459	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4460	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4461
4462	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4463	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4464	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4465	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4466	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4467	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4468
4469	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4470	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4471	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4472	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4473	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4474	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4475	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4476	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4477	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4478	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4479	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4480	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4481	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4482	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4483	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4484	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4485	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4486	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4487
4488	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4489	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4490	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4491	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4492	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4493	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4494	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4495	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4496	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4497	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4498	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4499	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4500	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4501	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4502	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4503	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4504	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4505	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4506	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4507	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4508	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
4509	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
4510
4511	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4512	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4513	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4514	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4515	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4516	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4517	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4518	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4519	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4520	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4521	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4522	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4523	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4524	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4525
4526	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4527	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4528	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4529	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4530	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4531	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4532	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4533	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4534	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4535	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4536	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4537	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4538	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4539	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4540	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4541	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4542	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
4543	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
4544	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4545	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4546	/** @} */
4547
4548	/** @name C instruction implementations for anything slightly complicated.
4549	* @{ */
4550
4551	/**
4552	* For typedef'ing or declaring a C instruction implementation function taking
4553	* no extra arguments.
4554	*
4555	* @param a_Name The name of the type.
4556	*/
4557	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4558	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4559	/**
4560	* For defining a C instruction implementation function taking no extra
4561	* arguments.
4562	*
4563	* @param a_Name The name of the function
4564	*/
4565	# define IEM_CIMPL_DEF_0(a_Name) \
4566	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4567	/**
4568	* Prototype version of IEM_CIMPL_DEF_0.
4569	*/
4570	# define IEM_CIMPL_PROTO_0(a_Name) \
4571	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4572	/**
4573	* For calling a C instruction implementation function taking no extra
4574	* arguments.
4575	*
4576	* This special call macro adds default arguments to the call and allow us to
4577	* change these later.
4578	*
4579	* @param a_fn The name of the function.
4580	*/
4581	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4582
4583	/** Type for a C instruction implementation function taking no extra
4584	* arguments. */
4585	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4586	/** Function pointer type for a C instruction implementation function taking
4587	* no extra arguments. */
4588	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4589
4590	/**
4591	* For typedef'ing or declaring a C instruction implementation function taking
4592	* one extra argument.
4593	*
4594	* @param a_Name The name of the type.
4595	* @param a_Type0 The argument type.
4596	* @param a_Arg0 The argument name.
4597	*/
4598	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4599	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4600	/**
4601	* For defining a C instruction implementation function taking one extra
4602	* argument.
4603	*
4604	* @param a_Name The name of the function
4605	* @param a_Type0 The argument type.
4606	* @param a_Arg0 The argument name.
4607	*/
4608	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4609	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4610	/**
4611	* Prototype version of IEM_CIMPL_DEF_1.
4612	*/
4613	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4614	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4615	/**
4616	* For calling a C instruction implementation function taking one extra
4617	* argument.
4618	*
4619	* This special call macro adds default arguments to the call and allow us to
4620	* change these later.
4621	*
4622	* @param a_fn The name of the function.
4623	* @param a0 The name of the 1st argument.
4624	*/
4625	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4626
4627	/**
4628	* For typedef'ing or declaring a C instruction implementation function taking
4629	* two extra arguments.
4630	*
4631	* @param a_Name The name of the type.
4632	* @param a_Type0 The type of the 1st argument
4633	* @param a_Arg0 The name of the 1st argument.
4634	* @param a_Type1 The type of the 2nd argument.
4635	* @param a_Arg1 The name of the 2nd argument.
4636	*/
4637	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4638	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4639	/**
4640	* For defining a C instruction implementation function taking two extra
4641	* arguments.
4642	*
4643	* @param a_Name The name of the function.
4644	* @param a_Type0 The type of the 1st argument
4645	* @param a_Arg0 The name of the 1st argument.
4646	* @param a_Type1 The type of the 2nd argument.
4647	* @param a_Arg1 The name of the 2nd argument.
4648	*/
4649	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4650	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4651	/**
4652	* Prototype version of IEM_CIMPL_DEF_2.
4653	*/
4654	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4655	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4656	/**
4657	* For calling a C instruction implementation function taking two extra
4658	* arguments.
4659	*
4660	* This special call macro adds default arguments to the call and allow us to
4661	* change these later.
4662	*
4663	* @param a_fn The name of the function.
4664	* @param a0 The name of the 1st argument.
4665	* @param a1 The name of the 2nd argument.
4666	*/
4667	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4668
4669	/**
4670	* For typedef'ing or declaring a C instruction implementation function taking
4671	* three extra arguments.
4672	*
4673	* @param a_Name The name of the type.
4674	* @param a_Type0 The type of the 1st argument
4675	* @param a_Arg0 The name of the 1st argument.
4676	* @param a_Type1 The type of the 2nd argument.
4677	* @param a_Arg1 The name of the 2nd argument.
4678	* @param a_Type2 The type of the 3rd argument.
4679	* @param a_Arg2 The name of the 3rd argument.
4680	*/
4681	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4682	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4683	/**
4684	* For defining a C instruction implementation function taking three extra
4685	* arguments.
4686	*
4687	* @param a_Name The name of the function.
4688	* @param a_Type0 The type of the 1st argument
4689	* @param a_Arg0 The name of the 1st argument.
4690	* @param a_Type1 The type of the 2nd argument.
4691	* @param a_Arg1 The name of the 2nd argument.
4692	* @param a_Type2 The type of the 3rd argument.
4693	* @param a_Arg2 The name of the 3rd argument.
4694	*/
4695	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4696	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4697	/**
4698	* Prototype version of IEM_CIMPL_DEF_3.
4699	*/
4700	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4701	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4702	/**
4703	* For calling a C instruction implementation function taking three extra
4704	* arguments.
4705	*
4706	* This special call macro adds default arguments to the call and allow us to
4707	* change these later.
4708	*
4709	* @param a_fn The name of the function.
4710	* @param a0 The name of the 1st argument.
4711	* @param a1 The name of the 2nd argument.
4712	* @param a2 The name of the 3rd argument.
4713	*/
4714	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4715
4716
4717	/**
4718	* For typedef'ing or declaring a C instruction implementation function taking
4719	* four extra arguments.
4720	*
4721	* @param a_Name The name of the type.
4722	* @param a_Type0 The type of the 1st argument
4723	* @param a_Arg0 The name of the 1st argument.
4724	* @param a_Type1 The type of the 2nd argument.
4725	* @param a_Arg1 The name of the 2nd argument.
4726	* @param a_Type2 The type of the 3rd argument.
4727	* @param a_Arg2 The name of the 3rd argument.
4728	* @param a_Type3 The type of the 4th argument.
4729	* @param a_Arg3 The name of the 4th argument.
4730	*/
4731	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4732	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4733	/**
4734	* For defining a C instruction implementation function taking four extra
4735	* arguments.
4736	*
4737	* @param a_Name The name of the function.
4738	* @param a_Type0 The type of the 1st argument
4739	* @param a_Arg0 The name of the 1st argument.
4740	* @param a_Type1 The type of the 2nd argument.
4741	* @param a_Arg1 The name of the 2nd argument.
4742	* @param a_Type2 The type of the 3rd argument.
4743	* @param a_Arg2 The name of the 3rd argument.
4744	* @param a_Type3 The type of the 4th argument.
4745	* @param a_Arg3 The name of the 4th argument.
4746	*/
4747	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4748	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4749	a_Type2 a_Arg2, a_Type3 a_Arg3))
4750	/**
4751	* Prototype version of IEM_CIMPL_DEF_4.
4752	*/
4753	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4754	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4755	a_Type2 a_Arg2, a_Type3 a_Arg3))
4756	/**
4757	* For calling a C instruction implementation function taking four extra
4758	* arguments.
4759	*
4760	* This special call macro adds default arguments to the call and allow us to
4761	* change these later.
4762	*
4763	* @param a_fn The name of the function.
4764	* @param a0 The name of the 1st argument.
4765	* @param a1 The name of the 2nd argument.
4766	* @param a2 The name of the 3rd argument.
4767	* @param a3 The name of the 4th argument.
4768	*/
4769	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4770
4771
4772	/**
4773	* For typedef'ing or declaring a C instruction implementation function taking
4774	* five extra arguments.
4775	*
4776	* @param a_Name The name of the type.
4777	* @param a_Type0 The type of the 1st argument
4778	* @param a_Arg0 The name of the 1st argument.
4779	* @param a_Type1 The type of the 2nd argument.
4780	* @param a_Arg1 The name of the 2nd argument.
4781	* @param a_Type2 The type of the 3rd argument.
4782	* @param a_Arg2 The name of the 3rd argument.
4783	* @param a_Type3 The type of the 4th argument.
4784	* @param a_Arg3 The name of the 4th argument.
4785	* @param a_Type4 The type of the 5th argument.
4786	* @param a_Arg4 The name of the 5th argument.
4787	*/
4788	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4789	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4790	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4791	a_Type3 a_Arg3, a_Type4 a_Arg4))
4792	/**
4793	* For defining a C instruction implementation function taking five extra
4794	* arguments.
4795	*
4796	* @param a_Name The name of the function.
4797	* @param a_Type0 The type of the 1st argument
4798	* @param a_Arg0 The name of the 1st argument.
4799	* @param a_Type1 The type of the 2nd argument.
4800	* @param a_Arg1 The name of the 2nd argument.
4801	* @param a_Type2 The type of the 3rd argument.
4802	* @param a_Arg2 The name of the 3rd argument.
4803	* @param a_Type3 The type of the 4th argument.
4804	* @param a_Arg3 The name of the 4th argument.
4805	* @param a_Type4 The type of the 5th argument.
4806	* @param a_Arg4 The name of the 5th argument.
4807	*/
4808	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4809	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4810	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4811	/**
4812	* Prototype version of IEM_CIMPL_DEF_5.
4813	*/
4814	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4815	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4816	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4817	/**
4818	* For calling a C instruction implementation function taking five extra
4819	* arguments.
4820	*
4821	* This special call macro adds default arguments to the call and allow us to
4822	* change these later.
4823	*
4824	* @param a_fn The name of the function.
4825	* @param a0 The name of the 1st argument.
4826	* @param a1 The name of the 2nd argument.
4827	* @param a2 The name of the 3rd argument.
4828	* @param a3 The name of the 4th argument.
4829	* @param a4 The name of the 5th argument.
4830	*/
4831	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4832
4833	/** @} */
4834
4835
4836	/** @name Opcode Decoder Function Types.
4837	* @{ */
4838
4839	/** @typedef PFNIEMOP
4840	* Pointer to an opcode decoder function.
4841	*/
4842
4843	/** @def FNIEMOP_DEF
4844	* Define an opcode decoder function.
4845	*
4846	* We're using macors for this so that adding and removing parameters as well as
4847	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4848	*
4849	* @param a_Name The function name.
4850	*/
4851
4852	/** @typedef PFNIEMOPRM
4853	* Pointer to an opcode decoder function with RM byte.
4854	*/
4855
4856	/** @def FNIEMOPRM_DEF
4857	* Define an opcode decoder function with RM byte.
4858	*
4859	* We're using macors for this so that adding and removing parameters as well as
4860	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4861	*
4862	* @param a_Name The function name.
4863	*/
4864
4865	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4866	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4867	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4868	# define FNIEMOP_DEF(a_Name) \
4869	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4870	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4871	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4872	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4873	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4874
4875	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4876	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4877	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4878	# define FNIEMOP_DEF(a_Name) \
4879	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4880	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4881	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4882	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4883	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4884
4885	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4886	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4887	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4888	# define FNIEMOP_DEF(a_Name) \
4889	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4890	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4891	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4892	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4893	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4894
4895	#else
4896	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4897	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4898	# define FNIEMOP_DEF(a_Name) \
4899	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4900	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4901	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4902	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4903	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4904
4905	#endif
4906	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4907
4908	/**
4909	* Call an opcode decoder function.
4910	*
4911	* We're using macors for this so that adding and removing parameters can be
4912	* done as we please. See FNIEMOP_DEF.
4913	*/
4914	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4915
4916	/**
4917	* Call a common opcode decoder function taking one extra argument.
4918	*
4919	* We're using macors for this so that adding and removing parameters can be
4920	* done as we please. See FNIEMOP_DEF_1.
4921	*/
4922	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4923
4924	/**
4925	* Call a common opcode decoder function taking one extra argument.
4926	*
4927	* We're using macors for this so that adding and removing parameters can be
4928	* done as we please. See FNIEMOP_DEF_1.
4929	*/
4930	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4931	/** @} */
4932
4933
4934	/** @name Misc Helpers
4935	* @{ */
4936
4937	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4938	* due to GCC lacking knowledge about the value range of a switch. */
4939	#if RT_CPLUSPLUS_PREREQ(202000)
4940	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4941	#else
4942	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4943	#endif
4944
4945	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4946	#if RT_CPLUSPLUS_PREREQ(202000)
4947	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4948	#else
4949	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4950	#endif
4951
4952	/**
4953	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4954	* occation.
4955	*/
4956	#ifdef LOG_ENABLED
4957	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4958	do { \
4959	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4960	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4961	} while (0)
4962	#else
4963	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4964	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4965	#endif
4966
4967	/**
4968	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4969	* occation using the supplied logger statement.
4970	*
4971	* @param a_LoggerArgs What to log on failure.
4972	*/
4973	#ifdef LOG_ENABLED
4974	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4975	do { \
4976	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4977	/LogFunc(a_LoggerArgs);/ \
4978	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4979	} while (0)
4980	#else
4981	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4982	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4983	#endif
4984
4985	/**
4986	* Gets the CPU mode (from fExec) as a IEMMODE value.
4987	*
4988	* @returns IEMMODE
4989	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4990	*/
4991	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4992
4993	/**
4994	* Check if we're currently executing in real or virtual 8086 mode.
4995	*
4996	* @returns @c true if it is, @c false if not.
4997	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4998	*/
4999	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5000	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5001
5002	/**
5003	* Check if we're currently executing in virtual 8086 mode.
5004	*
5005	* @returns @c true if it is, @c false if not.
5006	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5007	*/
5008	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5009
5010	/**
5011	* Check if we're currently executing in long mode.
5012	*
5013	* @returns @c true if it is, @c false if not.
5014	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5015	*/
5016	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5017
5018	/**
5019	* Check if we're currently executing in a 16-bit code segment.
5020	*
5021	* @returns @c true if it is, @c false if not.
5022	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5023	*/
5024	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5025
5026	/**
5027	* Check if we're currently executing in a 32-bit code segment.
5028	*
5029	* @returns @c true if it is, @c false if not.
5030	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5031	*/
5032	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5033
5034	/**
5035	* Check if we're currently executing in a 64-bit code segment.
5036	*
5037	* @returns @c true if it is, @c false if not.
5038	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5039	*/
5040	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5041
5042	/**
5043	* Check if we're currently executing in real mode.
5044	*
5045	* @returns @c true if it is, @c false if not.
5046	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5047	*/
5048	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5049
5050	/**
5051	* Gets the current protection level (CPL).
5052	*
5053	* @returns 0..3
5054	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5055	*/
5056	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5057
5058	/**
5059	* Sets the current protection level (CPL).
5060	*
5061	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5062	*/
5063	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5064	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5065
5066	/**
5067	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5068	* @returns PCCPUMFEATURES
5069	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5070	*/
5071	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5072
5073	/**
5074	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5075	* @returns PCCPUMFEATURES
5076	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5077	*/
5078	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5079
5080	/**
5081	* Evaluates to true if we're presenting an Intel CPU to the guest.
5082	*/
5083	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5084
5085	/**
5086	* Evaluates to true if we're presenting an AMD CPU to the guest.
5087	*/
5088	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5089
5090	/**
5091	* Check if the address is canonical.
5092	*/
5093	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5094
5095	/** Checks if the ModR/M byte is in register mode or not. */
5096	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5097	/** Checks if the ModR/M byte is in memory mode or not. */
5098	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5099
5100	/**
5101	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5102	*
5103	* For use during decoding.
5104	*/
5105	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5106	/**
5107	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5108	*
5109	* For use during decoding.
5110	*/
5111	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5112
5113	/**
5114	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5115	*
5116	* For use during decoding.
5117	*/
5118	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5119	/**
5120	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5121	*
5122	* For use during decoding.
5123	*/
5124	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5125
5126	/**
5127	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5128	* register index, with REX.R added in.
5129	*
5130	* For use during decoding.
5131	*
5132	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5133	*/
5134	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5135	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5136	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5137	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5138	/**
5139	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5140	* with REX.B added in.
5141	*
5142	* For use during decoding.
5143	*
5144	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5145	*/
5146	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5147	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5148	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5149	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5150
5151	/**
5152	* Combines the prefix REX and ModR/M byte for passing to
5153	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5154	*
5155	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5156	* The two bits are part of the REG sub-field, which isn't needed in
5157	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5158	*
5159	* For use during decoding/recompiling.
5160	*/
5161	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5162	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5163	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5164	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5165	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5166
5167	/**
5168	* Gets the effective VEX.VVVV value.
5169	*
5170	* The 4th bit is ignored if not 64-bit code.
5171	* @returns effective V-register value.
5172	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5173	*/
5174	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5175	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5176
5177
5178	/**
5179	* Gets the register (reg) part of a the special 4th register byte used by
5180	* vblendvps and vblendvpd.
5181	*
5182	* For use during decoding.
5183	*/
5184	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5185	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5186
5187
5188	/**
5189	* Checks if we're executing inside an AMD-V or VT-x guest.
5190	*/
5191	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5192	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5193	#else
5194	# define IEM_IS_IN_GUEST(a_pVCpu) false
5195	#endif
5196
5197
5198	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5199
5200	/**
5201	* Check if the guest has entered VMX root operation.
5202	*/
5203	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5204
5205	/**
5206	* Check if the guest has entered VMX non-root operation.
5207	*/
5208	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5209	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5210
5211	/**
5212	* Check if the nested-guest has the given Pin-based VM-execution control set.
5213	*/
5214	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5215
5216	/**
5217	* Check if the nested-guest has the given Processor-based VM-execution control set.
5218	*/
5219	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5220
5221	/**
5222	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5223	* control set.
5224	*/
5225	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5226
5227	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5228	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5229
5230	/** Whether a shadow VMCS is present for the given VCPU. */
5231	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5232
5233	/** Gets the VMXON region pointer. */
5234	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5235
5236	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5237	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5238
5239	/** Whether a current VMCS is present for the given VCPU. */
5240	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5241
5242	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5243	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5244	do \
5245	{ \
5246	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5247	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5248	} while (0)
5249
5250	/** Clears any current VMCS for the given VCPU. */
5251	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5252	do \
5253	{ \
5254	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5255	} while (0)
5256
5257	/**
5258	* Invokes the VMX VM-exit handler for an instruction intercept.
5259	*/
5260	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5261	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5262
5263	/**
5264	* Invokes the VMX VM-exit handler for an instruction intercept where the
5265	* instruction provides additional VM-exit information.
5266	*/
5267	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5268	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5269
5270	/**
5271	* Invokes the VMX VM-exit handler for a task switch.
5272	*/
5273	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5274	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5275
5276	/**
5277	* Invokes the VMX VM-exit handler for MWAIT.
5278	*/
5279	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5280	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5281
5282	/**
5283	* Invokes the VMX VM-exit handler for EPT faults.
5284	*/
5285	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5286	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5287
5288	/**
5289	* Invokes the VMX VM-exit handler.
5290	*/
5291	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5292	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5293
5294	#else
5295	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5296	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5297	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5298	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5299	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5300	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5301	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5302	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5303	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5304	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5305	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5306
5307	#endif
5308
5309	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5310	/**
5311	* Checks if we're executing a guest using AMD-V.
5312	*/
5313	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5314	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5315	/**
5316	* Check if an SVM control/instruction intercept is set.
5317	*/
5318	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5319	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5320
5321	/**
5322	* Check if an SVM read CRx intercept is set.
5323	*/
5324	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5325	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5326
5327	/**
5328	* Check if an SVM write CRx intercept is set.
5329	*/
5330	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5331	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5332
5333	/**
5334	* Check if an SVM read DRx intercept is set.
5335	*/
5336	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5337	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5338
5339	/**
5340	* Check if an SVM write DRx intercept is set.
5341	*/
5342	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5343	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5344
5345	/**
5346	* Check if an SVM exception intercept is set.
5347	*/
5348	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5349	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5350
5351	/**
5352	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5353	*/
5354	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5355	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5356
5357	/**
5358	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5359	* corresponding decode assist information.
5360	*/
5361	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5362	do \
5363	{ \
5364	uint64_t uExitInfo1; \
5365	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5366	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5367	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5368	else \
5369	uExitInfo1 = 0; \
5370	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5371	} while (0)
5372
5373	/** Check and handles SVM nested-guest instruction intercept and updates
5374	* NRIP if needed.
5375	*/
5376	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5377	do \
5378	{ \
5379	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5380	{ \
5381	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5382	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5383	} \
5384	} while (0)
5385
5386	/** Checks and handles SVM nested-guest CR0 read intercept. */
5387	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5388	do \
5389	{ \
5390	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5391	{ /* probably likely */ } \
5392	else \
5393	{ \
5394	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5395	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5396	} \
5397	} while (0)
5398
5399	/**
5400	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5401	*/
5402	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5403	do { \
5404	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5405	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5406	} while (0)
5407
5408	#else
5409	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5410	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5411	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5412	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5413	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5414	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5415	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5416	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5417	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5418	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5419	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5420	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5421
5422	#endif
5423
5424	/** @} */
5425
5426	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5427	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5428
5429
5430	/**
5431	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5432	*/
5433	typedef union IEMSELDESC
5434	{
5435	/** The legacy view. */
5436	X86DESC Legacy;
5437	/** The long mode view. */
5438	X86DESC64 Long;
5439	} IEMSELDESC;
5440	/** Pointer to a selector descriptor table entry. */
5441	typedef IEMSELDESC *PIEMSELDESC;
5442
5443	/** @name Raising Exceptions.
5444	* @{ */
5445	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5446	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5447
5448	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5449	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5450	#ifdef IEM_WITH_SETJMP
5451	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5452	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5453	#endif
5454	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5455	#ifdef IEM_WITH_SETJMP
5456	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5457	#endif
5458	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5459	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5460	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5461	#ifdef IEM_WITH_SETJMP
5462	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5463	#endif
5464	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5465	#ifdef IEM_WITH_SETJMP
5466	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5467	#endif
5468	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5469	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5470	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5471	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5472	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5473	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5474	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5475	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5476	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5477	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5478	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5479	#ifdef IEM_WITH_SETJMP
5480	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5481	#endif
5482	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5483	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5484	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5485	#ifdef IEM_WITH_SETJMP
5486	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5487	#endif
5488	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5489	#ifdef IEM_WITH_SETJMP
5490	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5491	#endif
5492	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5493	#ifdef IEM_WITH_SETJMP
5494	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5495	#endif
5496	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5497	#ifdef IEM_WITH_SETJMP
5498	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5499	#endif
5500	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5501	#ifdef IEM_WITH_SETJMP
5502	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5503	#endif
5504	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5505	#ifdef IEM_WITH_SETJMP
5506	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5507	#endif
5508	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5509	#ifdef IEM_WITH_SETJMP
5510	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5511	#endif
5512
5513	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5514	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5515
5516	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5517	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5518	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5519
5520	/**
5521	* Macro for calling iemCImplRaiseDivideError().
5522	*
5523	* This is for things that will _always_ decode to an \#DE, taking the
5524	* recompiler into consideration and everything.
5525	*
5526	* @return Strict VBox status code.
5527	*/
5528	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
5529
5530	/**
5531	* Macro for calling iemCImplRaiseInvalidLockPrefix().
5532	*
5533	* This is for things that will _always_ decode to an \#UD, taking the
5534	* recompiler into consideration and everything.
5535	*
5536	* @return Strict VBox status code.
5537	*/
5538	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
5539
5540	/**
5541	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5542	*
5543	* This is for things that will _always_ decode to an \#UD, taking the
5544	* recompiler into consideration and everything.
5545	*
5546	* @return Strict VBox status code.
5547	*/
5548	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5549
5550	/**
5551	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5552	*
5553	* Using this macro means you've got _buggy_ _code_ and are doing things that
5554	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5555	*
5556	* @return Strict VBox status code.
5557	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5558	*/
5559	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5560
5561	/** @} */
5562
5563	/** @name Register Access.
5564	* @{ */
5565	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5566	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5567	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5568	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5569	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5570	/** @} */
5571
5572	/** @name FPU access and helpers.
5573	* @{ */
5574	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5575	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5576	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5577	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5578	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5579	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5580	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5581	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5582	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5583	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5584	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5585	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5586	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5587	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5588	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5589	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5590	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5591	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5592	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5593	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5594	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5595	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5596	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5597	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5598	/** @} */
5599
5600	/** @name SSE+AVX SIMD access and helpers.
5601	* @{ */
5602	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5603	/** @} */
5604
5605	/** @name Memory access.
5606	* @{ */
5607
5608	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5609	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5610	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5611	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5612	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5613	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5614	* Users include FXSAVE & FXRSTOR. */
5615	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5616
5617	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5618	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5619	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5620	#ifndef IN_RING3
5621	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5622	#endif
5623	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5624	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5625	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5626	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5627	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5628
5629	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5630	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5631	#ifdef IEM_WITH_CODE_TLB
5632	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5633	#else
5634	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5635	#endif
5636	#ifdef IEM_WITH_SETJMP
5637	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5638	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5639	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5640	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5641	#else
5642	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5643	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5644	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5645	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5646	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5647	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5648	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5649	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5650	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5651	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5652	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5653	#endif
5654
5655	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5656	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5657	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5658	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5659	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5660	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5661	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5662	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5663	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5664	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5665	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5666	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5667	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5668	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5669	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5670	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5671	#ifdef IEM_WITH_SETJMP
5672	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5673	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5674	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5675	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5676	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5677	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5678	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5679	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5680	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5681	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5682	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5683	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5684	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5685	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5686	# if 0 /* these are inlined now */
5687	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5688	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5689	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5690	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5691	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5692	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5693	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5694	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5695	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5696	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5697	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5698	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5699	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5700	# endif
5701	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5702	#endif
5703
5704	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5705	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5706	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5707	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5708	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5709
5710	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5711	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5712	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5713	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5714	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5715	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5716	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5717	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5718	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5719	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5720	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5721	#ifdef IEM_WITH_SETJMP
5722	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5723	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5724	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5725	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5726	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5727	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5728	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5729	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5730	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5731	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5732	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5733	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5734	#if 0
5735	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5736	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5737	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5738	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5739	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5740	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5741	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5742	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5743	#endif
5744	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5745	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5746	#endif
5747
5748	#ifdef IEM_WITH_SETJMP
5749	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5750	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5751	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5752	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5753	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5754	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5755	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5756	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5757	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5758	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5759	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5760	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5761	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5762	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5763	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5764	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5765	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5766	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5767	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5768	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5769	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5770	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5771	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5772	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5773	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5774	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5775
5776	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5777	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5778	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5779	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5780	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5781	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5782	#endif
5783
5784	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5785	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5786	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5787	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5788	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5789	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5790	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5791	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5792	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5793	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5794	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5795	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5796	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5797	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5798	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5799	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5800	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5801	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5802	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5803	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5804	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5805
5806	#ifdef IEM_WITH_SETJMP
5807	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5808	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5809	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5810	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5811	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5812	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5813	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5814
5815	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5816	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5817	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5818	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5819	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5820
5821	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5822	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5823	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5824	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5825
5826	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5827	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5828	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5829	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5830
5831	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5832	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5833	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5834
5835	#endif
5836
5837	/** @} */
5838
5839	/** @name IEMAllCImpl.cpp
5840	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5841	* @{ */
5842	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5843	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5844	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5845	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5846	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5847	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5848	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5849	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5850	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5851	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5852	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5853	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5854	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5855	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5856	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5857	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5858	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5859	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5860	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5861	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5862	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5863	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5864	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5865	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5866	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5867	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5868	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5869	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5870	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5871	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5872	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5873	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5874	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5875	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5876	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5877	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5878	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5879	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5880	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5881	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5882	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5883	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5884	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5885	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5886	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5887	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5888	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5889	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5890	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5891	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5892	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5893	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5894	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5895	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5896	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5897	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5898	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5899	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5900	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5901	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5902	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5903	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5904	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5905	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5906	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5907	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5908	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5909	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5910	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5911	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5912	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5913	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5914	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5915	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5916	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5917	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5918	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5919	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5920	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5921	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5922	IEM_CIMPL_PROTO_0(iemCImpl_das);
5923	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5924	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5925	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5926	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5927	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5928	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5929	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5930	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
5931	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5932	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5933	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5934	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5935	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5936	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5937	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5938	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5939	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5940	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5941	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5942	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5943	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5944	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5945	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5946	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5947	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5948	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5949	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5950	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5951	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
5952	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
5953	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5954	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5955	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
5956	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
5957	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5958	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5959	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
5960	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
5961	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5962	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5963	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
5964	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
5965
5966	/** @} */
5967
5968	/** @name IEMAllCImplStrInstr.cpp.h
5969	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5970	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5971	* @{ */
5972	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5973	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5974	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5975	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5976	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5977	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5978	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5979	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5980	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5981	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5982	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5983
5984	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5985	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5986	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5987	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5988	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5989	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5990	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5991	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5992	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5993	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5994	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5995
5996	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5997	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5998	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5999	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6000	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6001	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6002	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6003	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6004	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6005	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6006	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6007
6008
6009	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6010	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6011	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6012	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6013	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6014	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6015	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6016	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6017	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6018	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6019	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6020
6021	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6022	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6023	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6024	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6025	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6026	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6027	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6028	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6029	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6030	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6031	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6032
6033	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6034	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6035	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6036	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6037	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6038	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6039	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6040	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6041	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6042	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6043	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6044
6045	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6046	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6047	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6048	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6049	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6050	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6051	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6052	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6053	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6054	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6055	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6056
6057
6058	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6059	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6060	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6061	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6062	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6063	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6064	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6065	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6066	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6067	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6068	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6069
6070	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6071	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6072	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6073	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6074	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6075	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6076	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6077	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6078	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6079	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6080	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6081
6082	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6083	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6084	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6085	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6086	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6087	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6088	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6089	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6090	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6091	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6092	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6093
6094	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6095	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6096	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6097	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6098	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6099	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6100	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6101	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6102	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6103	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6104	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6105	/** @} */
6106
6107	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6108	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6109	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6110	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6111	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6112	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6113	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6114	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6115	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6116	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6117	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6118	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6119	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6120	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6121	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6122	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6123	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6124	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6125	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6126	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6127	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6128	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6129	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6130	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6131	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6132	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6133	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6134	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6135	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6136	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6137	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6138	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6139	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6140	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6141	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6142	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6143	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6144	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6145	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6146	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6147	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6148	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6149	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6150	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6151	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6152	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6153	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6154	#endif
6155
6156	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6157	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6158	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6159	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6160	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6161	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6162	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6163	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6164	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6165	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6166	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6167	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6168	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6169	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6170	#endif
6171
6172	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6173	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6174	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6175
6176	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6177	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6178	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6179	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6180	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6181	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6182	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6183
6184	/*
6185	* Recompiler related stuff.
6186	*/
6187	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6188	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6189	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6190	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6191	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6192	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6193	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6194
6195	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6196	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6197	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6198	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6199	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6200	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6201	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6202	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6203
6204
6205	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6206	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6207	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6208	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6209	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6210	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6211	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6212	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6213
6214	#else
6215	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6216	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6217	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6218	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6219	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6220	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6221	#endif
6222
6223
6224	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6225	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6226
6227	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6228
6229	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6230	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6231	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6232	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6233
6234	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6235	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6236	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6237
6238	/* Branching: */
6239	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6240	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6241	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6242
6243	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6244	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6245	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6246
6247	/* Natural page crossing: */
6248	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6249	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6250	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6251
6252	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6253	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6254	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6255
6256	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6257	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6258	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6259
6260	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6261	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6262
6263	/* Native recompiler public bits: */
6264	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6265	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6266	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6267	DECLHIDDEN(void ) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, void *ppvExec) RT_NOEXCEPT;
6268	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6269	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6270	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6271
6272	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6273
6274
6275	/** @} */
6276
6277	RT_C_DECLS_END
6278
6279	/* ASM-INC: %include "IEMInternalStruct.mac" */
6280
6281	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6282

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 104932

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