IEMInternal.h@ 100931

Last change on this file since 100931 was 100889, checked in by vboxsync, 21 months ago
VMM/IEM: Adjusted IEM_MC_CALL_CIMPL_HLP_RET assertion to account for fExec not including the FLAT 32-bit flag if DS, ES or SS state is stored externally (HM, NEM). bugref:10369
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File size: 266.3 KB

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1	/* $Id: IEMInternal.h 100889 2023-08-16 22:31:44Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41	#include <iprt/list.h>
42
43
44	RT_C_DECLS_BEGIN
45
46
47	/** @defgroup grp_iem_int Internals
48	* @ingroup grp_iem
49	* @internal
50	* @{
51	*/
52
53	/** For expanding symbol in slickedit and other products tagging and
54	* crossreferencing IEM symbols. */
55	#ifndef IEM_STATIC
56	# define IEM_STATIC static
57	#endif
58
59	/** @def IEM_WITH_SETJMP
60	* Enables alternative status code handling using setjmps.
61	*
62	* This adds a bit of expense via the setjmp() call since it saves all the
63	* non-volatile registers. However, it eliminates return code checks and allows
64	* for more optimal return value passing (return regs instead of stack buffer).
65	*/
66	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
67	# define IEM_WITH_SETJMP
68	#endif
69
70	/** @def IEM_WITH_THROW_CATCH
71	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72	* mode code when IEM_WITH_SETJMP is in effect.
73	*
74	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76	* result value improving by more than 1%. (Best out of three.)
77	*
78	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81	* Linux, but it should be quite a bit faster for normal code.
82	*/
83	#if (defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
84	\|\| defined(DOXYGEN_RUNNING)
85	# define IEM_WITH_THROW_CATCH
86	#endif
87
88	/** @def IEM_DO_LONGJMP
89	*
90	* Wrapper around longjmp / throw.
91	*
92	* @param a_pVCpu The CPU handle.
93	* @param a_rc The status code jump back with / throw.
94	*/
95	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
96	# ifdef IEM_WITH_THROW_CATCH
97	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
98	# else
99	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
100	# endif
101	#endif
102
103	/** For use with IEM function that may do a longjmp (when enabled).
104	*
105	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
106	* attribute. So, we indicate that function that may be part of a longjmp may
107	* throw "exceptions" and that the compiler should definitely not generate and
108	* std::terminate calling unwind code.
109	*
110	* Here is one example of this ending in std::terminate:
111	* @code{.txt}
112	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
113	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
114	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
115	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
116	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
117	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
118	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
119	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
120	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
121	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
122	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
123	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
124	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
125	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
126	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
127	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
128	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
129	@endcode
130	*
131	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
132	*/
133	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
134	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
135	#else
136	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
137	#endif
138
139	#define IEM_IMPLEMENTS_TASKSWITCH
140
141	/** @def IEM_WITH_3DNOW
142	* Includes the 3DNow decoding. */
143	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
144	# define IEM_WITH_3DNOW
145	#endif
146
147	/** @def IEM_WITH_THREE_0F_38
148	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
149	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
150	# define IEM_WITH_THREE_0F_38
151	#endif
152
153	/** @def IEM_WITH_THREE_0F_3A
154	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
155	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
156	# define IEM_WITH_THREE_0F_3A
157	#endif
158
159	/** @def IEM_WITH_VEX
160	* Includes the VEX decoding. */
161	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
162	# define IEM_WITH_VEX
163	#endif
164
165	/** @def IEM_CFG_TARGET_CPU
166	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
167	*
168	* By default we allow this to be configured by the user via the
169	* CPUM/GuestCpuName config string, but this comes at a slight cost during
170	* decoding. So, for applications of this code where there is no need to
171	* be dynamic wrt target CPU, just modify this define.
172	*/
173	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
174	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
175	#endif
176
177	//#define IEM_WITH_CODE_TLB // - work in progress
178	//#define IEM_WITH_DATA_TLB // - work in progress
179
180
181	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
182	* Use unaligned accesses instead of elaborate byte assembly. */
183	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
184	# define IEM_USE_UNALIGNED_DATA_ACCESS
185	#endif
186
187	//#define IEM_LOG_MEMORY_WRITES
188
189	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
190	/** Instruction statistics. */
191	typedef struct IEMINSTRSTATS
192	{
193	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
194	# include "IEMInstructionStatisticsTmpl.h"
195	# undef IEM_DO_INSTR_STAT
196	} IEMINSTRSTATS;
197	#else
198	struct IEMINSTRSTATS;
199	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
200	#endif
201	/** Pointer to IEM instruction statistics. */
202	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
203
204
205	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
206	* @{ */
207	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
211	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
212	/** Selects the right variant from a_aArray.
213	* pVCpu is implicit in the caller context. */
214	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
215	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
216	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
217	* be used because the host CPU does not support the operation. */
218	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
219	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
220	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
221	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
222	* into the two.
223	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
224	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
225	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
226	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
227	#else
228	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
229	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
230	#endif
231	/** @} */
232
233	/**
234	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
235	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
236	*
237	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
238	* indicator.
239	*
240	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
241	*/
242	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
243	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
244	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
245	#else
246	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
247	#endif
248
249
250	/**
251	* Extended operand mode that includes a representation of 8-bit.
252	*
253	* This is used for packing down modes when invoking some C instruction
254	* implementations.
255	*/
256	typedef enum IEMMODEX
257	{
258	IEMMODEX_16BIT = IEMMODE_16BIT,
259	IEMMODEX_32BIT = IEMMODE_32BIT,
260	IEMMODEX_64BIT = IEMMODE_64BIT,
261	IEMMODEX_8BIT
262	} IEMMODEX;
263	AssertCompileSize(IEMMODEX, 4);
264
265
266	/**
267	* Branch types.
268	*/
269	typedef enum IEMBRANCH
270	{
271	IEMBRANCH_JUMP = 1,
272	IEMBRANCH_CALL,
273	IEMBRANCH_TRAP,
274	IEMBRANCH_SOFTWARE_INT,
275	IEMBRANCH_HARDWARE_INT
276	} IEMBRANCH;
277	AssertCompileSize(IEMBRANCH, 4);
278
279
280	/**
281	* INT instruction types.
282	*/
283	typedef enum IEMINT
284	{
285	/** INT n instruction (opcode 0xcd imm). */
286	IEMINT_INTN = 0,
287	/** Single byte INT3 instruction (opcode 0xcc). */
288	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
289	/** Single byte INTO instruction (opcode 0xce). */
290	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
291	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
292	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
293	} IEMINT;
294	AssertCompileSize(IEMINT, 4);
295
296
297	/**
298	* A FPU result.
299	*/
300	typedef struct IEMFPURESULT
301	{
302	/** The output value. */
303	RTFLOAT80U r80Result;
304	/** The output status. */
305	uint16_t FSW;
306	} IEMFPURESULT;
307	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
308	/** Pointer to a FPU result. */
309	typedef IEMFPURESULT *PIEMFPURESULT;
310	/** Pointer to a const FPU result. */
311	typedef IEMFPURESULT const *PCIEMFPURESULT;
312
313
314	/**
315	* A FPU result consisting of two output values and FSW.
316	*/
317	typedef struct IEMFPURESULTTWO
318	{
319	/** The first output value. */
320	RTFLOAT80U r80Result1;
321	/** The output status. */
322	uint16_t FSW;
323	/** The second output value. */
324	RTFLOAT80U r80Result2;
325	} IEMFPURESULTTWO;
326	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
327	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
328	/** Pointer to a FPU result consisting of two output values and FSW. */
329	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
330	/** Pointer to a const FPU result consisting of two output values and FSW. */
331	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
332
333
334	/**
335	* IEM TLB entry.
336	*
337	* Lookup assembly:
338	* @code{.asm}
339	; Calculate tag.
340	mov rax, [VA]
341	shl rax, 16
342	shr rax, 16 + X86_PAGE_SHIFT
343	or rax, [uTlbRevision]
344
345	; Do indexing.
346	movzx ecx, al
347	lea rcx, [pTlbEntries + rcx]
348
349	; Check tag.
350	cmp [rcx + IEMTLBENTRY.uTag], rax
351	jne .TlbMiss
352
353	; Check access.
354	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
355	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
356	cmp rax, [uTlbPhysRev]
357	jne .TlbMiss
358
359	; Calc address and we're done.
360	mov eax, X86_PAGE_OFFSET_MASK
361	and eax, [VA]
362	or rax, [rcx + IEMTLBENTRY.pMappingR3]
363	%ifdef VBOX_WITH_STATISTICS
364	inc qword [cTlbHits]
365	%endif
366	jmp .Done
367
368	.TlbMiss:
369	mov r8d, ACCESS_FLAGS
370	mov rdx, [VA]
371	mov rcx, [pVCpu]
372	call iemTlbTypeMiss
373	.Done:
374
375	@endcode
376	*
377	*/
378	typedef struct IEMTLBENTRY
379	{
380	/** The TLB entry tag.
381	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
382	* is ASSUMING a virtual address width of 48 bits.
383	*
384	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
385	*
386	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
387	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
388	* revision wraps around though, the tags needs to be zeroed.
389	*
390	* @note Try use SHRD instruction? After seeing
391	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
392	*
393	* @todo This will need to be reorganized for 57-bit wide virtual address and
394	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
395	* have to move the TLB entry versioning entirely to the
396	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
397	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
398	* consumed by PCID and ASID (12 + 6 = 18).
399	*/
400	uint64_t uTag;
401	/** Access flags and physical TLB revision.
402	*
403	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
404	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
405	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
406	* - Bit 3 - pgm phys/virt - not directly writable.
407	* - Bit 4 - pgm phys page - not directly readable.
408	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
409	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
410	* - Bit 7 - tlb entry - pMappingR3 member not valid.
411	* - Bits 63 thru 8 are used for the physical TLB revision number.
412	*
413	* We're using complemented bit meanings here because it makes it easy to check
414	* whether special action is required. For instance a user mode write access
415	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
416	* non-zero result would mean special handling needed because either it wasn't
417	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
418	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
419	* need to check any PTE flag.
420	*/
421	uint64_t fFlagsAndPhysRev;
422	/** The guest physical page address. */
423	uint64_t GCPhys;
424	/** Pointer to the ring-3 mapping. */
425	R3PTRTYPE(uint8_t *) pbMappingR3;
426	#if HC_ARCH_BITS == 32
427	uint32_t u32Padding1;
428	#endif
429	} IEMTLBENTRY;
430	AssertCompileSize(IEMTLBENTRY, 32);
431	/** Pointer to an IEM TLB entry. */
432	typedef IEMTLBENTRY *PIEMTLBENTRY;
433
434	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
435	* @{ */
436	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
437	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
438	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
439	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
440	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
441	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
442	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
443	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
444	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
445	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
446	/** @} */
447
448
449	/**
450	* An IEM TLB.
451	*
452	* We've got two of these, one for data and one for instructions.
453	*/
454	typedef struct IEMTLB
455	{
456	/** The TLB entries.
457	* We've choosen 256 because that way we can obtain the result directly from a
458	* 8-bit register without an additional AND instruction. */
459	IEMTLBENTRY aEntries[256];
460	/** The TLB revision.
461	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
462	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
463	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
464	* (The revision zero indicates an invalid TLB entry.)
465	*
466	* The initial value is choosen to cause an early wraparound. */
467	uint64_t uTlbRevision;
468	/** The TLB physical address revision - shadow of PGM variable.
469	*
470	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
471	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
472	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
473	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
474	*
475	* The initial value is choosen to cause an early wraparound. */
476	uint64_t volatile uTlbPhysRev;
477
478	/* Statistics: */
479
480	/** TLB hits (VBOX_WITH_STATISTICS only). */
481	uint64_t cTlbHits;
482	/** TLB misses. */
483	uint32_t cTlbMisses;
484	/** Slow read path. */
485	uint32_t cTlbSlowReadPath;
486	/** Safe read path. */
487	uint32_t cTlbSafeReadPath;
488	/** Safe write path. */
489	uint32_t cTlbSafeWritePath;
490	#if 0
491	/** TLB misses because of tag mismatch. */
492	uint32_t cTlbMissesTag;
493	/** TLB misses because of virtual access violation. */
494	uint32_t cTlbMissesVirtAccess;
495	/** TLB misses because of dirty bit. */
496	uint32_t cTlbMissesDirty;
497	/** TLB misses because of MMIO */
498	uint32_t cTlbMissesMmio;
499	/** TLB misses because of write access handlers. */
500	uint32_t cTlbMissesWriteHandler;
501	/** TLB misses because no r3(/r0) mapping. */
502	uint32_t cTlbMissesMapping;
503	#endif
504	/** Alignment padding. */
505	uint32_t au32Padding[6];
506	} IEMTLB;
507	AssertCompileSizeAlignment(IEMTLB, 64);
508	/** IEMTLB::uTlbRevision increment. */
509	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
510	/** IEMTLB::uTlbRevision mask. */
511	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
512	/** IEMTLB::uTlbPhysRev increment.
513	* @sa IEMTLBE_F_PHYS_REV */
514	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
515	/**
516	* Calculates the TLB tag for a virtual address.
517	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
518	* @param a_pTlb The TLB.
519	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
520	* the clearing of the top 16 bits won't work (if 32-bit
521	* we'll end up with mostly zeros).
522	*/
523	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
524	/**
525	* Calculates the TLB tag for a virtual address but without TLB revision.
526	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
527	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
528	* the clearing of the top 16 bits won't work (if 32-bit
529	* we'll end up with mostly zeros).
530	*/
531	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
532	/**
533	* Converts a TLB tag value into a TLB index.
534	* @returns Index into IEMTLB::aEntries.
535	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
536	*/
537	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
538	/**
539	* Converts a TLB tag value into a TLB index.
540	* @returns Index into IEMTLB::aEntries.
541	* @param a_pTlb The TLB.
542	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
543	*/
544	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
545
546
547	/** @name IEM_MC_F_XXX - MC block flags/clues.
548	* @{ */
549	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
550	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
551	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
552	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
553	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
554	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
555	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
556	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
557	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
558	#define IEM_MC_F_64BIT RT_BIT_32(6)
559	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
560	/** @} */
561
562
563	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
564	*
565	* These flags are set when entering IEM and adjusted as code is executed, such
566	* that they will always contain the current values as instructions are
567	* finished.
568	*
569	* In recompiled execution mode, (most of) these flags are included in the
570	* translation block selection key and stored in IEMTB::fFlags alongside the
571	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
572	* in IEMCPU::fExec.
573	*
574	* @{ */
575	/** Mode: The block target mode mask. */
576	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
577	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
578	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
579	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
580	* conditional in EIP/IP updating), and flat wide open CS, SS DS, and ES in
581	* 32-bit mode (for simplifying most memory accesses). */
582	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
583	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
584	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
585	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
586	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
587
588	/** X86 Mode: 16-bit on 386 or later. */
589	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
590	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
591	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
592	/** X86 Mode: 16-bit protected mode on 386 or later. */
593	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
594	/** X86 Mode: 16-bit protected mode on 386 or later. */
595	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
596	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
597	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
598
599	/** X86 Mode: 32-bit on 386 or later. */
600	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
601	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
602	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
603	/** X86 Mode: 32-bit protected mode. */
604	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
605	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
606	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
607
608	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
609	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
610
611
612	/** Bypass access handlers when set. */
613	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
614	/** Have pending hardware instruction breakpoints. */
615	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
616	/** Have pending hardware data breakpoints. */
617	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
618
619	/** X86: Have pending hardware I/O breakpoints. */
620	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
621	/** X86: Disregard the lock prefix (implied or not) when set. */
622	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
623
624	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
625	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
626
627	/** Caller configurable options. */
628	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
629
630	/** X86: The current protection level (CPL) shift factor. */
631	#define IEM_F_X86_CPL_SHIFT 8
632	/** X86: The current protection level (CPL) mask. */
633	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
634	/** X86: The current protection level (CPL) shifted mask. */
635	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
636
637	/** X86 execution context.
638	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
639	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
640	* mode. */
641	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
642	/** X86 context: Plain regular execution context. */
643	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
644	/** X86 context: VT-x enabled. */
645	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
646	/** X86 context: AMD-V enabled. */
647	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
648	/** X86 context: In AMD-V or VT-x guest mode. */
649	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
650	/** X86 context: System management mode (SMM). */
651	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
652
653	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
654	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
655	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
656	* alread). */
657
658	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
659	* iemRegFinishClearingRF() most for most situations
660	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
661	* the IEM_F_PENDING_BRK_XXX bits alread). */
662
663	/** @} */
664
665
666	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
667	*
668	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
669	* translation block flags. The combined flag mask (subject to
670	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
671	*
672	* @{ */
673	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
674	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
675
676	/** Type: The block type mask. */
677	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
678	/** Type: Purly threaded recompiler (via tables). */
679	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
680	/** Type: Native recompilation. */
681	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
682
683	/** State mask. */
684	#define IEMTB_F_STATE_MASK UINT32_C(0x0c000000)
685	/** State shift count. */
686	#define IEMTB_F_STATE_SHIFT 26
687	/** State: Compiling. */
688	#define IEMTB_F_STATE_COMPILING UINT32_C(0x04000000)
689	/** State: Ready. */
690	#define IEMTB_F_STATE_READY UINT32_C(0x08000000)
691	/** State: Obsolete, can be deleted when we're sure it's not used any longer. */
692	#define IEMTB_F_STATE_OBSOLETE UINT32_C(0x0c000000)
693
694	/** Set when we're starting the block in an "interrupt shadow".
695	* We don't need to distingish between the two types of this mask, thus the one.
696	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
697	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x10000000)
698	/** Set when we're currently inhibiting NMIs
699	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
700	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x20000000)
701
702	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
703	* we're close the limit before starting a TB, as determined by
704	* iemGetTbFlagsForCurrentPc(). */
705	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x40000000)
706
707	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
708	* @note We skip the CPL as we don't currently generate ring-specific code,
709	* that's all handled in CIMPL functions.
710	*
711	* For the same reasons, we skip all of IEM_F_X86_CTX_MASK, with the
712	* exception of SMM (which we don't implement). */
713	#define IEMTB_F_KEY_MASK ((UINT32_C(0xffffffff) & ~(IEM_F_X86_CTX_MASK \| IEM_F_X86_CPL_MASK)) \| IEM_F_X86_CTX_SMM)
714	/** @} */
715
716	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
717	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
718	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
719	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
720	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
721	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
722	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
723	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
724	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
725	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
726	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
727	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
728	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
729	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
730	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
731	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
732	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
733	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
734	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
735
736	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
737	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
738	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
739	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
740	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
741	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
742	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
743	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
744	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
745	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
746	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
747	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
748
749	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
750	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
751	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
752
753	/**
754	* A call for the threaded call table.
755	*/
756	typedef struct IEMTHRDEDCALLENTRY
757	{
758	/** The function to call (IEMTHREADEDFUNCS). */
759	uint16_t enmFunction;
760	/** Instruction number in the TB (for statistics). */
761	uint8_t idxInstr;
762	uint8_t uUnused0;
763
764	/** Offset into IEMTB::pabOpcodes. */
765	uint16_t offOpcode;
766	/** The opcode length. */
767	uint8_t cbOpcode;
768	/** Index in to IEMTB::aRanges. */
769	uint8_t idxRange;
770
771	/** Generic parameters. */
772	uint64_t auParams[3];
773	} IEMTHRDEDCALLENTRY;
774	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
775	/** Pointer to a threaded call entry. */
776	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
777	/** Pointer to a const threaded call entry. */
778	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
779
780	/**
781	* Translation block.
782	*/
783	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
784	typedef struct IEMTB
785	{
786	/** Next block with the same hash table entry. */
787	struct IEMTB * volatile pNext;
788	/** List on the local VCPU for blocks. */
789	RTLISTNODE LocalList;
790
791	/** @name What uniquely identifies the block.
792	* @{ */
793	RTGCPHYS GCPhysPc;
794	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
795	uint32_t fFlags;
796	union
797	{
798	struct
799	{
800	/*< Relevant CS X86DESCATTR_XXX bits. /
801	uint16_t fAttr;
802	} x86;
803	};
804	/** @} */
805
806	/** Number of opcode ranges. */
807	uint8_t cRanges;
808	/** Statistics: Number of instructions in the block. */
809	uint8_t cInstructions;
810
811	/** Type specific info. */
812	union
813	{
814	struct
815	{
816	/** The call sequence table. */
817	PIEMTHRDEDCALLENTRY paCalls;
818	/** Number of calls in paCalls. */
819	uint16_t cCalls;
820	/** Number of calls allocated. */
821	uint16_t cAllocated;
822	} Thrd;
823	};
824
825	/** Number of bytes of opcodes stored in pabOpcodes. */
826	uint16_t cbOpcodes;
827	/** The max storage available in the pabOpcodes block. */
828	uint16_t cbOpcodesAllocated;
829	/** Pointer to the opcode bytes this block was recompiled from. */
830	uint8_t *pabOpcodes;
831
832	/* --- 64 byte cache line end --- */
833
834	/** Opcode ranges.
835	*
836	* The opcode checkers and maybe TLB loading functions will use this to figure
837	* out what to do. The parameter will specify an entry and the opcode offset to
838	* start at and the minimum number of bytes to verify (instruction length).
839	*
840	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
841	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
842	* code TLB (must have a valid entry for that address) and scan the ranges to
843	* locate the corresponding opcodes. Probably.
844	*/
845	struct IEMTBOPCODERANGE
846	{
847	/** Offset within pabOpcodes. */
848	uint16_t offOpcodes;
849	/** Number of bytes. */
850	uint16_t cbOpcodes;
851	/** The page offset. */
852	RT_GCC_EXTENSION
853	uint16_t offPhysPage : 12;
854	/** Unused bits. */
855	RT_GCC_EXTENSION
856	uint16_t u2Unused : 2;
857	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
858	RT_GCC_EXTENSION
859	uint16_t idxPhysPage : 2;
860	} aRanges[8];
861
862	/** Physical pages that this TB covers.
863	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
864	RTGCPHYS aGCPhysPages[2];
865	} IEMTB;
866	#pragma pack()
867	AssertCompileMemberOffset(IEMTB, x86, 36);
868	AssertCompileMemberOffset(IEMTB, cRanges, 38);
869	AssertCompileMemberOffset(IEMTB, Thrd, 40);
870	AssertCompileMemberOffset(IEMTB, Thrd.cCalls, 48);
871	AssertCompileMemberOffset(IEMTB, cbOpcodes, 52);
872	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
873	AssertCompileSize(IEMTB, 128);
874	/** Pointer to a translation block. */
875	typedef IEMTB *PIEMTB;
876	/** Pointer to a const translation block. */
877	typedef IEMTB const *PCIEMTB;
878
879	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
880	*
881	* These flags parallels IEM_CIMPL_F_BRANCH_XXX.
882	*
883	* @{ */
884	/** Value if no branching happened recently. */
885	#define IEMBRANCHED_F_NO UINT8_C(0x00)
886	/** Flag set if direct branch, clear if absolute or indirect. */
887	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
888	/** Flag set if indirect branch, clear if direct or relative. */
889	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
890	/** Flag set if relative branch, clear if absolute or indirect. */
891	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
892	/** Flag set if conditional branch, clear if unconditional. */
893	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
894	/** Flag set if it's a far branch. */
895	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
896	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
897	#define IEMBRANCHED_F_ZERO UINT8_C(0x20)
898	/** @} */
899
900
901	/**
902	* The per-CPU IEM state.
903	*/
904	typedef struct IEMCPU
905	{
906	/** Info status code that needs to be propagated to the IEM caller.
907	* This cannot be passed internally, as it would complicate all success
908	* checks within the interpreter making the code larger and almost impossible
909	* to get right. Instead, we'll store status codes to pass on here. Each
910	* source of these codes will perform appropriate sanity checks. */
911	int32_t rcPassUp; /* 0x00 */
912	/** Execution flag, IEM_F_XXX. */
913	uint32_t fExec; /* 0x04 */
914
915	/** @name Decoder state.
916	* @{ */
917	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
918	# ifdef IEM_WITH_CODE_TLB
919	/** The offset of the next instruction byte. */
920	uint32_t offInstrNextByte; /* 0x08 */
921	/** The number of bytes available at pbInstrBuf for the current instruction.
922	* This takes the max opcode length into account so that doesn't need to be
923	* checked separately. */
924	uint32_t cbInstrBuf; /* 0x0c */
925	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
926	* This can be NULL if the page isn't mappable for some reason, in which
927	* case we'll do fallback stuff.
928	*
929	* If we're executing an instruction from a user specified buffer,
930	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
931	* aligned pointer but pointer to the user data.
932	*
933	* For instructions crossing pages, this will start on the first page and be
934	* advanced to the next page by the time we've decoded the instruction. This
935	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
936	*/
937	uint8_t const pbInstrBuf; / 0x10 */
938	# if ARCH_BITS == 32
939	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
940	# endif
941	/** The program counter corresponding to pbInstrBuf.
942	* This is set to a non-canonical address when we need to invalidate it. */
943	uint64_t uInstrBufPc; /* 0x18 */
944	/** The guest physical address corresponding to pbInstrBuf. */
945	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
946	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
947	* This takes the CS segment limit into account. */
948	uint16_t cbInstrBufTotal; /* 0x28 */
949	/** Offset into pbInstrBuf of the first byte of the current instruction.
950	* Can be negative to efficiently handle cross page instructions. */
951	int16_t offCurInstrStart; /* 0x2a */
952
953	/** The prefix mask (IEM_OP_PRF_XXX). */
954	uint32_t fPrefixes; /* 0x2c */
955	/** The extra REX ModR/M register field bit (REX.R << 3). */
956	uint8_t uRexReg; /* 0x30 */
957	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
958	* (REX.B << 3). */
959	uint8_t uRexB; /* 0x31 */
960	/** The extra REX SIB index field bit (REX.X << 3). */
961	uint8_t uRexIndex; /* 0x32 */
962
963	/** The effective segment register (X86_SREG_XXX). */
964	uint8_t iEffSeg; /* 0x33 */
965
966	/** The offset of the ModR/M byte relative to the start of the instruction. */
967	uint8_t offModRm; /* 0x34 */
968
969	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
970	/** The current offset into abOpcode. */
971	uint8_t offOpcode; /* 0x35 */
972	# else
973	uint8_t bUnused; /* 0x35 */
974	# endif
975	# else /* !IEM_WITH_CODE_TLB */
976	/** The size of what has currently been fetched into abOpcode. */
977	uint8_t cbOpcode; /* 0x08 */
978	/** The current offset into abOpcode. */
979	uint8_t offOpcode; /* 0x09 */
980	/** The offset of the ModR/M byte relative to the start of the instruction. */
981	uint8_t offModRm; /* 0x0a */
982
983	/** The effective segment register (X86_SREG_XXX). */
984	uint8_t iEffSeg; /* 0x0b */
985
986	/** The prefix mask (IEM_OP_PRF_XXX). */
987	uint32_t fPrefixes; /* 0x0c */
988	/** The extra REX ModR/M register field bit (REX.R << 3). */
989	uint8_t uRexReg; /* 0x10 */
990	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
991	* (REX.B << 3). */
992	uint8_t uRexB; /* 0x11 */
993	/** The extra REX SIB index field bit (REX.X << 3). */
994	uint8_t uRexIndex; /* 0x12 */
995
996	# endif /* !IEM_WITH_CODE_TLB */
997
998	/** The effective operand mode. */
999	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1000	/** The default addressing mode. */
1001	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1002	/** The effective addressing mode. */
1003	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1004	/** The default operand mode. */
1005	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1006
1007	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1008	uint8_t idxPrefix; /* 0x3a, 0x17 */
1009	/** 3rd VEX/EVEX/XOP register.
1010	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1011	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1012	/** The VEX/EVEX/XOP length field. */
1013	uint8_t uVexLength; /* 0x3c, 0x19 */
1014	/** Additional EVEX stuff. */
1015	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1016
1017	# ifndef IEM_WITH_CODE_TLB
1018	/** Explicit alignment padding. */
1019	uint8_t abAlignment2a[1]; /* 0x1b */
1020	# endif
1021	/** The FPU opcode (FOP). */
1022	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1023	# ifndef IEM_WITH_CODE_TLB
1024	/** Explicit alignment padding. */
1025	uint8_t abAlignment2b[2]; /* 0x1e */
1026	# endif
1027
1028	/** The opcode bytes. */
1029	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1030	/** Explicit alignment padding. */
1031	# ifdef IEM_WITH_CODE_TLB
1032	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1033	# else
1034	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1035	# endif
1036	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1037	uint8_t abOpaqueDecoder[0x4f - 0x8];
1038	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1039	/** @} */
1040
1041
1042	/** The number of active guest memory mappings. */
1043	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1044
1045	/** Records for tracking guest memory mappings. */
1046	struct
1047	{
1048	/** The address of the mapped bytes. */
1049	R3R0PTRTYPE(void *) pv;
1050	/** The access flags (IEM_ACCESS_XXX).
1051	* IEM_ACCESS_INVALID if the entry is unused. */
1052	uint32_t fAccess;
1053	#if HC_ARCH_BITS == 64
1054	uint32_t u32Alignment4; /*< Alignment padding. /
1055	#endif
1056	} aMemMappings[3]; /* 0x50 LB 0x30 */
1057
1058	/** Locking records for the mapped memory. */
1059	union
1060	{
1061	PGMPAGEMAPLOCK Lock;
1062	uint64_t au64Padding[2];
1063	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1064
1065	/** Bounce buffer info.
1066	* This runs in parallel to aMemMappings. */
1067	struct
1068	{
1069	/** The physical address of the first byte. */
1070	RTGCPHYS GCPhysFirst;
1071	/** The physical address of the second page. */
1072	RTGCPHYS GCPhysSecond;
1073	/** The number of bytes in the first page. */
1074	uint16_t cbFirst;
1075	/** The number of bytes in the second page. */
1076	uint16_t cbSecond;
1077	/** Whether it's unassigned memory. */
1078	bool fUnassigned;
1079	/** Explicit alignment padding. */
1080	bool afAlignment5[3];
1081	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1082
1083	/** The flags of the current exception / interrupt. */
1084	uint32_t fCurXcpt; /* 0xf8 */
1085	/** The current exception / interrupt. */
1086	uint8_t uCurXcpt; /* 0xfc */
1087	/** Exception / interrupt recursion depth. */
1088	int8_t cXcptRecursions; /* 0xfb */
1089
1090	/** The next unused mapping index.
1091	* @todo try find room for this up with cActiveMappings. */
1092	uint8_t iNextMapping; /* 0xfd */
1093	uint8_t abAlignment7[1];
1094
1095	/** Bounce buffer storage.
1096	* This runs in parallel to aMemMappings and aMemBbMappings. */
1097	struct
1098	{
1099	uint8_t ab[512];
1100	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1101
1102
1103	/** Pointer set jump buffer - ring-3 context. */
1104	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1105	/** Pointer set jump buffer - ring-0 context. */
1106	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1107
1108	/** @todo Should move this near @a fCurXcpt later. */
1109	/** The CR2 for the current exception / interrupt. */
1110	uint64_t uCurXcptCr2;
1111	/** The error code for the current exception / interrupt. */
1112	uint32_t uCurXcptErr;
1113
1114	/** @name Statistics
1115	* @{ */
1116	/** The number of instructions we've executed. */
1117	uint32_t cInstructions;
1118	/** The number of potential exits. */
1119	uint32_t cPotentialExits;
1120	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1121	* This may contain uncommitted writes. */
1122	uint32_t cbWritten;
1123	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1124	uint32_t cRetInstrNotImplemented;
1125	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1126	uint32_t cRetAspectNotImplemented;
1127	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1128	uint32_t cRetInfStatuses;
1129	/** Counts other error statuses returned. */
1130	uint32_t cRetErrStatuses;
1131	/** Number of times rcPassUp has been used. */
1132	uint32_t cRetPassUpStatus;
1133	/** Number of times RZ left with instruction commit pending for ring-3. */
1134	uint32_t cPendingCommit;
1135	/** Number of long jumps. */
1136	uint32_t cLongJumps;
1137	/** @} */
1138
1139	/** @name Target CPU information.
1140	* @{ */
1141	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1142	/** The target CPU. */
1143	uint8_t uTargetCpu;
1144	#else
1145	uint8_t bTargetCpuPadding;
1146	#endif
1147	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1148	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1149	* native host support and the 2nd for when there is.
1150	*
1151	* The two values are typically indexed by a g_CpumHostFeatures bit.
1152	*
1153	* This is for instance used for the BSF & BSR instructions where AMD and
1154	* Intel CPUs produce different EFLAGS. */
1155	uint8_t aidxTargetCpuEflFlavour[2];
1156
1157	/** The CPU vendor. */
1158	CPUMCPUVENDOR enmCpuVendor;
1159	/** @} */
1160
1161	/** @name Host CPU information.
1162	* @{ */
1163	/** The CPU vendor. */
1164	CPUMCPUVENDOR enmHostCpuVendor;
1165	/** @} */
1166
1167	/** Counts RDMSR \#GP(0) LogRel(). */
1168	uint8_t cLogRelRdMsr;
1169	/** Counts WRMSR \#GP(0) LogRel(). */
1170	uint8_t cLogRelWrMsr;
1171	/** Alignment padding. */
1172	uint8_t abAlignment9[46];
1173
1174	/** @name Recompilation
1175	* @{ */
1176	/** Pointer to the current translation block.
1177	* This can either be one being executed or one being compiled. */
1178	R3PTRTYPE(PIEMTB) pCurTbR3;
1179	/** Fixed TB used for threaded recompilation.
1180	* This is allocated once with maxed-out sizes and re-used afterwards. */
1181	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1182	/** Fixed TB used for native recompilation.
1183	* This is allocated once and re-used afterwards, growing individual
1184	* components as needed. */
1185	R3PTRTYPE(PIEMTB) pNativeCompileTbR3;
1186	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1187	* The TBs are based on physical addresses, so this is needed to correleated
1188	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1189	uint64_t uCurTbStartPc;
1190	/** Statistics: Number of TB lookup misses. */
1191	uint64_t cTbLookupMisses;
1192	/** Statistics: Number of TB lookup hits (debug only). */
1193	uint64_t cTbLookupHits;
1194	/** Number of TBs executed. */
1195	uint64_t cTbExec;
1196	/** Whether we need to check the opcode bytes for the current instruction.
1197	* This is set by a previous instruction if it modified memory or similar. */
1198	bool fTbCheckOpcodes;
1199	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1200	uint8_t fTbBranched;
1201	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1202	bool fTbCrossedPage;
1203	/** Whether to end the current TB. */
1204	bool fEndTb;
1205	/** Number of instructions before we need emit an IRQ check call again.
1206	* This helps making sure we don't execute too long w/o checking for
1207	* interrupts and immediately following instructions that may enable
1208	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1209	* required to make sure we check following the next instruction as well, see
1210	* fTbCurInstrIsSti. */
1211	uint8_t cInstrTillIrqCheck;
1212	/** Indicates that the current instruction is an STI. This is set by the
1213	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1214	bool fTbCurInstrIsSti;
1215	/** Spaced reserved for recompiler data / alignment. */
1216	bool afRecompilerStuff1[2];
1217	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1218	RTGCPHYS GCPhysInstrBufPrev;
1219	/** Copy of IEMCPU::GCPhysInstrBuf after decoding a branch instruction.
1220	* This is used together with fTbBranched and GCVirtTbBranchSrcBuf to determin
1221	* whether a branch instruction jumps to a new page or stays within the
1222	* current one. */
1223	RTGCPHYS GCPhysTbBranchSrcBuf;
1224	/** Copy of IEMCPU::uInstrBufPc after decoding a branch instruction. */
1225	uint64_t GCVirtTbBranchSrcBuf;
1226	/* Alignment. */
1227	uint64_t auAlignment10[6];
1228	/** Statistics: Number of TB allocation calls. */
1229	uint64_t cTbAllocs;
1230	/** Statistics: Number of TB free calls. */
1231	uint64_t cTbFrees;
1232	/** Statistics: Times TB execution was broken off before reaching the end. */
1233	STAMCOUNTER StatTbExecBreaks;
1234	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1235	STAMCOUNTER StatCheckIrqBreaks;
1236	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1237	STAMCOUNTER StatCheckModeBreaks;
1238	/** Statistics: Times a post jump target check missed and had to find new TB. */
1239	STAMCOUNTER StatCheckBranchMisses;
1240	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1241	STAMCOUNTER StatCheckNeedCsLimChecking;
1242	/** Threaded TB statistics: Number of instructions per TB. */
1243	STAMPROFILE StatTbThreadedInstr;
1244	/** Threaded TB statistics: Number of calls per TB. */
1245	STAMPROFILE StatTbThreadedCalls;
1246	/** @} */
1247
1248	/** Data TLB.
1249	* @remarks Must be 64-byte aligned. */
1250	IEMTLB DataTlb;
1251	/** Instruction TLB.
1252	* @remarks Must be 64-byte aligned. */
1253	IEMTLB CodeTlb;
1254
1255	/** Exception statistics. */
1256	STAMCOUNTER aStatXcpts[32];
1257	/** Interrupt statistics. */
1258	uint32_t aStatInts[256];
1259
1260	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1261	/** Instruction statistics for ring-0/raw-mode. */
1262	IEMINSTRSTATS StatsRZ;
1263	/** Instruction statistics for ring-3. */
1264	IEMINSTRSTATS StatsR3;
1265	#endif
1266	} IEMCPU;
1267	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1268	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1269	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1270	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1271	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1272	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1273
1274	/** Pointer to the per-CPU IEM state. */
1275	typedef IEMCPU *PIEMCPU;
1276	/** Pointer to the const per-CPU IEM state. */
1277	typedef IEMCPU const *PCIEMCPU;
1278
1279
1280	/** @def IEM_GET_CTX
1281	* Gets the guest CPU context for the calling EMT.
1282	* @returns PCPUMCTX
1283	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1284	*/
1285	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1286
1287	/** @def IEM_CTX_ASSERT
1288	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1289	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1290	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1291	*/
1292	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
1293	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1294	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
1295	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
1296
1297	/** @def IEM_CTX_IMPORT_RET
1298	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1299	*
1300	* Will call the keep to import the bits as needed.
1301	*
1302	* Returns on import failure.
1303	*
1304	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1305	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1306	*/
1307	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1308	do { \
1309	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1310	{ /* likely */ } \
1311	else \
1312	{ \
1313	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1314	AssertRCReturn(rcCtxImport, rcCtxImport); \
1315	} \
1316	} while (0)
1317
1318	/** @def IEM_CTX_IMPORT_NORET
1319	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1320	*
1321	* Will call the keep to import the bits as needed.
1322	*
1323	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1324	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1325	*/
1326	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1327	do { \
1328	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1329	{ /* likely */ } \
1330	else \
1331	{ \
1332	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1333	AssertLogRelRC(rcCtxImport); \
1334	} \
1335	} while (0)
1336
1337	/** @def IEM_CTX_IMPORT_JMP
1338	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1339	*
1340	* Will call the keep to import the bits as needed.
1341	*
1342	* Jumps on import failure.
1343	*
1344	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1345	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1346	*/
1347	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1348	do { \
1349	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1350	{ /* likely */ } \
1351	else \
1352	{ \
1353	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1354	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1355	} \
1356	} while (0)
1357
1358
1359
1360	/** @def IEM_GET_TARGET_CPU
1361	* Gets the current IEMTARGETCPU value.
1362	* @returns IEMTARGETCPU value.
1363	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1364	*/
1365	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1366	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1367	#else
1368	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1369	#endif
1370
1371	/** @def IEM_GET_INSTR_LEN
1372	* Gets the instruction length. */
1373	#ifdef IEM_WITH_CODE_TLB
1374	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1375	#else
1376	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1377	#endif
1378
1379	/** @def IEM_TRY_SETJMP
1380	* Wrapper around setjmp / try, hiding all the ugly differences.
1381	*
1382	* @note Use with extreme care as this is a fragile macro.
1383	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1384	* @param a_rcTarget The variable that should receive the status code in case
1385	* of a longjmp/throw.
1386	*/
1387	/** @def IEM_TRY_SETJMP_AGAIN
1388	* For when setjmp / try is used again in the same variable scope as a previous
1389	* IEM_TRY_SETJMP invocation.
1390	*/
1391	/** @def IEM_CATCH_LONGJMP_BEGIN
1392	* Start wrapper for catch / setjmp-else.
1393	*
1394	* This will set up a scope.
1395	*
1396	* @note Use with extreme care as this is a fragile macro.
1397	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1398	* @param a_rcTarget The variable that should receive the status code in case
1399	* of a longjmp/throw.
1400	*/
1401	/** @def IEM_CATCH_LONGJMP_END
1402	* End wrapper for catch / setjmp-else.
1403	*
1404	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1405	* state.
1406	*
1407	* @note Use with extreme care as this is a fragile macro.
1408	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1409	*/
1410	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
1411	# ifdef IEM_WITH_THROW_CATCH
1412	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1413	a_rcTarget = VINF_SUCCESS; \
1414	try
1415	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1416	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1417	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1418	catch (int rcThrown) \
1419	{ \
1420	a_rcTarget = rcThrown
1421	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1422	} \
1423	((void)0)
1424	# else /* !IEM_WITH_THROW_CATCH */
1425	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1426	jmp_buf JmpBuf; \
1427	jmp_buf * volatile pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1428	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1429	if ((rcStrict = setjmp(JmpBuf)) == 0)
1430	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1431	pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1432	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1433	if ((rcStrict = setjmp(JmpBuf)) == 0)
1434	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1435	else \
1436	{ \
1437	((void)0)
1438	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1439	} \
1440	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1441	# endif /* !IEM_WITH_THROW_CATCH */
1442	#endif /* IEM_WITH_SETJMP */
1443
1444
1445	/**
1446	* Shared per-VM IEM data.
1447	*/
1448	typedef struct IEM
1449	{
1450	/** The VMX APIC-access page handler type. */
1451	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1452	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1453	/** Set if the CPUID host call functionality is enabled. */
1454	bool fCpuIdHostCall;
1455	#endif
1456	} IEM;
1457
1458
1459
1460	/** @name IEM_ACCESS_XXX - Access details.
1461	* @{ */
1462	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1463	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1464	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1465	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1466	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1467	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1468	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1469	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1470	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1471	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1472	/** The writes are partial, so if initialize the bounce buffer with the
1473	* orignal RAM content. */
1474	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1475	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1476	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1477	/** Bounce buffer with ring-3 write pending, first page. */
1478	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1479	/** Bounce buffer with ring-3 write pending, second page. */
1480	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1481	/** Not locked, accessed via the TLB. */
1482	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1483	/** Valid bit mask. */
1484	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1485	/** Shift count for the TLB flags (upper word). */
1486	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1487
1488	/** Read+write data alias. */
1489	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1490	/** Write data alias. */
1491	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1492	/** Read data alias. */
1493	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1494	/** Instruction fetch alias. */
1495	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1496	/** Stack write alias. */
1497	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1498	/** Stack read alias. */
1499	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1500	/** Stack read+write alias. */
1501	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1502	/** Read system table alias. */
1503	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1504	/** Read+write system table alias. */
1505	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1506	/** @} */
1507
1508	/** @name Prefix constants (IEMCPU::fPrefixes)
1509	* @{ */
1510	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1511	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1512	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1513	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1514	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1515	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1516	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1517
1518	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1519	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1520	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1521
1522	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1523	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1524	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1525
1526	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1527	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1528	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1529	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1530	/** Mask with all the REX prefix flags.
1531	* This is generally for use when needing to undo the REX prefixes when they
1532	* are followed legacy prefixes and therefore does not immediately preceed
1533	* the first opcode byte.
1534	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1535	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1536
1537	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1538	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1539	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1540	/** @} */
1541
1542	/** @name IEMOPFORM_XXX - Opcode forms
1543	* @note These are ORed together with IEMOPHINT_XXX.
1544	* @{ */
1545	/** ModR/M: reg, r/m */
1546	#define IEMOPFORM_RM 0
1547	/** ModR/M: reg, r/m (register) */
1548	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1549	/** ModR/M: reg, r/m (memory) */
1550	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1551	/** ModR/M: reg, r/m */
1552	#define IEMOPFORM_RMI 1
1553	/** ModR/M: reg, r/m (register) */
1554	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1555	/** ModR/M: reg, r/m (memory) */
1556	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1557	/** ModR/M: r/m, reg */
1558	#define IEMOPFORM_MR 2
1559	/** ModR/M: r/m (register), reg */
1560	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1561	/** ModR/M: r/m (memory), reg */
1562	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1563	/** ModR/M: r/m, reg */
1564	#define IEMOPFORM_MRI 3
1565	/** ModR/M: r/m (register), reg */
1566	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1567	/** ModR/M: r/m (memory), reg */
1568	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1569	/** ModR/M: r/m only */
1570	#define IEMOPFORM_M 4
1571	/** ModR/M: r/m only (register). */
1572	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1573	/** ModR/M: r/m only (memory). */
1574	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1575	/** ModR/M: reg only */
1576	#define IEMOPFORM_R 5
1577
1578	/** VEX+ModR/M: reg, r/m */
1579	#define IEMOPFORM_VEX_RM 8
1580	/** VEX+ModR/M: reg, r/m (register) */
1581	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1582	/** VEX+ModR/M: reg, r/m (memory) */
1583	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1584	/** VEX+ModR/M: r/m, reg */
1585	#define IEMOPFORM_VEX_MR 9
1586	/** VEX+ModR/M: r/m (register), reg */
1587	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1588	/** VEX+ModR/M: r/m (memory), reg */
1589	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1590	/** VEX+ModR/M: r/m only */
1591	#define IEMOPFORM_VEX_M 10
1592	/** VEX+ModR/M: r/m only (register). */
1593	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1594	/** VEX+ModR/M: r/m only (memory). */
1595	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1596	/** VEX+ModR/M: reg only */
1597	#define IEMOPFORM_VEX_R 11
1598	/** VEX+ModR/M: reg, vvvv, r/m */
1599	#define IEMOPFORM_VEX_RVM 12
1600	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1601	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1602	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1603	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1604	/** VEX+ModR/M: reg, r/m, vvvv */
1605	#define IEMOPFORM_VEX_RMV 13
1606	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1607	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1608	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1609	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1610	/** VEX+ModR/M: reg, r/m, imm8 */
1611	#define IEMOPFORM_VEX_RMI 14
1612	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1613	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1614	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1615	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1616	/** VEX+ModR/M: r/m, vvvv, reg */
1617	#define IEMOPFORM_VEX_MVR 15
1618	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1619	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1620	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1621	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1622	/** VEX+ModR/M+/n: vvvv, r/m */
1623	#define IEMOPFORM_VEX_VM 16
1624	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1625	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1626	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1627	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1628
1629	/** Fixed register instruction, no R/M. */
1630	#define IEMOPFORM_FIXED 32
1631
1632	/** The r/m is a register. */
1633	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1634	/** The r/m is a memory access. */
1635	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1636	/** @} */
1637
1638	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1639	* @note These are ORed together with IEMOPFORM_XXX.
1640	* @{ */
1641	/** Ignores the operand size prefix (66h). */
1642	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1643	/** Ignores REX.W (aka WIG). */
1644	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1645	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1646	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1647	/** Allowed with the lock prefix. */
1648	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1649	/** The VEX.L value is ignored (aka LIG). */
1650	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1651	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1652	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1653	/** The VEX.V value must be zero. */
1654	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1655
1656	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1657	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1658	/** @} */
1659
1660	/**
1661	* Possible hardware task switch sources.
1662	*/
1663	typedef enum IEMTASKSWITCH
1664	{
1665	/** Task switch caused by an interrupt/exception. */
1666	IEMTASKSWITCH_INT_XCPT = 1,
1667	/** Task switch caused by a far CALL. */
1668	IEMTASKSWITCH_CALL,
1669	/** Task switch caused by a far JMP. */
1670	IEMTASKSWITCH_JUMP,
1671	/** Task switch caused by an IRET. */
1672	IEMTASKSWITCH_IRET
1673	} IEMTASKSWITCH;
1674	AssertCompileSize(IEMTASKSWITCH, 4);
1675
1676	/**
1677	* Possible CrX load (write) sources.
1678	*/
1679	typedef enum IEMACCESSCRX
1680	{
1681	/** CrX access caused by 'mov crX' instruction. */
1682	IEMACCESSCRX_MOV_CRX,
1683	/** CrX (CR0) write caused by 'lmsw' instruction. */
1684	IEMACCESSCRX_LMSW,
1685	/** CrX (CR0) write caused by 'clts' instruction. */
1686	IEMACCESSCRX_CLTS,
1687	/** CrX (CR0) read caused by 'smsw' instruction. */
1688	IEMACCESSCRX_SMSW
1689	} IEMACCESSCRX;
1690
1691	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1692	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1693	*
1694	* These flags provide further context to SLAT page-walk failures that could not be
1695	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1696	*
1697	* @{
1698	*/
1699	/** Translating a nested-guest linear address failed accessing a nested-guest
1700	* physical address. */
1701	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1702	/** Translating a nested-guest linear address failed accessing a
1703	* paging-structure entry or updating accessed/dirty bits. */
1704	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1705	/** @} */
1706
1707	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1708	# ifndef IN_RING3
1709	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1710	# endif
1711	#endif
1712
1713	/**
1714	* Indicates to the verifier that the given flag set is undefined.
1715	*
1716	* Can be invoked again to add more flags.
1717	*
1718	* This is a NOOP if the verifier isn't compiled in.
1719	*
1720	* @note We're temporarily keeping this until code is converted to new
1721	* disassembler style opcode handling.
1722	*/
1723	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1724
1725
1726	/** @def IEM_DECL_IMPL_TYPE
1727	* For typedef'ing an instruction implementation function.
1728	*
1729	* @param a_RetType The return type.
1730	* @param a_Name The name of the type.
1731	* @param a_ArgList The argument list enclosed in parentheses.
1732	*/
1733
1734	/** @def IEM_DECL_IMPL_DEF
1735	* For defining an instruction implementation function.
1736	*
1737	* @param a_RetType The return type.
1738	* @param a_Name The name of the type.
1739	* @param a_ArgList The argument list enclosed in parentheses.
1740	*/
1741
1742	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1743	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1744	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1745	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1746	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
1747	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1748	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
1749
1750	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1751	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1752	a_RetType (__fastcall a_Name) a_ArgList
1753	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1754	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1755	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1756	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1757
1758	#elif __cplusplus >= 201700 /* P0012R1 support */
1759	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1760	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1761	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1762	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1763	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1764	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1765
1766	#else
1767	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1768	a_RetType (VBOXCALL a_Name) a_ArgList
1769	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1770	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
1771	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1772	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
1773
1774	#endif
1775
1776	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1777	RT_C_DECLS_BEGIN
1778	extern uint8_t const g_afParity[256];
1779	RT_C_DECLS_END
1780
1781
1782	/** @name Arithmetic assignment operations on bytes (binary).
1783	* @{ */
1784	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1785	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1786	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1787	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1788	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1789	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1790	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1791	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1792	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1793	/** @} */
1794
1795	/** @name Arithmetic assignment operations on words (binary).
1796	* @{ */
1797	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1798	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1799	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1800	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1801	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1802	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1803	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1804	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1805	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1806	/** @} */
1807
1808	/** @name Arithmetic assignment operations on double words (binary).
1809	* @{ */
1810	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1811	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1812	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1813	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1814	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1815	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1816	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1817	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1818	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1819	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1820	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1821	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1822	/** @} */
1823
1824	/** @name Arithmetic assignment operations on quad words (binary).
1825	* @{ */
1826	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1827	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1828	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1829	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1830	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1831	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1832	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1833	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1834	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1835	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1836	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1837	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1838	/** @} */
1839
1840	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1841	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
1842	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1843	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
1844	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1845	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
1846	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1847	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
1848
1849	/** @name Compare operations (thrown in with the binary ops).
1850	* @{ */
1851	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
1852	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
1853	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
1854	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
1855	/** @} */
1856
1857	/** @name Test operations (thrown in with the binary ops).
1858	* @{ */
1859	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
1860	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
1861	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
1862	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
1863	/** @} */
1864
1865	/** @name Bit operations operations (thrown in with the binary ops).
1866	* @{ */
1867	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
1868	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
1869	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
1870	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1871	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1872	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1873	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1874	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1875	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1876	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1877	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1878	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1879	/** @} */
1880
1881	/** @name Arithmetic three operand operations on double words (binary).
1882	* @{ */
1883	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1884	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1885	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1886	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1887	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1888	/** @} */
1889
1890	/** @name Arithmetic three operand operations on quad words (binary).
1891	* @{ */
1892	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1893	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1894	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1895	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1896	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1897	/** @} */
1898
1899	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1900	* @{ */
1901	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1902	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1903	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1904	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1905	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1906	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1907	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1908	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1909	/** @} */
1910
1911	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1912	* @{ */
1913	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1914	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1915	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1916	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1917	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1918	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1919	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1920	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1921	/** @} */
1922
1923	/** @name MULX 32-bit and 64-bit.
1924	* @{ */
1925	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1926	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1927	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1928
1929	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1930	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1931	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1932	/** @} */
1933
1934
1935	/** @name Exchange memory with register operations.
1936	* @{ */
1937	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1938	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1939	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1940	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1941	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1942	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1943	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1944	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1945	/** @} */
1946
1947	/** @name Exchange and add operations.
1948	* @{ */
1949	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1950	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1951	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1952	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1953	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1954	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1955	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1956	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1957	/** @} */
1958
1959	/** @name Compare and exchange.
1960	* @{ */
1961	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1962	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1963	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1964	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1965	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1966	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1967	#if ARCH_BITS == 32
1968	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1969	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1970	#else
1971	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1972	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1973	#endif
1974	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1975	uint32_t *pEFlags));
1976	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1977	uint32_t *pEFlags));
1978	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1979	uint32_t *pEFlags));
1980	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1981	uint32_t *pEFlags));
1982	#ifndef RT_ARCH_ARM64
1983	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1984	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1985	#endif
1986	/** @} */
1987
1988	/** @name Memory ordering
1989	* @{ */
1990	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1991	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1992	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1993	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1994	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1995	#ifndef RT_ARCH_ARM64
1996	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1997	#endif
1998	/** @} */
1999
2000	/** @name Double precision shifts
2001	* @{ */
2002	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2003	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2004	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2005	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2006	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2007	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2008	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2009	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2010	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2011	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2012	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2013	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2014	/** @} */
2015
2016
2017	/** @name Bit search operations (thrown in with the binary ops).
2018	* @{ */
2019	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2020	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2021	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2022	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2023	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2024	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2025	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2026	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2027	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2028	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2029	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2030	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2031	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2032	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2033	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2034	/** @} */
2035
2036	/** @name Signed multiplication operations (thrown in with the binary ops).
2037	* @{ */
2038	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2039	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2040	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2041	/** @} */
2042
2043	/** @name Arithmetic assignment operations on bytes (unary).
2044	* @{ */
2045	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2046	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2047	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2048	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2049	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2050	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2051	/** @} */
2052
2053	/** @name Arithmetic assignment operations on words (unary).
2054	* @{ */
2055	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2056	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2057	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2058	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2059	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2060	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2061	/** @} */
2062
2063	/** @name Arithmetic assignment operations on double words (unary).
2064	* @{ */
2065	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2066	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2067	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2068	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2069	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2070	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2071	/** @} */
2072
2073	/** @name Arithmetic assignment operations on quad words (unary).
2074	* @{ */
2075	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2076	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2077	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2078	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2079	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2080	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2081	/** @} */
2082
2083
2084	/** @name Shift operations on bytes (Group 2).
2085	* @{ */
2086	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
2087	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2088	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2089	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2090	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2091	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2092	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2093	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2094	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
2095	/** @} */
2096
2097	/** @name Shift operations on words (Group 2).
2098	* @{ */
2099	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
2100	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
2101	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
2102	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
2103	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
2104	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
2105	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2106	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2107	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2108	/** @} */
2109
2110	/** @name Shift operations on double words (Group 2).
2111	* @{ */
2112	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
2113	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2114	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2115	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2116	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2117	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2118	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2119	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2120	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2121	/** @} */
2122
2123	/** @name Shift operations on words (Group 2).
2124	* @{ */
2125	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
2126	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2127	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2128	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2129	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2130	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2131	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2132	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2133	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2134	/** @} */
2135
2136	/** @name Multiplication and division operations.
2137	* @{ */
2138	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
2139	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2140	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2141	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2142	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2143	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2144
2145	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2146	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2147	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2148	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2149	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2150	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2151
2152	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2153	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2154	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2155	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2156	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2157	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2158
2159	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2160	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2161	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2162	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2163	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2164	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2165	/** @} */
2166
2167	/** @name Byte Swap.
2168	* @{ */
2169	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
2170	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2171	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2172	/** @} */
2173
2174	/** @name Misc.
2175	* @{ */
2176	FNIEMAIMPLBINU16 iemAImpl_arpl;
2177	/** @} */
2178
2179	/** @name RDRAND and RDSEED
2180	* @{ */
2181	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
2182	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
2183	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
2184	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
2185	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
2186	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
2187
2188	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2189	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2190	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2191	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2192	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2193	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2194	/** @} */
2195
2196	/** @name ADOX and ADCX
2197	* @{ */
2198	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
2199	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
2200	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
2201	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
2202
2203	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2204	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2205	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2206	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2207	/** @} */
2208
2209	/** @name FPU operations taking a 32-bit float argument
2210	* @{ */
2211	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2212	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2213	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2214
2215	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2216	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2217	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2218
2219	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2220	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2221	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2222	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2223	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2224	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2225	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2226
2227	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2228	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2229	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2230	/** @} */
2231
2232	/** @name FPU operations taking a 64-bit float argument
2233	* @{ */
2234	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2235	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2236	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2237
2238	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2239	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2240	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2241
2242	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2243	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2244	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2245	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2246	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2247	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2248	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2249
2250	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2251	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2252	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2253	/** @} */
2254
2255	/** @name FPU operations taking a 80-bit float argument
2256	* @{ */
2257	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2258	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2259	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2260	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2261	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2262	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2263	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2264	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2265	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2266	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2267	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2268	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2269
2270	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2271	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2272	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2273
2274	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2275	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2276	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2277	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2278	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2279
2280	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2281	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2282	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2283	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2284	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2285
2286	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2287	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2288	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2289	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2290	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2291	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2292	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2293	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2294	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2295
2296	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2297	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2298	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2299	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2300
2301	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2302	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2303	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2304	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2305	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2306	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2307	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2308	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2309	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2310
2311	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2312	PCRTFLOAT80U pr80Val));
2313	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2314	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2315	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2316	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2317
2318	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2319	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2320	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2321
2322	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2323	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2324	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2325
2326	/** @} */
2327
2328	/** @name FPU operations taking a 16-bit signed integer argument
2329	* @{ */
2330	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2331	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2332	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2333	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2334	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2335	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2336
2337	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2338	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2339	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2340	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2341	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2342	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2343
2344	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2345	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2346	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2347	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2348
2349	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2350	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2351	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2352	/** @} */
2353
2354	/** @name FPU operations taking a 32-bit signed integer argument
2355	* @{ */
2356	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2357	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2358	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2359	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2360	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2361	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2362
2363	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2364	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2365	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2366	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2367	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2368	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2369
2370	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2371	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2372	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2373	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2374
2375	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2376	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2377	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2378	/** @} */
2379
2380	/** @name FPU operations taking a 64-bit signed integer argument
2381	* @{ */
2382	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2383	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2384	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2385
2386	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2387	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2388	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2389	/** @} */
2390
2391
2392	/** Temporary type representing a 256-bit vector register. */
2393	typedef struct { uint64_t au64[4]; } IEMVMM256;
2394	/** Temporary type pointing to a 256-bit vector register. */
2395	typedef IEMVMM256 *PIEMVMM256;
2396	/** Temporary type pointing to a const 256-bit vector register. */
2397	typedef IEMVMM256 *PCIEMVMM256;
2398
2399
2400	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2401	* @{ */
2402	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
2403	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2404	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2405	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2406	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2407	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2408	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2409	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2410	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
2411	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2412	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2413	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2414	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2415	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2416	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2417	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2418	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2419	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2420	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2421	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2422	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2423	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2424	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2425	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2426	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2427	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2428	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2429	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2430	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2431	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2432	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2433	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2434	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2435	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2436	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2437	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2438	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2439	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2440	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2441	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2442	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2443	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2444	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2445	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2446	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2447	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2448	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2449	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2450	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2451	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2452	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2453	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2454	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2455	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2456	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2457	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2458	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2459
2460	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2461	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2462	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2463	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2464	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2465	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2466	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2467	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2468	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2469	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2470	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2471	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2472	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2473	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2474	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2475	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2476	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2477	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2478	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2479	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2480	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2481	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2482	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2483	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2484	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2485	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2486	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2487	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2488	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2489	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2490	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2491	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2492	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2493	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2494	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2495	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2496	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2497	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2498	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2499	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2500	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2501	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2502	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2503	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2504	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2505	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2506	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2507	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2508	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2509	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2510	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2511	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2512	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2513	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2514	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2515	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2516	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2517
2518	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2519	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2520	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2521	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2522	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2523	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2524	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2525	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2526	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2527	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2528	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2529	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2530	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2531	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2532	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2533	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2534	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2535	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2536	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2537	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2538	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2539	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2540	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2541	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2542	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2543	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2544	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2545	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2546	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2547	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2548	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2549	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2550	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2551	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2552	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2553	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2554	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2555	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2556	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2557	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2558	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2559	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2560	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2561	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2562	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2563	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2564	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2565	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2566	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2567	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2568	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2569	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2570	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2571	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2572	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2573	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2574	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2575	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
2576	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
2577	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
2578	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
2579	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
2580	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
2581	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
2582	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
2583
2584	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2585	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2586	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2587	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2588
2589	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2590	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2591	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2592	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2593	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2594	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2595	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2596	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2597	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2598	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2599	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2600	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2601	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2602	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2603	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2604	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2605	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2606	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2607	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2608	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2609	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2610	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2611	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2612	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2613	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2614	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2615	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2616	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2617	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2618	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2619	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2620	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2621	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2622	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2623	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2624	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2625	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2626	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2627	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2628	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2629	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2630	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2631	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2632	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2633	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2634	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2635	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2636	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2637	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2638	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2639	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2640	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2641	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2642	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2643	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2644	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2645	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2646	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
2647	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
2648	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
2649	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
2650	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
2651	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
2652	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
2653	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
2654
2655	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2656	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2657	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2658	/** @} */
2659
2660	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2661	* @{ */
2662	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2663	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2664	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2665	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2666	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2667	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2668	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2669	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2670	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2671	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2672
2673	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2674	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2675	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2676	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2677	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2678	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2679	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2680	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2681	/** @} */
2682
2683	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2684	* @{ */
2685	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2686	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2687	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2688	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2689	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2690	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2691	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2692	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2693	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2694	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2695	/** @} */
2696
2697	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2698	* @{ */
2699	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2700	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2701	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2702	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2703	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2704	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2705	#ifndef IEM_WITHOUT_ASSEMBLY
2706	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2707	#endif
2708	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2709	/** @} */
2710
2711	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2712	* @{ */
2713	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2714	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2715	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2716	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2717	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2718	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2719	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2720	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2721	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2722	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2723	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2724	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2725	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2726	/** @} */
2727
2728	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2729	* @{ */
2730	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2731	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2732	#ifndef IEM_WITHOUT_ASSEMBLY
2733	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2734	#endif
2735	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2736	/** @} */
2737
2738	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2739	* @{ */
2740	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2741	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2742	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2743	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2744	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2745	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2746
2747	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2748	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2749	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2750	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2751	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2752	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2753
2754	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2755	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2756	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2757	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2758	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2759	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2760
2761	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2762	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2763	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2764	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2765	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2766	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2767	/** @} */
2768
2769
2770	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2771	* @{ */
2772	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2773	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2774	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2775	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2776	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2777	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2778
2779	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2780	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2781	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2782	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2783	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2784
2785	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2786	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2787	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2788	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2789	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2790
2791	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2792	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2793	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2794	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2795	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2796
2797	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2798	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2799	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2800	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2801	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2802
2803	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2804	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2805	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2806	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2807	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2808
2809	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2810	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2811	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2812	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2813	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2814
2815	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2816	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2817	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2818	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2819	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2820
2821	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2822	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2823	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2824	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2825	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2826
2827	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2828	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2829	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2830	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2831	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2832
2833	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2834	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2835	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2836	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2837	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2838
2839	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2840	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2841	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2842	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2843	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2844
2845	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2846	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2847	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2848	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2849	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2850
2851	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2852	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2853	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2854	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2855	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2856
2857	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2858	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2859	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2860	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2861	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2862
2863	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2864	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2865
2866	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2867	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2868	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2869	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2870
2871	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2872	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2873	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2874	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2875
2876	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2877	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2878	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2879	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2880	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2881
2882	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2883	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2884	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2885	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2886	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2887
2888
2889	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2890	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2891	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2892	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2893	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2894	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2895
2896	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2897	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2898	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2899	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2900
2901	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2902	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2903	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2904	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2905
2906	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2907	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2908	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2909	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2910	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
2911	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
2912
2913	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2914	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2915	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2916	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2917	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2918
2919	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2920	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2921	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2922	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2923	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2924
2925	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2926
2927	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2928
2929	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
2930	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
2931	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
2932	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
2933	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
2934	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
2935	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2936	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2937
2938	typedef struct IEMPCMPISTRXSRC
2939	{
2940	RTUINT128U uSrc1;
2941	RTUINT128U uSrc2;
2942	} IEMPCMPISTRXSRC;
2943	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
2944	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
2945
2946	typedef struct IEMPCMPESTRXSRC
2947	{
2948	RTUINT128U uSrc1;
2949	RTUINT128U uSrc2;
2950	uint64_t u64Rax;
2951	uint64_t u64Rdx;
2952	} IEMPCMPESTRXSRC;
2953	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
2954	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
2955
2956	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2957	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
2958	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2959	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
2960
2961	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2962	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
2963	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2964	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
2965
2966	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
2967	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
2968	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
2969	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
2970
2971	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2972	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2973
2974	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
2975	/** @} */
2976
2977	/** @name Media Odds and Ends
2978	* @{ */
2979	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2980	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2981	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2982	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2983	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2984	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2985	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2986	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2987
2988	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2989	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2990	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2991	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2992
2993	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2994	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2995	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2996	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2997	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2998	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2999	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3000	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3001
3002	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3003	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3004
3005	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3006	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3007
3008	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3009	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3010
3011	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3012	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3013
3014	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
3015	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3016	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
3017	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3018
3019	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3020	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3021
3022	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
3023	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
3024	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
3025	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
3026
3027	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
3028	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3029
3030
3031	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3032	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
3033
3034	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
3035	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
3036
3037	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
3038	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
3039
3040	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
3041	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
3042
3043	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
3044	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
3045
3046
3047	typedef struct IEMMEDIAF2XMMSRC
3048	{
3049	X86XMMREG uSrc1;
3050	X86XMMREG uSrc2;
3051	} IEMMEDIAF2XMMSRC;
3052	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
3053	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
3054
3055	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
3056	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
3057
3058	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
3059	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
3060	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
3061	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
3062	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
3063	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
3064
3065	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
3066	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
3067
3068	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
3069	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
3070
3071	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
3072	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
3073
3074	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
3075	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
3076
3077	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
3078	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
3079
3080	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
3081	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
3082
3083	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
3084	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
3085
3086	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
3087	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
3088
3089	/** @} */
3090
3091
3092	/** @name Function tables.
3093	* @{
3094	*/
3095
3096	/**
3097	* Function table for a binary operator providing implementation based on
3098	* operand size.
3099	*/
3100	typedef struct IEMOPBINSIZES
3101	{
3102	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
3103	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
3104	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
3105	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3106	} IEMOPBINSIZES;
3107	/** Pointer to a binary operator function table. */
3108	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3109
3110
3111	/**
3112	* Function table for a unary operator providing implementation based on
3113	* operand size.
3114	*/
3115	typedef struct IEMOPUNARYSIZES
3116	{
3117	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3118	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3119	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3120	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3121	} IEMOPUNARYSIZES;
3122	/** Pointer to a unary operator function table. */
3123	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3124
3125
3126	/**
3127	* Function table for a shift operator providing implementation based on
3128	* operand size.
3129	*/
3130	typedef struct IEMOPSHIFTSIZES
3131	{
3132	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3133	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3134	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3135	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3136	} IEMOPSHIFTSIZES;
3137	/** Pointer to a shift operator function table. */
3138	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3139
3140
3141	/**
3142	* Function table for a multiplication or division operation.
3143	*/
3144	typedef struct IEMOPMULDIVSIZES
3145	{
3146	PFNIEMAIMPLMULDIVU8 pfnU8;
3147	PFNIEMAIMPLMULDIVU16 pfnU16;
3148	PFNIEMAIMPLMULDIVU32 pfnU32;
3149	PFNIEMAIMPLMULDIVU64 pfnU64;
3150	} IEMOPMULDIVSIZES;
3151	/** Pointer to a multiplication or division operation function table. */
3152	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3153
3154
3155	/**
3156	* Function table for a double precision shift operator providing implementation
3157	* based on operand size.
3158	*/
3159	typedef struct IEMOPSHIFTDBLSIZES
3160	{
3161	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3162	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3163	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3164	} IEMOPSHIFTDBLSIZES;
3165	/** Pointer to a double precision shift function table. */
3166	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3167
3168
3169	/**
3170	* Function table for media instruction taking two full sized media source
3171	* registers and one full sized destination register (AVX).
3172	*/
3173	typedef struct IEMOPMEDIAF3
3174	{
3175	PFNIEMAIMPLMEDIAF3U128 pfnU128;
3176	PFNIEMAIMPLMEDIAF3U256 pfnU256;
3177	} IEMOPMEDIAF3;
3178	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3179	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
3180
3181	/** @def IEMOPMEDIAF3_INIT_VARS_EX
3182	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3183	* given functions as initializers. For use in AVX functions where a pair of
3184	* functions are only used once and the function table need not be public. */
3185	#ifndef TST_IEM_CHECK_MC
3186	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3187	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3188	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3189	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3190	# else
3191	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3192	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3193	# endif
3194	#else
3195	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3196	#endif
3197	/** @def IEMOPMEDIAF3_INIT_VARS
3198	* Generate AVX function tables for the @a a_InstrNm instruction.
3199	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
3200	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
3201	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3202	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3203
3204	/**
3205	* Function table for media instruction taking two full sized media source
3206	* registers and one full sized destination register, but no additional state
3207	* (AVX).
3208	*/
3209	typedef struct IEMOPMEDIAOPTF3
3210	{
3211	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
3212	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
3213	} IEMOPMEDIAOPTF3;
3214	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3215	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
3216
3217	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
3218	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3219	* given functions as initializers. For use in AVX functions where a pair of
3220	* functions are only used once and the function table need not be public. */
3221	#ifndef TST_IEM_CHECK_MC
3222	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3223	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3224	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3225	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3226	# else
3227	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3228	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3229	# endif
3230	#else
3231	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3232	#endif
3233	/** @def IEMOPMEDIAOPTF3_INIT_VARS
3234	* Generate AVX function tables for the @a a_InstrNm instruction.
3235	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
3236	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
3237	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3238	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3239
3240	/**
3241	* Function table for media instruction taking one full sized media source
3242	* registers and one full sized destination register, but no additional state
3243	* (AVX).
3244	*/
3245	typedef struct IEMOPMEDIAOPTF2
3246	{
3247	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
3248	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
3249	} IEMOPMEDIAOPTF2;
3250	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
3251	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
3252
3253	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
3254	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3255	* given functions as initializers. For use in AVX functions where a pair of
3256	* functions are only used once and the function table need not be public. */
3257	#ifndef TST_IEM_CHECK_MC
3258	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3259	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3260	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3261	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3262	# else
3263	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3264	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3265	# endif
3266	#else
3267	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3268	#endif
3269	/** @def IEMOPMEDIAOPTF2_INIT_VARS
3270	* Generate AVX function tables for the @a a_InstrNm instruction.
3271	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3272	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3273	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3274	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3275
3276	/**
3277	* Function table for media instruction taking two full sized media source
3278	* registers and one full sized destination register and an 8-bit immediate, but no additional state
3279	* (AVX).
3280	*/
3281	typedef struct IEMOPMEDIAOPTF3IMM8
3282	{
3283	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3284	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3285	} IEMOPMEDIAOPTF3IMM8;
3286	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3287	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3288
3289	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3290	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3291	* given functions as initializers. For use in AVX functions where a pair of
3292	* functions are only used once and the function table need not be public. */
3293	#ifndef TST_IEM_CHECK_MC
3294	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3295	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3296	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3297	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3298	# else
3299	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3300	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3301	# endif
3302	#else
3303	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3304	#endif
3305	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3306	* Generate AVX function tables for the @a a_InstrNm instruction.
3307	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3308	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3309	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3310	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3311	/** @} */
3312
3313
3314	/**
3315	* Function table for blend type instruction taking three full sized media source
3316	* registers and one full sized destination register, but no additional state
3317	* (AVX).
3318	*/
3319	typedef struct IEMOPBLENDOP
3320	{
3321	PFNIEMAIMPLAVXBLENDU128 pfnU128;
3322	PFNIEMAIMPLAVXBLENDU256 pfnU256;
3323	} IEMOPBLENDOP;
3324	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3325	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3326
3327	/** @def IEMOPBLENDOP_INIT_VARS_EX
3328	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3329	* given functions as initializers. For use in AVX functions where a pair of
3330	* functions are only used once and the function table need not be public. */
3331	#ifndef TST_IEM_CHECK_MC
3332	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3333	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3334	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3335	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3336	# else
3337	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3338	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3339	# endif
3340	#else
3341	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3342	#endif
3343	/** @def IEMOPBLENDOP_INIT_VARS
3344	* Generate AVX function tables for the @a a_InstrNm instruction.
3345	* @sa IEMOPBLENDOP_INIT_VARS_EX */
3346	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3347	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3348	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3349
3350
3351	/** @name SSE/AVX single/double precision floating point operations.
3352	* @{ */
3353	/**
3354	* A SSE result.
3355	*/
3356	typedef struct IEMSSERESULT
3357	{
3358	/** The output value. */
3359	X86XMMREG uResult;
3360	/** The output status. */
3361	uint32_t MXCSR;
3362	} IEMSSERESULT;
3363	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3364	/** Pointer to a SSE result. */
3365	typedef IEMSSERESULT *PIEMSSERESULT;
3366	/** Pointer to a const SSE result. */
3367	typedef IEMSSERESULT const *PCIEMSSERESULT;
3368
3369
3370	/**
3371	* A AVX128 result.
3372	*/
3373	typedef struct IEMAVX128RESULT
3374	{
3375	/** The output value. */
3376	X86XMMREG uResult;
3377	/** The output status. */
3378	uint32_t MXCSR;
3379	} IEMAVX128RESULT;
3380	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3381	/** Pointer to a AVX128 result. */
3382	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3383	/** Pointer to a const AVX128 result. */
3384	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3385
3386
3387	/**
3388	* A AVX256 result.
3389	*/
3390	typedef struct IEMAVX256RESULT
3391	{
3392	/** The output value. */
3393	X86YMMREG uResult;
3394	/** The output status. */
3395	uint32_t MXCSR;
3396	} IEMAVX256RESULT;
3397	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3398	/** Pointer to a AVX256 result. */
3399	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3400	/** Pointer to a const AVX256 result. */
3401	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3402
3403
3404	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3405	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3406	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3407	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3408	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3409	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3410
3411	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3412	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3413	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3414	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3415	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3416	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3417
3418	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3419	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3420
3421	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3422	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3423	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3424	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3425	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3426	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3427	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3428	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3429	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3430	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3431	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3432	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3433	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3434	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3435	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3436	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3437	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3438	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3439	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3440	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3441	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3442	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3443	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3444
3445	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3446	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3447	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3448	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3449	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3450	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3451
3452	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3453	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3454	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3455	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3456	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3457	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3458	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3459	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3460	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3461	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3462	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3463	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3464	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3465	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3466	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3467	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3468	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3469
3470	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3471	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3472	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3473	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3474	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3475	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3476	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3477	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3478	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3479	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3480	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3481	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3482	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3483	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3484	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3485	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3486	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3487	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3488	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3489	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3490	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3491	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3492
3493	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3494	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3495	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3496	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3497	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3498	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3499	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3500	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3501	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3502	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3503	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3504	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3505	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3506	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3507
3508	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3509	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3510	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3511	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3512	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3513	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3514	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3515	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3516	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3517	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3518	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3519	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3520	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3521	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3522	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3523	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3524	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3525	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3526	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3527	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3528	/** @} */
3529
3530	/** @name C instruction implementations for anything slightly complicated.
3531	* @{ */
3532
3533	/**
3534	* For typedef'ing or declaring a C instruction implementation function taking
3535	* no extra arguments.
3536	*
3537	* @param a_Name The name of the type.
3538	*/
3539	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3540	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3541	/**
3542	* For defining a C instruction implementation function taking no extra
3543	* arguments.
3544	*
3545	* @param a_Name The name of the function
3546	*/
3547	# define IEM_CIMPL_DEF_0(a_Name) \
3548	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3549	/**
3550	* Prototype version of IEM_CIMPL_DEF_0.
3551	*/
3552	# define IEM_CIMPL_PROTO_0(a_Name) \
3553	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3554	/**
3555	* For calling a C instruction implementation function taking no extra
3556	* arguments.
3557	*
3558	* This special call macro adds default arguments to the call and allow us to
3559	* change these later.
3560	*
3561	* @param a_fn The name of the function.
3562	*/
3563	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3564
3565	/** Type for a C instruction implementation function taking no extra
3566	* arguments. */
3567	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
3568	/** Function pointer type for a C instruction implementation function taking
3569	* no extra arguments. */
3570	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
3571
3572	/**
3573	* For typedef'ing or declaring a C instruction implementation function taking
3574	* one extra argument.
3575	*
3576	* @param a_Name The name of the type.
3577	* @param a_Type0 The argument type.
3578	* @param a_Arg0 The argument name.
3579	*/
3580	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3581	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3582	/**
3583	* For defining a C instruction implementation function taking one extra
3584	* argument.
3585	*
3586	* @param a_Name The name of the function
3587	* @param a_Type0 The argument type.
3588	* @param a_Arg0 The argument name.
3589	*/
3590	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3591	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3592	/**
3593	* Prototype version of IEM_CIMPL_DEF_1.
3594	*/
3595	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3596	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3597	/**
3598	* For calling a C instruction implementation function taking one extra
3599	* argument.
3600	*
3601	* This special call macro adds default arguments to the call and allow us to
3602	* change these later.
3603	*
3604	* @param a_fn The name of the function.
3605	* @param a0 The name of the 1st argument.
3606	*/
3607	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3608
3609	/**
3610	* For typedef'ing or declaring a C instruction implementation function taking
3611	* two extra arguments.
3612	*
3613	* @param a_Name The name of the type.
3614	* @param a_Type0 The type of the 1st argument
3615	* @param a_Arg0 The name of the 1st argument.
3616	* @param a_Type1 The type of the 2nd argument.
3617	* @param a_Arg1 The name of the 2nd argument.
3618	*/
3619	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3620	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3621	/**
3622	* For defining a C instruction implementation function taking two extra
3623	* arguments.
3624	*
3625	* @param a_Name The name of the function.
3626	* @param a_Type0 The type of the 1st argument
3627	* @param a_Arg0 The name of the 1st argument.
3628	* @param a_Type1 The type of the 2nd argument.
3629	* @param a_Arg1 The name of the 2nd argument.
3630	*/
3631	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3632	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3633	/**
3634	* Prototype version of IEM_CIMPL_DEF_2.
3635	*/
3636	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3637	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3638	/**
3639	* For calling a C instruction implementation function taking two extra
3640	* arguments.
3641	*
3642	* This special call macro adds default arguments to the call and allow us to
3643	* change these later.
3644	*
3645	* @param a_fn The name of the function.
3646	* @param a0 The name of the 1st argument.
3647	* @param a1 The name of the 2nd argument.
3648	*/
3649	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3650
3651	/**
3652	* For typedef'ing or declaring a C instruction implementation function taking
3653	* three extra arguments.
3654	*
3655	* @param a_Name The name of the type.
3656	* @param a_Type0 The type of the 1st argument
3657	* @param a_Arg0 The name of the 1st argument.
3658	* @param a_Type1 The type of the 2nd argument.
3659	* @param a_Arg1 The name of the 2nd argument.
3660	* @param a_Type2 The type of the 3rd argument.
3661	* @param a_Arg2 The name of the 3rd argument.
3662	*/
3663	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3664	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3665	/**
3666	* For defining a C instruction implementation function taking three extra
3667	* arguments.
3668	*
3669	* @param a_Name The name of the function.
3670	* @param a_Type0 The type of the 1st argument
3671	* @param a_Arg0 The name of the 1st argument.
3672	* @param a_Type1 The type of the 2nd argument.
3673	* @param a_Arg1 The name of the 2nd argument.
3674	* @param a_Type2 The type of the 3rd argument.
3675	* @param a_Arg2 The name of the 3rd argument.
3676	*/
3677	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3678	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3679	/**
3680	* Prototype version of IEM_CIMPL_DEF_3.
3681	*/
3682	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3683	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3684	/**
3685	* For calling a C instruction implementation function taking three extra
3686	* arguments.
3687	*
3688	* This special call macro adds default arguments to the call and allow us to
3689	* change these later.
3690	*
3691	* @param a_fn The name of the function.
3692	* @param a0 The name of the 1st argument.
3693	* @param a1 The name of the 2nd argument.
3694	* @param a2 The name of the 3rd argument.
3695	*/
3696	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3697
3698
3699	/**
3700	* For typedef'ing or declaring a C instruction implementation function taking
3701	* four extra arguments.
3702	*
3703	* @param a_Name The name of the type.
3704	* @param a_Type0 The type of the 1st argument
3705	* @param a_Arg0 The name of the 1st argument.
3706	* @param a_Type1 The type of the 2nd argument.
3707	* @param a_Arg1 The name of the 2nd argument.
3708	* @param a_Type2 The type of the 3rd argument.
3709	* @param a_Arg2 The name of the 3rd argument.
3710	* @param a_Type3 The type of the 4th argument.
3711	* @param a_Arg3 The name of the 4th argument.
3712	*/
3713	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3714	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3715	/**
3716	* For defining a C instruction implementation function taking four extra
3717	* arguments.
3718	*
3719	* @param a_Name The name of the function.
3720	* @param a_Type0 The type of the 1st argument
3721	* @param a_Arg0 The name of the 1st argument.
3722	* @param a_Type1 The type of the 2nd argument.
3723	* @param a_Arg1 The name of the 2nd argument.
3724	* @param a_Type2 The type of the 3rd argument.
3725	* @param a_Arg2 The name of the 3rd argument.
3726	* @param a_Type3 The type of the 4th argument.
3727	* @param a_Arg3 The name of the 4th argument.
3728	*/
3729	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3730	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3731	a_Type2 a_Arg2, a_Type3 a_Arg3))
3732	/**
3733	* Prototype version of IEM_CIMPL_DEF_4.
3734	*/
3735	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3736	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3737	a_Type2 a_Arg2, a_Type3 a_Arg3))
3738	/**
3739	* For calling a C instruction implementation function taking four extra
3740	* arguments.
3741	*
3742	* This special call macro adds default arguments to the call and allow us to
3743	* change these later.
3744	*
3745	* @param a_fn The name of the function.
3746	* @param a0 The name of the 1st argument.
3747	* @param a1 The name of the 2nd argument.
3748	* @param a2 The name of the 3rd argument.
3749	* @param a3 The name of the 4th argument.
3750	*/
3751	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3752
3753
3754	/**
3755	* For typedef'ing or declaring a C instruction implementation function taking
3756	* five extra arguments.
3757	*
3758	* @param a_Name The name of the type.
3759	* @param a_Type0 The type of the 1st argument
3760	* @param a_Arg0 The name of the 1st argument.
3761	* @param a_Type1 The type of the 2nd argument.
3762	* @param a_Arg1 The name of the 2nd argument.
3763	* @param a_Type2 The type of the 3rd argument.
3764	* @param a_Arg2 The name of the 3rd argument.
3765	* @param a_Type3 The type of the 4th argument.
3766	* @param a_Arg3 The name of the 4th argument.
3767	* @param a_Type4 The type of the 5th argument.
3768	* @param a_Arg4 The name of the 5th argument.
3769	*/
3770	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3771	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3772	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3773	a_Type3 a_Arg3, a_Type4 a_Arg4))
3774	/**
3775	* For defining a C instruction implementation function taking five extra
3776	* arguments.
3777	*
3778	* @param a_Name The name of the function.
3779	* @param a_Type0 The type of the 1st argument
3780	* @param a_Arg0 The name of the 1st argument.
3781	* @param a_Type1 The type of the 2nd argument.
3782	* @param a_Arg1 The name of the 2nd argument.
3783	* @param a_Type2 The type of the 3rd argument.
3784	* @param a_Arg2 The name of the 3rd argument.
3785	* @param a_Type3 The type of the 4th argument.
3786	* @param a_Arg3 The name of the 4th argument.
3787	* @param a_Type4 The type of the 5th argument.
3788	* @param a_Arg4 The name of the 5th argument.
3789	*/
3790	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3791	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3792	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3793	/**
3794	* Prototype version of IEM_CIMPL_DEF_5.
3795	*/
3796	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3797	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3798	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3799	/**
3800	* For calling a C instruction implementation function taking five extra
3801	* arguments.
3802	*
3803	* This special call macro adds default arguments to the call and allow us to
3804	* change these later.
3805	*
3806	* @param a_fn The name of the function.
3807	* @param a0 The name of the 1st argument.
3808	* @param a1 The name of the 2nd argument.
3809	* @param a2 The name of the 3rd argument.
3810	* @param a3 The name of the 4th argument.
3811	* @param a4 The name of the 5th argument.
3812	*/
3813	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3814
3815	/** @} */
3816
3817
3818	/** @name Opcode Decoder Function Types.
3819	* @{ */
3820
3821	/** @typedef PFNIEMOP
3822	* Pointer to an opcode decoder function.
3823	*/
3824
3825	/** @def FNIEMOP_DEF
3826	* Define an opcode decoder function.
3827	*
3828	* We're using macors for this so that adding and removing parameters as well as
3829	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3830	*
3831	* @param a_Name The function name.
3832	*/
3833
3834	/** @typedef PFNIEMOPRM
3835	* Pointer to an opcode decoder function with RM byte.
3836	*/
3837
3838	/** @def FNIEMOPRM_DEF
3839	* Define an opcode decoder function with RM byte.
3840	*
3841	* We're using macors for this so that adding and removing parameters as well as
3842	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3843	*
3844	* @param a_Name The function name.
3845	*/
3846
3847	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3848	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3849	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3850	# define FNIEMOP_DEF(a_Name) \
3851	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3852	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3853	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3854	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3855	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3856
3857	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3858	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3859	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3860	# define FNIEMOP_DEF(a_Name) \
3861	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3862	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3863	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3864	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3865	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3866
3867	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
3868	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3869	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3870	# define FNIEMOP_DEF(a_Name) \
3871	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3872	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3873	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3874	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3875	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3876
3877	#else
3878	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3879	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3880	# define FNIEMOP_DEF(a_Name) \
3881	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3882	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3883	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3884	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3885	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3886
3887	#endif
3888	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3889
3890	/**
3891	* Call an opcode decoder function.
3892	*
3893	* We're using macors for this so that adding and removing parameters can be
3894	* done as we please. See FNIEMOP_DEF.
3895	*/
3896	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3897
3898	/**
3899	* Call a common opcode decoder function taking one extra argument.
3900	*
3901	* We're using macors for this so that adding and removing parameters can be
3902	* done as we please. See FNIEMOP_DEF_1.
3903	*/
3904	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3905
3906	/**
3907	* Call a common opcode decoder function taking one extra argument.
3908	*
3909	* We're using macors for this so that adding and removing parameters can be
3910	* done as we please. See FNIEMOP_DEF_1.
3911	*/
3912	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3913	/** @} */
3914
3915
3916	/** @name Misc Helpers
3917	* @{ */
3918
3919	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3920	* due to GCC lacking knowledge about the value range of a switch. */
3921	#if RT_CPLUSPLUS_PREREQ(202000)
3922	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3923	#else
3924	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3925	#endif
3926
3927	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3928	#if RT_CPLUSPLUS_PREREQ(202000)
3929	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3930	#else
3931	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3932	#endif
3933
3934	/**
3935	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3936	* occation.
3937	*/
3938	#ifdef LOG_ENABLED
3939	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3940	do { \
3941	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3942	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3943	} while (0)
3944	#else
3945	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3946	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3947	#endif
3948
3949	/**
3950	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3951	* occation using the supplied logger statement.
3952	*
3953	* @param a_LoggerArgs What to log on failure.
3954	*/
3955	#ifdef LOG_ENABLED
3956	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3957	do { \
3958	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3959	/LogFunc(a_LoggerArgs);/ \
3960	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3961	} while (0)
3962	#else
3963	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3964	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3965	#endif
3966
3967	/**
3968	* Gets the CPU mode (from fExec) as a IEMMODE value.
3969	*
3970	* @returns IEMMODE
3971	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3972	*/
3973	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
3974
3975	/**
3976	* Check if we're currently executing in real or virtual 8086 mode.
3977	*
3978	* @returns @c true if it is, @c false if not.
3979	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3980	*/
3981	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
3982	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
3983
3984	/**
3985	* Check if we're currently executing in virtual 8086 mode.
3986	*
3987	* @returns @c true if it is, @c false if not.
3988	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3989	*/
3990	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
3991
3992	/**
3993	* Check if we're currently executing in long mode.
3994	*
3995	* @returns @c true if it is, @c false if not.
3996	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3997	*/
3998	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3999
4000	/**
4001	* Check if we're currently executing in a 16-bit code segment.
4002	*
4003	* @returns @c true if it is, @c false if not.
4004	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4005	*/
4006	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4007
4008	/**
4009	* Check if we're currently executing in a 32-bit code segment.
4010	*
4011	* @returns @c true if it is, @c false if not.
4012	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4013	*/
4014	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4015
4016	/**
4017	* Check if we're currently executing in a 64-bit code segment.
4018	*
4019	* @returns @c true if it is, @c false if not.
4020	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4021	*/
4022	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4023
4024	/**
4025	* Check if we're currently executing in real mode.
4026	*
4027	* @returns @c true if it is, @c false if not.
4028	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4029	*/
4030	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4031
4032	/**
4033	* Gets the current protection level (CPL).
4034	*
4035	* @returns 0..3
4036	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4037	*/
4038	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4039
4040	/**
4041	* Sets the current protection level (CPL).
4042	*
4043	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4044	*/
4045	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4046	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4047
4048	/**
4049	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
4050	* @returns PCCPUMFEATURES
4051	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4052	*/
4053	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
4054
4055	/**
4056	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
4057	* @returns PCCPUMFEATURES
4058	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4059	*/
4060	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
4061
4062	/**
4063	* Evaluates to true if we're presenting an Intel CPU to the guest.
4064	*/
4065	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
4066
4067	/**
4068	* Evaluates to true if we're presenting an AMD CPU to the guest.
4069	*/
4070	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
4071
4072	/**
4073	* Check if the address is canonical.
4074	*/
4075	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
4076
4077	/** Checks if the ModR/M byte is in register mode or not. */
4078	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
4079	/** Checks if the ModR/M byte is in memory mode or not. */
4080	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
4081
4082	/**
4083	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
4084	*
4085	* For use during decoding.
4086	*/
4087	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
4088	/**
4089	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
4090	*
4091	* For use during decoding.
4092	*/
4093	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
4094
4095	/**
4096	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
4097	*
4098	* For use during decoding.
4099	*/
4100	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
4101	/**
4102	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
4103	*
4104	* For use during decoding.
4105	*/
4106	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
4107
4108	/**
4109	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
4110	* register index, with REX.R added in.
4111	*
4112	* For use during decoding.
4113	*
4114	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4115	*/
4116	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4117	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4118	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4119	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
4120	/**
4121	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4122	* with REX.B added in.
4123	*
4124	* For use during decoding.
4125	*
4126	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4127	*/
4128	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4129	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4130	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4131	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
4132
4133	/**
4134	* Combines the prefix REX and ModR/M byte for passing to
4135	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4136	*
4137	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4138	* The two bits are part of the REG sub-field, which isn't needed in
4139	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4140	*
4141	* For use during decoding/recompiling.
4142	*/
4143	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
4144	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
4145	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
4146	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
4147	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
4148
4149	/**
4150	* Gets the effective VEX.VVVV value.
4151	*
4152	* The 4th bit is ignored if not 64-bit code.
4153	* @returns effective V-register value.
4154	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4155	*/
4156	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
4157	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
4158
4159
4160	/**
4161	* Checks if we're executing inside an AMD-V or VT-x guest.
4162	*/
4163	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
4164	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
4165	#else
4166	# define IEM_IS_IN_GUEST(a_pVCpu) false
4167	#endif
4168
4169
4170	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4171
4172	/**
4173	* Check if the guest has entered VMX root operation.
4174	*/
4175	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
4176
4177	/**
4178	* Check if the guest has entered VMX non-root operation.
4179	*/
4180	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
4181	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
4182
4183	/**
4184	* Check if the nested-guest has the given Pin-based VM-execution control set.
4185	*/
4186	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
4187
4188	/**
4189	* Check if the nested-guest has the given Processor-based VM-execution control set.
4190	*/
4191	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
4192
4193	/**
4194	* Check if the nested-guest has the given Secondary Processor-based VM-execution
4195	* control set.
4196	*/
4197	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
4198
4199	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
4200	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
4201
4202	/** Whether a shadow VMCS is present for the given VCPU. */
4203	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4204
4205	/** Gets the VMXON region pointer. */
4206	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
4207
4208	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
4209	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
4210
4211	/** Whether a current VMCS is present for the given VCPU. */
4212	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4213
4214	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
4215	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
4216	do \
4217	{ \
4218	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
4219	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
4220	} while (0)
4221
4222	/** Clears any current VMCS for the given VCPU. */
4223	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
4224	do \
4225	{ \
4226	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
4227	} while (0)
4228
4229	/**
4230	* Invokes the VMX VM-exit handler for an instruction intercept.
4231	*/
4232	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
4233	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
4234
4235	/**
4236	* Invokes the VMX VM-exit handler for an instruction intercept where the
4237	* instruction provides additional VM-exit information.
4238	*/
4239	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
4240	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
4241
4242	/**
4243	* Invokes the VMX VM-exit handler for a task switch.
4244	*/
4245	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
4246	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
4247
4248	/**
4249	* Invokes the VMX VM-exit handler for MWAIT.
4250	*/
4251	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
4252	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
4253
4254	/**
4255	* Invokes the VMX VM-exit handler for EPT faults.
4256	*/
4257	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
4258	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
4259
4260	/**
4261	* Invokes the VMX VM-exit handler.
4262	*/
4263	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
4264	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
4265
4266	#else
4267	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
4268	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
4269	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4270	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4271	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4272	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4273	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4274	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4275	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4276	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4277	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4278
4279	#endif
4280
4281	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4282	/**
4283	* Checks if we're executing a guest using AMD-V.
4284	*/
4285	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
4286	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
4287	/**
4288	* Check if an SVM control/instruction intercept is set.
4289	*/
4290	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4291	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4292
4293	/**
4294	* Check if an SVM read CRx intercept is set.
4295	*/
4296	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4297	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4298
4299	/**
4300	* Check if an SVM write CRx intercept is set.
4301	*/
4302	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4303	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4304
4305	/**
4306	* Check if an SVM read DRx intercept is set.
4307	*/
4308	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4309	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4310
4311	/**
4312	* Check if an SVM write DRx intercept is set.
4313	*/
4314	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4315	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4316
4317	/**
4318	* Check if an SVM exception intercept is set.
4319	*/
4320	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4321	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4322
4323	/**
4324	* Invokes the SVM \#VMEXIT handler for the nested-guest.
4325	*/
4326	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4327	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4328
4329	/**
4330	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4331	* corresponding decode assist information.
4332	*/
4333	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4334	do \
4335	{ \
4336	uint64_t uExitInfo1; \
4337	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4338	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4339	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
4340	else \
4341	uExitInfo1 = 0; \
4342	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4343	} while (0)
4344
4345	/** Check and handles SVM nested-guest instruction intercept and updates
4346	* NRIP if needed.
4347	*/
4348	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4349	do \
4350	{ \
4351	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4352	{ \
4353	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4354	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4355	} \
4356	} while (0)
4357
4358	/** Checks and handles SVM nested-guest CR0 read intercept. */
4359	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4360	do \
4361	{ \
4362	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4363	{ /* probably likely */ } \
4364	else \
4365	{ \
4366	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4367	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4368	} \
4369	} while (0)
4370
4371	/**
4372	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
4373	*/
4374	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4375	do { \
4376	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4377	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4378	} while (0)
4379
4380	#else
4381	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4382	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4383	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4384	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4385	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4386	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4387	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4388	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4389	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4390	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4391	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4392	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4393
4394	#endif
4395
4396	/** @} */
4397
4398	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4399	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4400
4401
4402	/**
4403	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4404	*/
4405	typedef union IEMSELDESC
4406	{
4407	/** The legacy view. */
4408	X86DESC Legacy;
4409	/** The long mode view. */
4410	X86DESC64 Long;
4411	} IEMSELDESC;
4412	/** Pointer to a selector descriptor table entry. */
4413	typedef IEMSELDESC *PIEMSELDESC;
4414
4415	/** @name Raising Exceptions.
4416	* @{ */
4417	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4418	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4419
4420	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4421	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4422	#ifdef IEM_WITH_SETJMP
4423	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4424	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4425	#endif
4426	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4427	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4428	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4429	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4430	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4431	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4432	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4433	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4434	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4435	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
4436	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4437	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4438	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4439	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4440	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4441	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4442	#ifdef IEM_WITH_SETJMP
4443	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4444	#endif
4445	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4446	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4447	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4448	#ifdef IEM_WITH_SETJMP
4449	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4450	#endif
4451	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4452	#ifdef IEM_WITH_SETJMP
4453	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4454	#endif
4455	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4456	#ifdef IEM_WITH_SETJMP
4457	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4458	#endif
4459	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4460	#ifdef IEM_WITH_SETJMP
4461	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4462	#endif
4463	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4464	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4465	#ifdef IEM_WITH_SETJMP
4466	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4467	#endif
4468	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4469
4470	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
4471
4472	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4473	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4474	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4475
4476	/**
4477	* Macro for calling iemCImplRaiseDivideError().
4478	*
4479	* This is for things that will _always_ decode to an \#DE, taking the
4480	* recompiler into consideration and everything.
4481	*
4482	* @return Strict VBox status code.
4483	*/
4484	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseDivideError)
4485
4486	/**
4487	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4488	*
4489	* This is for things that will _always_ decode to an \#UD, taking the
4490	* recompiler into consideration and everything.
4491	*
4492	* @return Strict VBox status code.
4493	*/
4494	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidLockPrefix)
4495
4496	/**
4497	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
4498	*
4499	* This is for things that will _always_ decode to an \#UD, taking the
4500	* recompiler into consideration and everything.
4501	*
4502	* @return Strict VBox status code.
4503	*/
4504	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4505
4506	/**
4507	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
4508	*
4509	* Using this macro means you've got _buggy_ _code_ and are doing things that
4510	* belongs exclusively in IEMAllCImpl.cpp during decoding.
4511	*
4512	* @return Strict VBox status code.
4513	* @see IEMOP_RAISE_INVALID_OPCODE_RET
4514	*/
4515	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4516
4517	/** @} */
4518
4519	/** @name Register Access.
4520	* @{ */
4521	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4522	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4523	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4524	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4525	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4526	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4527	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4528	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4529	/** @} */
4530
4531	/** @name FPU access and helpers.
4532	* @{ */
4533	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4534	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4535	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4536	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4537	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4538	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4539	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4540	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4541	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4542	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4543	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4544	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4545	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4546	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4547	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4548	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4549	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4550	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4551	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4552	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4553	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4554	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4555	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4556	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4557	/** @} */
4558
4559	/** @name SSE+AVX SIMD access and helpers.
4560	* @{ */
4561	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
4562	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
4563	/** @} */
4564
4565	/** @name Memory access.
4566	* @{ */
4567
4568	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
4569	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
4570	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
4571	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
4572	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
4573	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
4574	* Users include FXSAVE & FXRSTOR. */
4575	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
4576
4577	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
4578	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
4579	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4580	#ifndef IN_RING3
4581	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4582	#endif
4583	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
4584	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
4585	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4586	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
4587
4588	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
4589	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
4590	#ifdef IEM_WITH_CODE_TLB
4591	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
4592	#else
4593	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
4594	#endif
4595	#ifdef IEM_WITH_SETJMP
4596	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4597	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4598	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4599	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4600	#else
4601	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
4602	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4603	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4604	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4605	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4606	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4607	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4608	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4609	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4610	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4611	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4612	#endif
4613
4614	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4615	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4616	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4617	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4618	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4619	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4620	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4621	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4622	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4623	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4624	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4625	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4626	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
4627	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
4628	#ifdef IEM_WITH_SETJMP
4629	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4630	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4631	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4632	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4633	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4634	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4635	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4636	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4637	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4638	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4639	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4640	void iemMemFetchDataU256AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4641	# if 0 /* these are inlined now */
4642	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4643	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4644	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4645	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4646	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4647	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4648	# endif
4649	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4650	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4651	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4652	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4653	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4654	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4655	#endif
4656
4657	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4658	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4659	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4660	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4661	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
4662
4663	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
4664	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
4665	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
4666	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
4667	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4668	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4669	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4670	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4671	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4672	#ifdef IEM_WITH_SETJMP
4673	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4674	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4675	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4676	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4677	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4678	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4679	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4680	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4681	#if 0
4682	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4683	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4684	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4685	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4686	#endif
4687	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4688	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4689	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4690	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4691	#endif
4692
4693	#ifdef IEM_WITH_SETJMP
4694	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4695	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4696	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4697	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4698	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4699	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4700	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4701	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4702	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4703	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4704	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4705	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4706
4707	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
4708	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
4709	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, const void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
4710	#endif
4711
4712	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4713	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4714	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
4715	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
4716	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4717	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
4718	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4719	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4720	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4721	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4722	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4723	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4724	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
4725	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
4726	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
4727	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
4728	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
4729	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
4730	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4731	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4732	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4733
4734	#ifdef IEM_WITH_SETJMP
4735	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4736	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4737	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4738	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4739	uint16_t iemMemStackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4740	uint32_t iemMemStackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4741	uint64_t iemMemStackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4742
4743	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4744	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4745	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4746	uint16_t iemMemFlat32StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4747	uint32_t iemMemFlat32StackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4748
4749	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4750	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4751	uint16_t iemMemFlat64StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4752	uint64_t iemMemFlat64StackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4753	#endif
4754
4755	/** @} */
4756
4757	/** @name IEMAllCImpl.cpp
4758	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
4759	* @{ */
4760	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4761	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4762	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4763	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
4764	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
4765	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
4766	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
4767	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
4768	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
4769	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
4770	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
4771	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
4772	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
4773	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
4774	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
4775	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4776	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4777	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4778	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
4779	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
4780	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
4781	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
4782	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
4783	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
4784	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
4785	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
4786	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
4787	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
4788	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
4789	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
4790	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
4791	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
4792	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
4793	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
4794	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
4795	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
4796	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
4797	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
4798	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
4799	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4800	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4801	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4802	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4803	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4804	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4805	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4806	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4807	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4808	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4809	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4810	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4811	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4812	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4813	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4814	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4815	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4816	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4817	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4818	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4819	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4820	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4821	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4822	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4823	IEM_CIMPL_PROTO_0(iemCImpl_clts);
4824	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4825	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4826	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4827	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4828	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4829	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4830	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4831	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4832	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4833	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4834	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4835	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4836	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4837	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4838	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4839	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4840	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4841	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4842	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4843	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4844	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4845	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4846	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4847	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4848	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4849	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4850	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4851	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4852	IEM_CIMPL_PROTO_0(iemCImpl_das);
4853	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4854	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4855	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4856	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4857	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4858	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4859	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4860	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4861	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4862	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4863	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4864	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4865	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4866	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4867	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4868	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4869	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4870	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4871	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4872	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4873	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4874	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4875	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
4876	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, uint32_t, uPopAndFpuOpcode);
4877	/** @} */
4878
4879	/** @name IEMAllCImplStrInstr.cpp.h
4880	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4881	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4882	* @{ */
4883	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4884	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4885	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4886	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4887	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4888	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4889	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4890	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4891	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4892	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4893	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4894
4895	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4896	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4897	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4898	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4899	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4900	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4901	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4902	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4903	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4904	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4905	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4906
4907	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4908	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4909	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4910	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4911	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4912	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4913	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4914	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4915	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4916	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4917	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4918
4919
4920	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4921	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4922	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4923	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4924	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4925	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4926	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4927	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4928	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4929	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4930	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4931
4932	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4933	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4934	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4935	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4936	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4937	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4938	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4939	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4940	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4941	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4942	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4943
4944	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4945	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4946	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4947	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4948	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4949	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4950	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4951	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4952	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4953	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4954	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4955
4956	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4957	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4958	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4959	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4960	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4961	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4962	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4963	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4964	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4965	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4966	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4967
4968
4969	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4970	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4971	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4972	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4973	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4974	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4975	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4976	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4977	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4978	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4979	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4980
4981	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4982	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4983	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4984	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4985	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4986	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4987	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4988	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4989	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4990	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4991	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4992
4993	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4994	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4995	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4996	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4997	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4998	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4999	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
5000	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
5001	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
5002	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5003	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5004
5005	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
5006	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
5007	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
5008	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
5009	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
5010	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
5011	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
5012	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
5013	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
5014	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5015	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5016	/** @} */
5017
5018	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5019	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
5020	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
5021	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
5022	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
5023	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
5024	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5025	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
5026	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
5027	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
5028	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
5029	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
5030	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
5031	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
5032	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5033	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5034	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5035	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5036	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5037	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5038	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
5039	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
5040	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
5041	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
5042	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
5043	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
5044	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
5045	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
5046	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
5047	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
5048	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
5049	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
5050	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
5051	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
5052	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
5053	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5054	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5055	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5056	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
5057	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
5058	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
5059	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
5060	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
5061	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
5062	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
5063	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
5064	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
5065	#endif
5066
5067	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5068	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
5069	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5070	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
5071	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
5072	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
5073	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
5074	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
5075	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
5076	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
5077	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
5078	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
5079	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
5080	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
5081	#endif
5082
5083	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
5084	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
5085	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
5086
5087	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
5088	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
5089	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
5090	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
5091	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
5092	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
5093	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
5094
5095	/*
5096	* Recompiler related stuff.
5097	*/
5098	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
5099	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
5100	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
5101	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
5102	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
5103	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
5104	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
5105
5106	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb);
5107
5108	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
5109	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5110	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5111	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5112	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5113	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5114	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5115	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5116
5117	#else
5118	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5119	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5120	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5121	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5122	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5123	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5124	#endif
5125
5126
5127	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
5128
5129	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
5130	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
5131	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
5132	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
5133
5134	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
5135	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
5136	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
5137
5138	/* Branching: */
5139	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
5140	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
5141	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
5142
5143	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
5144	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
5145	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
5146
5147	/* Natural page crossing: */
5148	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
5149	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
5150	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
5151
5152	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
5153	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
5154	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
5155
5156	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
5157	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
5158	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
5159
5160	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
5161	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
5162
5163
5164	/** @} */
5165
5166	RT_C_DECLS_END
5167
5168	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
5169

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 100931

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