VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 100594

Last change on this file since 100594 was 100591, checked in by vboxsync, 17 months ago

VMM/IEM: Must pass the FPU opcode word to the various MCs updating FOP as IEMCPU::uFpuOpcode isn't available during recompiled code execution. bugref:10369

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1/* $Id: IEMInternal.h 100591 2023-07-15 01:20:13Z vboxsync $ */
2/** @file
3 * IEM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29#define VMM_INCLUDED_SRC_include_IEMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/vmm/cpum.h>
35#include <VBox/vmm/iem.h>
36#include <VBox/vmm/pgm.h>
37#include <VBox/vmm/stam.h>
38#include <VBox/param.h>
39
40#include <iprt/setjmp-without-sigmask.h>
41
42
43RT_C_DECLS_BEGIN
44
45
46/** @defgroup grp_iem_int Internals
47 * @ingroup grp_iem
48 * @internal
49 * @{
50 */
51
52/** For expanding symbol in slickedit and other products tagging and
53 * crossreferencing IEM symbols. */
54#ifndef IEM_STATIC
55# define IEM_STATIC static
56#endif
57
58/** @def IEM_WITH_SETJMP
59 * Enables alternative status code handling using setjmps.
60 *
61 * This adds a bit of expense via the setjmp() call since it saves all the
62 * non-volatile registers. However, it eliminates return code checks and allows
63 * for more optimal return value passing (return regs instead of stack buffer).
64 */
65#if defined(DOXYGEN_RUNNING) || defined(RT_OS_WINDOWS) || 1
66# define IEM_WITH_SETJMP
67#endif
68
69/** @def IEM_WITH_THROW_CATCH
70 * Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
71 * mode code when IEM_WITH_SETJMP is in effect.
72 *
73 * With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
74 * setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
75 * result value improving by more than 1%. (Best out of three.)
76 *
77 * With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
78 * setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
79 * the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
80 * Linux, but it should be quite a bit faster for normal code.
81 */
82#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) || defined(_MSC_VER))) \
83 || defined(DOXYGEN_RUNNING)
84# define IEM_WITH_THROW_CATCH
85#endif
86
87/** @def IEM_DO_LONGJMP
88 *
89 * Wrapper around longjmp / throw.
90 *
91 * @param a_pVCpu The CPU handle.
92 * @param a_rc The status code jump back with / throw.
93 */
94#if defined(IEM_WITH_SETJMP) || defined(DOXYGEN_RUNNING)
95# ifdef IEM_WITH_THROW_CATCH
96# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
97# else
98# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
99# endif
100#endif
101
102/** For use with IEM function that may do a longjmp (when enabled).
103 *
104 * Visual C++ has trouble longjmp'ing from/over functions with the noexcept
105 * attribute. So, we indicate that function that may be part of a longjmp may
106 * throw "exceptions" and that the compiler should definitely not generate and
107 * std::terminate calling unwind code.
108 *
109 * Here is one example of this ending in std::terminate:
110 * @code{.txt}
11100 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
11201 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
11302 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
11403 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
11504 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
11605 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
11706 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
11807 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
11908 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
12009 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
1210a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
1220b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
1230c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
1240d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
1250e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
1260f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
12710 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
128 @endcode
129 *
130 * @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
131 */
132#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) || defined(IEM_WITH_THROW_CATCH))
133# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
134#else
135# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
136#endif
137
138#define IEM_IMPLEMENTS_TASKSWITCH
139
140/** @def IEM_WITH_3DNOW
141 * Includes the 3DNow decoding. */
142#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
143# define IEM_WITH_3DNOW
144#endif
145
146/** @def IEM_WITH_THREE_0F_38
147 * Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
148#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
149# define IEM_WITH_THREE_0F_38
150#endif
151
152/** @def IEM_WITH_THREE_0F_3A
153 * Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
154#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
155# define IEM_WITH_THREE_0F_3A
156#endif
157
158/** @def IEM_WITH_VEX
159 * Includes the VEX decoding. */
160#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
161# define IEM_WITH_VEX
162#endif
163
164/** @def IEM_CFG_TARGET_CPU
165 * The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
166 *
167 * By default we allow this to be configured by the user via the
168 * CPUM/GuestCpuName config string, but this comes at a slight cost during
169 * decoding. So, for applications of this code where there is no need to
170 * be dynamic wrt target CPU, just modify this define.
171 */
172#if !defined(IEM_CFG_TARGET_CPU) || defined(DOXYGEN_RUNNING)
173# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
174#endif
175
176//#define IEM_WITH_CODE_TLB // - work in progress
177//#define IEM_WITH_DATA_TLB // - work in progress
178
179
180/** @def IEM_USE_UNALIGNED_DATA_ACCESS
181 * Use unaligned accesses instead of elaborate byte assembly. */
182#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) || defined(DOXYGEN_RUNNING)
183# define IEM_USE_UNALIGNED_DATA_ACCESS
184#endif
185
186//#define IEM_LOG_MEMORY_WRITES
187
188#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
189/** Instruction statistics. */
190typedef struct IEMINSTRSTATS
191{
192# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
193# include "IEMInstructionStatisticsTmpl.h"
194# undef IEM_DO_INSTR_STAT
195} IEMINSTRSTATS;
196#else
197struct IEMINSTRSTATS;
198typedef struct IEMINSTRSTATS IEMINSTRSTATS;
199#endif
200/** Pointer to IEM instruction statistics. */
201typedef IEMINSTRSTATS *PIEMINSTRSTATS;
202
203
204/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
205 * @{ */
206#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /**< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. */
207#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /**< Intel EFLAGS result. */
208#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /**< AMD EFLAGS result */
209#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /**< Reserved/dummy entry slot that's the same as 0. */
210#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /**< For masking the index before use. */
211/** Selects the right variant from a_aArray.
212 * pVCpu is implicit in the caller context. */
213#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
214 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
215/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
216 * be used because the host CPU does not support the operation. */
217#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
218 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
219/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
220 * array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
221 * into the two.
222 * @sa IEM_SELECT_NATIVE_OR_FALLBACK */
223#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
224# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
225 (a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
226#else
227# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
228 (a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
229#endif
230/** @} */
231
232/**
233 * Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
234 * indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
235 *
236 * On non-x86 hosts, this will shortcut to the fallback w/o checking the
237 * indicator.
238 *
239 * @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
240 */
241#if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
242# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
243 (g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
244#else
245# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
246#endif
247
248
249/**
250 * Extended operand mode that includes a representation of 8-bit.
251 *
252 * This is used for packing down modes when invoking some C instruction
253 * implementations.
254 */
255typedef enum IEMMODEX
256{
257 IEMMODEX_16BIT = IEMMODE_16BIT,
258 IEMMODEX_32BIT = IEMMODE_32BIT,
259 IEMMODEX_64BIT = IEMMODE_64BIT,
260 IEMMODEX_8BIT
261} IEMMODEX;
262AssertCompileSize(IEMMODEX, 4);
263
264
265/**
266 * Branch types.
267 */
268typedef enum IEMBRANCH
269{
270 IEMBRANCH_JUMP = 1,
271 IEMBRANCH_CALL,
272 IEMBRANCH_TRAP,
273 IEMBRANCH_SOFTWARE_INT,
274 IEMBRANCH_HARDWARE_INT
275} IEMBRANCH;
276AssertCompileSize(IEMBRANCH, 4);
277
278
279/**
280 * INT instruction types.
281 */
282typedef enum IEMINT
283{
284 /** INT n instruction (opcode 0xcd imm). */
285 IEMINT_INTN = 0,
286 /** Single byte INT3 instruction (opcode 0xcc). */
287 IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
288 /** Single byte INTO instruction (opcode 0xce). */
289 IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
290 /** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
291 IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
292} IEMINT;
293AssertCompileSize(IEMINT, 4);
294
295
296/**
297 * A FPU result.
298 */
299typedef struct IEMFPURESULT
300{
301 /** The output value. */
302 RTFLOAT80U r80Result;
303 /** The output status. */
304 uint16_t FSW;
305} IEMFPURESULT;
306AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
307/** Pointer to a FPU result. */
308typedef IEMFPURESULT *PIEMFPURESULT;
309/** Pointer to a const FPU result. */
310typedef IEMFPURESULT const *PCIEMFPURESULT;
311
312
313/**
314 * A FPU result consisting of two output values and FSW.
315 */
316typedef struct IEMFPURESULTTWO
317{
318 /** The first output value. */
319 RTFLOAT80U r80Result1;
320 /** The output status. */
321 uint16_t FSW;
322 /** The second output value. */
323 RTFLOAT80U r80Result2;
324} IEMFPURESULTTWO;
325AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
326AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
327/** Pointer to a FPU result consisting of two output values and FSW. */
328typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
329/** Pointer to a const FPU result consisting of two output values and FSW. */
330typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
331
332
333/**
334 * IEM TLB entry.
335 *
336 * Lookup assembly:
337 * @code{.asm}
338 ; Calculate tag.
339 mov rax, [VA]
340 shl rax, 16
341 shr rax, 16 + X86_PAGE_SHIFT
342 or rax, [uTlbRevision]
343
344 ; Do indexing.
345 movzx ecx, al
346 lea rcx, [pTlbEntries + rcx]
347
348 ; Check tag.
349 cmp [rcx + IEMTLBENTRY.uTag], rax
350 jne .TlbMiss
351
352 ; Check access.
353 mov rax, ACCESS_FLAGS | MAPPING_R3_NOT_VALID | 0xffffff00
354 and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
355 cmp rax, [uTlbPhysRev]
356 jne .TlbMiss
357
358 ; Calc address and we're done.
359 mov eax, X86_PAGE_OFFSET_MASK
360 and eax, [VA]
361 or rax, [rcx + IEMTLBENTRY.pMappingR3]
362 %ifdef VBOX_WITH_STATISTICS
363 inc qword [cTlbHits]
364 %endif
365 jmp .Done
366
367 .TlbMiss:
368 mov r8d, ACCESS_FLAGS
369 mov rdx, [VA]
370 mov rcx, [pVCpu]
371 call iemTlbTypeMiss
372 .Done:
373
374 @endcode
375 *
376 */
377typedef struct IEMTLBENTRY
378{
379 /** The TLB entry tag.
380 * Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
381 * is ASSUMING a virtual address width of 48 bits.
382 *
383 * Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
384 *
385 * The TLB lookup code uses the current TLB revision, which won't ever be zero,
386 * enabling an extremely cheap TLB invalidation most of the time. When the TLB
387 * revision wraps around though, the tags needs to be zeroed.
388 *
389 * @note Try use SHRD instruction? After seeing
390 * https://gmplib.org/~tege/x86-timing.pdf, maybe not.
391 *
392 * @todo This will need to be reorganized for 57-bit wide virtual address and
393 * PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
394 * have to move the TLB entry versioning entirely to the
395 * fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
396 * 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
397 * consumed by PCID and ASID (12 + 6 = 18).
398 */
399 uint64_t uTag;
400 /** Access flags and physical TLB revision.
401 *
402 * - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
403 * - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
404 * - Bit 2 - page tables - not user (complemented X86_PTE_US).
405 * - Bit 3 - pgm phys/virt - not directly writable.
406 * - Bit 4 - pgm phys page - not directly readable.
407 * - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
408 * - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
409 * - Bit 7 - tlb entry - pMappingR3 member not valid.
410 * - Bits 63 thru 8 are used for the physical TLB revision number.
411 *
412 * We're using complemented bit meanings here because it makes it easy to check
413 * whether special action is required. For instance a user mode write access
414 * would do a "TEST fFlags, (X86_PTE_RW | X86_PTE_US | X86_PTE_D)" and a
415 * non-zero result would mean special handling needed because either it wasn't
416 * writable, or it wasn't user, or the page wasn't dirty. A user mode read
417 * access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
418 * need to check any PTE flag.
419 */
420 uint64_t fFlagsAndPhysRev;
421 /** The guest physical page address. */
422 uint64_t GCPhys;
423 /** Pointer to the ring-3 mapping. */
424 R3PTRTYPE(uint8_t *) pbMappingR3;
425#if HC_ARCH_BITS == 32
426 uint32_t u32Padding1;
427#endif
428} IEMTLBENTRY;
429AssertCompileSize(IEMTLBENTRY, 32);
430/** Pointer to an IEM TLB entry. */
431typedef IEMTLBENTRY *PIEMTLBENTRY;
432
433/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
434 * @{ */
435#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /**< Page tables: Not executable. */
436#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /**< Page tables: Not writable. */
437#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /**< Page tables: Not user accessible (supervisor only). */
438#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /**< Phys page: Not writable (access handler, ROM, whatever). */
439#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /**< Phys page: Not readable (MMIO / access handler, ROM) */
440#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /**< Phys tables: Not accessed (need to be marked accessed). */
441#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /**< Page tables: Not dirty (needs to be made dirty on write). */
442#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /**< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. */
443#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /**< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
444#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
445/** @} */
446
447
448/**
449 * An IEM TLB.
450 *
451 * We've got two of these, one for data and one for instructions.
452 */
453typedef struct IEMTLB
454{
455 /** The TLB entries.
456 * We've choosen 256 because that way we can obtain the result directly from a
457 * 8-bit register without an additional AND instruction. */
458 IEMTLBENTRY aEntries[256];
459 /** The TLB revision.
460 * This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
461 * by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
462 * the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
463 * (The revision zero indicates an invalid TLB entry.)
464 *
465 * The initial value is choosen to cause an early wraparound. */
466 uint64_t uTlbRevision;
467 /** The TLB physical address revision - shadow of PGM variable.
468 *
469 * This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
470 * incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
471 * a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
472 * as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
473 *
474 * The initial value is choosen to cause an early wraparound. */
475 uint64_t volatile uTlbPhysRev;
476
477 /* Statistics: */
478
479 /** TLB hits (VBOX_WITH_STATISTICS only). */
480 uint64_t cTlbHits;
481 /** TLB misses. */
482 uint32_t cTlbMisses;
483 /** Slow read path. */
484 uint32_t cTlbSlowReadPath;
485#if 0
486 /** TLB misses because of tag mismatch. */
487 uint32_t cTlbMissesTag;
488 /** TLB misses because of virtual access violation. */
489 uint32_t cTlbMissesVirtAccess;
490 /** TLB misses because of dirty bit. */
491 uint32_t cTlbMissesDirty;
492 /** TLB misses because of MMIO */
493 uint32_t cTlbMissesMmio;
494 /** TLB misses because of write access handlers. */
495 uint32_t cTlbMissesWriteHandler;
496 /** TLB misses because no r3(/r0) mapping. */
497 uint32_t cTlbMissesMapping;
498#endif
499 /** Alignment padding. */
500 uint32_t au32Padding[3+5];
501} IEMTLB;
502AssertCompileSizeAlignment(IEMTLB, 64);
503/** IEMTLB::uTlbRevision increment. */
504#define IEMTLB_REVISION_INCR RT_BIT_64(36)
505/** IEMTLB::uTlbRevision mask. */
506#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
507/** IEMTLB::uTlbPhysRev increment.
508 * @sa IEMTLBE_F_PHYS_REV */
509#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
510/**
511 * Calculates the TLB tag for a virtual address.
512 * @returns Tag value for indexing and comparing with IEMTLB::uTag.
513 * @param a_pTlb The TLB.
514 * @param a_GCPtr The virtual address.
515 */
516#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) | (a_pTlb)->uTlbRevision )
517/**
518 * Calculates the TLB tag for a virtual address but without TLB revision.
519 * @returns Tag value for indexing and comparing with IEMTLB::uTag.
520 * @param a_GCPtr The virtual address.
521 */
522#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
523/**
524 * Converts a TLB tag value into a TLB index.
525 * @returns Index into IEMTLB::aEntries.
526 * @param a_uTag Value returned by IEMTLB_CALC_TAG.
527 */
528#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
529/**
530 * Converts a TLB tag value into a TLB index.
531 * @returns Index into IEMTLB::aEntries.
532 * @param a_pTlb The TLB.
533 * @param a_uTag Value returned by IEMTLB_CALC_TAG.
534 */
535#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
536
537
538/** Pointer to a translation block. */
539typedef struct IEMTB *PIEMTB;
540
541/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
542 *
543 * These flags are set when entering IEM and adjusted as code is executed, such
544 * that they will always contain the current values as instructions are
545 * finished.
546 *
547 * In recompiled execution mode, (most of) these flags are included in the
548 * translation block selection key and stored in IEMTB::fFlags alongside the
549 * IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
550 * in IEMCPU::fExec.
551 *
552 * @{ */
553/** Mode: The block target mode mask. */
554#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
555/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
556#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
557/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
558 * conditional in EIP/IP updating), and flat wide open CS, SS DS, and ES in
559 * 32-bit mode (for simplifying most memory accesses). */
560#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
561/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
562#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
563/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
564#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
565
566/** X86 Mode: 16-bit on 386 or later. */
567#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
568/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
569#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
570/** X86 Mode: 16-bit protected mode on 386 or later. */
571#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
572/** X86 Mode: 16-bit protected mode on 386 or later. */
573#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
574/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
575#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
576
577/** X86 Mode: 32-bit on 386 or later. */
578#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
579/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
580#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
581/** X86 Mode: 32-bit protected mode. */
582#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
583/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
584#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
585
586/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
587#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
588
589
590/** Bypass access handlers when set. */
591#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
592/** Have pending hardware instruction breakpoints. */
593#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
594/** Have pending hardware data breakpoints. */
595#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
596
597/** X86: Have pending hardware I/O breakpoints. */
598#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
599/** X86: Disregard the lock prefix (implied or not) when set. */
600#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
601
602/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
603#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR | IEM_F_PENDING_BRK_DATA | IEM_F_PENDING_BRK_X86_IO)
604
605/** Caller configurable options. */
606#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS | IEM_F_X86_DISREGARD_LOCK)
607
608/** X86: The current protection level (CPL) shift factor. */
609#define IEM_F_X86_CPL_SHIFT 8
610/** X86: The current protection level (CPL) mask. */
611#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
612/** X86: The current protection level (CPL) shifted mask. */
613#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
614
615/** X86 execution context.
616 * The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
617 * the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
618 * mode. */
619#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
620/** X86 context: Plain regular execution context. */
621#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
622/** X86 context: VT-x enabled. */
623#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
624/** X86 context: AMD-V enabled. */
625#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
626/** X86 context: In AMD-V or VT-x guest mode. */
627#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
628/** X86 context: System management mode (SMM). */
629#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
630
631/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
632 * iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
633 * and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
634 * alread). */
635
636/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
637 * iemRegFinishClearingRF() most for most situations
638 * (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
639 * the IEM_F_PENDING_BRK_XXX bits alread). */
640
641/** @} */
642
643
644/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
645 *
646 * Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
647 * translation block flags. The combined flag mask (subject to
648 * IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
649 *
650 * @{ */
651/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
652#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
653
654/** Type: The block type mask. */
655#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
656/** Type: Purly threaded recompiler (via tables). */
657#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
658/** Type: Native recompilation. */
659#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
660
661/** State mask. */
662#define IEMTB_F_STATE_MASK UINT32_C(0x0c000000)
663/** State shift count. */
664#define IEMTB_F_STATE_SHIFT 26
665/** State: Compiling. */
666#define IEMTB_F_STATE_COMPILING UINT32_C(0x04000000)
667/** State: Ready. */
668#define IEMTB_F_STATE_READY UINT32_C(0x08000000)
669/** State: Obsolete, can be deleted when we're sure it's not used any longer. */
670#define IEMTB_F_STATE_OBSOLETE UINT32_C(0x0c000000)
671
672/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
673 * we're close the limit before starting a TB, as determined by
674 * iemGetTbFlagsForCurrentPc(). */
675#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x0c000000)
676
677/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
678 * @note We skip the CPL as we don't currently generate ring-specific code,
679 * that's all handled in CIMPL functions.
680 *
681 * For the same reasons, we skip all of IEM_F_X86_CTX_MASK, with the
682 * exception of SMM (which we don't implement). */
683#define IEMTB_F_KEY_MASK ((UINT32_C(0xffffffff) & ~(IEM_F_X86_CTX_MASK | IEM_F_X86_CPL_MASK)) | IEM_F_X86_CTX_SMM)
684/** @} */
685
686AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
687AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
688AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
689AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
690AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
691AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
692AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
693AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
694AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
695AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
696AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
697AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
698AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
699AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
700AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
701AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
702AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
703AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
704AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
705
706AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
707AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
708AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
709AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
710AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
711AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
712AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
713AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
714AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
715AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
716AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
717AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
718
719AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
720AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
721AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
722
723
724/**
725 * The per-CPU IEM state.
726 */
727typedef struct IEMCPU
728{
729 /** Info status code that needs to be propagated to the IEM caller.
730 * This cannot be passed internally, as it would complicate all success
731 * checks within the interpreter making the code larger and almost impossible
732 * to get right. Instead, we'll store status codes to pass on here. Each
733 * source of these codes will perform appropriate sanity checks. */
734 int32_t rcPassUp; /* 0x00 */
735 /** Execution flag, IEM_F_XXX. */
736 uint32_t fExec; /* 0x04 */
737
738 /** @name Decoder state.
739 * @{ */
740#ifndef IEM_WITH_OPAQUE_DECODER_STATE
741# ifdef IEM_WITH_CODE_TLB
742 /** The offset of the next instruction byte. */
743 uint32_t offInstrNextByte; /* 0x08 */
744 /** The number of bytes available at pbInstrBuf for the current instruction.
745 * This takes the max opcode length into account so that doesn't need to be
746 * checked separately. */
747 uint32_t cbInstrBuf; /* 0x0c */
748 /** Pointer to the page containing RIP, user specified buffer or abOpcode.
749 * This can be NULL if the page isn't mappable for some reason, in which
750 * case we'll do fallback stuff.
751 *
752 * If we're executing an instruction from a user specified buffer,
753 * IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
754 * aligned pointer but pointer to the user data.
755 *
756 * For instructions crossing pages, this will start on the first page and be
757 * advanced to the next page by the time we've decoded the instruction. This
758 * therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
759 */
760 uint8_t const *pbInstrBuf; /* 0x10 */
761# if ARCH_BITS == 32
762 uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
763# endif
764 /** The program counter corresponding to pbInstrBuf.
765 * This is set to a non-canonical address when we need to invalidate it. */
766 uint64_t uInstrBufPc; /* 0x18 */
767 /** The guest physical address corresponding to pbInstrBuf. */
768 RTGCPHYS GCPhysInstrBuf; /* 0x20 */
769 /** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
770 * This takes the CS segment limit into account. */
771 uint16_t cbInstrBufTotal; /* 0x28 */
772 /** Offset into pbInstrBuf of the first byte of the current instruction.
773 * Can be negative to efficiently handle cross page instructions. */
774 int16_t offCurInstrStart; /* 0x2a */
775
776 /** The prefix mask (IEM_OP_PRF_XXX). */
777 uint32_t fPrefixes; /* 0x2c */
778 /** The extra REX ModR/M register field bit (REX.R << 3). */
779 uint8_t uRexReg; /* 0x30 */
780 /** The extra REX ModR/M r/m field, SIB base and opcode reg bit
781 * (REX.B << 3). */
782 uint8_t uRexB; /* 0x31 */
783 /** The extra REX SIB index field bit (REX.X << 3). */
784 uint8_t uRexIndex; /* 0x32 */
785
786 /** The effective segment register (X86_SREG_XXX). */
787 uint8_t iEffSeg; /* 0x33 */
788
789 /** The offset of the ModR/M byte relative to the start of the instruction. */
790 uint8_t offModRm; /* 0x34 */
791
792# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
793 /** The current offset into abOpcode. */
794 uint8_t offOpcode; /* 0x35 */
795# else
796 uint8_t bUnused; /* 0x35 */
797# endif
798# else /* !IEM_WITH_CODE_TLB */
799 /** The size of what has currently been fetched into abOpcode. */
800 uint8_t cbOpcode; /* 0x08 */
801 /** The current offset into abOpcode. */
802 uint8_t offOpcode; /* 0x09 */
803 /** The offset of the ModR/M byte relative to the start of the instruction. */
804 uint8_t offModRm; /* 0x0a */
805
806 /** The effective segment register (X86_SREG_XXX). */
807 uint8_t iEffSeg; /* 0x0b */
808
809 /** The prefix mask (IEM_OP_PRF_XXX). */
810 uint32_t fPrefixes; /* 0x0c */
811 /** The extra REX ModR/M register field bit (REX.R << 3). */
812 uint8_t uRexReg; /* 0x10 */
813 /** The extra REX ModR/M r/m field, SIB base and opcode reg bit
814 * (REX.B << 3). */
815 uint8_t uRexB; /* 0x11 */
816 /** The extra REX SIB index field bit (REX.X << 3). */
817 uint8_t uRexIndex; /* 0x12 */
818
819# endif /* !IEM_WITH_CODE_TLB */
820
821 /** The effective operand mode. */
822 IEMMODE enmEffOpSize; /* 0x36, 0x13 */
823 /** The default addressing mode. */
824 IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
825 /** The effective addressing mode. */
826 IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
827 /** The default operand mode. */
828 IEMMODE enmDefOpSize; /* 0x39, 0x16 */
829
830 /** Prefix index (VEX.pp) for two byte and three byte tables. */
831 uint8_t idxPrefix; /* 0x3a, 0x17 */
832 /** 3rd VEX/EVEX/XOP register.
833 * Please use IEM_GET_EFFECTIVE_VVVV to access. */
834 uint8_t uVex3rdReg; /* 0x3b, 0x18 */
835 /** The VEX/EVEX/XOP length field. */
836 uint8_t uVexLength; /* 0x3c, 0x19 */
837 /** Additional EVEX stuff. */
838 uint8_t fEvexStuff; /* 0x3d, 0x1a */
839
840# ifndef IEM_WITH_CODE_TLB
841 /** Explicit alignment padding. */
842 uint8_t abAlignment2a[1]; /* 0x1b */
843# endif
844 /** The FPU opcode (FOP). */
845 uint16_t uFpuOpcode; /* 0x3e, 0x1c */
846# ifndef IEM_WITH_CODE_TLB
847 /** Explicit alignment padding. */
848 uint8_t abAlignment2b[2]; /* 0x1e */
849# endif
850
851 /** The opcode bytes. */
852 uint8_t abOpcode[15]; /* 0x40, 0x20 */
853 /** Explicit alignment padding. */
854# ifdef IEM_WITH_CODE_TLB
855 //uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
856# else
857 uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
858# endif
859#else /* IEM_WITH_OPAQUE_DECODER_STATE */
860 uint8_t abOpaqueDecoder[0x4f - 0x8];
861#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
862 /** @} */
863
864
865 /** The number of active guest memory mappings. */
866 uint8_t cActiveMappings; /* 0x4f, 0x4f */
867
868 /** Records for tracking guest memory mappings. */
869 struct
870 {
871 /** The address of the mapped bytes. */
872 R3R0PTRTYPE(void *) pv;
873 /** The access flags (IEM_ACCESS_XXX).
874 * IEM_ACCESS_INVALID if the entry is unused. */
875 uint32_t fAccess;
876#if HC_ARCH_BITS == 64
877 uint32_t u32Alignment4; /**< Alignment padding. */
878#endif
879 } aMemMappings[3]; /* 0x50 LB 0x30 */
880
881 /** Locking records for the mapped memory. */
882 union
883 {
884 PGMPAGEMAPLOCK Lock;
885 uint64_t au64Padding[2];
886 } aMemMappingLocks[3]; /* 0x80 LB 0x30 */
887
888 /** Bounce buffer info.
889 * This runs in parallel to aMemMappings. */
890 struct
891 {
892 /** The physical address of the first byte. */
893 RTGCPHYS GCPhysFirst;
894 /** The physical address of the second page. */
895 RTGCPHYS GCPhysSecond;
896 /** The number of bytes in the first page. */
897 uint16_t cbFirst;
898 /** The number of bytes in the second page. */
899 uint16_t cbSecond;
900 /** Whether it's unassigned memory. */
901 bool fUnassigned;
902 /** Explicit alignment padding. */
903 bool afAlignment5[3];
904 } aMemBbMappings[3]; /* 0xb0 LB 0x48 */
905
906 /** The flags of the current exception / interrupt. */
907 uint32_t fCurXcpt; /* 0xf8 */
908 /** The current exception / interrupt. */
909 uint8_t uCurXcpt; /* 0xfc */
910 /** Exception / interrupt recursion depth. */
911 int8_t cXcptRecursions; /* 0xfb */
912
913 /** The next unused mapping index.
914 * @todo try find room for this up with cActiveMappings. */
915 uint8_t iNextMapping; /* 0xfd */
916 uint8_t abAlignment7[1];
917
918 /** Bounce buffer storage.
919 * This runs in parallel to aMemMappings and aMemBbMappings. */
920 struct
921 {
922 uint8_t ab[512];
923 } aBounceBuffers[3]; /* 0x100 LB 0x600 */
924
925
926 /** Pointer set jump buffer - ring-3 context. */
927 R3PTRTYPE(jmp_buf *) pJmpBufR3;
928 /** Pointer set jump buffer - ring-0 context. */
929 R0PTRTYPE(jmp_buf *) pJmpBufR0;
930
931 /** @todo Should move this near @a fCurXcpt later. */
932 /** The CR2 for the current exception / interrupt. */
933 uint64_t uCurXcptCr2;
934 /** The error code for the current exception / interrupt. */
935 uint32_t uCurXcptErr;
936
937 /** @name Statistics
938 * @{ */
939 /** The number of instructions we've executed. */
940 uint32_t cInstructions;
941 /** The number of potential exits. */
942 uint32_t cPotentialExits;
943 /** The number of bytes data or stack written (mostly for IEMExecOneEx).
944 * This may contain uncommitted writes. */
945 uint32_t cbWritten;
946 /** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
947 uint32_t cRetInstrNotImplemented;
948 /** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
949 uint32_t cRetAspectNotImplemented;
950 /** Counts informational statuses returned (other than VINF_SUCCESS). */
951 uint32_t cRetInfStatuses;
952 /** Counts other error statuses returned. */
953 uint32_t cRetErrStatuses;
954 /** Number of times rcPassUp has been used. */
955 uint32_t cRetPassUpStatus;
956 /** Number of times RZ left with instruction commit pending for ring-3. */
957 uint32_t cPendingCommit;
958 /** Number of long jumps. */
959 uint32_t cLongJumps;
960 /** @} */
961
962 /** @name Target CPU information.
963 * @{ */
964#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
965 /** The target CPU. */
966 uint8_t uTargetCpu;
967#else
968 uint8_t bTargetCpuPadding;
969#endif
970 /** For selecting assembly works matching the target CPU EFLAGS behaviour, see
971 * IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
972 * native host support and the 2nd for when there is.
973 *
974 * The two values are typically indexed by a g_CpumHostFeatures bit.
975 *
976 * This is for instance used for the BSF & BSR instructions where AMD and
977 * Intel CPUs produce different EFLAGS. */
978 uint8_t aidxTargetCpuEflFlavour[2];
979
980 /** The CPU vendor. */
981 CPUMCPUVENDOR enmCpuVendor;
982 /** @} */
983
984 /** @name Host CPU information.
985 * @{ */
986 /** The CPU vendor. */
987 CPUMCPUVENDOR enmHostCpuVendor;
988 /** @} */
989
990 /** Counts RDMSR \#GP(0) LogRel(). */
991 uint8_t cLogRelRdMsr;
992 /** Counts WRMSR \#GP(0) LogRel(). */
993 uint8_t cLogRelWrMsr;
994 /** Alignment padding. */
995 uint8_t abAlignment9[46];
996
997 /** @name Recompilation
998 * @{ */
999 /** Pointer to the current translation block.
1000 * This can either be one being executed or one being compiled. */
1001 R3PTRTYPE(PIEMTB) pCurTbR3;
1002 /** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1003 * The TBs are based on physical addresses, so this is needed to correleated
1004 * RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1005 uint64_t uCurTbStartPc;
1006 /** Statistics: Number of TB allocation calls. */
1007 uint64_t cTbAllocs;
1008 /** Statistics: Number of TB free calls. */
1009 uint64_t cTbFrees;
1010 /** Statistics: Number of TB lookup misses. */
1011 uint64_t cTbLookupMisses;
1012 /** Statistics: Number of TB lookup hits (debug only). */
1013 uint64_t cTbLookupHits;
1014 /** Number of TBs executed. */
1015 uint64_t cTbExec;
1016 /** Whether to end the current TB. */
1017 bool fEndTb;
1018 /** Spaced reserved for recompiler data / alignment. */
1019 bool afRecompilerStuff1[7];
1020 /** @} */
1021
1022 /** Data TLB.
1023 * @remarks Must be 64-byte aligned. */
1024 IEMTLB DataTlb;
1025 /** Instruction TLB.
1026 * @remarks Must be 64-byte aligned. */
1027 IEMTLB CodeTlb;
1028
1029 /** Exception statistics. */
1030 STAMCOUNTER aStatXcpts[32];
1031 /** Interrupt statistics. */
1032 uint32_t aStatInts[256];
1033
1034#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1035 /** Instruction statistics for ring-0/raw-mode. */
1036 IEMINSTRSTATS StatsRZ;
1037 /** Instruction statistics for ring-3. */
1038 IEMINSTRSTATS StatsR3;
1039#endif
1040} IEMCPU;
1041AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1042AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1043AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1044AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1045AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1046AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1047
1048/** Pointer to the per-CPU IEM state. */
1049typedef IEMCPU *PIEMCPU;
1050/** Pointer to the const per-CPU IEM state. */
1051typedef IEMCPU const *PCIEMCPU;
1052
1053
1054/** @def IEM_GET_CTX
1055 * Gets the guest CPU context for the calling EMT.
1056 * @returns PCPUMCTX
1057 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1058 */
1059#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1060
1061/** @def IEM_CTX_ASSERT
1062 * Asserts that the @a a_fExtrnMbz is present in the CPU context.
1063 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1064 * @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1065 */
1066#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1067 ("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
1068 (a_fExtrnMbz)))
1069
1070/** @def IEM_CTX_IMPORT_RET
1071 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1072 *
1073 * Will call the keep to import the bits as needed.
1074 *
1075 * Returns on import failure.
1076 *
1077 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1078 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1079 */
1080#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1081 do { \
1082 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1083 { /* likely */ } \
1084 else \
1085 { \
1086 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1087 AssertRCReturn(rcCtxImport, rcCtxImport); \
1088 } \
1089 } while (0)
1090
1091/** @def IEM_CTX_IMPORT_NORET
1092 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1093 *
1094 * Will call the keep to import the bits as needed.
1095 *
1096 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1097 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1098 */
1099#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1100 do { \
1101 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1102 { /* likely */ } \
1103 else \
1104 { \
1105 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1106 AssertLogRelRC(rcCtxImport); \
1107 } \
1108 } while (0)
1109
1110/** @def IEM_CTX_IMPORT_JMP
1111 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1112 *
1113 * Will call the keep to import the bits as needed.
1114 *
1115 * Jumps on import failure.
1116 *
1117 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1118 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1119 */
1120#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1121 do { \
1122 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1123 { /* likely */ } \
1124 else \
1125 { \
1126 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1127 AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1128 } \
1129 } while (0)
1130
1131
1132
1133/** @def IEM_GET_TARGET_CPU
1134 * Gets the current IEMTARGETCPU value.
1135 * @returns IEMTARGETCPU value.
1136 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1137 */
1138#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1139# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1140#else
1141# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1142#endif
1143
1144/** @def IEM_GET_INSTR_LEN
1145 * Gets the instruction length. */
1146#ifdef IEM_WITH_CODE_TLB
1147# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1148#else
1149# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1150#endif
1151
1152/** @def IEM_TRY_SETJMP
1153 * Wrapper around setjmp / try, hiding all the ugly differences.
1154 *
1155 * @note Use with extreme care as this is a fragile macro.
1156 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1157 * @param a_rcTarget The variable that should receive the status code in case
1158 * of a longjmp/throw.
1159 */
1160/** @def IEM_TRY_SETJMP_AGAIN
1161 * For when setjmp / try is used again in the same variable scope as a previous
1162 * IEM_TRY_SETJMP invocation.
1163 */
1164/** @def IEM_CATCH_LONGJMP_BEGIN
1165 * Start wrapper for catch / setjmp-else.
1166 *
1167 * This will set up a scope.
1168 *
1169 * @note Use with extreme care as this is a fragile macro.
1170 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1171 * @param a_rcTarget The variable that should receive the status code in case
1172 * of a longjmp/throw.
1173 */
1174/** @def IEM_CATCH_LONGJMP_END
1175 * End wrapper for catch / setjmp-else.
1176 *
1177 * This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1178 * state.
1179 *
1180 * @note Use with extreme care as this is a fragile macro.
1181 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1182 */
1183#if defined(IEM_WITH_SETJMP) || defined(DOXYGEN_RUNNING)
1184# ifdef IEM_WITH_THROW_CATCH
1185# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1186 a_rcTarget = VINF_SUCCESS; \
1187 try
1188# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1189 IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1190# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1191 catch (int rcThrown) \
1192 { \
1193 a_rcTarget = rcThrown
1194# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1195 } \
1196 ((void)0)
1197# else /* !IEM_WITH_THROW_CATCH */
1198# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1199 jmp_buf JmpBuf; \
1200 jmp_buf * volatile pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1201 pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1202 if ((rcStrict = setjmp(JmpBuf)) == 0)
1203# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1204 pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1205 pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1206 if ((rcStrict = setjmp(JmpBuf)) == 0)
1207# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1208 else \
1209 { \
1210 ((void)0)
1211# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1212 } \
1213 (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1214# endif /* !IEM_WITH_THROW_CATCH */
1215#endif /* IEM_WITH_SETJMP */
1216
1217
1218/**
1219 * Shared per-VM IEM data.
1220 */
1221typedef struct IEM
1222{
1223 /** The VMX APIC-access page handler type. */
1224 PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1225#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1226 /** Set if the CPUID host call functionality is enabled. */
1227 bool fCpuIdHostCall;
1228#endif
1229} IEM;
1230
1231
1232
1233/** @name IEM_ACCESS_XXX - Access details.
1234 * @{ */
1235#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1236#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1237#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1238#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1239#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1240#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1241#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1242#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1243#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1244#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1245/** The writes are partial, so if initialize the bounce buffer with the
1246 * orignal RAM content. */
1247#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1248/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1249#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1250/** Bounce buffer with ring-3 write pending, first page. */
1251#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1252/** Bounce buffer with ring-3 write pending, second page. */
1253#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1254/** Not locked, accessed via the TLB. */
1255#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1256/** Valid bit mask. */
1257#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1258/** Shift count for the TLB flags (upper word). */
1259#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1260
1261/** Read+write data alias. */
1262#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
1263/** Write data alias. */
1264#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
1265/** Read data alias. */
1266#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA)
1267/** Instruction fetch alias. */
1268#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC | IEM_ACCESS_WHAT_CODE)
1269/** Stack write alias. */
1270#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
1271/** Stack read alias. */
1272#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_STACK)
1273/** Stack read+write alias. */
1274#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
1275/** Read system table alias. */
1276#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_SYS)
1277/** Read+write system table alias. */
1278#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_SYS)
1279/** @} */
1280
1281/** @name Prefix constants (IEMCPU::fPrefixes)
1282 * @{ */
1283#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /**< CS segment prefix (0x2e). */
1284#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /**< SS segment prefix (0x36). */
1285#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /**< DS segment prefix (0x3e). */
1286#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /**< ES segment prefix (0x26). */
1287#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /**< FS segment prefix (0x64). */
1288#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /**< GS segment prefix (0x65). */
1289#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1290
1291#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /**< Operand size prefix (0x66). */
1292#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /**< REX.W prefix (0x48-0x4f). */
1293#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /**< Address size prefix (0x67). */
1294
1295#define IEM_OP_PRF_LOCK RT_BIT_32(16) /**< Lock prefix (0xf0). */
1296#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /**< Repeat-not-zero prefix (0xf2). */
1297#define IEM_OP_PRF_REPZ RT_BIT_32(18) /**< Repeat-if-zero prefix (0xf3). */
1298
1299#define IEM_OP_PRF_REX RT_BIT_32(24) /**< Any REX prefix (0x40-0x4f). */
1300#define IEM_OP_PRF_REX_R RT_BIT_32(25) /**< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). */
1301#define IEM_OP_PRF_REX_B RT_BIT_32(26) /**< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). */
1302#define IEM_OP_PRF_REX_X RT_BIT_32(27) /**< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). */
1303/** Mask with all the REX prefix flags.
1304 * This is generally for use when needing to undo the REX prefixes when they
1305 * are followed legacy prefixes and therefore does not immediately preceed
1306 * the first opcode byte.
1307 * For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1308#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X | IEM_OP_PRF_SIZE_REX_W )
1309
1310#define IEM_OP_PRF_VEX RT_BIT_32(28) /**< Indiciates VEX prefix. */
1311#define IEM_OP_PRF_EVEX RT_BIT_32(29) /**< Indiciates EVEX prefix. */
1312#define IEM_OP_PRF_XOP RT_BIT_32(30) /**< Indiciates XOP prefix. */
1313/** @} */
1314
1315/** @name IEMOPFORM_XXX - Opcode forms
1316 * @note These are ORed together with IEMOPHINT_XXX.
1317 * @{ */
1318/** ModR/M: reg, r/m */
1319#define IEMOPFORM_RM 0
1320/** ModR/M: reg, r/m (register) */
1321#define IEMOPFORM_RM_REG (IEMOPFORM_RM | IEMOPFORM_MOD3)
1322/** ModR/M: reg, r/m (memory) */
1323#define IEMOPFORM_RM_MEM (IEMOPFORM_RM | IEMOPFORM_NOT_MOD3)
1324/** ModR/M: reg, r/m */
1325#define IEMOPFORM_RMI 1
1326/** ModR/M: reg, r/m (register) */
1327#define IEMOPFORM_RMI_REG (IEMOPFORM_RM | IEMOPFORM_MOD3)
1328/** ModR/M: reg, r/m (memory) */
1329#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM | IEMOPFORM_NOT_MOD3)
1330/** ModR/M: r/m, reg */
1331#define IEMOPFORM_MR 2
1332/** ModR/M: r/m (register), reg */
1333#define IEMOPFORM_MR_REG (IEMOPFORM_MR | IEMOPFORM_MOD3)
1334/** ModR/M: r/m (memory), reg */
1335#define IEMOPFORM_MR_MEM (IEMOPFORM_MR | IEMOPFORM_NOT_MOD3)
1336/** ModR/M: r/m, reg */
1337#define IEMOPFORM_MRI 3
1338/** ModR/M: r/m (register), reg */
1339#define IEMOPFORM_MRI_REG (IEMOPFORM_MR | IEMOPFORM_MOD3)
1340/** ModR/M: r/m (memory), reg */
1341#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR | IEMOPFORM_NOT_MOD3)
1342/** ModR/M: r/m only */
1343#define IEMOPFORM_M 4
1344/** ModR/M: r/m only (register). */
1345#define IEMOPFORM_M_REG (IEMOPFORM_M | IEMOPFORM_MOD3)
1346/** ModR/M: r/m only (memory). */
1347#define IEMOPFORM_M_MEM (IEMOPFORM_M | IEMOPFORM_NOT_MOD3)
1348/** ModR/M: reg only */
1349#define IEMOPFORM_R 5
1350
1351/** VEX+ModR/M: reg, r/m */
1352#define IEMOPFORM_VEX_RM 8
1353/** VEX+ModR/M: reg, r/m (register) */
1354#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM | IEMOPFORM_MOD3)
1355/** VEX+ModR/M: reg, r/m (memory) */
1356#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM | IEMOPFORM_NOT_MOD3)
1357/** VEX+ModR/M: r/m, reg */
1358#define IEMOPFORM_VEX_MR 9
1359/** VEX+ModR/M: r/m (register), reg */
1360#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR | IEMOPFORM_MOD3)
1361/** VEX+ModR/M: r/m (memory), reg */
1362#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR | IEMOPFORM_NOT_MOD3)
1363/** VEX+ModR/M: r/m only */
1364#define IEMOPFORM_VEX_M 10
1365/** VEX+ModR/M: r/m only (register). */
1366#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M | IEMOPFORM_MOD3)
1367/** VEX+ModR/M: r/m only (memory). */
1368#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M | IEMOPFORM_NOT_MOD3)
1369/** VEX+ModR/M: reg only */
1370#define IEMOPFORM_VEX_R 11
1371/** VEX+ModR/M: reg, vvvv, r/m */
1372#define IEMOPFORM_VEX_RVM 12
1373/** VEX+ModR/M: reg, vvvv, r/m (register). */
1374#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM | IEMOPFORM_MOD3)
1375/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1376#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM | IEMOPFORM_NOT_MOD3)
1377/** VEX+ModR/M: reg, r/m, vvvv */
1378#define IEMOPFORM_VEX_RMV 13
1379/** VEX+ModR/M: reg, r/m, vvvv (register). */
1380#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV | IEMOPFORM_MOD3)
1381/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1382#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV | IEMOPFORM_NOT_MOD3)
1383/** VEX+ModR/M: reg, r/m, imm8 */
1384#define IEMOPFORM_VEX_RMI 14
1385/** VEX+ModR/M: reg, r/m, imm8 (register). */
1386#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI | IEMOPFORM_MOD3)
1387/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1388#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI | IEMOPFORM_NOT_MOD3)
1389/** VEX+ModR/M: r/m, vvvv, reg */
1390#define IEMOPFORM_VEX_MVR 15
1391/** VEX+ModR/M: r/m, vvvv, reg (register) */
1392#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR | IEMOPFORM_MOD3)
1393/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1394#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR | IEMOPFORM_NOT_MOD3)
1395/** VEX+ModR/M+/n: vvvv, r/m */
1396#define IEMOPFORM_VEX_VM 16
1397/** VEX+ModR/M+/n: vvvv, r/m (register) */
1398#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM | IEMOPFORM_MOD3)
1399/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1400#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM | IEMOPFORM_NOT_MOD3)
1401
1402/** Fixed register instruction, no R/M. */
1403#define IEMOPFORM_FIXED 32
1404
1405/** The r/m is a register. */
1406#define IEMOPFORM_MOD3 RT_BIT_32(8)
1407/** The r/m is a memory access. */
1408#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1409/** @} */
1410
1411/** @name IEMOPHINT_XXX - Additional Opcode Hints
1412 * @note These are ORed together with IEMOPFORM_XXX.
1413 * @{ */
1414/** Ignores the operand size prefix (66h). */
1415#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1416/** Ignores REX.W (aka WIG). */
1417#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1418/** Both the operand size prefixes (66h + REX.W) are ignored. */
1419#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_IGNORES_REXW)
1420/** Allowed with the lock prefix. */
1421#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1422/** The VEX.L value is ignored (aka LIG). */
1423#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1424/** The VEX.L value must be zero (i.e. 128-bit width only). */
1425#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1426/** The VEX.V value must be zero. */
1427#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1428
1429/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1430#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1431/** @} */
1432
1433/**
1434 * Possible hardware task switch sources.
1435 */
1436typedef enum IEMTASKSWITCH
1437{
1438 /** Task switch caused by an interrupt/exception. */
1439 IEMTASKSWITCH_INT_XCPT = 1,
1440 /** Task switch caused by a far CALL. */
1441 IEMTASKSWITCH_CALL,
1442 /** Task switch caused by a far JMP. */
1443 IEMTASKSWITCH_JUMP,
1444 /** Task switch caused by an IRET. */
1445 IEMTASKSWITCH_IRET
1446} IEMTASKSWITCH;
1447AssertCompileSize(IEMTASKSWITCH, 4);
1448
1449/**
1450 * Possible CrX load (write) sources.
1451 */
1452typedef enum IEMACCESSCRX
1453{
1454 /** CrX access caused by 'mov crX' instruction. */
1455 IEMACCESSCRX_MOV_CRX,
1456 /** CrX (CR0) write caused by 'lmsw' instruction. */
1457 IEMACCESSCRX_LMSW,
1458 /** CrX (CR0) write caused by 'clts' instruction. */
1459 IEMACCESSCRX_CLTS,
1460 /** CrX (CR0) read caused by 'smsw' instruction. */
1461 IEMACCESSCRX_SMSW
1462} IEMACCESSCRX;
1463
1464#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1465/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1466 *
1467 * These flags provide further context to SLAT page-walk failures that could not be
1468 * determined by PGM (e.g, PGM is not privy to memory access permissions).
1469 *
1470 * @{
1471 */
1472/** Translating a nested-guest linear address failed accessing a nested-guest
1473 * physical address. */
1474# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1475/** Translating a nested-guest linear address failed accessing a
1476 * paging-structure entry or updating accessed/dirty bits. */
1477# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1478/** @} */
1479
1480DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1481# ifndef IN_RING3
1482DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1483# endif
1484#endif
1485
1486/**
1487 * Indicates to the verifier that the given flag set is undefined.
1488 *
1489 * Can be invoked again to add more flags.
1490 *
1491 * This is a NOOP if the verifier isn't compiled in.
1492 *
1493 * @note We're temporarily keeping this until code is converted to new
1494 * disassembler style opcode handling.
1495 */
1496#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1497
1498
1499/** @def IEM_DECL_IMPL_TYPE
1500 * For typedef'ing an instruction implementation function.
1501 *
1502 * @param a_RetType The return type.
1503 * @param a_Name The name of the type.
1504 * @param a_ArgList The argument list enclosed in parentheses.
1505 */
1506
1507/** @def IEM_DECL_IMPL_DEF
1508 * For defining an instruction implementation function.
1509 *
1510 * @param a_RetType The return type.
1511 * @param a_Name The name of the type.
1512 * @param a_ArgList The argument list enclosed in parentheses.
1513 */
1514
1515#if defined(__GNUC__) && defined(RT_ARCH_X86)
1516# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1517 __attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1518# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1519 __attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1520# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1521 __attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1522
1523#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1524# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1525 a_RetType (__fastcall a_Name) a_ArgList
1526# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1527 a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1528# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1529 a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1530
1531#elif __cplusplus >= 201700 /* P0012R1 support */
1532# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1533 a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1534# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1535 a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1536# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1537 a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1538
1539#else
1540# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1541 a_RetType (VBOXCALL a_Name) a_ArgList
1542# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1543 a_RetType VBOXCALL a_Name a_ArgList
1544# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1545 a_RetType VBOXCALL a_Name a_ArgList
1546
1547#endif
1548
1549/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1550RT_C_DECLS_BEGIN
1551extern uint8_t const g_afParity[256];
1552RT_C_DECLS_END
1553
1554
1555/** @name Arithmetic assignment operations on bytes (binary).
1556 * @{ */
1557typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t *pu8Dst, uint8_t u8Src, uint32_t *pEFlags));
1558typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1559FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1560FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1561FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1562FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1563FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1564FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1565FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1566/** @} */
1567
1568/** @name Arithmetic assignment operations on words (binary).
1569 * @{ */
1570typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t *pu16Dst, uint16_t u16Src, uint32_t *pEFlags));
1571typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1572FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1573FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1574FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1575FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1576FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1577FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1578FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1579/** @} */
1580
1581/** @name Arithmetic assignment operations on double words (binary).
1582 * @{ */
1583typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t *pu32Dst, uint32_t u32Src, uint32_t *pEFlags));
1584typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1585FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1586FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1587FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1588FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1589FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1590FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1591FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1592FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1593FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1594FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1595/** @} */
1596
1597/** @name Arithmetic assignment operations on quad words (binary).
1598 * @{ */
1599typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t *pu64Dst, uint64_t u64Src, uint32_t *pEFlags));
1600typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1601FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1602FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1603FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1604FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1605FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1606FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1607FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1608FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1609FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1610FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1611/** @} */
1612
1613/** @name Compare operations (thrown in with the binary ops).
1614 * @{ */
1615FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1616FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1617FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1618FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1619/** @} */
1620
1621/** @name Test operations (thrown in with the binary ops).
1622 * @{ */
1623FNIEMAIMPLBINU8 iemAImpl_test_u8;
1624FNIEMAIMPLBINU16 iemAImpl_test_u16;
1625FNIEMAIMPLBINU32 iemAImpl_test_u32;
1626FNIEMAIMPLBINU64 iemAImpl_test_u64;
1627/** @} */
1628
1629/** @name Bit operations operations (thrown in with the binary ops).
1630 * @{ */
1631FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1632FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1633FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1634FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1635FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1636FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1637FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1638FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1639FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1640FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1641FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1642FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1643/** @} */
1644
1645/** @name Arithmetic three operand operations on double words (binary).
1646 * @{ */
1647typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t *pEFlags));
1648typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1649FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1650FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1651FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1652/** @} */
1653
1654/** @name Arithmetic three operand operations on quad words (binary).
1655 * @{ */
1656typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t *pEFlags));
1657typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1658FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1659FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1660FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1661/** @} */
1662
1663/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1664 * @{ */
1665typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1666typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1667FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1668FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1669FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1670FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1671FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1672FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1673/** @} */
1674
1675/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1676 * @{ */
1677typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1678typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1679FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1680FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1681FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1682FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1683FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1684FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1685/** @} */
1686
1687/** @name MULX 32-bit and 64-bit.
1688 * @{ */
1689typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t *puDst1, uint32_t *puDst2, uint32_t uSrc1, uint32_t uSrc2));
1690typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1691FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1692
1693typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t *puDst1, uint64_t *puDst2, uint64_t uSrc1, uint64_t uSrc2));
1694typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1695FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1696/** @} */
1697
1698
1699/** @name Exchange memory with register operations.
1700 * @{ */
1701IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t *pu8Mem, uint8_t *pu8Reg));
1702IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t *pu16Mem, uint16_t *pu16Reg));
1703IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t *pu32Mem, uint32_t *pu32Reg));
1704IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t *pu64Mem, uint64_t *pu64Reg));
1705IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t *pu8Mem, uint8_t *pu8Reg));
1706IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t *pu16Mem, uint16_t *pu16Reg));
1707IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t *pu32Mem, uint32_t *pu32Reg));
1708IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t *pu64Mem, uint64_t *pu64Reg));
1709/** @} */
1710
1711/** @name Exchange and add operations.
1712 * @{ */
1713IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t *pu8Dst, uint8_t *pu8Reg, uint32_t *pEFlags));
1714IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t *pu16Dst, uint16_t *pu16Reg, uint32_t *pEFlags));
1715IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t *pu32Dst, uint32_t *pu32Reg, uint32_t *pEFlags));
1716IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t *pu64Dst, uint64_t *pu64Reg, uint32_t *pEFlags));
1717IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t *pu8Dst, uint8_t *pu8Reg, uint32_t *pEFlags));
1718IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t *pu16Dst, uint16_t *pu16Reg, uint32_t *pEFlags));
1719IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t *pu32Dst, uint32_t *pu32Reg, uint32_t *pEFlags));
1720IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t *pu64Dst, uint64_t *pu64Reg, uint32_t *pEFlags));
1721/** @} */
1722
1723/** @name Compare and exchange.
1724 * @{ */
1725IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1726IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1727IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1728IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1729IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1730IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1731#if ARCH_BITS == 32
1732IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags));
1733IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags));
1734#else
1735IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1736IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1737#endif
1738IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1739 uint32_t *pEFlags));
1740IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1741 uint32_t *pEFlags));
1742IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1743 uint32_t *pEFlags));
1744IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1745 uint32_t *pEFlags));
1746#ifndef RT_ARCH_ARM64
1747IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1748 PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1749#endif
1750/** @} */
1751
1752/** @name Memory ordering
1753 * @{ */
1754typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1755typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1756IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1757IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1758IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1759#ifndef RT_ARCH_ARM64
1760IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1761#endif
1762/** @} */
1763
1764/** @name Double precision shifts
1765 * @{ */
1766typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t *pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t *pEFlags));
1767typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1768typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t *pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t *pEFlags));
1769typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1770typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t *pEFlags));
1771typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1772FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1773FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1774FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1775FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1776FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1777FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1778/** @} */
1779
1780
1781/** @name Bit search operations (thrown in with the binary ops).
1782 * @{ */
1783FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1784FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1785FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1786FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1787FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1788FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1789FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1790FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1791FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1792FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1793FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1794FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1795FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1796FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1797FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1798/** @} */
1799
1800/** @name Signed multiplication operations (thrown in with the binary ops).
1801 * @{ */
1802FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1803FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1804FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1805/** @} */
1806
1807/** @name Arithmetic assignment operations on bytes (unary).
1808 * @{ */
1809typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t *pu8Dst, uint32_t *pEFlags));
1810typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1811FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1812FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1813FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1814FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1815/** @} */
1816
1817/** @name Arithmetic assignment operations on words (unary).
1818 * @{ */
1819typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t *pu16Dst, uint32_t *pEFlags));
1820typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1821FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1822FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1823FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1824FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1825/** @} */
1826
1827/** @name Arithmetic assignment operations on double words (unary).
1828 * @{ */
1829typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t *pu32Dst, uint32_t *pEFlags));
1830typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1831FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1832FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1833FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1834FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1835/** @} */
1836
1837/** @name Arithmetic assignment operations on quad words (unary).
1838 * @{ */
1839typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t *pu64Dst, uint32_t *pEFlags));
1840typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1841FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1842FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1843FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1844FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1845/** @} */
1846
1847
1848/** @name Shift operations on bytes (Group 2).
1849 * @{ */
1850typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t *pu8Dst, uint8_t cShift, uint32_t *pEFlags));
1851typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1852FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1853FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1854FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1855FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1856FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1857FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1858FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1859/** @} */
1860
1861/** @name Shift operations on words (Group 2).
1862 * @{ */
1863typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t *pu16Dst, uint8_t cShift, uint32_t *pEFlags));
1864typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1865FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1866FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1867FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1868FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1869FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1870FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1871FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1872/** @} */
1873
1874/** @name Shift operations on double words (Group 2).
1875 * @{ */
1876typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t *pu32Dst, uint8_t cShift, uint32_t *pEFlags));
1877typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1878FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1879FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1880FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1881FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1882FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1883FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1884FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1885/** @} */
1886
1887/** @name Shift operations on words (Group 2).
1888 * @{ */
1889typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t *pu64Dst, uint8_t cShift, uint32_t *pEFlags));
1890typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1891FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1892FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1893FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1894FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1895FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1896FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1897FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1898/** @} */
1899
1900/** @name Multiplication and division operations.
1901 * @{ */
1902typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t *pu16AX, uint8_t u8FactorDivisor, uint32_t *pEFlags));
1903typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1904FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1905FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1906FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1907FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1908
1909typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t *pu16AX, uint16_t *pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1910typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1911FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1912FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1913FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1914FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1915
1916typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t *pu32EAX, uint32_t *pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1917typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1918FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1919FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1920FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1921FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1922
1923typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1924typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1925FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1926FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1927FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1928FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1929/** @} */
1930
1931/** @name Byte Swap.
1932 * @{ */
1933IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t *pu32Dst)); /* Yes, 32-bit register access. */
1934IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1935IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1936/** @} */
1937
1938/** @name Misc.
1939 * @{ */
1940FNIEMAIMPLBINU16 iemAImpl_arpl;
1941/** @} */
1942
1943/** @name RDRAND and RDSEED
1944 * @{ */
1945typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t *puDst, uint32_t *pEFlags));
1946typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t *puDst, uint32_t *pEFlags));
1947typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t *puDst, uint32_t *pEFlags));
1948typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
1949typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
1950typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
1951
1952FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
1953FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
1954FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
1955FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
1956FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
1957FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
1958/** @} */
1959
1960/** @name ADOX and ADCX
1961 * @{ */
1962typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t *puDst, uint32_t *pfEFlags, uint32_t uSrc));
1963typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t *puDst, uint32_t *pfEFlags, uint64_t uSrc));
1964typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
1965typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
1966
1967FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
1968FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
1969FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
1970FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
1971/** @} */
1972
1973/** @name FPU operations taking a 32-bit float argument
1974 * @{ */
1975typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1976 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1977typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1978
1979typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1980 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1981typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1982
1983FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1984FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1985FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1986FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1987FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1988FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1989FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1990
1991IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1992IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1993 PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1994/** @} */
1995
1996/** @name FPU operations taking a 64-bit float argument
1997 * @{ */
1998typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1999 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2000typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2001
2002typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2003 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2004typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2005
2006FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2007FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2008FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2009FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2010FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2011FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2012FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2013
2014IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2015IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2016 PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2017/** @} */
2018
2019/** @name FPU operations taking a 80-bit float argument
2020 * @{ */
2021typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2022 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2023typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2024FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2025FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2026FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2027FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2028FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2029FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2030FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2031FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2032FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2033
2034FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2035FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2036FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2037
2038typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2039 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2040typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2041FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2042FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2043
2044typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2045 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2046typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2047FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2048FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2049
2050typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2051typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2052FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2053FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2054FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2055FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2056FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2057FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2058FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2059
2060typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2061typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2062FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2063FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2064
2065typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2066typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2067FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2068FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2069FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2070FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2071FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2072FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2073FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2074
2075typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2076 PCRTFLOAT80U pr80Val));
2077typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2078FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2079FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2080FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2081
2082IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2083IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2084 PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2085
2086IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2087IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2088 PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2089
2090/** @} */
2091
2092/** @name FPU operations taking a 16-bit signed integer argument
2093 * @{ */
2094typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2095 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2096typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2097typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2098 int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2099typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2100
2101FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2102FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2103FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2104FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2105FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2106FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2107
2108typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2109 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2110typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2111FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2112
2113IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2114FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2115FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2116/** @} */
2117
2118/** @name FPU operations taking a 32-bit signed integer argument
2119 * @{ */
2120typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2121 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2122typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2123typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2124 int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2125typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2126
2127FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2128FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2129FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2130FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2131FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2132FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2133
2134typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2135 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2136typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2137FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2138
2139IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2140FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2141FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2142/** @} */
2143
2144/** @name FPU operations taking a 64-bit signed integer argument
2145 * @{ */
2146typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2147 int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2148typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2149
2150IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2151FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2152FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2153/** @} */
2154
2155
2156/** Temporary type representing a 256-bit vector register. */
2157typedef struct { uint64_t au64[4]; } IEMVMM256;
2158/** Temporary type pointing to a 256-bit vector register. */
2159typedef IEMVMM256 *PIEMVMM256;
2160/** Temporary type pointing to a const 256-bit vector register. */
2161typedef IEMVMM256 *PCIEMVMM256;
2162
2163
2164/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2165 * @{ */
2166typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t *puDst, uint64_t const *puSrc));
2167typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2168typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2169typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2170typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2171typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2172typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2173typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2174typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t *puDst, uint64_t const *puSrc));
2175typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2176typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2177typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2178typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2179typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2180typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2181typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2182typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2183typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2184FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2185FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2186FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2187FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2188FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2189FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2190FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2191FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2192FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2193FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2194FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2195FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2196FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2197FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2198FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2199FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2200FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2201FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2202FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2203FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2204FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2205FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2206FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2207FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2208FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2209FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2210FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2211FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2212FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2213FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2214FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2215FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2216FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2217FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2218FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2219FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2220FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2221FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2222FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2223
2224FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2225FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2226FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2227FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2228FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2229FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2230FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2231FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2232FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2233FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2234FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2235FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2236FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2237FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2238FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2239FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2240FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2241FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2242FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2243FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2244FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2245FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2246FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2247FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2248FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2249FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2250FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2251FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2252FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2253FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2254FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2255FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2256FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2257FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2258FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2259FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2260FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2261FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2262FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2263FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2264FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2265FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2266FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2267FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2268FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2269FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2270FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2271FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2272FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2273FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2274FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2275FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2276FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2277FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2278FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2279FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2280FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2281
2282FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2283FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2284FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2285FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2286FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2287FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2288FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2289FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2290FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2291FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2292FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2293FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2294FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2295FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2296FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2297FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2298FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2299FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2300FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2301FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2302FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2303FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2304FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2305FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2306FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2307FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2308FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2309FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2310FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2311FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2312FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2313FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2314FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2315FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2316FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2317FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2318FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2319FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2320FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2321FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2322FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2323FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2324FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2325FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2326FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2327FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2328FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2329FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2330FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2331FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2332FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2333FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2334FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2335FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2336FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2337FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2338FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2339
2340FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2341FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2342FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2343FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2344
2345FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2346FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2347FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2348FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2349FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2350FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2351FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2352FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2353FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2354FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2355FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2356FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2357FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2358FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2359FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2360FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2361FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2362FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2363FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2364FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2365FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2366FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2367FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2368FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2369FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2370FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2371FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2372FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2373FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2374FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2375FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2376FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2377FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2378FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2379FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2380FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2381FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2382FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2383FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2384FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2385FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2386FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2387FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2388FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2389FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2390FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2391FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2392FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2393FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2394FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2395FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2396FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2397FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2398FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2399FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2400FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2401FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2402
2403FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2404FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2405FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2406/** @} */
2407
2408/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2409 * @{ */
2410FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2411FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2412FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2413 iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2414 iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2415 iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2416 iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2417 iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2418 iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2419 iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2420
2421FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2422 iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2423 iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2424 iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2425 iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2426 iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2427 iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2428 iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2429/** @} */
2430
2431/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2432 * @{ */
2433FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2434FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2435FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2436 iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2437 iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2438 iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2439FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2440 iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2441 iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2442 iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2443/** @} */
2444
2445/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2446 * @{ */
2447typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2448typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2449typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2450typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2451IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t *puDst, uint64_t const *puSrc, uint8_t bEvil));
2452FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2453#ifndef IEM_WITHOUT_ASSEMBLY
2454FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2455#endif
2456FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2457/** @} */
2458
2459/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2460 * @{ */
2461typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2462typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2463typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2464typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2465typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2466typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2467FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2468FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2469FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2470FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2471FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2472FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2473FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2474/** @} */
2475
2476/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2477 * @{ */
2478IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t *pu64Dst, uint64_t const *puSrc));
2479IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2480#ifndef IEM_WITHOUT_ASSEMBLY
2481IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2482#endif
2483IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2484/** @} */
2485
2486/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2487 * @{ */
2488typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2489typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2490typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2491typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2492typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2493typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2494
2495FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2496FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2497FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2498FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2499FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2500FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2501
2502FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2503FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2504FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2505FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2506FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2507FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2508
2509FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2510FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2511FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2512FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2513FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2514FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2515/** @} */
2516
2517
2518/** @name Media (SSE/MMX/AVX) operation: Sort this later
2519 * @{ */
2520IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2521IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2522IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2523IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2524IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2525IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2526
2527IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2528IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2529IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2530IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2531IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2532
2533IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2534IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2535IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2536IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2537IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2538
2539IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2540IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2541IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2542IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2543IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2544
2545IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2546IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2547IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2548IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2549IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2550
2551IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2552IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2553IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2554IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2555IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2556
2557IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2558IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2559IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2560IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2561IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2562
2563IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2564IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2565IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2566IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2567IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2568
2569IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2570IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2571IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2572IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2573IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2574
2575IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2576IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2577IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2578IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2579IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2580
2581IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2582IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2583IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2584IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2585IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2586
2587IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2588IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2589IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2590IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2591IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2592
2593IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2594IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2595IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2596IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2597IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2598
2599IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2600IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2601IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2602IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2603IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2604
2605IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2606IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2607IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2608IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2609IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2610
2611IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2612IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2613
2614IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2615IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2616IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2617IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2618
2619IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2620IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2621IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2622IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2623
2624IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2625IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2626IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2627IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2628IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2629
2630IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2631IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2632IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2633IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2634IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2635
2636
2637typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2638typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2639typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2640typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2641typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2642typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2643
2644FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2645FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2646FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2647FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2648
2649FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2650FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2651FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2652FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2653
2654FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2655FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2656FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2657FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2658
2659FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2660FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2661FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2662FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2663FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2664
2665FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2666FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2667FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2668FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2669FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2670
2671FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2672
2673FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2674
2675FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
2676FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
2677FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
2678FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
2679FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
2680FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
2681IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2682IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2683
2684typedef struct IEMPCMPISTRXSRC
2685{
2686 RTUINT128U uSrc1;
2687 RTUINT128U uSrc2;
2688} IEMPCMPISTRXSRC;
2689typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
2690typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
2691
2692typedef struct IEMPCMPESTRXSRC
2693{
2694 RTUINT128U uSrc1;
2695 RTUINT128U uSrc2;
2696 uint64_t u64Rax;
2697 uint64_t u64Rdx;
2698} IEMPCMPESTRXSRC;
2699typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
2700typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
2701
2702typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pu32Ecx, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2703typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
2704typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t *pu32Ecx, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2705typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
2706
2707typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2708typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
2709typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2710typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
2711
2712FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
2713FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
2714FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
2715FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
2716
2717FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2718FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2719
2720FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
2721/** @} */
2722
2723/** @name Media Odds and Ends
2724 * @{ */
2725typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2726typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2727typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2728typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2729FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2730FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2731FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2732FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2733
2734typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2735typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2736FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2737FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2738
2739typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */
2740typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2741typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */
2742typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2743typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */
2744typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2745typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */
2746typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2747
2748FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2749FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2750
2751FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2752FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2753
2754FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2755FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2756
2757FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2758FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2759
2760typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
2761typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2762typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
2763typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2764
2765FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2766FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2767
2768typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
2769typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2770typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
2771typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2772
2773FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2774FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2775
2776
2777typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2778typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2779
2780FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2781FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2782
2783FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2784FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2785
2786FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2787FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2788
2789FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2790FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2791
2792
2793typedef struct IEMMEDIAF2XMMSRC
2794{
2795 X86XMMREG uSrc1;
2796 X86XMMREG uSrc2;
2797} IEMMEDIAF2XMMSRC;
2798typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2799typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2800
2801typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2802typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2803
2804FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2805FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2806FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2807FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2808FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
2809FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
2810
2811FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
2812FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
2813
2814FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
2815FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
2816
2817typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t *pfMxcsr, uint64_t *pu64Dst, PCX86XMMREG pSrc));
2818typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
2819
2820FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
2821FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
2822
2823typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
2824typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
2825
2826FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
2827FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
2828
2829typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t *pfMxcsr, uint64_t *pu64Dst, uint64_t u64Src));
2830typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
2831
2832FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
2833FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
2834
2835/** @} */
2836
2837
2838/** @name Function tables.
2839 * @{
2840 */
2841
2842/**
2843 * Function table for a binary operator providing implementation based on
2844 * operand size.
2845 */
2846typedef struct IEMOPBINSIZES
2847{
2848 PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2849 PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2850 PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2851 PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2852} IEMOPBINSIZES;
2853/** Pointer to a binary operator function table. */
2854typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2855
2856
2857/**
2858 * Function table for a unary operator providing implementation based on
2859 * operand size.
2860 */
2861typedef struct IEMOPUNARYSIZES
2862{
2863 PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2864 PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2865 PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2866 PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2867} IEMOPUNARYSIZES;
2868/** Pointer to a unary operator function table. */
2869typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2870
2871
2872/**
2873 * Function table for a shift operator providing implementation based on
2874 * operand size.
2875 */
2876typedef struct IEMOPSHIFTSIZES
2877{
2878 PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2879 PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2880 PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2881 PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2882} IEMOPSHIFTSIZES;
2883/** Pointer to a shift operator function table. */
2884typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2885
2886
2887/**
2888 * Function table for a multiplication or division operation.
2889 */
2890typedef struct IEMOPMULDIVSIZES
2891{
2892 PFNIEMAIMPLMULDIVU8 pfnU8;
2893 PFNIEMAIMPLMULDIVU16 pfnU16;
2894 PFNIEMAIMPLMULDIVU32 pfnU32;
2895 PFNIEMAIMPLMULDIVU64 pfnU64;
2896} IEMOPMULDIVSIZES;
2897/** Pointer to a multiplication or division operation function table. */
2898typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2899
2900
2901/**
2902 * Function table for a double precision shift operator providing implementation
2903 * based on operand size.
2904 */
2905typedef struct IEMOPSHIFTDBLSIZES
2906{
2907 PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2908 PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2909 PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2910} IEMOPSHIFTDBLSIZES;
2911/** Pointer to a double precision shift function table. */
2912typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2913
2914
2915/**
2916 * Function table for media instruction taking two full sized media source
2917 * registers and one full sized destination register (AVX).
2918 */
2919typedef struct IEMOPMEDIAF3
2920{
2921 PFNIEMAIMPLMEDIAF3U128 pfnU128;
2922 PFNIEMAIMPLMEDIAF3U256 pfnU256;
2923} IEMOPMEDIAF3;
2924/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2925typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2926
2927/** @def IEMOPMEDIAF3_INIT_VARS_EX
2928 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2929 * given functions as initializers. For use in AVX functions where a pair of
2930 * functions are only used once and the function table need not be public. */
2931#ifndef TST_IEM_CHECK_MC
2932# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2933# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2934 static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2935 static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2936# else
2937# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2938 static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2939# endif
2940#else
2941# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2942#endif
2943/** @def IEMOPMEDIAF3_INIT_VARS
2944 * Generate AVX function tables for the @a a_InstrNm instruction.
2945 * @sa IEMOPMEDIAF3_INIT_VARS_EX */
2946#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2947 IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2948 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2949
2950/**
2951 * Function table for media instruction taking two full sized media source
2952 * registers and one full sized destination register, but no additional state
2953 * (AVX).
2954 */
2955typedef struct IEMOPMEDIAOPTF3
2956{
2957 PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2958 PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2959} IEMOPMEDIAOPTF3;
2960/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2961typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2962
2963/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2964 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2965 * given functions as initializers. For use in AVX functions where a pair of
2966 * functions are only used once and the function table need not be public. */
2967#ifndef TST_IEM_CHECK_MC
2968# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2969# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2970 static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2971 static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2972# else
2973# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2974 static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2975# endif
2976#else
2977# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2978#endif
2979/** @def IEMOPMEDIAOPTF3_INIT_VARS
2980 * Generate AVX function tables for the @a a_InstrNm instruction.
2981 * @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2982#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2983 IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2984 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2985
2986/**
2987 * Function table for media instruction taking one full sized media source
2988 * registers and one full sized destination register, but no additional state
2989 * (AVX).
2990 */
2991typedef struct IEMOPMEDIAOPTF2
2992{
2993 PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2994 PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2995} IEMOPMEDIAOPTF2;
2996/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2997typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2998
2999/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
3000 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3001 * given functions as initializers. For use in AVX functions where a pair of
3002 * functions are only used once and the function table need not be public. */
3003#ifndef TST_IEM_CHECK_MC
3004# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3005# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3006 static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3007 static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3008# else
3009# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3010 static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3011# endif
3012#else
3013# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3014#endif
3015/** @def IEMOPMEDIAOPTF2_INIT_VARS
3016 * Generate AVX function tables for the @a a_InstrNm instruction.
3017 * @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3018#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3019 IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3020 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3021
3022/**
3023 * Function table for media instruction taking two full sized media source
3024 * registers and one full sized destination register and an 8-bit immediate, but no additional state
3025 * (AVX).
3026 */
3027typedef struct IEMOPMEDIAOPTF3IMM8
3028{
3029 PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3030 PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3031} IEMOPMEDIAOPTF3IMM8;
3032/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3033typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3034
3035/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3036 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3037 * given functions as initializers. For use in AVX functions where a pair of
3038 * functions are only used once and the function table need not be public. */
3039#ifndef TST_IEM_CHECK_MC
3040# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3041# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3042 static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3043 static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3044# else
3045# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3046 static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3047# endif
3048#else
3049# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3050#endif
3051/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3052 * Generate AVX function tables for the @a a_InstrNm instruction.
3053 * @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3054#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3055 IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3056 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3057/** @} */
3058
3059
3060/**
3061 * Function table for blend type instruction taking three full sized media source
3062 * registers and one full sized destination register, but no additional state
3063 * (AVX).
3064 */
3065typedef struct IEMOPBLENDOP
3066{
3067 PFNIEMAIMPLAVXBLENDU128 pfnU128;
3068 PFNIEMAIMPLAVXBLENDU256 pfnU256;
3069} IEMOPBLENDOP;
3070/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3071typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3072
3073/** @def IEMOPBLENDOP_INIT_VARS_EX
3074 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3075 * given functions as initializers. For use in AVX functions where a pair of
3076 * functions are only used once and the function table need not be public. */
3077#ifndef TST_IEM_CHECK_MC
3078# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3079# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3080 static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3081 static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3082# else
3083# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3084 static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3085# endif
3086#else
3087# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3088#endif
3089/** @def IEMOPBLENDOP_INIT_VARS
3090 * Generate AVX function tables for the @a a_InstrNm instruction.
3091 * @sa IEMOPBLENDOP_INIT_VARS_EX */
3092#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3093 IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3094 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3095
3096
3097/** @name SSE/AVX single/double precision floating point operations.
3098 * @{ */
3099/**
3100 * A SSE result.
3101 */
3102typedef struct IEMSSERESULT
3103{
3104 /** The output value. */
3105 X86XMMREG uResult;
3106 /** The output status. */
3107 uint32_t MXCSR;
3108} IEMSSERESULT;
3109AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3110/** Pointer to a SSE result. */
3111typedef IEMSSERESULT *PIEMSSERESULT;
3112/** Pointer to a const SSE result. */
3113typedef IEMSSERESULT const *PCIEMSSERESULT;
3114
3115
3116/**
3117 * A AVX128 result.
3118 */
3119typedef struct IEMAVX128RESULT
3120{
3121 /** The output value. */
3122 X86XMMREG uResult;
3123 /** The output status. */
3124 uint32_t MXCSR;
3125} IEMAVX128RESULT;
3126AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3127/** Pointer to a AVX128 result. */
3128typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3129/** Pointer to a const AVX128 result. */
3130typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3131
3132
3133/**
3134 * A AVX256 result.
3135 */
3136typedef struct IEMAVX256RESULT
3137{
3138 /** The output value. */
3139 X86YMMREG uResult;
3140 /** The output status. */
3141 uint32_t MXCSR;
3142} IEMAVX256RESULT;
3143AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3144/** Pointer to a AVX256 result. */
3145typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3146/** Pointer to a const AVX256 result. */
3147typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3148
3149
3150typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3151typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3152typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3153typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3154typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3155typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3156
3157typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3158typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3159typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3160typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3161typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3162typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3163
3164typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3165typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3166
3167FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3168FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3169FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3170FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3171FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3172FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3173FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3174FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3175FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3176FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3177FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3178FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3179FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3180FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3181FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3182FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3183FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3184FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3185FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3186FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3187FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3188FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3189FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3190
3191FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3192FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3193FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3194FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3195FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3196FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3197
3198FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3199FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3200FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3201FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3202FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3203FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3204FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3205FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3206FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3207FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3208FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3209FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3210FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3211FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3212FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3213FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3214FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3215
3216FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3217FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3218FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3219FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3220FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3221FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3222FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3223FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3224FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3225FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3226FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3227FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3228FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3229FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3230FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3231FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3232FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3233FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3234FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3235FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3236FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3237FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3238
3239FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3240FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3241FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3242FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3243FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3244FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3245FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3246FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3247FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3248FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3249FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3250FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3251FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3252FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3253
3254FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3255FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3256FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3257FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3258FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3259FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3260FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3261FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3262FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3263FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3264FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3265FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3266FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3267FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3268FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3269FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3270FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3271FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3272FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3273FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3274/** @} */
3275
3276/** @name C instruction implementations for anything slightly complicated.
3277 * @{ */
3278
3279/**
3280 * For typedef'ing or declaring a C instruction implementation function taking
3281 * no extra arguments.
3282 *
3283 * @param a_Name The name of the type.
3284 */
3285# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3286 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3287/**
3288 * For defining a C instruction implementation function taking no extra
3289 * arguments.
3290 *
3291 * @param a_Name The name of the function
3292 */
3293# define IEM_CIMPL_DEF_0(a_Name) \
3294 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3295/**
3296 * Prototype version of IEM_CIMPL_DEF_0.
3297 */
3298# define IEM_CIMPL_PROTO_0(a_Name) \
3299 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3300/**
3301 * For calling a C instruction implementation function taking no extra
3302 * arguments.
3303 *
3304 * This special call macro adds default arguments to the call and allow us to
3305 * change these later.
3306 *
3307 * @param a_fn The name of the function.
3308 */
3309# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3310
3311/**
3312 * For typedef'ing or declaring a C instruction implementation function taking
3313 * one extra argument.
3314 *
3315 * @param a_Name The name of the type.
3316 * @param a_Type0 The argument type.
3317 * @param a_Arg0 The argument name.
3318 */
3319# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3320 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3321/**
3322 * For defining a C instruction implementation function taking one extra
3323 * argument.
3324 *
3325 * @param a_Name The name of the function
3326 * @param a_Type0 The argument type.
3327 * @param a_Arg0 The argument name.
3328 */
3329# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3330 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3331/**
3332 * Prototype version of IEM_CIMPL_DEF_1.
3333 */
3334# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3335 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3336/**
3337 * For calling a C instruction implementation function taking one extra
3338 * argument.
3339 *
3340 * This special call macro adds default arguments to the call and allow us to
3341 * change these later.
3342 *
3343 * @param a_fn The name of the function.
3344 * @param a0 The name of the 1st argument.
3345 */
3346# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3347
3348/**
3349 * For typedef'ing or declaring a C instruction implementation function taking
3350 * two extra arguments.
3351 *
3352 * @param a_Name The name of the type.
3353 * @param a_Type0 The type of the 1st argument
3354 * @param a_Arg0 The name of the 1st argument.
3355 * @param a_Type1 The type of the 2nd argument.
3356 * @param a_Arg1 The name of the 2nd argument.
3357 */
3358# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3359 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3360/**
3361 * For defining a C instruction implementation function taking two extra
3362 * arguments.
3363 *
3364 * @param a_Name The name of the function.
3365 * @param a_Type0 The type of the 1st argument
3366 * @param a_Arg0 The name of the 1st argument.
3367 * @param a_Type1 The type of the 2nd argument.
3368 * @param a_Arg1 The name of the 2nd argument.
3369 */
3370# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3371 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3372/**
3373 * Prototype version of IEM_CIMPL_DEF_2.
3374 */
3375# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3376 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3377/**
3378 * For calling a C instruction implementation function taking two extra
3379 * arguments.
3380 *
3381 * This special call macro adds default arguments to the call and allow us to
3382 * change these later.
3383 *
3384 * @param a_fn The name of the function.
3385 * @param a0 The name of the 1st argument.
3386 * @param a1 The name of the 2nd argument.
3387 */
3388# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3389
3390/**
3391 * For typedef'ing or declaring a C instruction implementation function taking
3392 * three extra arguments.
3393 *
3394 * @param a_Name The name of the type.
3395 * @param a_Type0 The type of the 1st argument
3396 * @param a_Arg0 The name of the 1st argument.
3397 * @param a_Type1 The type of the 2nd argument.
3398 * @param a_Arg1 The name of the 2nd argument.
3399 * @param a_Type2 The type of the 3rd argument.
3400 * @param a_Arg2 The name of the 3rd argument.
3401 */
3402# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3403 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3404/**
3405 * For defining a C instruction implementation function taking three extra
3406 * arguments.
3407 *
3408 * @param a_Name The name of the function.
3409 * @param a_Type0 The type of the 1st argument
3410 * @param a_Arg0 The name of the 1st argument.
3411 * @param a_Type1 The type of the 2nd argument.
3412 * @param a_Arg1 The name of the 2nd argument.
3413 * @param a_Type2 The type of the 3rd argument.
3414 * @param a_Arg2 The name of the 3rd argument.
3415 */
3416# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3417 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3418/**
3419 * Prototype version of IEM_CIMPL_DEF_3.
3420 */
3421# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3422 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3423/**
3424 * For calling a C instruction implementation function taking three extra
3425 * arguments.
3426 *
3427 * This special call macro adds default arguments to the call and allow us to
3428 * change these later.
3429 *
3430 * @param a_fn The name of the function.
3431 * @param a0 The name of the 1st argument.
3432 * @param a1 The name of the 2nd argument.
3433 * @param a2 The name of the 3rd argument.
3434 */
3435# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3436
3437
3438/**
3439 * For typedef'ing or declaring a C instruction implementation function taking
3440 * four extra arguments.
3441 *
3442 * @param a_Name The name of the type.
3443 * @param a_Type0 The type of the 1st argument
3444 * @param a_Arg0 The name of the 1st argument.
3445 * @param a_Type1 The type of the 2nd argument.
3446 * @param a_Arg1 The name of the 2nd argument.
3447 * @param a_Type2 The type of the 3rd argument.
3448 * @param a_Arg2 The name of the 3rd argument.
3449 * @param a_Type3 The type of the 4th argument.
3450 * @param a_Arg3 The name of the 4th argument.
3451 */
3452# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3453 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3454/**
3455 * For defining a C instruction implementation function taking four extra
3456 * arguments.
3457 *
3458 * @param a_Name The name of the function.
3459 * @param a_Type0 The type of the 1st argument
3460 * @param a_Arg0 The name of the 1st argument.
3461 * @param a_Type1 The type of the 2nd argument.
3462 * @param a_Arg1 The name of the 2nd argument.
3463 * @param a_Type2 The type of the 3rd argument.
3464 * @param a_Arg2 The name of the 3rd argument.
3465 * @param a_Type3 The type of the 4th argument.
3466 * @param a_Arg3 The name of the 4th argument.
3467 */
3468# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3469 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3470 a_Type2 a_Arg2, a_Type3 a_Arg3))
3471/**
3472 * Prototype version of IEM_CIMPL_DEF_4.
3473 */
3474# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3475 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3476 a_Type2 a_Arg2, a_Type3 a_Arg3))
3477/**
3478 * For calling a C instruction implementation function taking four extra
3479 * arguments.
3480 *
3481 * This special call macro adds default arguments to the call and allow us to
3482 * change these later.
3483 *
3484 * @param a_fn The name of the function.
3485 * @param a0 The name of the 1st argument.
3486 * @param a1 The name of the 2nd argument.
3487 * @param a2 The name of the 3rd argument.
3488 * @param a3 The name of the 4th argument.
3489 */
3490# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3491
3492
3493/**
3494 * For typedef'ing or declaring a C instruction implementation function taking
3495 * five extra arguments.
3496 *
3497 * @param a_Name The name of the type.
3498 * @param a_Type0 The type of the 1st argument
3499 * @param a_Arg0 The name of the 1st argument.
3500 * @param a_Type1 The type of the 2nd argument.
3501 * @param a_Arg1 The name of the 2nd argument.
3502 * @param a_Type2 The type of the 3rd argument.
3503 * @param a_Arg2 The name of the 3rd argument.
3504 * @param a_Type3 The type of the 4th argument.
3505 * @param a_Arg3 The name of the 4th argument.
3506 * @param a_Type4 The type of the 5th argument.
3507 * @param a_Arg4 The name of the 5th argument.
3508 */
3509# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3510 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3511 a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3512 a_Type3 a_Arg3, a_Type4 a_Arg4))
3513/**
3514 * For defining a C instruction implementation function taking five extra
3515 * arguments.
3516 *
3517 * @param a_Name The name of the function.
3518 * @param a_Type0 The type of the 1st argument
3519 * @param a_Arg0 The name of the 1st argument.
3520 * @param a_Type1 The type of the 2nd argument.
3521 * @param a_Arg1 The name of the 2nd argument.
3522 * @param a_Type2 The type of the 3rd argument.
3523 * @param a_Arg2 The name of the 3rd argument.
3524 * @param a_Type3 The type of the 4th argument.
3525 * @param a_Arg3 The name of the 4th argument.
3526 * @param a_Type4 The type of the 5th argument.
3527 * @param a_Arg4 The name of the 5th argument.
3528 */
3529# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3530 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3531 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3532/**
3533 * Prototype version of IEM_CIMPL_DEF_5.
3534 */
3535# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3536 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3537 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3538/**
3539 * For calling a C instruction implementation function taking five extra
3540 * arguments.
3541 *
3542 * This special call macro adds default arguments to the call and allow us to
3543 * change these later.
3544 *
3545 * @param a_fn The name of the function.
3546 * @param a0 The name of the 1st argument.
3547 * @param a1 The name of the 2nd argument.
3548 * @param a2 The name of the 3rd argument.
3549 * @param a3 The name of the 4th argument.
3550 * @param a4 The name of the 5th argument.
3551 */
3552# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3553
3554/** @} */
3555
3556
3557/** @name Opcode Decoder Function Types.
3558 * @{ */
3559
3560/** @typedef PFNIEMOP
3561 * Pointer to an opcode decoder function.
3562 */
3563
3564/** @def FNIEMOP_DEF
3565 * Define an opcode decoder function.
3566 *
3567 * We're using macors for this so that adding and removing parameters as well as
3568 * tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3569 *
3570 * @param a_Name The function name.
3571 */
3572
3573/** @typedef PFNIEMOPRM
3574 * Pointer to an opcode decoder function with RM byte.
3575 */
3576
3577/** @def FNIEMOPRM_DEF
3578 * Define an opcode decoder function with RM byte.
3579 *
3580 * We're using macors for this so that adding and removing parameters as well as
3581 * tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3582 *
3583 * @param a_Name The function name.
3584 */
3585
3586#if defined(__GNUC__) && defined(RT_ARCH_X86)
3587typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3588typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3589# define FNIEMOP_DEF(a_Name) \
3590 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3591# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3592 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3593# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3594 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3595
3596#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3597typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3598typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3599# define FNIEMOP_DEF(a_Name) \
3600 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3601# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3602 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3603# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3604 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3605
3606#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
3607typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3608typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3609# define FNIEMOP_DEF(a_Name) \
3610 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3611# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3612 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3613# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3614 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3615
3616#else
3617typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3618typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3619# define FNIEMOP_DEF(a_Name) \
3620 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3621# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3622 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3623# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3624 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3625
3626#endif
3627#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3628
3629/**
3630 * Call an opcode decoder function.
3631 *
3632 * We're using macors for this so that adding and removing parameters can be
3633 * done as we please. See FNIEMOP_DEF.
3634 */
3635#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3636
3637/**
3638 * Call a common opcode decoder function taking one extra argument.
3639 *
3640 * We're using macors for this so that adding and removing parameters can be
3641 * done as we please. See FNIEMOP_DEF_1.
3642 */
3643#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3644
3645/**
3646 * Call a common opcode decoder function taking one extra argument.
3647 *
3648 * We're using macors for this so that adding and removing parameters can be
3649 * done as we please. See FNIEMOP_DEF_1.
3650 */
3651#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3652/** @} */
3653
3654
3655/** @name Misc Helpers
3656 * @{ */
3657
3658/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3659 * due to GCC lacking knowledge about the value range of a switch. */
3660#if RT_CPLUSPLUS_PREREQ(202000)
3661# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3662#else
3663# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3664#endif
3665
3666/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3667#if RT_CPLUSPLUS_PREREQ(202000)
3668# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3669#else
3670# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3671#endif
3672
3673/**
3674 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3675 * occation.
3676 */
3677#ifdef LOG_ENABLED
3678# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3679 do { \
3680 /*Log*/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3681 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3682 } while (0)
3683#else
3684# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3685 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3686#endif
3687
3688/**
3689 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3690 * occation using the supplied logger statement.
3691 *
3692 * @param a_LoggerArgs What to log on failure.
3693 */
3694#ifdef LOG_ENABLED
3695# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3696 do { \
3697 LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3698 /*LogFunc(a_LoggerArgs);*/ \
3699 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3700 } while (0)
3701#else
3702# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3703 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3704#endif
3705
3706/**
3707 * Gets the CPU mode (from fExec) as a IEMMODE value.
3708 *
3709 * @returns IEMMODE
3710 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3711 */
3712#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
3713
3714/**
3715 * Check if we're currently executing in real or virtual 8086 mode.
3716 *
3717 * @returns @c true if it is, @c false if not.
3718 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3719 */
3720#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
3721 & (IEM_F_MODE_X86_V86_MASK | IEM_F_MODE_X86_PROT_MASK)) != 0)
3722
3723/**
3724 * Check if we're currently executing in virtual 8086 mode.
3725 *
3726 * @returns @c true if it is, @c false if not.
3727 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3728 */
3729#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
3730
3731/**
3732 * Check if we're currently executing in long mode.
3733 *
3734 * @returns @c true if it is, @c false if not.
3735 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3736 */
3737#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3738
3739/**
3740 * Check if we're currently executing in a 16-bit code segment.
3741 *
3742 * @returns @c true if it is, @c false if not.
3743 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3744 */
3745#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
3746
3747/**
3748 * Check if we're currently executing in a 32-bit code segment.
3749 *
3750 * @returns @c true if it is, @c false if not.
3751 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3752 */
3753#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
3754
3755/**
3756 * Check if we're currently executing in a 64-bit code segment.
3757 *
3758 * @returns @c true if it is, @c false if not.
3759 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3760 */
3761#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
3762
3763/**
3764 * Check if we're currently executing in real mode.
3765 *
3766 * @returns @c true if it is, @c false if not.
3767 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3768 */
3769#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
3770
3771/**
3772 * Gets the current protection level (CPL).
3773 *
3774 * @returns 0..3
3775 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3776 */
3777#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
3778
3779/**
3780 * Sets the current protection level (CPL).
3781 *
3782 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3783 */
3784#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
3785 do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) | ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
3786
3787/**
3788 * Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3789 * @returns PCCPUMFEATURES
3790 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3791 */
3792#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3793
3794/**
3795 * Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3796 * @returns PCCPUMFEATURES
3797 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3798 */
3799#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3800
3801/**
3802 * Evaluates to true if we're presenting an Intel CPU to the guest.
3803 */
3804#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3805
3806/**
3807 * Evaluates to true if we're presenting an AMD CPU to the guest.
3808 */
3809#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD || (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3810
3811/**
3812 * Check if the address is canonical.
3813 */
3814#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3815
3816/** Checks if the ModR/M byte is in register mode or not. */
3817#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3818/** Checks if the ModR/M byte is in memory mode or not. */
3819#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3820
3821/**
3822 * Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3823 *
3824 * For use during decoding.
3825 */
3826#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | (a_pVCpu)->iem.s.uRexReg )
3827/**
3828 * Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3829 *
3830 * For use during decoding.
3831 */
3832#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) | (a_pVCpu)->iem.s.uRexB )
3833
3834/**
3835 * Gets the register (reg) part of a ModR/M encoding, without REX.R.
3836 *
3837 * For use during decoding.
3838 */
3839#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3840/**
3841 * Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3842 *
3843 * For use during decoding.
3844 */
3845#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3846
3847/**
3848 * Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
3849 * register index, with REX.R added in.
3850 *
3851 * For use during decoding.
3852 *
3853 * @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
3854 */
3855#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
3856 ( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
3857 || !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
3858 ? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) | 16)
3859/**
3860 * Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
3861 * with REX.B added in.
3862 *
3863 * For use during decoding.
3864 *
3865 * @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
3866 */
3867#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
3868 ( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
3869 || !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
3870 ? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) | 16)
3871
3872/**
3873 * Combines the prefix REX and ModR/M byte for passing to
3874 * iemOpHlpCalcRmEffAddrThreadedAddr64().
3875 *
3876 * @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
3877 * The two bits are part of the REG sub-field, which isn't needed in
3878 * iemOpHlpCalcRmEffAddrThreadedAddr64().
3879 *
3880 * For use during decoding/recompiling.
3881 */
3882#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
3883 ( ((a_bRm) & ~X86_MODRM_REG_MASK) \
3884 | (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
3885AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
3886AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
3887
3888/**
3889 * Gets the effective VEX.VVVV value.
3890 *
3891 * The 4th bit is ignored if not 64-bit code.
3892 * @returns effective V-register value.
3893 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3894 */
3895#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3896 (IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3897
3898
3899/**
3900 * Checks if we're executing inside an AMD-V or VT-x guest.
3901 */
3902#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) || defined(VBOX_WITH_NESTED_HWVIRT_SVM)
3903# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
3904#else
3905# define IEM_IS_IN_GUEST(a_pVCpu) false
3906#endif
3907
3908
3909#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3910
3911/**
3912 * Check if the guest has entered VMX root operation.
3913 */
3914# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3915
3916/**
3917 * Check if the guest has entered VMX non-root operation.
3918 */
3919# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX | IEM_F_X86_CTX_IN_GUEST)) \
3920 == (IEM_F_X86_CTX_VMX | IEM_F_X86_CTX_IN_GUEST) )
3921
3922/**
3923 * Check if the nested-guest has the given Pin-based VM-execution control set.
3924 */
3925# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3926
3927/**
3928 * Check if the nested-guest has the given Processor-based VM-execution control set.
3929 */
3930# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3931
3932/**
3933 * Check if the nested-guest has the given Secondary Processor-based VM-execution
3934 * control set.
3935 */
3936# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3937
3938/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3939# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3940
3941/** Whether a shadow VMCS is present for the given VCPU. */
3942# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3943
3944/** Gets the VMXON region pointer. */
3945# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3946
3947/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3948# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3949
3950/** Whether a current VMCS is present for the given VCPU. */
3951# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3952
3953/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3954# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3955 do \
3956 { \
3957 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3958 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3959 } while (0)
3960
3961/** Clears any current VMCS for the given VCPU. */
3962# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3963 do \
3964 { \
3965 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3966 } while (0)
3967
3968/**
3969 * Invokes the VMX VM-exit handler for an instruction intercept.
3970 */
3971# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3972 do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3973
3974/**
3975 * Invokes the VMX VM-exit handler for an instruction intercept where the
3976 * instruction provides additional VM-exit information.
3977 */
3978# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3979 do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3980
3981/**
3982 * Invokes the VMX VM-exit handler for a task switch.
3983 */
3984# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3985 do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3986
3987/**
3988 * Invokes the VMX VM-exit handler for MWAIT.
3989 */
3990# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3991 do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3992
3993/**
3994 * Invokes the VMX VM-exit handler for EPT faults.
3995 */
3996# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3997 do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3998
3999/**
4000 * Invokes the VMX VM-exit handler.
4001 */
4002# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
4003 do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
4004
4005#else
4006# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
4007# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
4008# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4009# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4010# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4011# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4012# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4013# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4014# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4015# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4016# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4017
4018#endif
4019
4020#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4021/**
4022 * Checks if we're executing a guest using AMD-V.
4023 */
4024# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM | IEM_F_X86_CTX_IN_GUEST)) \
4025 == (IEM_F_X86_CTX_SVM | IEM_F_X86_CTX_IN_GUEST))
4026/**
4027 * Check if an SVM control/instruction intercept is set.
4028 */
4029# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4030 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4031
4032/**
4033 * Check if an SVM read CRx intercept is set.
4034 */
4035# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4036 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4037
4038/**
4039 * Check if an SVM write CRx intercept is set.
4040 */
4041# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4042 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4043
4044/**
4045 * Check if an SVM read DRx intercept is set.
4046 */
4047# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4048 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4049
4050/**
4051 * Check if an SVM write DRx intercept is set.
4052 */
4053# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4054 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4055
4056/**
4057 * Check if an SVM exception intercept is set.
4058 */
4059# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4060 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4061
4062/**
4063 * Invokes the SVM \#VMEXIT handler for the nested-guest.
4064 */
4065# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4066 do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4067
4068/**
4069 * Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4070 * corresponding decode assist information.
4071 */
4072# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4073 do \
4074 { \
4075 uint64_t uExitInfo1; \
4076 if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4077 && (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4078 uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK | ((a_iGReg) & 7); \
4079 else \
4080 uExitInfo1 = 0; \
4081 IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4082 } while (0)
4083
4084/** Check and handles SVM nested-guest instruction intercept and updates
4085 * NRIP if needed.
4086 */
4087# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4088 do \
4089 { \
4090 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4091 { \
4092 IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4093 IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4094 } \
4095 } while (0)
4096
4097/** Checks and handles SVM nested-guest CR0 read intercept. */
4098# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4099 do \
4100 { \
4101 if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4102 { /* probably likely */ } \
4103 else \
4104 { \
4105 IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4106 IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4107 } \
4108 } while (0)
4109
4110/**
4111 * Updates the NextRIP (NRI) field in the nested-guest VMCB.
4112 */
4113# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4114 do { \
4115 if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4116 CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4117 } while (0)
4118
4119#else
4120# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4121# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4122# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4123# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4124# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4125# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4126# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4127# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4128# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4129 a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4130# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4131# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4132
4133#endif
4134
4135/** @} */
4136
4137uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4138VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4139
4140
4141/**
4142 * Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4143 */
4144typedef union IEMSELDESC
4145{
4146 /** The legacy view. */
4147 X86DESC Legacy;
4148 /** The long mode view. */
4149 X86DESC64 Long;
4150} IEMSELDESC;
4151/** Pointer to a selector descriptor table entry. */
4152typedef IEMSELDESC *PIEMSELDESC;
4153
4154/** @name Raising Exceptions.
4155 * @{ */
4156VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4157 uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4158
4159VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4160 uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4161#ifdef IEM_WITH_SETJMP
4162DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4163 uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4164#endif
4165VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4166VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4167VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4168VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4169VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4170VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4171VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4172VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4173VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4174/*VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;*/
4175VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4176VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4177VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4178VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4179VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4180VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4181#ifdef IEM_WITH_SETJMP
4182DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4183#endif
4184VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4185VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4186VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4187#ifdef IEM_WITH_SETJMP
4188DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4189#endif
4190VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4191#ifdef IEM_WITH_SETJMP
4192DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4193#endif
4194VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4195#ifdef IEM_WITH_SETJMP
4196DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4197#endif
4198VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4199#ifdef IEM_WITH_SETJMP
4200DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4201#endif
4202VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4203VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4204#ifdef IEM_WITH_SETJMP
4205DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4206#endif
4207VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4208
4209IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4210IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4211IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4212
4213/**
4214 * Macro for calling iemCImplRaiseDivideError().
4215 *
4216 * This enables us to add/remove arguments and force different levels of
4217 * inlining as we wish.
4218 *
4219 * @return Strict VBox status code.
4220 */
4221#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseDivideError)
4222
4223/**
4224 * Macro for calling iemCImplRaiseInvalidLockPrefix().
4225 *
4226 * This enables us to add/remove arguments and force different levels of
4227 * inlining as we wish.
4228 *
4229 * @return Strict VBox status code.
4230 */
4231#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidLockPrefix)
4232
4233/**
4234 * Macro for calling iemCImplRaiseInvalidOpcode().
4235 *
4236 * This enables us to add/remove arguments and force different levels of
4237 * inlining as we wish.
4238 *
4239 * @return Strict VBox status code.
4240 */
4241#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4242/** @} */
4243
4244/** @name Register Access.
4245 * @{ */
4246VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4247 IEMMODE enmEffOpSize) RT_NOEXCEPT;
4248VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4249VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4250 IEMMODE enmEffOpSize) RT_NOEXCEPT;
4251VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4252VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4253VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4254/** @} */
4255
4256/** @name FPU access and helpers.
4257 * @{ */
4258void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4259void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4260void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4261void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4262void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4263void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4264 uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4265void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4266 uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4267void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4268void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4269void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4270void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4271void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4272void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4273void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4274void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4275void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4276void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4277void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4278void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4279void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4280void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4281void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4282/** @} */
4283
4284/** @name SSE+AVX SIMD access and helpers.
4285 * @{ */
4286void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
4287void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
4288/** @} */
4289
4290/** @name Memory access.
4291 * @{ */
4292
4293/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
4294#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
4295/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
4296 * when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
4297#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
4298/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
4299 * Users include FXSAVE & FXRSTOR. */
4300#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
4301
4302VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
4303 uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
4304VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4305#ifndef IN_RING3
4306VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4307#endif
4308void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
4309VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
4310VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4311VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
4312
4313void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
4314void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
4315#ifdef IEM_WITH_CODE_TLB
4316void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
4317#else
4318VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
4319#endif
4320#ifdef IEM_WITH_SETJMP
4321uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4322uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4323uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4324uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4325#else
4326VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
4327VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4328VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4329VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4330VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4331VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4332VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4333VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4334VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4335VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4336VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4337#endif
4338
4339VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4340VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4341VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4342VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4343VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4344VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4345VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4346VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4347VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4348VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4349VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4350VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4351VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
4352 RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
4353#ifdef IEM_WITH_SETJMP
4354uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4355uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4356uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4357uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4358uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4359void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4360void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4361void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4362void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4363void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4364void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4365#endif
4366
4367VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4368VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4369VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4370VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4371VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
4372
4373VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
4374VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
4375VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
4376VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
4377VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4378VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4379VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4380VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4381VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4382#ifdef IEM_WITH_SETJMP
4383void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4384void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4385void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4386void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4387void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4388void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4389void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4390void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4391#endif
4392
4393VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4394 void **ppvMem, uint64_t *puNewRsp) RT_NOEXCEPT;
4395VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
4396VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
4397VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4398VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
4399VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4400VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4401VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4402VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4403VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4404 void const **ppvMem, uint64_t *puNewRsp) RT_NOEXCEPT;
4405VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
4406 void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
4407VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
4408VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
4409VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
4410VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
4411VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4412VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4413VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4414/** @} */
4415
4416/** @name IEMAllCImpl.cpp
4417 * @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
4418 * @{ */
4419IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4420IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4421IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4422IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
4423IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
4424IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
4425IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
4426IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
4427IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
4428IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
4429IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
4430IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
4431IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
4432IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
4433IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
4434IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4435IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4436typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4437typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
4438IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
4439IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
4440IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
4441IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
4442IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
4443IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
4444IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
4445IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
4446IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
4447IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
4448IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
4449IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
4450IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
4451IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
4452IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
4453IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
4454IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
4455IEM_CIMPL_PROTO_0(iemCImpl_syscall);
4456IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
4457IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
4458IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4459IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4460IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4461IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4462IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4463IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4464IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4465IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4466IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4467IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4468IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4469IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4470IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4471IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4472IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4473IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4474IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4475IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4476IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4477IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4478IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4479IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4480IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4481IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4482IEM_CIMPL_PROTO_0(iemCImpl_clts);
4483IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4484IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4485IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4486IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4487IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4488IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4489IEM_CIMPL_PROTO_0(iemCImpl_invd);
4490IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4491IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4492IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4493IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4494IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4495IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4496IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4497IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4498IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4499IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4500IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4501IEM_CIMPL_PROTO_0(iemCImpl_cli);
4502IEM_CIMPL_PROTO_0(iemCImpl_sti);
4503IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4504IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4505IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4506IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4507IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4508IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4509IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4510IEM_CIMPL_PROTO_0(iemCImpl_daa);
4511IEM_CIMPL_PROTO_0(iemCImpl_das);
4512IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4513IEM_CIMPL_PROTO_0(iemCImpl_aas);
4514IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4515IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4516IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4517IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4518IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4519 PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4520IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4521IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4522IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4523IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4524IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4525IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4526IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4527IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4528IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4529IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4530IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4531IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4532IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4533IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4534IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
4535IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, uint32_t, uPopAndFpuOpcode);
4536/** @} */
4537
4538/** @name IEMAllCImplStrInstr.cpp.h
4539 * @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4540 * -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4541 * @{ */
4542IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4543IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4544IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4545IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4546IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4547IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4548IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4549IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4550IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4551IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4552IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4553
4554IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4555IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4556IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4557IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4558IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4559IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4560IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4561IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4562IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4563IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4564IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4565
4566IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4567IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4568IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4569IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4570IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4571IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4572IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4573IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4574IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4575IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4576IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4577
4578
4579IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4580IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4581IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4582IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4583IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4584IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4585IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4586IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4587IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4588IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4589IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4590
4591IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4592IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4593IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4594IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4595IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4596IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4597IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4598IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4599IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4600IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4601IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4602
4603IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4604IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4605IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4606IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4607IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4608IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4609IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4610IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4611IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4612IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4613IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4614
4615IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4616IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4617IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4618IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4619IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4620IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4621IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4622IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4623IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4624IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4625IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4626
4627
4628IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4629IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4630IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4631IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4632IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4633IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4634IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4635IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4636IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4637IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4638IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4639
4640IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4641IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4642IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4643IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4644IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4645IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4646IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4647IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4648IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4649IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4650IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4651
4652IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4653IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4654IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4655IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4656IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4657IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4658IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4659IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4660IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4661IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4662IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4663
4664IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4665IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4666IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4667IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4668IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4669IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4670IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4671IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4672IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4673IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4674IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4675/** @} */
4676
4677#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4678VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4679VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4680VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4681VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4682VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4683VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4684VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4685VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4686VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4687VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4688 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4689VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4690 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4691VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4692VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4693VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4694VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4695VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4696VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4697VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4698VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4699 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4700VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4701VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4702VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4703uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4704void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4705VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4706 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4707bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4708IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4709IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4710IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4711IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4712IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4713IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4714IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4715IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4716IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4717IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4718IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
4719IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4720IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4721IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4722IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4723IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4724#endif
4725
4726#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4727VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4728VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4729VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4730 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4731VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
4732IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4733IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4734IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4735IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4736IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4737IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4738IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4739IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4740#endif
4741
4742IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4743IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4744IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4745
4746
4747extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
4748
4749/** @} */
4750
4751RT_C_DECLS_END
4752
4753#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4754
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