VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h

Last change on this file was 106453, checked in by vboxsync, 7 weeks ago

VMM/IEM: Eliminated the IEMNATIVE_WITH_SIMD_REG_ALLOCATOR define. Fixed bug in iemNativeEmitMemFetchStoreDataCommon where a SIMD register was masked in calls to iemNativeVarSaveVolatileRegsPreHlpCall and friends. Fixed theoretical loop-forever bugs in iemNativeSimdRegAllocFindFree & iemNativeRegAllocFindFree. bugref:10720

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 357.3 KB
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1/* $Id: IEMInternal.h 106453 2024-10-17 13:54:35Z vboxsync $ */
2/** @file
3 * IEM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2011-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29#define VMM_INCLUDED_SRC_include_IEMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef RT_IN_ASSEMBLER
35# include <VBox/vmm/cpum.h>
36# include <VBox/vmm/iem.h>
37# include <VBox/vmm/pgm.h>
38# include <VBox/vmm/stam.h>
39# include <VBox/param.h>
40
41# include <iprt/setjmp-without-sigmask.h>
42# include <iprt/list.h>
43#endif /* !RT_IN_ASSEMBLER */
44
45
46RT_C_DECLS_BEGIN
47
48
49/** @defgroup grp_iem_int Internals
50 * @ingroup grp_iem
51 * @internal
52 * @{
53 */
54
55/* Make doxygen happy w/o overcomplicating the #if checks. */
56#ifdef DOXYGEN_RUNNING
57# define IEM_WITH_THROW_CATCH
58# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59#endif
60
61/** For expanding symbol in slickedit and other products tagging and
62 * crossreferencing IEM symbols. */
63#ifndef IEM_STATIC
64# define IEM_STATIC static
65#endif
66
67/** @def IEM_WITH_SETJMP
68 * Enables alternative status code handling using setjmps.
69 *
70 * This adds a bit of expense via the setjmp() call since it saves all the
71 * non-volatile registers. However, it eliminates return code checks and allows
72 * for more optimal return value passing (return regs instead of stack buffer).
73 */
74#if defined(DOXYGEN_RUNNING) || defined(RT_OS_WINDOWS) || 1
75# define IEM_WITH_SETJMP
76#endif
77
78/** @def IEM_WITH_THROW_CATCH
79 * Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80 * mode code when IEM_WITH_SETJMP is in effect.
81 *
82 * With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83 * setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84 * result value improving by more than 1%. (Best out of three.)
85 *
86 * With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87 * setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88 * the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89 * Linux, but it should be quite a bit faster for normal code.
90 */
91#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) || defined(_MSC_VER)) /* ASM-NOINC-START */
92# define IEM_WITH_THROW_CATCH
93#endif /*ASM-NOINC-END*/
94
95/** @def IEM_WITH_ADAPTIVE_TIMER_POLLING
96 * Enables the adaptive timer polling code.
97 */
98#if defined(DOXYGEN_RUNNING) || 1
99# define IEM_WITH_ADAPTIVE_TIMER_POLLING
100#endif
101
102/** @def IEM_WITH_INTRA_TB_JUMPS
103 * Enables loop-jumps within a TB (currently only to the first call).
104 */
105#if defined(DOXYGEN_RUNNING) || 1
106# define IEM_WITH_INTRA_TB_JUMPS
107#endif
108
109/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
110 * Enables the delayed PC updating optimization (see @bugref{10373}).
111 */
112#if defined(DOXYGEN_RUNNING) || 1
113# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
114#endif
115/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
116 * Enabled delayed PC updating debugging code.
117 * This is an alternative to the ARM64-only IEMNATIVE_REG_FIXED_PC_DBG. */
118#if defined(DOXYGEN_RUNNING) || 0
119# define IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
120#endif
121
122/** Enables access to even callee saved registers. */
123/*# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS*/
124
125#if defined(DOXYGEN_RUNNING) || 1
126/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
127 * Delay the writeback or dirty registers as long as possible. */
128# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
129#endif
130
131/** @def IEM_WITH_TLB_STATISTICS
132 * Enables all TLB statistics. */
133#if defined(VBOX_WITH_STATISTICS) || defined(DOXYGEN_RUNNING)
134# define IEM_WITH_TLB_STATISTICS
135#endif
136
137/** @def IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
138 * Enable this to use native emitters for certain SIMD FP operations. */
139#if 1 || defined(DOXYGEN_RUNNING)
140# define IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
141#endif
142
143/** @def VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING
144 * Enable this to create a saved state file with the threaded translation
145 * blocks fed to the native recompiler on VCPU \#0. The resulting file can
146 * then be fed into the native recompiler for code profiling purposes.
147 * This is not a feature that should be normally be enabled! */
148#if 0 || defined(DOXYGEN_RUNNING)
149# define VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING
150#endif
151
152/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
153 * Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
154 * executing native translation blocks.
155 *
156 * This exploits the fact that we save all non-volatile registers in the TB
157 * prologue and thus just need to do the same as the TB epilogue to get the
158 * effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
159 * non-volatile (and does something even more crazy for ARM), this probably
160 * won't work reliably on Windows. */
161#ifdef RT_ARCH_ARM64
162# ifndef RT_OS_WINDOWS
163# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
164# endif
165#endif
166/* ASM-NOINC-START */
167#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
168# if !defined(IN_RING3) \
169 || !defined(VBOX_WITH_IEM_RECOMPILER) \
170 || !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
171# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
172# elif defined(RT_OS_WINDOWS)
173# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
174# endif
175#endif
176
177
178/** @def IEM_DO_LONGJMP
179 *
180 * Wrapper around longjmp / throw.
181 *
182 * @param a_pVCpu The CPU handle.
183 * @param a_rc The status code jump back with / throw.
184 */
185#if defined(IEM_WITH_SETJMP) || defined(DOXYGEN_RUNNING)
186# ifdef IEM_WITH_THROW_CATCH
187# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
188# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
189 if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
190 iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
191 throw int(a_rc); \
192 } while (0)
193# else
194# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
195# endif
196# else
197# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
198# endif
199#endif
200
201/** For use with IEM function that may do a longjmp (when enabled).
202 *
203 * Visual C++ has trouble longjmp'ing from/over functions with the noexcept
204 * attribute. So, we indicate that function that may be part of a longjmp may
205 * throw "exceptions" and that the compiler should definitely not generate and
206 * std::terminate calling unwind code.
207 *
208 * Here is one example of this ending in std::terminate:
209 * @code{.txt}
21000 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
21101 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
21202 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
21303 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
21404 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
21505 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
21606 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
21707 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
21808 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
21909 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
2200a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
2210b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
2220c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
2230d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
2240e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
2250f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
22610 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
227 @endcode
228 *
229 * @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
230 */
231#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) || defined(IEM_WITH_THROW_CATCH))
232# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
233#else
234# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
235#endif
236/* ASM-NOINC-END */
237
238#define IEM_IMPLEMENTS_TASKSWITCH
239
240/** @def IEM_WITH_3DNOW
241 * Includes the 3DNow decoding. */
242#if !defined(IEM_WITH_3DNOW) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
243# ifndef IEM_WITHOUT_3DNOW
244# define IEM_WITH_3DNOW
245# endif
246#endif
247
248/** @def IEM_WITH_THREE_0F_38
249 * Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
250#if !defined(IEM_WITH_THREE_0F_38) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
251# ifndef IEM_WITHOUT_THREE_0F_38
252# define IEM_WITH_THREE_0F_38
253# endif
254#endif
255
256/** @def IEM_WITH_THREE_0F_3A
257 * Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
258#if !defined(IEM_WITH_THREE_0F_3A) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
259# ifndef IEM_WITHOUT_THREE_0F_3A
260# define IEM_WITH_THREE_0F_3A
261# endif
262#endif
263
264/** @def IEM_WITH_VEX
265 * Includes the VEX decoding. */
266#if !defined(IEM_WITH_VEX) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
267# ifndef IEM_WITHOUT_VEX
268# define IEM_WITH_VEX
269# endif
270#endif
271
272/** @def IEM_CFG_TARGET_CPU
273 * The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
274 *
275 * By default we allow this to be configured by the user via the
276 * CPUM/GuestCpuName config string, but this comes at a slight cost during
277 * decoding. So, for applications of this code where there is no need to
278 * be dynamic wrt target CPU, just modify this define.
279 */
280#if !defined(IEM_CFG_TARGET_CPU) || defined(DOXYGEN_RUNNING)
281# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
282#endif
283
284//#define IEM_WITH_CODE_TLB // - work in progress
285//#define IEM_WITH_DATA_TLB // - work in progress
286
287
288/** @def IEM_USE_UNALIGNED_DATA_ACCESS
289 * Use unaligned accesses instead of elaborate byte assembly. */
290#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) || defined(DOXYGEN_RUNNING) /*ASM-NOINC*/
291# define IEM_USE_UNALIGNED_DATA_ACCESS
292#endif /*ASM-NOINC*/
293
294//#define IEM_LOG_MEMORY_WRITES
295
296
297
298#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
299
300# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
301/** Instruction statistics. */
302typedef struct IEMINSTRSTATS
303{
304# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
305# include "IEMInstructionStatisticsTmpl.h"
306# undef IEM_DO_INSTR_STAT
307} IEMINSTRSTATS;
308#else
309struct IEMINSTRSTATS;
310typedef struct IEMINSTRSTATS IEMINSTRSTATS;
311#endif
312/** Pointer to IEM instruction statistics. */
313typedef IEMINSTRSTATS *PIEMINSTRSTATS;
314
315
316/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
317 * @{ */
318#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /**< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. */
319#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /**< Intel EFLAGS result. */
320#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /**< AMD EFLAGS result */
321#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /**< Reserved/dummy entry slot that's the same as 0. */
322#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /**< For masking the index before use. */
323/** Selects the right variant from a_aArray.
324 * pVCpu is implicit in the caller context. */
325#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
326 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
327/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
328 * be used because the host CPU does not support the operation. */
329#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
330 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
331/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
332 * array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
333 * into the two.
334 * @sa IEM_SELECT_NATIVE_OR_FALLBACK */
335#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
336# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
337 (a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
338#else
339# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
340 (a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
341#endif
342/** @} */
343
344/**
345 * Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
346 * indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
347 *
348 * On non-x86 hosts, this will shortcut to the fallback w/o checking the
349 * indicator.
350 *
351 * @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
352 */
353#if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
354# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
355 (g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
356#else
357# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
358#endif
359
360/** @name Helpers for passing C++ template arguments to an
361 * IEM_MC_NATIVE_EMIT_3/4/5 style macro.
362 * @{
363 */
364#define IEM_TEMPL_ARG_1(a1) <a1>
365#define IEM_TEMPL_ARG_2(a1, a2) <a1,a2>
366#define IEM_TEMPL_ARG_3(a1, a2, a3) <a1,a2,a3>
367/** @} */
368
369
370/**
371 * Branch types.
372 */
373typedef enum IEMBRANCH
374{
375 IEMBRANCH_JUMP = 1,
376 IEMBRANCH_CALL,
377 IEMBRANCH_TRAP,
378 IEMBRANCH_SOFTWARE_INT,
379 IEMBRANCH_HARDWARE_INT
380} IEMBRANCH;
381AssertCompileSize(IEMBRANCH, 4);
382
383
384/**
385 * INT instruction types.
386 */
387typedef enum IEMINT
388{
389 /** INT n instruction (opcode 0xcd imm). */
390 IEMINT_INTN = 0,
391 /** Single byte INT3 instruction (opcode 0xcc). */
392 IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
393 /** Single byte INTO instruction (opcode 0xce). */
394 IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
395 /** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
396 IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
397} IEMINT;
398AssertCompileSize(IEMINT, 4);
399
400
401/**
402 * A FPU result.
403 */
404typedef struct IEMFPURESULT
405{
406 /** The output value. */
407 RTFLOAT80U r80Result;
408 /** The output status. */
409 uint16_t FSW;
410} IEMFPURESULT;
411AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
412/** Pointer to a FPU result. */
413typedef IEMFPURESULT *PIEMFPURESULT;
414/** Pointer to a const FPU result. */
415typedef IEMFPURESULT const *PCIEMFPURESULT;
416
417
418/**
419 * A FPU result consisting of two output values and FSW.
420 */
421typedef struct IEMFPURESULTTWO
422{
423 /** The first output value. */
424 RTFLOAT80U r80Result1;
425 /** The output status. */
426 uint16_t FSW;
427 /** The second output value. */
428 RTFLOAT80U r80Result2;
429} IEMFPURESULTTWO;
430AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
431AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
432/** Pointer to a FPU result consisting of two output values and FSW. */
433typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
434/** Pointer to a const FPU result consisting of two output values and FSW. */
435typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
436
437
438/**
439 * IEM TLB entry.
440 *
441 * Lookup assembly:
442 * @code{.asm}
443 ; Calculate tag.
444 mov rax, [VA]
445 shl rax, 16
446 shr rax, 16 + X86_PAGE_SHIFT
447 or rax, [uTlbRevision]
448
449 ; Do indexing.
450 movzx ecx, al
451 lea rcx, [pTlbEntries + rcx]
452
453 ; Check tag.
454 cmp [rcx + IEMTLBENTRY.uTag], rax
455 jne .TlbMiss
456
457 ; Check access.
458 mov rax, ACCESS_FLAGS | MAPPING_R3_NOT_VALID | 0xffffff00
459 and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
460 cmp rax, [uTlbPhysRev]
461 jne .TlbMiss
462
463 ; Calc address and we're done.
464 mov eax, X86_PAGE_OFFSET_MASK
465 and eax, [VA]
466 or rax, [rcx + IEMTLBENTRY.pMappingR3]
467 %ifdef VBOX_WITH_STATISTICS
468 inc qword [cTlbHits]
469 %endif
470 jmp .Done
471
472 .TlbMiss:
473 mov r8d, ACCESS_FLAGS
474 mov rdx, [VA]
475 mov rcx, [pVCpu]
476 call iemTlbTypeMiss
477 .Done:
478
479 @endcode
480 *
481 */
482typedef struct IEMTLBENTRY
483{
484 /** The TLB entry tag.
485 * Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
486 * is ASSUMING a virtual address width of 48 bits.
487 *
488 * Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
489 *
490 * The TLB lookup code uses the current TLB revision, which won't ever be zero,
491 * enabling an extremely cheap TLB invalidation most of the time. When the TLB
492 * revision wraps around though, the tags needs to be zeroed.
493 *
494 * @note Try use SHRD instruction? After seeing
495 * https://gmplib.org/~tege/x86-timing.pdf, maybe not.
496 *
497 * @todo This will need to be reorganized for 57-bit wide virtual address and
498 * PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
499 * have to move the TLB entry versioning entirely to the
500 * fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
501 * 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
502 * consumed by PCID and ASID (12 + 6 = 18).
503 */
504 uint64_t uTag;
505 /** Access flags and physical TLB revision.
506 *
507 * - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
508 * - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
509 * - Bit 2 - page tables - not user (complemented X86_PTE_US).
510 * - Bit 3 - pgm phys/virt - not directly writable.
511 * - Bit 4 - pgm phys page - not directly readable.
512 * - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
513 * - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
514 * - Bit 7 - tlb entry - pMappingR3 member not valid.
515 * - Bits 63 thru 8 are used for the physical TLB revision number.
516 *
517 * We're using complemented bit meanings here because it makes it easy to check
518 * whether special action is required. For instance a user mode write access
519 * would do a "TEST fFlags, (X86_PTE_RW | X86_PTE_US | X86_PTE_D)" and a
520 * non-zero result would mean special handling needed because either it wasn't
521 * writable, or it wasn't user, or the page wasn't dirty. A user mode read
522 * access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
523 * need to check any PTE flag.
524 */
525 uint64_t fFlagsAndPhysRev;
526 /** The guest physical page address. */
527 uint64_t GCPhys;
528 /** Pointer to the ring-3 mapping. */
529 R3PTRTYPE(uint8_t *) pbMappingR3;
530#if HC_ARCH_BITS == 32
531 uint32_t u32Padding1;
532#endif
533} IEMTLBENTRY;
534AssertCompileSize(IEMTLBENTRY, 32);
535/** Pointer to an IEM TLB entry. */
536typedef IEMTLBENTRY *PIEMTLBENTRY;
537/** Pointer to a const IEM TLB entry. */
538typedef IEMTLBENTRY const *PCIEMTLBENTRY;
539
540/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
541 * @{ */
542#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /**< Page tables: Not executable. */
543#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /**< Page tables: Not writable. */
544#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /**< Page tables: Not user accessible (supervisor only). */
545#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /**< Phys page: Not writable (access handler, ROM, whatever). */
546#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /**< Phys page: Not readable (MMIO / access handler, ROM) */
547#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /**< Phys tables: Not accessed (need to be marked accessed). */
548#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /**< Page tables: Not dirty (needs to be made dirty on write). */
549#define IEMTLBE_F_PT_LARGE_PAGE RT_BIT_64(7) /**< Page tables: Large 2 or 4 MiB page (for flushing). */
550#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(8) /**< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. */
551#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(9) /**< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
552#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(10) /**< Phys page: Code page. */
553#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffff800) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
554/** @} */
555AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
556AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
557AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
558AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
559AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
560AssertCompile(PGM_WALKINFO_BIG_PAGE == IEMTLBE_F_PT_LARGE_PAGE);
561/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
562#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
563 | PGMIEMGCPHYS2PTR_F_NO_READ \
564 | PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
565 | PGMIEMGCPHYS2PTR_F_UNASSIGNED \
566 | PGMIEMGCPHYS2PTR_F_CODE_PAGE \
567 | IEMTLBE_F_PHYS_REV )
568
569
570/** The TLB size (power of two).
571 * We initially chose 256 because that way we can obtain the result directly
572 * from a 8-bit register without an additional AND instruction.
573 * See also @bugref{10687}. */
574#if defined(RT_ARCH_AMD64)
575# define IEMTLB_ENTRY_COUNT 256
576# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
577#else
578# define IEMTLB_ENTRY_COUNT 8192
579# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 13
580#endif
581AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
582
583/** TLB slot format spec (assumes uint32_t or unsigned value). */
584#if IEMTLB_ENTRY_COUNT <= 0x100 / 2
585# define IEMTLB_SLOT_FMT "%02x"
586#elif IEMTLB_ENTRY_COUNT <= 0x1000 / 2
587# define IEMTLB_SLOT_FMT "%03x"
588#elif IEMTLB_ENTRY_COUNT <= 0x10000 / 2
589# define IEMTLB_SLOT_FMT "%04x"
590#else
591# define IEMTLB_SLOT_FMT "%05x"
592#endif
593
594/** Enable the large page bitmap TLB optimization.
595 *
596 * The idea here is to avoid scanning the full 32 KB (2MB pages, 2*512 TLB
597 * entries) or 64 KB (4MB pages, 2*1024 TLB entries) worth of TLB entries during
598 * invlpg when large pages are used, and instead just scan 128 or 256 bytes of
599 * the bmLargePage bitmap to determin which TLB entires that might be containing
600 * large pages and actually require checking.
601 *
602 * There is a good posibility of false positives since we currently don't clear
603 * the bitmap when flushing the TLB, but it should help reduce the workload when
604 * the large pages aren't fully loaded into the TLB in their entirity...
605 */
606#define IEMTLB_WITH_LARGE_PAGE_BITMAP
607
608/**
609 * An IEM TLB.
610 *
611 * We've got two of these, one for data and one for instructions.
612 */
613typedef struct IEMTLB
614{
615 /** The non-global TLB revision.
616 * This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
617 * by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
618 * the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
619 * (The revision zero indicates an invalid TLB entry.)
620 *
621 * The initial value is choosen to cause an early wraparound. */
622 uint64_t uTlbRevision;
623 /** The TLB physical address revision - shadow of PGM variable.
624 *
625 * This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
626 * incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
627 * a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
628 * as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
629 *
630 * The initial value is choosen to cause an early wraparound.
631 *
632 * @note This is placed between the two TLB revisions because we
633 * load it in pair with one or the other on arm64. */
634 uint64_t volatile uTlbPhysRev;
635 /** The global TLB revision.
636 * Same as uTlbRevision, but only increased for global flushes. */
637 uint64_t uTlbRevisionGlobal;
638
639 /** Large page tag range.
640 *
641 * This is used to avoid scanning a large page's worth of TLB entries for each
642 * INVLPG instruction, and only to do so iff we've loaded any and when the
643 * address is in this range. This is kept up to date when we loading new TLB
644 * entries.
645 */
646 struct LARGEPAGERANGE
647 {
648 /** The lowest large page address tag, UINT64_MAX if none. */
649 uint64_t uFirstTag;
650 /** The highest large page address tag (with offset mask part set), 0 if none. */
651 uint64_t uLastTag;
652 }
653 /** Large page range for non-global pages. */
654 NonGlobalLargePageRange,
655 /** Large page range for global pages. */
656 GlobalLargePageRange;
657 /** Number of non-global entries for large pages loaded since last TLB flush. */
658 uint32_t cTlbNonGlobalLargePageCurLoads;
659 /** Number of global entries for large pages loaded since last TLB flush. */
660 uint32_t cTlbGlobalLargePageCurLoads;
661
662 /* Statistics: */
663
664 /** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
665 * @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
666 * not via safe read/write path) calls to iemMemMapJmp. */
667 uint64_t cTlbCoreHits;
668 /** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
669 * only; data tlb only). */
670 uint64_t cTlbSafeHits;
671 /** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
672 uint64_t cTlbInlineCodeHits;
673
674 /** TLB misses in IEMAll.cpp code (both).
675 * @note For the data TLB this is only used in iemMemMap and for direct (i.e.
676 * not via safe read/write path) calls to iemMemMapJmp. So,
677 * for the data TLB this more like 'other misses', while for the code
678 * TLB is all misses. */
679 uint64_t cTlbCoreMisses;
680 /** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
681 uint64_t cTlbCoreGlobalLoads;
682 /** Safe read/write TLB misses in iemMemMapJmp (so data only). */
683 uint64_t cTlbSafeMisses;
684 /** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
685 uint64_t cTlbSafeGlobalLoads;
686 /** Safe read path taken (data only). */
687 uint64_t cTlbSafeReadPath;
688 /** Safe write path taken (data only). */
689 uint64_t cTlbSafeWritePath;
690
691 /** @name Details for native code TLB misses.
692 * @note These counts are included in the above counters (cTlbSafeReadPath,
693 * cTlbSafeWritePath, cTlbInlineCodeHits).
694 * @{ */
695 /** TLB misses in native code due to tag mismatch. */
696 STAMCOUNTER cTlbNativeMissTag;
697 /** TLB misses in native code due to flags or physical revision mismatch. */
698 STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
699 /** TLB misses in native code due to misaligned access. */
700 STAMCOUNTER cTlbNativeMissAlignment;
701 /** TLB misses in native code due to cross page access. */
702 uint32_t cTlbNativeMissCrossPage;
703 /** TLB misses in native code due to non-canonical address. */
704 uint32_t cTlbNativeMissNonCanonical;
705 /** @} */
706
707 /** Slow read path (code only). */
708 uint32_t cTlbSlowCodeReadPath;
709
710 /** Regular TLB flush count. */
711 uint32_t cTlsFlushes;
712 /** Global TLB flush count. */
713 uint32_t cTlsGlobalFlushes;
714 /** Revision rollovers. */
715 uint32_t cTlbRevisionRollovers;
716 /** Physical revision flushes. */
717 uint32_t cTlbPhysRevFlushes;
718 /** Physical revision rollovers. */
719 uint32_t cTlbPhysRevRollovers;
720
721 /** Number of INVLPG (and similar) operations. */
722 uint32_t cTlbInvlPg;
723 /** Subset of cTlbInvlPg that involved non-global large pages. */
724 uint32_t cTlbInvlPgLargeNonGlobal;
725 /** Subset of cTlbInvlPg that involved global large pages. */
726 uint32_t cTlbInvlPgLargeGlobal;
727
728 uint32_t au32Padding[13];
729
730 /** The TLB entries.
731 * Even entries are for PTE.G=0 and uses uTlbRevision.
732 * Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
733 IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
734#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
735 /** Bitmap tracking TLB entries for large pages.
736 * This duplicates IEMTLBE_F_PT_LARGE_PAGE for each TLB entry. */
737 uint64_t bmLargePage[IEMTLB_ENTRY_COUNT * 2 / 64];
738#endif
739} IEMTLB;
740AssertCompileSizeAlignment(IEMTLB, 64);
741#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
742AssertCompile(IEMTLB_ENTRY_COUNT >= 32 /* bmLargePage ASSUMPTION */);
743#endif
744/** The width (in bits) of the address portion of the TLB tag. */
745#define IEMTLB_TAG_ADDR_WIDTH 36
746/** IEMTLB::uTlbRevision increment. */
747#define IEMTLB_REVISION_INCR RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH)
748/** IEMTLB::uTlbRevision mask. */
749#define IEMTLB_REVISION_MASK (~(RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH) - 1))
750
751/** IEMTLB::uTlbPhysRev increment.
752 * @sa IEMTLBE_F_PHYS_REV */
753#define IEMTLB_PHYS_REV_INCR RT_BIT_64(11)
754AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
755
756/**
757 * Calculates the TLB tag for a virtual address but without TLB revision.
758 * @returns Tag value for indexing and comparing with IEMTLB::uTag.
759 * @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
760 * the clearing of the top 16 bits won't work (if 32-bit
761 * we'll end up with mostly zeros).
762 */
763#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
764/**
765 * Converts a TLB tag value into a even TLB index.
766 * @returns Index into IEMTLB::aEntries.
767 * @param a_uTag Value returned by IEMTLB_CALC_TAG.
768 */
769#if IEMTLB_ENTRY_COUNT == 256
770# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
771#else
772# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
773AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
774#endif
775/**
776 * Converts a TLB tag value into an even TLB index.
777 * @returns Pointer into IEMTLB::aEntries corresponding to .
778 * @param a_pTlb The TLB.
779 * @param a_uTag Value returned by IEMTLB_CALC_TAG or
780 * IEMTLB_CALC_TAG_NO_REV.
781 */
782#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
783
784/** Converts a GC address to an even TLB index. */
785#define IEMTLB_ADDR_TO_EVEN_INDEX(a_GCPtr) IEMTLB_TAG_TO_EVEN_INDEX(IEMTLB_CALC_TAG_NO_REV(a_GCPtr))
786
787
788/** @def IEM_WITH_TLB_TRACE
789 * Enables the TLB tracing.
790 * Adjust buffer size in IEMR3Init. */
791#if defined(DOXYGEN_RUNNING) || 0
792# define IEM_WITH_TLB_TRACE
793#endif
794
795#ifdef IEM_WITH_TLB_TRACE
796
797/** TLB trace entry types. */
798typedef enum : uint8_t
799{
800 kIemTlbTraceType_Invalid,
801 kIemTlbTraceType_InvlPg,
802 kIemTlbTraceType_EvictSlot,
803 kIemTlbTraceType_LargeEvictSlot,
804 kIemTlbTraceType_LargeScan,
805 kIemTlbTraceType_Flush,
806 kIemTlbTraceType_FlushGlobal,
807 kIemTlbTraceType_Load,
808 kIemTlbTraceType_LoadGlobal,
809 kIemTlbTraceType_Load_Cr0,
810 kIemTlbTraceType_Load_Cr3,
811 kIemTlbTraceType_Load_Cr4,
812 kIemTlbTraceType_Load_Efer,
813 kIemTlbTraceType_Irq,
814 kIemTlbTraceType_Xcpt,
815 kIemTlbTraceType_IRet,
816 kIemTlbTraceType_Tb_Compile,
817 kIemTlbTraceType_Tb_Exec_Threaded,
818 kIemTlbTraceType_Tb_Exec_Native,
819 kIemTlbTraceType_User0,
820 kIemTlbTraceType_User1,
821 kIemTlbTraceType_User2,
822 kIemTlbTraceType_User3,
823} IEMTLBTRACETYPE;
824
825/** TLB trace entry. */
826typedef struct IEMTLBTRACEENTRY
827{
828 /** The flattened RIP for the event. */
829 uint64_t rip;
830 /** The event type. */
831 IEMTLBTRACETYPE enmType;
832 /** Byte parameter - typically used as 'bool fDataTlb'. */
833 uint8_t bParam;
834 /** 16-bit parameter value. */
835 uint16_t u16Param;
836 /** 32-bit parameter value. */
837 uint32_t u32Param;
838 /** 64-bit parameter value. */
839 uint64_t u64Param;
840 /** 64-bit parameter value. */
841 uint64_t u64Param2;
842} IEMTLBTRACEENTRY;
843AssertCompileSize(IEMTLBTRACEENTRY, 32);
844/** Pointer to a TLB trace entry. */
845typedef IEMTLBTRACEENTRY *PIEMTLBTRACEENTRY;
846/** Pointer to a const TLB trace entry. */
847typedef IEMTLBTRACEENTRY const *PCIEMTLBTRACEENTRY;
848#endif /* !IEM_WITH_TLB_TRACE */
849
850#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
851# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) \
852 iemTlbTrace(a_pVCpu, kIemTlbTraceType_InvlPg, a_GCPtr)
853# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
854 iemTlbTrace(a_pVCpu, kIemTlbTraceType_EvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
855# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
856 iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeEvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
857# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) \
858 iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeScan, 0, 0, a_fDataTlb, (uint8_t)a_fGlobal | ((uint8_t)a_fNonGlobal << 1))
859# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) \
860 iemTlbTrace(a_pVCpu, kIemTlbTraceType_Flush, a_uRev, 0, a_fDataTlb)
861# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) \
862 iemTlbTrace(a_pVCpu, kIemTlbTraceType_FlushGlobal, a_uRev, a_uGRev, a_fDataTlb)
863# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
864 iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
865# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
866 iemTlbTrace(a_pVCpu, kIemTlbTraceType_LoadGlobal, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
867#else
868# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) do { } while (0)
869# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
870# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
871# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) do { } while (0)
872# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) do { } while (0)
873# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) do { } while (0)
874# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
875# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
876#endif
877
878#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
879# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr0, a_uNew, a_uOld)
880# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr3, a_uNew, a_uOld)
881# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr4, a_uNew, a_uOld)
882# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Efer, a_uNew, a_uOld)
883#else
884# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) do { } while (0)
885# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) do { } while (0)
886# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) do { } while (0)
887# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) do { } while (0)
888#endif
889
890#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
891# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) \
892 iemTlbTrace(a_pVCpu, kIemTlbTraceType_Irq, a_fEFlags, 0, a_uVector, a_fFlags)
893# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) \
894 iemTlbTrace(a_pVCpu, kIemTlbTraceType_Xcpt, a_uErr, a_uCr2, a_uVector, a_fFlags)
895# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) \
896 iemTlbTrace(a_pVCpu, kIemTlbTraceType_IRet, a_uRetRip, a_fEFlags, 0, a_uRetCs)
897#else
898# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) do { } while (0)
899# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) do { } while (0)
900# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) do { } while (0)
901#endif
902
903#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
904# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) \
905 iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Compile, a_GCPhysPc)
906# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) \
907 iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Threaded, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
908# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) \
909 iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Native, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
910#else
911# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) do { } while (0)
912# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) do { } while (0)
913# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) do { } while (0)
914#endif
915
916#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
917# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
918 iemTlbTrace(a_pVCpu, kIemTlbTraceType_User0, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
919# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
920 iemTlbTrace(a_pVCpu, kIemTlbTraceType_User1, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
921# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
922 iemTlbTrace(a_pVCpu, kIemTlbTraceType_User2, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
923# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
924 iemTlbTrace(a_pVCpu, kIemTlbTraceType_User3, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
925#else
926# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
927# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
928# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
929# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
930#endif
931
932
933/** @name IEM_MC_F_XXX - MC block flags/clues.
934 * @todo Merge with IEM_CIMPL_F_XXX
935 * @{ */
936#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
937#define IEM_MC_F_MIN_186 RT_BIT_32(1)
938#define IEM_MC_F_MIN_286 RT_BIT_32(2)
939#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
940#define IEM_MC_F_MIN_386 RT_BIT_32(3)
941#define IEM_MC_F_MIN_486 RT_BIT_32(4)
942#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
943#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
944#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
945#define IEM_MC_F_64BIT RT_BIT_32(6)
946#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
947/** This is set by IEMAllN8vePython.py to indicate a variation with the
948 * flags-clearing-and-checking. */
949#define IEM_MC_F_WITH_FLAGS RT_BIT_32(8)
950/** This is set by IEMAllN8vePython.py to indicate a variation without the
951 * flags-clearing-and-checking, when there is also a variation with that.
952 * @note Do not set this manully, it's only for python and for testing in
953 * the native recompiler! */
954#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(9)
955/** @} */
956
957/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
958 *
959 * These clues are mainly for the recompiler, so that it can emit correct code.
960 *
961 * They are processed by the python script and which also automatically
962 * calculates flags for MC blocks based on the statements, extending the use of
963 * these flags to describe MC block behavior to the recompiler core. The python
964 * script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
965 * error checking purposes. The script emits the necessary fEndTb = true and
966 * similar statements as this reduces compile time a tiny bit.
967 *
968 * @{ */
969/** Flag set if direct branch, clear if absolute or indirect. */
970#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
971/** Flag set if indirect branch, clear if direct or relative.
972 * This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
973 * as well as for return instructions (RET, IRET, RETF). */
974#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
975/** Flag set if relative branch, clear if absolute or indirect. */
976#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
977/** Flag set if conditional branch, clear if unconditional. */
978#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
979/** Flag set if it's a far branch (changes CS). */
980#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
981/** Convenience: Testing any kind of branch. */
982#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT | IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_RELATIVE)
983
984/** Execution flags may change (IEMCPU::fExec). */
985#define IEM_CIMPL_F_MODE RT_BIT_32(5)
986/** May change significant portions of RFLAGS. */
987#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
988/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
989#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
990/** May trigger interrupt shadowing. */
991#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
992/** May enable interrupts, so recheck IRQ immediately afterwards executing
993 * the instruction. */
994#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
995/** May disable interrupts, so recheck IRQ immediately before executing the
996 * instruction. */
997#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
998/** Convenience: Check for IRQ both before and after an instruction. */
999#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE | IEM_CIMPL_F_CHECK_IRQ_AFTER)
1000/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
1001#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
1002/** May modify FPU state.
1003 * @todo Not sure if this is useful yet. */
1004#define IEM_CIMPL_F_FPU RT_BIT_32(12)
1005/** REP prefixed instruction which may yield before updating PC.
1006 * @todo Not sure if this is useful, REP functions now return non-zero
1007 * status if they don't update the PC. */
1008#define IEM_CIMPL_F_REP RT_BIT_32(13)
1009/** I/O instruction.
1010 * @todo Not sure if this is useful yet. */
1011#define IEM_CIMPL_F_IO RT_BIT_32(14)
1012/** Force end of TB after the instruction. */
1013#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
1014/** Flag set if a branch may also modify the stack (push/pop return address). */
1015#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
1016/** Flag set if a branch may also modify the stack (push/pop return address)
1017 * and switch it (load/restore SS:RSP). */
1018#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
1019/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
1020#define IEM_CIMPL_F_XCPT \
1021 (IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR \
1022 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT)
1023
1024/** The block calls a C-implementation instruction function with two implicit arguments.
1025 * Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
1026 * IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1027 * @note The python scripts will add this if missing. */
1028#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
1029/** The block calls an ASM-implementation instruction function.
1030 * Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
1031 * IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1032 * @note The python scripts will add this if missing. */
1033#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
1034/** The block calls an ASM-implementation instruction function with an implicit
1035 * X86FXSTATE pointer argument.
1036 * Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1037 * IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
1038 * @note The python scripts will add this if missing. */
1039#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
1040/** The block calls an ASM-implementation instruction function with an implicit
1041 * X86XSAVEAREA pointer argument.
1042 * Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1043 * IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1044 * @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
1045 * @note The python scripts will add this if missing. */
1046#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
1047/** @} */
1048
1049
1050/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
1051 *
1052 * These flags are set when entering IEM and adjusted as code is executed, such
1053 * that they will always contain the current values as instructions are
1054 * finished.
1055 *
1056 * In recompiled execution mode, (most of) these flags are included in the
1057 * translation block selection key and stored in IEMTB::fFlags alongside the
1058 * IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
1059 * in IEMCPU::fExec.
1060 *
1061 * @{ */
1062/** Mode: The block target mode mask. */
1063#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
1064/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
1065#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
1066/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
1067 * conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
1068 * 32-bit mode (for simplifying most memory accesses). */
1069#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
1070/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
1071#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
1072/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
1073#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
1074
1075/** X86 Mode: 16-bit on 386 or later. */
1076#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
1077/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
1078#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
1079/** X86 Mode: 16-bit protected mode on 386 or later. */
1080#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
1081/** X86 Mode: 16-bit protected mode on 386 or later. */
1082#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
1083/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
1084#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
1085
1086/** X86 Mode: 32-bit on 386 or later. */
1087#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
1088/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
1089#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
1090/** X86 Mode: 32-bit protected mode. */
1091#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
1092/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
1093#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
1094
1095/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
1096#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
1097
1098/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
1099#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
1100 || ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
1101 || ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
1102
1103/** Bypass access handlers when set. */
1104#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
1105/** Have pending hardware instruction breakpoints. */
1106#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
1107/** Have pending hardware data breakpoints. */
1108#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
1109
1110/** X86: Have pending hardware I/O breakpoints. */
1111#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
1112/** X86: Disregard the lock prefix (implied or not) when set. */
1113#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
1114
1115/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
1116#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR | IEM_F_PENDING_BRK_DATA | IEM_F_PENDING_BRK_X86_IO)
1117
1118/** Caller configurable options. */
1119#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS | IEM_F_X86_DISREGARD_LOCK)
1120
1121/** X86: The current protection level (CPL) shift factor. */
1122#define IEM_F_X86_CPL_SHIFT 8
1123/** X86: The current protection level (CPL) mask. */
1124#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
1125/** X86: The current protection level (CPL) shifted mask. */
1126#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
1127
1128/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
1129#define IEM_F_X86_AC UINT32_C(0x00080000)
1130
1131/** X86 execution context.
1132 * The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
1133 * the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
1134 * mode. */
1135#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
1136/** X86 context: Plain regular execution context. */
1137#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
1138/** X86 context: VT-x enabled. */
1139#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
1140/** X86 context: AMD-V enabled. */
1141#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
1142/** X86 context: In AMD-V or VT-x guest mode. */
1143#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
1144/** X86 context: System management mode (SMM). */
1145#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
1146
1147/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1148 * iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
1149 * and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
1150 * alread). */
1151
1152/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1153 * iemRegFinishClearingRF() most for most situations
1154 * (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
1155 * the IEM_F_PENDING_BRK_XXX bits alread). */
1156
1157/** @} */
1158
1159
1160/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
1161 *
1162 * Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
1163 * translation block flags. The combined flag mask (subject to
1164 * IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
1165 *
1166 * @{ */
1167/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
1168#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
1169
1170/** Type: The block type mask. */
1171#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
1172/** Type: Purly threaded recompiler (via tables). */
1173#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
1174/** Type: Native recompilation. */
1175#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
1176
1177/** Set when we're starting the block in an "interrupt shadow".
1178 * We don't need to distingish between the two types of this mask, thus the one.
1179 * @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
1180#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
1181/** Set when we're currently inhibiting NMIs
1182 * @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
1183#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
1184
1185/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
1186 * we're close the limit before starting a TB, as determined by
1187 * iemGetTbFlagsForCurrentPc(). */
1188#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
1189
1190/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
1191 *
1192 * @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
1193 * don't implement), because we don't currently generate any context
1194 * specific code - that's all handled in CIMPL functions.
1195 *
1196 * For the threaded recompiler we don't generate any CPL specific code
1197 * either, but the native recompiler does for memory access (saves getting
1198 * the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
1199 * Since most OSes will not share code between rings, this shouldn't
1200 * have any real effect on TB/memory/recompiling load.
1201 */
1202#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK | IEMTB_F_TYPE_MASK)) | IEM_F_X86_CTX_SMM)
1203/** @} */
1204
1205AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1206AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1207AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
1208AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
1209AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1210AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1211AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
1212AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1213AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1214AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1215AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1216AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
1217AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1218AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1219AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
1220AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1221AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
1222AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1223AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
1224
1225AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1226AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1227AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
1228AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1229AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1230AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
1231AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1232AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1233AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1234AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1235AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1236AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
1237
1238AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
1239AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
1240AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1241
1242/** Native instruction type for use with the native code generator.
1243 * This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
1244#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
1245typedef uint8_t IEMNATIVEINSTR;
1246#else
1247typedef uint32_t IEMNATIVEINSTR;
1248#endif
1249/** Pointer to a native instruction unit. */
1250typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
1251/** Pointer to a const native instruction unit. */
1252typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
1253
1254/**
1255 * A call for the threaded call table.
1256 */
1257typedef struct IEMTHRDEDCALLENTRY
1258{
1259 /** The function to call (IEMTHREADEDFUNCS). */
1260 uint16_t enmFunction;
1261
1262 /** Instruction number in the TB (for statistics). */
1263 uint8_t idxInstr;
1264 /** The opcode length. */
1265 uint8_t cbOpcode;
1266 /** Offset into IEMTB::pabOpcodes. */
1267 uint16_t offOpcode;
1268
1269 /** TB lookup table index (7 bits) and large size (1 bits).
1270 *
1271 * The default size is 1 entry, but for indirect calls and returns we set the
1272 * top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1273 * tables uses RIP for selecting the entry to use, as it is assumed a hash table
1274 * lookup isn't that slow compared to sequentially trying out 4 TBs.
1275 *
1276 * By default lookup table entry 0 for a TB is reserved as a fallback for
1277 * calltable entries w/o explicit entreis, so this member will be non-zero if
1278 * there is a lookup entry associated with this call.
1279 *
1280 * @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1281 */
1282 uint8_t uTbLookup;
1283
1284 /** Flags - IEMTHREADEDCALLENTRY_F_XXX. */
1285 uint8_t fFlags;
1286
1287 /** Generic parameters. */
1288 uint64_t auParams[3];
1289} IEMTHRDEDCALLENTRY;
1290AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1291/** Pointer to a threaded call entry. */
1292typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1293/** Pointer to a const threaded call entry. */
1294typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1295
1296/** The number of TB lookup table entries for a large allocation
1297 * (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1298#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1299/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1300#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1301/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1302#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1303/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1304#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1305 (!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1306
1307/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1308#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) | ((a_fLarge) ? 0x80 : 0))
1309
1310
1311/** The call entry is a jump target. */
1312#define IEMTHREADEDCALLENTRY_F_JUMP_TARGET UINT8_C(0x01)
1313
1314
1315/**
1316 * Native IEM TB 'function' typedef.
1317 *
1318 * This will throw/longjmp on occation.
1319 *
1320 * @note AMD64 doesn't have that many non-volatile registers and does sport
1321 * 32-bit address displacments, so we don't need pCtx.
1322 *
1323 * On ARM64 pCtx allows us to directly address the whole register
1324 * context without requiring a separate indexing register holding the
1325 * offset. This saves an instruction loading the offset for each guest
1326 * CPU context access, at the cost of a non-volatile register.
1327 * Fortunately, ARM64 has quite a lot more registers.
1328 */
1329typedef
1330#ifdef RT_ARCH_AMD64
1331int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1332#else
1333int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1334#endif
1335#if RT_CPLUSPLUS_PREREQ(201700)
1336 IEM_NOEXCEPT_MAY_LONGJMP
1337#endif
1338 ;
1339/** Pointer to a native IEM TB entry point function.
1340 * This will throw/longjmp on occation. */
1341typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1342
1343
1344/**
1345 * Translation block.
1346 *
1347 * The current plan is to just keep TBs and associated lookup hash table private
1348 * to each VCpu as that simplifies TB removal greatly (no races) and generally
1349 * avoids using expensive atomic primitives for updating lists and stuff.
1350 */
1351#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1352typedef struct IEMTB
1353{
1354 /** Next block with the same hash table entry. */
1355 struct IEMTB *pNext;
1356 /** Usage counter. */
1357 uint32_t cUsed;
1358 /** The IEMCPU::msRecompilerPollNow last time it was used. */
1359 uint32_t msLastUsed;
1360
1361 /** @name What uniquely identifies the block.
1362 * @{ */
1363 RTGCPHYS GCPhysPc;
1364 /** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1365 uint32_t fFlags;
1366 union
1367 {
1368 struct
1369 {
1370 /**< Relevant CS X86DESCATTR_XXX bits. */
1371 uint16_t fAttr;
1372 } x86;
1373 };
1374 /** @} */
1375
1376 /** Number of opcode ranges. */
1377 uint8_t cRanges;
1378 /** Statistics: Number of instructions in the block. */
1379 uint8_t cInstructions;
1380
1381 /** Type specific info. */
1382 union
1383 {
1384 struct
1385 {
1386 /** The call sequence table. */
1387 PIEMTHRDEDCALLENTRY paCalls;
1388 /** Number of calls in paCalls. */
1389 uint16_t cCalls;
1390 /** Number of calls allocated. */
1391 uint16_t cAllocated;
1392 } Thrd;
1393 struct
1394 {
1395 /** The native instructions (PFNIEMTBNATIVE). */
1396 PIEMNATIVEINSTR paInstructions;
1397 /** Number of instructions pointed to by paInstructions. */
1398 uint32_t cInstructions;
1399 } Native;
1400 /** Generic view for zeroing when freeing. */
1401 struct
1402 {
1403 uintptr_t uPtr;
1404 uint32_t uData;
1405 } Gen;
1406 };
1407
1408 /** The allocation chunk this TB belongs to. */
1409 uint8_t idxAllocChunk;
1410 /** The number of entries in the lookup table.
1411 * Because we're out of space, the TB lookup table is located before the
1412 * opcodes pointed to by pabOpcodes. */
1413 uint8_t cTbLookupEntries;
1414
1415 /** Number of bytes of opcodes stored in pabOpcodes.
1416 * @todo this field isn't really needed, aRanges keeps the actual info. */
1417 uint16_t cbOpcodes;
1418 /** Pointer to the opcode bytes this block was recompiled from.
1419 * This also points to the TB lookup table, which starts cTbLookupEntries
1420 * entries before the opcodes (we don't have room atm for another point). */
1421 uint8_t *pabOpcodes;
1422
1423 union
1424 {
1425 /** Native recompilation debug info if enabled.
1426 * This is only generated by the native recompiler. */
1427 struct IEMTBDBG *pDbgInfo;
1428 /** For threaded TBs and natives when debug info is disabled, this is the flat
1429 * PC corresponding to GCPhysPc. */
1430 RTGCPTR FlatPc;
1431 };
1432
1433 /* --- 64 byte cache line end --- */
1434
1435 /** Opcode ranges.
1436 *
1437 * The opcode checkers and maybe TLB loading functions will use this to figure
1438 * out what to do. The parameter will specify an entry and the opcode offset to
1439 * start at and the minimum number of bytes to verify (instruction length).
1440 *
1441 * When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1442 * they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1443 * code TLB (must have a valid entry for that address) and scan the ranges to
1444 * locate the corresponding opcodes. Probably.
1445 */
1446 struct IEMTBOPCODERANGE
1447 {
1448 /** Offset within pabOpcodes. */
1449 uint16_t offOpcodes;
1450 /** Number of bytes. */
1451 uint16_t cbOpcodes;
1452 /** The page offset. */
1453 RT_GCC_EXTENSION
1454 uint16_t offPhysPage : 12;
1455 /** Unused bits. */
1456 RT_GCC_EXTENSION
1457 uint16_t u2Unused : 2;
1458 /** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1459 RT_GCC_EXTENSION
1460 uint16_t idxPhysPage : 2;
1461 } aRanges[8];
1462
1463 /** Physical pages that this TB covers.
1464 * The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1465 RTGCPHYS aGCPhysPages[2];
1466} IEMTB;
1467#pragma pack()
1468AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1469AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1470AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1471AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1472AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1473AssertCompileMemberOffset(IEMTB, aRanges, 64);
1474AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1475#if 1
1476AssertCompileSize(IEMTB, 128);
1477# define IEMTB_SIZE_IS_POWER_OF_TWO /**< The IEMTB size is a power of two. */
1478#else
1479AssertCompileSize(IEMTB, 168);
1480# undef IEMTB_SIZE_IS_POWER_OF_TWO
1481#endif
1482
1483/** Pointer to a translation block. */
1484typedef IEMTB *PIEMTB;
1485/** Pointer to a const translation block. */
1486typedef IEMTB const *PCIEMTB;
1487
1488/** Gets address of the given TB lookup table entry. */
1489#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1490 ((PIEMTB *)&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) * sizeof(PIEMTB)])
1491
1492/**
1493 * Gets the physical address for a TB opcode range.
1494 */
1495DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1496{
1497 Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1498 uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1499 Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1500 if (idxPage == 0)
1501 return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1502 Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1503 return pTb->aGCPhysPages[idxPage - 1];
1504}
1505
1506
1507/**
1508 * A chunk of memory in the TB allocator.
1509 */
1510typedef struct IEMTBCHUNK
1511{
1512 /** Pointer to the translation blocks in this chunk. */
1513 PIEMTB paTbs;
1514#ifdef IN_RING0
1515 /** Allocation handle. */
1516 RTR0MEMOBJ hMemObj;
1517#endif
1518} IEMTBCHUNK;
1519
1520/**
1521 * A per-CPU translation block allocator.
1522 *
1523 * Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1524 * the length of the collision list, and of course also for cache line alignment
1525 * reasons, the TBs must be allocated with at least 64-byte alignment.
1526 * Memory is there therefore allocated using one of the page aligned allocators.
1527 *
1528 *
1529 * To avoid wasting too much memory, it is allocated piecemeal as needed,
1530 * in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1531 * that enables us to quickly calculate the allocation bitmap position when
1532 * freeing the translation block.
1533 */
1534typedef struct IEMTBALLOCATOR
1535{
1536 /** Magic value (IEMTBALLOCATOR_MAGIC). */
1537 uint32_t uMagic;
1538
1539#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1540 /** Mask corresponding to cTbsPerChunk - 1. */
1541 uint32_t fChunkMask;
1542 /** Shift count corresponding to cTbsPerChunk. */
1543 uint8_t cChunkShift;
1544#else
1545 uint32_t uUnused;
1546 uint8_t bUnused;
1547#endif
1548 /** Number of chunks we're allowed to allocate. */
1549 uint8_t cMaxChunks;
1550 /** Number of chunks currently populated. */
1551 uint16_t cAllocatedChunks;
1552 /** Number of translation blocks per chunk. */
1553 uint32_t cTbsPerChunk;
1554 /** Chunk size. */
1555 uint32_t cbPerChunk;
1556
1557 /** The maximum number of TBs. */
1558 uint32_t cMaxTbs;
1559 /** Total number of TBs in the populated chunks.
1560 * (cAllocatedChunks * cTbsPerChunk) */
1561 uint32_t cTotalTbs;
1562 /** The current number of TBs in use.
1563 * The number of free TBs: cAllocatedTbs - cInUseTbs; */
1564 uint32_t cInUseTbs;
1565 /** Statistics: Number of the cInUseTbs that are native ones. */
1566 uint32_t cNativeTbs;
1567 /** Statistics: Number of the cInUseTbs that are threaded ones. */
1568 uint32_t cThreadedTbs;
1569
1570 /** Where to start pruning TBs from when we're out.
1571 * See iemTbAllocatorAllocSlow for details. */
1572 uint32_t iPruneFrom;
1573 /** Where to start pruning native TBs from when we're out of executable memory.
1574 * See iemTbAllocatorFreeupNativeSpace for details. */
1575 uint32_t iPruneNativeFrom;
1576 uint64_t u64Padding;
1577
1578 /** Statistics: Number of TB allocation calls. */
1579 STAMCOUNTER StatAllocs;
1580 /** Statistics: Number of TB free calls. */
1581 STAMCOUNTER StatFrees;
1582 /** Statistics: Time spend pruning. */
1583 STAMPROFILE StatPrune;
1584 /** Statistics: Time spend pruning native TBs. */
1585 STAMPROFILE StatPruneNative;
1586
1587 /** The delayed free list (see iemTbAlloctorScheduleForFree). */
1588 PIEMTB pDelayedFreeHead;
1589 /* Head of the list of free TBs. */
1590 PIEMTB pTbsFreeHead;
1591
1592 /** Allocation chunks. */
1593 IEMTBCHUNK aChunks[256];
1594} IEMTBALLOCATOR;
1595/** Pointer to a TB allocator. */
1596typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1597
1598/** Magic value for the TB allocator (Emmet Harley Cohen). */
1599#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1600
1601
1602/**
1603 * A per-CPU translation block cache (hash table).
1604 *
1605 * The hash table is allocated once during IEM initialization and size double
1606 * the max TB count, rounded up to the nearest power of two (so we can use and
1607 * AND mask rather than a rest division when hashing).
1608 */
1609typedef struct IEMTBCACHE
1610{
1611 /** Magic value (IEMTBCACHE_MAGIC). */
1612 uint32_t uMagic;
1613 /** Size of the hash table. This is a power of two. */
1614 uint32_t cHash;
1615 /** The mask corresponding to cHash. */
1616 uint32_t uHashMask;
1617 uint32_t uPadding;
1618
1619 /** @name Statistics
1620 * @{ */
1621 /** Number of collisions ever. */
1622 STAMCOUNTER cCollisions;
1623
1624 /** Statistics: Number of TB lookup misses. */
1625 STAMCOUNTER cLookupMisses;
1626 /** Statistics: Number of TB lookup hits via hash table (debug only). */
1627 STAMCOUNTER cLookupHits;
1628 /** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1629 STAMCOUNTER cLookupHitsViaTbLookupTable;
1630 STAMCOUNTER auPadding2[2];
1631 /** Statistics: Collision list length pruning. */
1632 STAMPROFILE StatPrune;
1633 /** @} */
1634
1635 /** The hash table itself.
1636 * @note The lower 6 bits of the pointer is used for keeping the collision
1637 * list length, so we can take action when it grows too long.
1638 * This works because TBs are allocated using a 64 byte (or
1639 * higher) alignment from page aligned chunks of memory, so the lower
1640 * 6 bits of the address will always be zero.
1641 * See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1642 */
1643 RT_FLEXIBLE_ARRAY_EXTENSION
1644 PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1645} IEMTBCACHE;
1646/** Pointer to a per-CPU translation block cahce. */
1647typedef IEMTBCACHE *PIEMTBCACHE;
1648
1649/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1650#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1651
1652/** The collision count mask for IEMTBCACHE::apHash entries. */
1653#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1654/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1655#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1656/** Combine a TB pointer and a collision list length into a value for an
1657 * IEMTBCACHE::apHash entry. */
1658#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) | (a_cCount))
1659/** Combine a TB pointer and a collision list length into a value for an
1660 * IEMTBCACHE::apHash entry. */
1661#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1662/** Combine a TB pointer and a collision list length into a value for an
1663 * IEMTBCACHE::apHash entry. */
1664#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1665
1666/**
1667 * Calculates the hash table slot for a TB from physical PC address and TB flags.
1668 */
1669#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1670 IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1671
1672/**
1673 * Calculates the hash table slot for a TB from physical PC address and TB
1674 * flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1675 */
1676#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1677 (((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1678
1679
1680/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1681 *
1682 * These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1683 *
1684 * @{ */
1685/** Value if no branching happened recently. */
1686#define IEMBRANCHED_F_NO UINT8_C(0x00)
1687/** Flag set if direct branch, clear if absolute or indirect. */
1688#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1689/** Flag set if indirect branch, clear if direct or relative. */
1690#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1691/** Flag set if relative branch, clear if absolute or indirect. */
1692#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1693/** Flag set if conditional branch, clear if unconditional. */
1694#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1695/** Flag set if it's a far branch. */
1696#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1697/** Flag set if the stack pointer is modified. */
1698#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1699/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1700#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1701/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1702#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1703/** @} */
1704
1705
1706/**
1707 * The per-CPU IEM state.
1708 */
1709typedef struct IEMCPU
1710{
1711 /** Info status code that needs to be propagated to the IEM caller.
1712 * This cannot be passed internally, as it would complicate all success
1713 * checks within the interpreter making the code larger and almost impossible
1714 * to get right. Instead, we'll store status codes to pass on here. Each
1715 * source of these codes will perform appropriate sanity checks. */
1716 int32_t rcPassUp; /* 0x00 */
1717 /** Execution flag, IEM_F_XXX. */
1718 uint32_t fExec; /* 0x04 */
1719
1720 /** @name Decoder state.
1721 * @{ */
1722#ifdef IEM_WITH_CODE_TLB
1723 /** The offset of the next instruction byte. */
1724 uint32_t offInstrNextByte; /* 0x08 */
1725 /** The number of bytes available at pbInstrBuf for the current instruction.
1726 * This takes the max opcode length into account so that doesn't need to be
1727 * checked separately. */
1728 uint32_t cbInstrBuf; /* 0x0c */
1729 /** Pointer to the page containing RIP, user specified buffer or abOpcode.
1730 * This can be NULL if the page isn't mappable for some reason, in which
1731 * case we'll do fallback stuff.
1732 *
1733 * If we're executing an instruction from a user specified buffer,
1734 * IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1735 * aligned pointer but pointer to the user data.
1736 *
1737 * For instructions crossing pages, this will start on the first page and be
1738 * advanced to the next page by the time we've decoded the instruction. This
1739 * therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1740 */
1741 uint8_t const *pbInstrBuf; /* 0x10 */
1742# if ARCH_BITS == 32
1743 uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1744# endif
1745 /** The program counter corresponding to pbInstrBuf.
1746 * This is set to a non-canonical address when we need to invalidate it. */
1747 uint64_t uInstrBufPc; /* 0x18 */
1748 /** The guest physical address corresponding to pbInstrBuf. */
1749 RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1750 /** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1751 * This takes the CS segment limit into account.
1752 * @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1753 uint16_t cbInstrBufTotal; /* 0x28 */
1754 /** Offset into pbInstrBuf of the first byte of the current instruction.
1755 * Can be negative to efficiently handle cross page instructions. */
1756 int16_t offCurInstrStart; /* 0x2a */
1757
1758# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1759 /** The prefix mask (IEM_OP_PRF_XXX). */
1760 uint32_t fPrefixes; /* 0x2c */
1761 /** The extra REX ModR/M register field bit (REX.R << 3). */
1762 uint8_t uRexReg; /* 0x30 */
1763 /** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1764 * (REX.B << 3). */
1765 uint8_t uRexB; /* 0x31 */
1766 /** The extra REX SIB index field bit (REX.X << 3). */
1767 uint8_t uRexIndex; /* 0x32 */
1768
1769 /** The effective segment register (X86_SREG_XXX). */
1770 uint8_t iEffSeg; /* 0x33 */
1771
1772 /** The offset of the ModR/M byte relative to the start of the instruction. */
1773 uint8_t offModRm; /* 0x34 */
1774
1775# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1776 /** The current offset into abOpcode. */
1777 uint8_t offOpcode; /* 0x35 */
1778# else
1779 uint8_t bUnused; /* 0x35 */
1780# endif
1781# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1782 uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1783# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1784
1785#else /* !IEM_WITH_CODE_TLB */
1786# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1787 /** The size of what has currently been fetched into abOpcode. */
1788 uint8_t cbOpcode; /* 0x08 */
1789 /** The current offset into abOpcode. */
1790 uint8_t offOpcode; /* 0x09 */
1791 /** The offset of the ModR/M byte relative to the start of the instruction. */
1792 uint8_t offModRm; /* 0x0a */
1793
1794 /** The effective segment register (X86_SREG_XXX). */
1795 uint8_t iEffSeg; /* 0x0b */
1796
1797 /** The prefix mask (IEM_OP_PRF_XXX). */
1798 uint32_t fPrefixes; /* 0x0c */
1799 /** The extra REX ModR/M register field bit (REX.R << 3). */
1800 uint8_t uRexReg; /* 0x10 */
1801 /** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1802 * (REX.B << 3). */
1803 uint8_t uRexB; /* 0x11 */
1804 /** The extra REX SIB index field bit (REX.X << 3). */
1805 uint8_t uRexIndex; /* 0x12 */
1806
1807# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1808 uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1809# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1810#endif /* !IEM_WITH_CODE_TLB */
1811
1812#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1813 /** The effective operand mode. */
1814 IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1815 /** The default addressing mode. */
1816 IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1817 /** The effective addressing mode. */
1818 IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1819 /** The default operand mode. */
1820 IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1821
1822 /** Prefix index (VEX.pp) for two byte and three byte tables. */
1823 uint8_t idxPrefix; /* 0x3a, 0x17 */
1824 /** 3rd VEX/EVEX/XOP register.
1825 * Please use IEM_GET_EFFECTIVE_VVVV to access. */
1826 uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1827 /** The VEX/EVEX/XOP length field. */
1828 uint8_t uVexLength; /* 0x3c, 0x19 */
1829 /** Additional EVEX stuff. */
1830 uint8_t fEvexStuff; /* 0x3d, 0x1a */
1831
1832# ifndef IEM_WITH_CODE_TLB
1833 /** Explicit alignment padding. */
1834 uint8_t abAlignment2a[1]; /* 0x1b */
1835# endif
1836 /** The FPU opcode (FOP). */
1837 uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1838# ifndef IEM_WITH_CODE_TLB
1839 /** Explicit alignment padding. */
1840 uint8_t abAlignment2b[2]; /* 0x1e */
1841# endif
1842
1843 /** The opcode bytes. */
1844 uint8_t abOpcode[15]; /* 0x40, 0x20 */
1845 /** Explicit alignment padding. */
1846# ifdef IEM_WITH_CODE_TLB
1847 //uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1848# else
1849 uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1850# endif
1851
1852#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1853# ifdef IEM_WITH_CODE_TLB
1854 uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1855# else
1856 uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1857# endif
1858#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1859 /** @} */
1860
1861
1862 /** The number of active guest memory mappings. */
1863 uint8_t cActiveMappings; /* 0x4f, 0x4f */
1864
1865 /** Records for tracking guest memory mappings. */
1866 struct
1867 {
1868 /** The address of the mapped bytes. */
1869 R3R0PTRTYPE(void *) pv;
1870 /** The access flags (IEM_ACCESS_XXX).
1871 * IEM_ACCESS_INVALID if the entry is unused. */
1872 uint32_t fAccess;
1873#if HC_ARCH_BITS == 64
1874 uint32_t u32Alignment4; /**< Alignment padding. */
1875#endif
1876 } aMemMappings[3]; /* 0x50 LB 0x30 */
1877
1878 /** Locking records for the mapped memory. */
1879 union
1880 {
1881 PGMPAGEMAPLOCK Lock;
1882 uint64_t au64Padding[2];
1883 } aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1884
1885 /** Bounce buffer info.
1886 * This runs in parallel to aMemMappings. */
1887 struct
1888 {
1889 /** The physical address of the first byte. */
1890 RTGCPHYS GCPhysFirst;
1891 /** The physical address of the second page. */
1892 RTGCPHYS GCPhysSecond;
1893 /** The number of bytes in the first page. */
1894 uint16_t cbFirst;
1895 /** The number of bytes in the second page. */
1896 uint16_t cbSecond;
1897 /** Whether it's unassigned memory. */
1898 bool fUnassigned;
1899 /** Explicit alignment padding. */
1900 bool afAlignment5[3];
1901 } aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1902
1903 /** The flags of the current exception / interrupt. */
1904 uint32_t fCurXcpt; /* 0xf8 */
1905 /** The current exception / interrupt. */
1906 uint8_t uCurXcpt; /* 0xfc */
1907 /** Exception / interrupt recursion depth. */
1908 int8_t cXcptRecursions; /* 0xfb */
1909
1910 /** The next unused mapping index.
1911 * @todo try find room for this up with cActiveMappings. */
1912 uint8_t iNextMapping; /* 0xfd */
1913 uint8_t abAlignment7[1];
1914
1915 /** Bounce buffer storage.
1916 * This runs in parallel to aMemMappings and aMemBbMappings. */
1917 struct
1918 {
1919 uint8_t ab[512];
1920 } aBounceBuffers[3]; /* 0x100 LB 0x600 */
1921
1922
1923 /** Pointer set jump buffer - ring-3 context. */
1924 R3PTRTYPE(jmp_buf *) pJmpBufR3;
1925 /** Pointer set jump buffer - ring-0 context. */
1926 R0PTRTYPE(jmp_buf *) pJmpBufR0;
1927
1928 /** @todo Should move this near @a fCurXcpt later. */
1929 /** The CR2 for the current exception / interrupt. */
1930 uint64_t uCurXcptCr2;
1931 /** The error code for the current exception / interrupt. */
1932 uint32_t uCurXcptErr;
1933
1934 /** @name Statistics
1935 * @{ */
1936 /** The number of instructions we've executed. */
1937 uint32_t cInstructions;
1938 /** The number of potential exits. */
1939 uint32_t cPotentialExits;
1940 /** The number of bytes data or stack written (mostly for IEMExecOneEx).
1941 * This may contain uncommitted writes. */
1942 uint32_t cbWritten;
1943 /** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1944 uint32_t cRetInstrNotImplemented;
1945 /** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1946 uint32_t cRetAspectNotImplemented;
1947 /** Counts informational statuses returned (other than VINF_SUCCESS). */
1948 uint32_t cRetInfStatuses;
1949 /** Counts other error statuses returned. */
1950 uint32_t cRetErrStatuses;
1951 /** Number of times rcPassUp has been used. */
1952 uint32_t cRetPassUpStatus;
1953 /** Number of times RZ left with instruction commit pending for ring-3. */
1954 uint32_t cPendingCommit;
1955 /** Number of misaligned (host sense) atomic instruction accesses. */
1956 uint32_t cMisalignedAtomics;
1957 /** Number of long jumps. */
1958 uint32_t cLongJumps;
1959 /** @} */
1960
1961 /** @name Target CPU information.
1962 * @{ */
1963#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1964 /** The target CPU. */
1965 uint8_t uTargetCpu;
1966#else
1967 uint8_t bTargetCpuPadding;
1968#endif
1969 /** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1970 * IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1971 * native host support and the 2nd for when there is.
1972 *
1973 * The two values are typically indexed by a g_CpumHostFeatures bit.
1974 *
1975 * This is for instance used for the BSF & BSR instructions where AMD and
1976 * Intel CPUs produce different EFLAGS. */
1977 uint8_t aidxTargetCpuEflFlavour[2];
1978
1979 /** The CPU vendor. */
1980 CPUMCPUVENDOR enmCpuVendor;
1981 /** @} */
1982
1983 /** @name Host CPU information.
1984 * @{ */
1985 /** The CPU vendor. */
1986 CPUMCPUVENDOR enmHostCpuVendor;
1987 /** @} */
1988
1989 /** Counts RDMSR \#GP(0) LogRel(). */
1990 uint8_t cLogRelRdMsr;
1991 /** Counts WRMSR \#GP(0) LogRel(). */
1992 uint8_t cLogRelWrMsr;
1993 /** Alignment padding. */
1994 uint8_t abAlignment9[42];
1995
1996
1997 /** @name Recompiled Exection
1998 * @{ */
1999 /** Pointer to the current translation block.
2000 * This can either be one being executed or one being compiled. */
2001 R3PTRTYPE(PIEMTB) pCurTbR3;
2002#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
2003 /** Frame pointer for the last native TB to execute. */
2004 R3PTRTYPE(void *) pvTbFramePointerR3;
2005#else
2006 R3PTRTYPE(void *) pvUnusedR3;
2007#endif
2008#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
2009 /** The saved host floating point control register (MXCSR on x86, FPCR on arm64)
2010 * needing restore when the TB finished, IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED indicates the TB
2011 * didn't modify it so we don't need to restore it. */
2012# ifdef RT_ARCH_AMD64
2013 uint32_t uRegFpCtrl;
2014 /** Temporary copy of MXCSR for stmxcsr/ldmxcsr (so we don't have to fiddle with stack pointers). */
2015 uint32_t uRegMxcsrTmp;
2016# elif defined(RT_ARCH_ARM64)
2017 uint64_t uRegFpCtrl;
2018# else
2019# error "Port me"
2020# endif
2021#else
2022 uint64_t u64Unused;
2023#endif
2024 /** Pointer to the ring-3 TB cache for this EMT. */
2025 R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
2026 /** Pointer to the ring-3 TB lookup entry.
2027 * This either points to pTbLookupEntryDummyR3 or an actually lookuptable
2028 * entry, thus it can always safely be used w/o NULL checking. */
2029 R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
2030#if 0 /* unused */
2031 /** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
2032 * The TBs are based on physical addresses, so this is needed to correleated
2033 * RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
2034 uint64_t uCurTbStartPc;
2035#endif
2036
2037 /** Number of threaded TBs executed. */
2038 uint64_t cTbExecThreaded;
2039 /** Number of native TBs executed. */
2040 uint64_t cTbExecNative;
2041
2042 /** The number of IRQ/FF checks till the next timer poll call. */
2043 uint32_t cTbsTillNextTimerPoll;
2044 /** The virtual sync time at the last timer poll call in milliseconds. */
2045 uint32_t msRecompilerPollNow;
2046 /** The virtual sync time at the last timer poll call in nanoseconds. */
2047 uint64_t nsRecompilerPollNow;
2048 /** The previous cTbsTillNextTimerPoll value. */
2049 uint32_t cTbsTillNextTimerPollPrev;
2050
2051 /** The current instruction number in a native TB.
2052 * This is set by code that may trigger an unexpected TB exit (throw/longjmp)
2053 * and will be picked up by the TB execution loop. Only used when
2054 * IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
2055 uint8_t idxTbCurInstr;
2056 /** @} */
2057
2058 /** @name Recompilation
2059 * @{ */
2060 /** Whether we need to check the opcode bytes for the current instruction.
2061 * This is set by a previous instruction if it modified memory or similar. */
2062 bool fTbCheckOpcodes;
2063 /** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
2064 uint8_t fTbBranched;
2065 /** Set when GCPhysInstrBuf is updated because of a page crossing. */
2066 bool fTbCrossedPage;
2067 /** Whether to end the current TB. */
2068 bool fEndTb;
2069 /** Indicates that the current instruction is an STI. This is set by the
2070 * iemCImpl_sti code and subsequently cleared by the recompiler. */
2071 bool fTbCurInstrIsSti;
2072 /** Spaced reserved for recompiler data / alignment. */
2073 bool afRecompilerStuff1[1];
2074 /** Number of instructions before we need emit an IRQ check call again.
2075 * This helps making sure we don't execute too long w/o checking for
2076 * interrupts and immediately following instructions that may enable
2077 * interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
2078 * required to make sure we check following the next instruction as well, see
2079 * fTbCurInstrIsSti. */
2080 uint8_t cInstrTillIrqCheck;
2081 /** The index of the last CheckIrq call during threaded recompilation. */
2082 uint16_t idxLastCheckIrqCallNo;
2083 /** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
2084 uint16_t cbOpcodesAllocated;
2085 /** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
2086 uint32_t uTbNativeRecompileAtUsedCount;
2087 /** The IEM_CIMPL_F_XXX mask for the current instruction. */
2088 uint32_t fTbCurInstr;
2089 /** The IEM_CIMPL_F_XXX mask for the previous instruction. */
2090 uint32_t fTbPrevInstr;
2091 /** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
2092 * currently not up to date in EFLAGS. */
2093 uint32_t fSkippingEFlags;
2094#if 0 /* unused */
2095 /** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
2096 RTGCPHYS GCPhysInstrBufPrev;
2097#endif
2098
2099 /** Fixed TB used for threaded recompilation.
2100 * This is allocated once with maxed-out sizes and re-used afterwards. */
2101 R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
2102 /** Pointer to the ring-3 TB allocator for this EMT. */
2103 R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
2104 /** Pointer to the ring-3 executable memory allocator for this EMT. */
2105 R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
2106 /** Pointer to the native recompiler state for ring-3. */
2107 R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
2108 /** Dummy entry for ppTbLookupEntryR3. */
2109 R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
2110#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
2111 /** The debug code advances this register as if it was CPUMCTX::rip and we
2112 * didn't do delayed PC updating. When CPUMCTX::rip is finally updated,
2113 * the result is compared with this value. */
2114 uint64_t uPcUpdatingDebug;
2115#elif defined(VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING)
2116 /** The SSM handle used for saving threaded TBs for recompiler profiling. */
2117 R3PTRTYPE(PSSMHANDLE) pSsmThreadedTbsForProfiling;
2118#else
2119 uint64_t u64Placeholder;
2120#endif
2121 /**
2122 * Whether we should use the host instruction invalidation APIs of the
2123 * host OS or our own version of it (macOS). */
2124 uint8_t fHostICacheInvalidation;
2125#define IEMNATIVE_ICACHE_F_USE_HOST_API UINT8_C(0x01) /**< Use the host API (macOS) instead of our code. */
2126#define IEMNATIVE_ICACHE_F_END_WITH_ISH UINT8_C(0x02) /**< Whether to end with a ISH barrier (arm). */
2127 bool afRecompilerStuff2[7];
2128 /** @} */
2129
2130 /** Dummy TLB entry used for accesses to pages with databreakpoints. */
2131 IEMTLBENTRY DataBreakpointTlbe;
2132
2133 /** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
2134 STAMCOUNTER StatTbThreadedExecBreaks;
2135 /** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
2136 STAMCOUNTER StatCheckIrqBreaks;
2137 /** Statistics: Times BltIn_CheckTimers breaks direct linking TBs. */
2138 STAMCOUNTER StatCheckTimersBreaks;
2139 /** Statistics: Times BltIn_CheckMode breaks out of the TB. */
2140 STAMCOUNTER StatCheckModeBreaks;
2141 /** Threaded TB statistics: Times execution break on call with lookup entries. */
2142 STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
2143 /** Threaded TB statistics: Times execution break on call without lookup entries. */
2144 STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
2145 /** Statistics: Times a post jump target check missed and had to find new TB. */
2146 STAMCOUNTER StatCheckBranchMisses;
2147 /** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
2148 STAMCOUNTER StatCheckNeedCsLimChecking;
2149 /** Statistics: Times a loop was detected within a TB. */
2150 STAMCOUNTER StatTbLoopInTbDetected;
2151 /** Statistics: Times a loop back to the start of the TB was detected. */
2152 STAMCOUNTER StatTbLoopFullTbDetected;
2153 /** Statistics: Times a loop back to the start of the TB was detected, var 2. */
2154 STAMCOUNTER StatTbLoopFullTbDetected2;
2155 /** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2156 STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2157 /** Native TB statistics: Number of fully recompiled TBs. */
2158 STAMCOUNTER StatNativeFullyRecompiledTbs;
2159 /** TB statistics: Number of instructions per TB. */
2160 STAMPROFILE StatTbInstr;
2161 /** TB statistics: Number of TB lookup table entries per TB. */
2162 STAMPROFILE StatTbLookupEntries;
2163 /** Threaded TB statistics: Number of calls per TB. */
2164 STAMPROFILE StatTbThreadedCalls;
2165 /** Native TB statistics: Native code size per TB. */
2166 STAMPROFILE StatTbNativeCode;
2167 /** Native TB statistics: Profiling native recompilation. */
2168 STAMPROFILE StatNativeRecompilation;
2169 /** Native TB statistics: Number of calls per TB that were recompiled properly. */
2170 STAMPROFILE StatNativeCallsRecompiled;
2171 /** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2172 STAMPROFILE StatNativeCallsThreaded;
2173 /** Native recompiled execution: TLB hits for data fetches. */
2174 STAMCOUNTER StatNativeTlbHitsForFetch;
2175 /** Native recompiled execution: TLB hits for data stores. */
2176 STAMCOUNTER StatNativeTlbHitsForStore;
2177 /** Native recompiled execution: TLB hits for stack accesses. */
2178 STAMCOUNTER StatNativeTlbHitsForStack;
2179 /** Native recompiled execution: TLB hits for mapped accesses. */
2180 STAMCOUNTER StatNativeTlbHitsForMapped;
2181 /** Native recompiled execution: Code TLB misses for new page. */
2182 STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2183 /** Native recompiled execution: Code TLB hits for new page. */
2184 STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2185 /** Native recompiled execution: Code TLB misses for new page with offset. */
2186 STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2187 /** Native recompiled execution: Code TLB hits for new page with offset. */
2188 STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2189
2190 /** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2191 STAMCOUNTER StatNativeRegFindFree;
2192 /** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2193 * to free a variable. */
2194 STAMCOUNTER StatNativeRegFindFreeVar;
2195 /** Native recompiler: Number of times iemNativeRegAllocFindFree did
2196 * not need to free any variables. */
2197 STAMCOUNTER StatNativeRegFindFreeNoVar;
2198 /** Native recompiler: Liveness info freed shadowed guest registers in
2199 * iemNativeRegAllocFindFree. */
2200 STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2201 /** Native recompiler: Liveness info helped with the allocation in
2202 * iemNativeRegAllocFindFree. */
2203 STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2204
2205 /** Native recompiler: Number of times status flags calc has been skipped. */
2206 STAMCOUNTER StatNativeEflSkippedArithmetic;
2207 /** Native recompiler: Number of times status flags calc has been postponed. */
2208 STAMCOUNTER StatNativeEflPostponedArithmetic;
2209 /** Native recompiler: Total number instructions in this category. */
2210 STAMCOUNTER StatNativeEflTotalArithmetic;
2211
2212 /** Native recompiler: Number of times status flags calc has been skipped. */
2213 STAMCOUNTER StatNativeEflSkippedLogical;
2214 /** Native recompiler: Number of times status flags calc has been postponed. */
2215 STAMCOUNTER StatNativeEflPostponedLogical;
2216 /** Native recompiler: Total number instructions in this category. */
2217 STAMCOUNTER StatNativeEflTotalLogical;
2218
2219 /** Native recompiler: Number of times status flags calc has been skipped. */
2220 STAMCOUNTER StatNativeEflSkippedShift;
2221 /** Native recompiler: Number of times status flags calc has been postponed. */
2222 STAMCOUNTER StatNativeEflPostponedShift;
2223 /** Native recompiler: Total number instructions in this category. */
2224 STAMCOUNTER StatNativeEflTotalShift;
2225
2226 /** Native recompiler: Number of emits per postponement. */
2227 STAMPROFILE StatNativeEflPostponedEmits;
2228
2229 /** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2230 STAMCOUNTER StatNativeLivenessEflCfSkippable;
2231 /** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2232 STAMCOUNTER StatNativeLivenessEflPfSkippable;
2233 /** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2234 STAMCOUNTER StatNativeLivenessEflAfSkippable;
2235 /** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2236 STAMCOUNTER StatNativeLivenessEflZfSkippable;
2237 /** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2238 STAMCOUNTER StatNativeLivenessEflSfSkippable;
2239 /** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2240 STAMCOUNTER StatNativeLivenessEflOfSkippable;
2241 /** Native recompiler: Number of required EFLAGS.CF updates. */
2242 STAMCOUNTER StatNativeLivenessEflCfRequired;
2243 /** Native recompiler: Number of required EFLAGS.PF updates. */
2244 STAMCOUNTER StatNativeLivenessEflPfRequired;
2245 /** Native recompiler: Number of required EFLAGS.AF updates. */
2246 STAMCOUNTER StatNativeLivenessEflAfRequired;
2247 /** Native recompiler: Number of required EFLAGS.ZF updates. */
2248 STAMCOUNTER StatNativeLivenessEflZfRequired;
2249 /** Native recompiler: Number of required EFLAGS.SF updates. */
2250 STAMCOUNTER StatNativeLivenessEflSfRequired;
2251 /** Native recompiler: Number of required EFLAGS.OF updates. */
2252 STAMCOUNTER StatNativeLivenessEflOfRequired;
2253 /** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2254 STAMCOUNTER StatNativeLivenessEflCfDelayable;
2255 /** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2256 STAMCOUNTER StatNativeLivenessEflPfDelayable;
2257 /** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2258 STAMCOUNTER StatNativeLivenessEflAfDelayable;
2259 /** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2260 STAMCOUNTER StatNativeLivenessEflZfDelayable;
2261 /** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2262 STAMCOUNTER StatNativeLivenessEflSfDelayable;
2263 /** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2264 STAMCOUNTER StatNativeLivenessEflOfDelayable;
2265
2266 /** Native recompiler: Number of potential PC updates in total. */
2267 STAMCOUNTER StatNativePcUpdateTotal;
2268 /** Native recompiler: Number of PC updates which could be delayed. */
2269 STAMCOUNTER StatNativePcUpdateDelayed;
2270
2271 /** Native recompiler: Number of time we had complicated dirty shadow
2272 * register situations with the other branch in IEM_MC_ENDIF. */
2273 STAMCOUNTER StatNativeEndIfOtherBranchDirty;
2274
2275 /** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2276 STAMCOUNTER StatNativeSimdRegFindFree;
2277 /** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2278 * to free a variable. */
2279 STAMCOUNTER StatNativeSimdRegFindFreeVar;
2280 /** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2281 * not need to free any variables. */
2282 STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2283 /** Native recompiler: Liveness info freed shadowed guest registers in
2284 * iemNativeSimdRegAllocFindFree. */
2285 STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2286 /** Native recompiler: Liveness info helped with the allocation in
2287 * iemNativeSimdRegAllocFindFree. */
2288 STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2289
2290 /** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2291 STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2292 /** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2293 STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2294 /** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2295 STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2296 /** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2297 STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2298
2299 /** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2300 STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2301 /** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2302 STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2303 /** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2304 STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2305 /** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2306 STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2307
2308 /** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2309 * Not availabe in release builds. */
2310 STAMCOUNTER StatNativeTbFinished;
2311 /** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2312 STAMCOUNTER StatNativeTbExitReturnBreak;
2313 /** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2314 STAMCOUNTER StatNativeTbExitReturnBreakFF;
2315 /** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2316 STAMCOUNTER StatNativeTbExitReturnWithFlags;
2317 /** Native recompiler: The TB finished executing with other non-zero status. */
2318 STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2319 /** Native recompiler: The TB finished executing via throw / long jump. */
2320 STAMCOUNTER StatNativeTbExitLongJump;
2321 /** Native recompiler: The TB finished executing jumping to the ReturnBreak
2322 * label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2323 STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2324 /** Native recompiler: The TB finished executing jumping to the ReturnBreak
2325 * label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2326 STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2327 /** Native recompiler: The TB finished executing jumping to the ReturnBreak
2328 * label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2329 STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2330 /** Native recompiler: The TB finished executing jumping to the ReturnBreak
2331 * label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2332 STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2333
2334 /** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2335 STAMCOUNTER StatNativeTbExitRaiseDe;
2336 /** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2337 STAMCOUNTER StatNativeTbExitRaiseUd;
2338 /** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2339 STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2340 /** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2341 STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2342 /** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2343 STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2344 /** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2345 STAMCOUNTER StatNativeTbExitRaiseNm;
2346 /** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2347 STAMCOUNTER StatNativeTbExitRaiseGp0;
2348 /** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2349 STAMCOUNTER StatNativeTbExitRaiseMf;
2350 /** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2351 STAMCOUNTER StatNativeTbExitRaiseXf;
2352 /** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2353 STAMCOUNTER StatNativeTbExitObsoleteTb;
2354
2355 /** Native recompiler: Number of full TB loops (jumps from end to start). */
2356 STAMCOUNTER StatNativeTbExitLoopFullTb;
2357
2358 /** Native recompiler: Failure situations with direct linking scenario \#1.
2359 * Counter with StatNativeTbExitReturnBreak. Not in release builds.
2360 * @{ */
2361 STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2362 STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2363 STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2364 STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2365 /** @} */
2366
2367 /** Native recompiler: Failure situations with direct linking scenario \#2.
2368 * Counter with StatNativeTbExitReturnBreak. Not in release builds.
2369 * @{ */
2370 STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2371 STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2372 STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2373 STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2374 /** @} */
2375
2376 /** iemMemMap and iemMemMapJmp statistics.
2377 * @{ */
2378 STAMCOUNTER StatMemMapJmp;
2379 STAMCOUNTER StatMemMapNoJmp;
2380 STAMCOUNTER StatMemBounceBufferCrossPage;
2381 STAMCOUNTER StatMemBounceBufferMapPhys;
2382 /** @} */
2383
2384 /** Timer polling statistics (debug only).
2385 * @{ */
2386 STAMPROFILE StatTimerPoll;
2387 STAMPROFILE StatTimerPollPoll;
2388 STAMPROFILE StatTimerPollRun;
2389 STAMCOUNTER StatTimerPollUnchanged;
2390 STAMCOUNTER StatTimerPollTiny;
2391 STAMCOUNTER StatTimerPollDefaultCalc;
2392 STAMCOUNTER StatTimerPollMax;
2393 STAMPROFILE StatTimerPollFactorDivision;
2394 STAMPROFILE StatTimerPollFactorMultiplication;
2395 /** @} */
2396
2397
2398 STAMCOUNTER aStatAdHoc[8];
2399
2400#ifdef IEM_WITH_TLB_TRACE
2401 /*uint64_t au64Padding[0];*/
2402#else
2403 uint64_t au64Padding[2];
2404#endif
2405
2406#ifdef IEM_WITH_TLB_TRACE
2407 /** The end (next) trace entry. */
2408 uint32_t idxTlbTraceEntry;
2409 /** Number of trace entries allocated expressed as a power of two. */
2410 uint32_t cTlbTraceEntriesShift;
2411 /** The trace entries. */
2412 PIEMTLBTRACEENTRY paTlbTraceEntries;
2413#endif
2414
2415 /** Data TLB.
2416 * @remarks Must be 64-byte aligned. */
2417 IEMTLB DataTlb;
2418 /** Instruction TLB.
2419 * @remarks Must be 64-byte aligned. */
2420 IEMTLB CodeTlb;
2421
2422 /** Exception statistics. */
2423 STAMCOUNTER aStatXcpts[32];
2424 /** Interrupt statistics. */
2425 uint32_t aStatInts[256];
2426
2427#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2428 /** Instruction statistics for ring-0/raw-mode. */
2429 IEMINSTRSTATS StatsRZ;
2430 /** Instruction statistics for ring-3. */
2431 IEMINSTRSTATS StatsR3;
2432# ifdef VBOX_WITH_IEM_RECOMPILER
2433 /** Statistics per threaded function call.
2434 * Updated by both the threaded and native recompilers. */
2435 uint32_t acThreadedFuncStats[0x6000 /*24576*/];
2436# endif
2437#endif
2438} IEMCPU;
2439AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2440AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2441AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2442AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2443AssertCompileMemberAlignment(IEMCPU, pCurTbR3, 64);
2444AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2445AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2446
2447/** Pointer to the per-CPU IEM state. */
2448typedef IEMCPU *PIEMCPU;
2449/** Pointer to the const per-CPU IEM state. */
2450typedef IEMCPU const *PCIEMCPU;
2451
2452/** @def IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED
2453 * Value indicating the TB didn't modified the floating point control register.
2454 * @note Neither FPCR nor MXCSR accept this as a valid value (MXCSR is not fully populated,
2455 * FPCR has the upper 32-bit reserved), so this is safe. */
2456#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) || defined(DOXYGEN_RUNNING)
2457# ifdef RT_ARCH_AMD64
2458# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT32_MAX
2459# elif defined(RT_ARCH_ARM64)
2460# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT64_MAX
2461# else
2462# error "Port me"
2463# endif
2464#endif
2465
2466/** @def IEM_GET_CTX
2467 * Gets the guest CPU context for the calling EMT.
2468 * @returns PCPUMCTX
2469 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2470 */
2471#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2472
2473/** @def IEM_CTX_ASSERT
2474 * Asserts that the @a a_fExtrnMbz is present in the CPU context.
2475 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2476 * @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2477 */
2478#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2479 AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2480 ("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2481 (a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2482
2483/** @def IEM_CTX_IMPORT_RET
2484 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2485 *
2486 * Will call the keep to import the bits as needed.
2487 *
2488 * Returns on import failure.
2489 *
2490 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2491 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2492 */
2493#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2494 do { \
2495 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2496 { /* likely */ } \
2497 else \
2498 { \
2499 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2500 AssertRCReturn(rcCtxImport, rcCtxImport); \
2501 } \
2502 } while (0)
2503
2504/** @def IEM_CTX_IMPORT_NORET
2505 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2506 *
2507 * Will call the keep to import the bits as needed.
2508 *
2509 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2510 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2511 */
2512#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2513 do { \
2514 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2515 { /* likely */ } \
2516 else \
2517 { \
2518 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2519 AssertLogRelRC(rcCtxImport); \
2520 } \
2521 } while (0)
2522
2523/** @def IEM_CTX_IMPORT_JMP
2524 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2525 *
2526 * Will call the keep to import the bits as needed.
2527 *
2528 * Jumps on import failure.
2529 *
2530 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2531 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2532 */
2533#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2534 do { \
2535 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2536 { /* likely */ } \
2537 else \
2538 { \
2539 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2540 AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2541 } \
2542 } while (0)
2543
2544
2545
2546/** @def IEM_GET_TARGET_CPU
2547 * Gets the current IEMTARGETCPU value.
2548 * @returns IEMTARGETCPU value.
2549 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2550 */
2551#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2552# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2553#else
2554# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2555#endif
2556
2557/** @def IEM_GET_INSTR_LEN
2558 * Gets the instruction length. */
2559#ifdef IEM_WITH_CODE_TLB
2560# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2561#else
2562# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2563#endif
2564
2565/** @def IEM_TRY_SETJMP
2566 * Wrapper around setjmp / try, hiding all the ugly differences.
2567 *
2568 * @note Use with extreme care as this is a fragile macro.
2569 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2570 * @param a_rcTarget The variable that should receive the status code in case
2571 * of a longjmp/throw.
2572 */
2573/** @def IEM_TRY_SETJMP_AGAIN
2574 * For when setjmp / try is used again in the same variable scope as a previous
2575 * IEM_TRY_SETJMP invocation.
2576 */
2577/** @def IEM_CATCH_LONGJMP_BEGIN
2578 * Start wrapper for catch / setjmp-else.
2579 *
2580 * This will set up a scope.
2581 *
2582 * @note Use with extreme care as this is a fragile macro.
2583 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2584 * @param a_rcTarget The variable that should receive the status code in case
2585 * of a longjmp/throw.
2586 */
2587/** @def IEM_CATCH_LONGJMP_END
2588 * End wrapper for catch / setjmp-else.
2589 *
2590 * This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2591 * state.
2592 *
2593 * @note Use with extreme care as this is a fragile macro.
2594 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2595 */
2596#if defined(IEM_WITH_SETJMP) || defined(DOXYGEN_RUNNING)
2597# ifdef IEM_WITH_THROW_CATCH
2598# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2599 a_rcTarget = VINF_SUCCESS; \
2600 try
2601# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2602 IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2603# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2604 catch (int rcThrown) \
2605 { \
2606 a_rcTarget = rcThrown
2607# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2608 } \
2609 ((void)0)
2610# else /* !IEM_WITH_THROW_CATCH */
2611# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2612 jmp_buf JmpBuf; \
2613 jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2614 (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2615 if ((rcStrict = setjmp(JmpBuf)) == 0)
2616# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2617 pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2618 (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2619 if ((rcStrict = setjmp(JmpBuf)) == 0)
2620# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2621 else \
2622 { \
2623 ((void)0)
2624# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2625 } \
2626 (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2627# endif /* !IEM_WITH_THROW_CATCH */
2628#endif /* IEM_WITH_SETJMP */
2629
2630
2631/**
2632 * Shared per-VM IEM data.
2633 */
2634typedef struct IEM
2635{
2636 /** The VMX APIC-access page handler type. */
2637 PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2638#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2639 /** Set if the CPUID host call functionality is enabled. */
2640 bool fCpuIdHostCall;
2641#endif
2642} IEM;
2643
2644
2645
2646/** @name IEM_ACCESS_XXX - Access details.
2647 * @{ */
2648#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2649#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2650#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2651#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2652#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2653#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2654#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2655#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2656#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2657#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2658/** The writes are partial, so if initialize the bounce buffer with the
2659 * orignal RAM content. */
2660#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2661/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2662#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2663/** Bounce buffer with ring-3 write pending, first page. */
2664#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2665/** Bounce buffer with ring-3 write pending, second page. */
2666#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2667/** Not locked, accessed via the TLB. */
2668#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2669/** Atomic access.
2670 * This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2671 * fallback for misaligned stuff. See @bugref{10547}. */
2672#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2673/** Valid bit mask. */
2674#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2675/** Shift count for the TLB flags (upper word). */
2676#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2677
2678/** Atomic read+write data alias. */
2679#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA | IEM_ACCESS_ATOMIC)
2680/** Read+write data alias. */
2681#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
2682/** Write data alias. */
2683#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
2684/** Read data alias. */
2685#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA)
2686/** Instruction fetch alias. */
2687#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC | IEM_ACCESS_WHAT_CODE)
2688/** Stack write alias. */
2689#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
2690/** Stack read alias. */
2691#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_STACK)
2692/** Stack read+write alias. */
2693#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
2694/** Read system table alias. */
2695#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_SYS)
2696/** Read+write system table alias. */
2697#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_SYS)
2698/** @} */
2699
2700/** @name Prefix constants (IEMCPU::fPrefixes)
2701 * @{ */
2702#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /**< CS segment prefix (0x2e). */
2703#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /**< SS segment prefix (0x36). */
2704#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /**< DS segment prefix (0x3e). */
2705#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /**< ES segment prefix (0x26). */
2706#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /**< FS segment prefix (0x64). */
2707#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /**< GS segment prefix (0x65). */
2708#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2709
2710#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /**< Operand size prefix (0x66). */
2711#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /**< REX.W prefix (0x48-0x4f). */
2712#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /**< Address size prefix (0x67). */
2713
2714#define IEM_OP_PRF_LOCK RT_BIT_32(16) /**< Lock prefix (0xf0). */
2715#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /**< Repeat-not-zero prefix (0xf2). */
2716#define IEM_OP_PRF_REPZ RT_BIT_32(18) /**< Repeat-if-zero prefix (0xf3). */
2717
2718#define IEM_OP_PRF_REX RT_BIT_32(24) /**< Any REX prefix (0x40-0x4f). */
2719#define IEM_OP_PRF_REX_B RT_BIT_32(25) /**< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). */
2720#define IEM_OP_PRF_REX_X RT_BIT_32(26) /**< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). */
2721#define IEM_OP_PRF_REX_R RT_BIT_32(27) /**< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). */
2722/** Mask with all the REX prefix flags.
2723 * This is generally for use when needing to undo the REX prefixes when they
2724 * are followed legacy prefixes and therefore does not immediately preceed
2725 * the first opcode byte.
2726 * For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2727#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X | IEM_OP_PRF_SIZE_REX_W )
2728
2729#define IEM_OP_PRF_VEX RT_BIT_32(28) /**< Indiciates VEX prefix. */
2730#define IEM_OP_PRF_EVEX RT_BIT_32(29) /**< Indiciates EVEX prefix. */
2731#define IEM_OP_PRF_XOP RT_BIT_32(30) /**< Indiciates XOP prefix. */
2732/** @} */
2733
2734/** @name IEMOPFORM_XXX - Opcode forms
2735 * @note These are ORed together with IEMOPHINT_XXX.
2736 * @{ */
2737/** ModR/M: reg, r/m */
2738#define IEMOPFORM_RM 0
2739/** ModR/M: reg, r/m (register) */
2740#define IEMOPFORM_RM_REG (IEMOPFORM_RM | IEMOPFORM_MOD3)
2741/** ModR/M: reg, r/m (memory) */
2742#define IEMOPFORM_RM_MEM (IEMOPFORM_RM | IEMOPFORM_NOT_MOD3)
2743/** ModR/M: reg, r/m, imm */
2744#define IEMOPFORM_RMI 1
2745/** ModR/M: reg, r/m (register), imm */
2746#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI | IEMOPFORM_MOD3)
2747/** ModR/M: reg, r/m (memory), imm */
2748#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI | IEMOPFORM_NOT_MOD3)
2749/** ModR/M: reg, r/m, xmm0 */
2750#define IEMOPFORM_RM0 2
2751/** ModR/M: reg, r/m (register), xmm0 */
2752#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 | IEMOPFORM_MOD3)
2753/** ModR/M: reg, r/m (memory), xmm0 */
2754#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 | IEMOPFORM_NOT_MOD3)
2755/** ModR/M: r/m, reg */
2756#define IEMOPFORM_MR 3
2757/** ModR/M: r/m (register), reg */
2758#define IEMOPFORM_MR_REG (IEMOPFORM_MR | IEMOPFORM_MOD3)
2759/** ModR/M: r/m (memory), reg */
2760#define IEMOPFORM_MR_MEM (IEMOPFORM_MR | IEMOPFORM_NOT_MOD3)
2761/** ModR/M: r/m, reg, imm */
2762#define IEMOPFORM_MRI 4
2763/** ModR/M: r/m (register), reg, imm */
2764#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI | IEMOPFORM_MOD3)
2765/** ModR/M: r/m (memory), reg, imm */
2766#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI | IEMOPFORM_NOT_MOD3)
2767/** ModR/M: r/m only */
2768#define IEMOPFORM_M 5
2769/** ModR/M: r/m only (register). */
2770#define IEMOPFORM_M_REG (IEMOPFORM_M | IEMOPFORM_MOD3)
2771/** ModR/M: r/m only (memory). */
2772#define IEMOPFORM_M_MEM (IEMOPFORM_M | IEMOPFORM_NOT_MOD3)
2773/** ModR/M: r/m, imm */
2774#define IEMOPFORM_MI 6
2775/** ModR/M: r/m (register), imm */
2776#define IEMOPFORM_MI_REG (IEMOPFORM_MI | IEMOPFORM_MOD3)
2777/** ModR/M: r/m (memory), imm */
2778#define IEMOPFORM_MI_MEM (IEMOPFORM_MI | IEMOPFORM_NOT_MOD3)
2779/** ModR/M: r/m, 1 (shift and rotate instructions) */
2780#define IEMOPFORM_M1 7
2781/** ModR/M: r/m (register), 1. */
2782#define IEMOPFORM_M1_REG (IEMOPFORM_M1 | IEMOPFORM_MOD3)
2783/** ModR/M: r/m (memory), 1. */
2784#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 | IEMOPFORM_NOT_MOD3)
2785/** ModR/M: r/m, CL (shift and rotate instructions)
2786 * @todo This should just've been a generic fixed register. But the python
2787 * code doesn't needs more convincing. */
2788#define IEMOPFORM_M_CL 8
2789/** ModR/M: r/m (register), CL. */
2790#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL | IEMOPFORM_MOD3)
2791/** ModR/M: r/m (memory), CL. */
2792#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL | IEMOPFORM_NOT_MOD3)
2793/** ModR/M: reg only */
2794#define IEMOPFORM_R 9
2795
2796/** VEX+ModR/M: reg, r/m */
2797#define IEMOPFORM_VEX_RM 16
2798/** VEX+ModR/M: reg, r/m (register) */
2799#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM | IEMOPFORM_MOD3)
2800/** VEX+ModR/M: reg, r/m (memory) */
2801#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM | IEMOPFORM_NOT_MOD3)
2802/** VEX+ModR/M: r/m, reg */
2803#define IEMOPFORM_VEX_MR 17
2804/** VEX+ModR/M: r/m (register), reg */
2805#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR | IEMOPFORM_MOD3)
2806/** VEX+ModR/M: r/m (memory), reg */
2807#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR | IEMOPFORM_NOT_MOD3)
2808/** VEX+ModR/M: r/m, reg, imm8 */
2809#define IEMOPFORM_VEX_MRI 18
2810/** VEX+ModR/M: r/m (register), reg, imm8 */
2811#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI | IEMOPFORM_MOD3)
2812/** VEX+ModR/M: r/m (memory), reg, imm8 */
2813#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI | IEMOPFORM_NOT_MOD3)
2814/** VEX+ModR/M: r/m only */
2815#define IEMOPFORM_VEX_M 19
2816/** VEX+ModR/M: r/m only (register). */
2817#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M | IEMOPFORM_MOD3)
2818/** VEX+ModR/M: r/m only (memory). */
2819#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M | IEMOPFORM_NOT_MOD3)
2820/** VEX+ModR/M: reg only */
2821#define IEMOPFORM_VEX_R 20
2822/** VEX+ModR/M: reg, vvvv, r/m */
2823#define IEMOPFORM_VEX_RVM 21
2824/** VEX+ModR/M: reg, vvvv, r/m (register). */
2825#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM | IEMOPFORM_MOD3)
2826/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2827#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM | IEMOPFORM_NOT_MOD3)
2828/** VEX+ModR/M: reg, vvvv, r/m, imm */
2829#define IEMOPFORM_VEX_RVMI 22
2830/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2831#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI | IEMOPFORM_MOD3)
2832/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2833#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI | IEMOPFORM_NOT_MOD3)
2834/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2835#define IEMOPFORM_VEX_RVMR 23
2836/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2837#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI | IEMOPFORM_MOD3)
2838/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2839#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI | IEMOPFORM_NOT_MOD3)
2840/** VEX+ModR/M: reg, r/m, vvvv */
2841#define IEMOPFORM_VEX_RMV 24
2842/** VEX+ModR/M: reg, r/m, vvvv (register). */
2843#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV | IEMOPFORM_MOD3)
2844/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2845#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV | IEMOPFORM_NOT_MOD3)
2846/** VEX+ModR/M: reg, r/m, imm8 */
2847#define IEMOPFORM_VEX_RMI 25
2848/** VEX+ModR/M: reg, r/m, imm8 (register). */
2849#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI | IEMOPFORM_MOD3)
2850/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2851#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI | IEMOPFORM_NOT_MOD3)
2852/** VEX+ModR/M: r/m, vvvv, reg */
2853#define IEMOPFORM_VEX_MVR 26
2854/** VEX+ModR/M: r/m, vvvv, reg (register) */
2855#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR | IEMOPFORM_MOD3)
2856/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2857#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR | IEMOPFORM_NOT_MOD3)
2858/** VEX+ModR/M+/n: vvvv, r/m */
2859#define IEMOPFORM_VEX_VM 27
2860/** VEX+ModR/M+/n: vvvv, r/m (register) */
2861#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM | IEMOPFORM_MOD3)
2862/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2863#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM | IEMOPFORM_NOT_MOD3)
2864/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2865#define IEMOPFORM_VEX_VMI 28
2866/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2867#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI | IEMOPFORM_MOD3)
2868/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2869#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI | IEMOPFORM_NOT_MOD3)
2870
2871/** Fixed register instruction, no R/M. */
2872#define IEMOPFORM_FIXED 32
2873
2874/** The r/m is a register. */
2875#define IEMOPFORM_MOD3 RT_BIT_32(8)
2876/** The r/m is a memory access. */
2877#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2878/** @} */
2879
2880/** @name IEMOPHINT_XXX - Additional Opcode Hints
2881 * @note These are ORed together with IEMOPFORM_XXX.
2882 * @{ */
2883/** Ignores the operand size prefix (66h). */
2884#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2885/** Ignores REX.W (aka WIG). */
2886#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2887/** Both the operand size prefixes (66h + REX.W) are ignored. */
2888#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_IGNORES_REXW)
2889/** Allowed with the lock prefix. */
2890#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2891/** The VEX.L value is ignored (aka LIG). */
2892#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2893/** The VEX.L value must be zero (i.e. 128-bit width only). */
2894#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2895/** The VEX.L value must be one (i.e. 256-bit width only). */
2896#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2897/** The VEX.V value must be zero. */
2898#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2899/** The REX.W/VEX.V value must be zero. */
2900#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2901#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2902/** The REX.W/VEX.V value must be one. */
2903#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2904#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2905
2906/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2907#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2908/** @} */
2909
2910/**
2911 * Possible hardware task switch sources.
2912 */
2913typedef enum IEMTASKSWITCH
2914{
2915 /** Task switch caused by an interrupt/exception. */
2916 IEMTASKSWITCH_INT_XCPT = 1,
2917 /** Task switch caused by a far CALL. */
2918 IEMTASKSWITCH_CALL,
2919 /** Task switch caused by a far JMP. */
2920 IEMTASKSWITCH_JUMP,
2921 /** Task switch caused by an IRET. */
2922 IEMTASKSWITCH_IRET
2923} IEMTASKSWITCH;
2924AssertCompileSize(IEMTASKSWITCH, 4);
2925
2926/**
2927 * Possible CrX load (write) sources.
2928 */
2929typedef enum IEMACCESSCRX
2930{
2931 /** CrX access caused by 'mov crX' instruction. */
2932 IEMACCESSCRX_MOV_CRX,
2933 /** CrX (CR0) write caused by 'lmsw' instruction. */
2934 IEMACCESSCRX_LMSW,
2935 /** CrX (CR0) write caused by 'clts' instruction. */
2936 IEMACCESSCRX_CLTS,
2937 /** CrX (CR0) read caused by 'smsw' instruction. */
2938 IEMACCESSCRX_SMSW
2939} IEMACCESSCRX;
2940
2941#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2942/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2943 *
2944 * These flags provide further context to SLAT page-walk failures that could not be
2945 * determined by PGM (e.g, PGM is not privy to memory access permissions).
2946 *
2947 * @{
2948 */
2949/** Translating a nested-guest linear address failed accessing a nested-guest
2950 * physical address. */
2951# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2952/** Translating a nested-guest linear address failed accessing a
2953 * paging-structure entry or updating accessed/dirty bits. */
2954# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2955/** @} */
2956
2957DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2958# ifndef IN_RING3
2959DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2960# endif
2961#endif
2962
2963/**
2964 * Indicates to the verifier that the given flag set is undefined.
2965 *
2966 * Can be invoked again to add more flags.
2967 *
2968 * This is a NOOP if the verifier isn't compiled in.
2969 *
2970 * @note We're temporarily keeping this until code is converted to new
2971 * disassembler style opcode handling.
2972 */
2973#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2974
2975
2976/** @def IEM_DECL_MSC_GUARD_IGNORE
2977 * Disables control flow guards checks inside a method and any function pointers
2978 * referenced by it. */
2979#if defined(_MSC_VER) && !defined(IN_RING0)
2980# define IEM_DECL_MSC_GUARD_IGNORE __declspec(guard(ignore))
2981#else
2982# define IEM_DECL_MSC_GUARD_IGNORE
2983#endif
2984
2985/** @def IEM_DECL_MSC_GUARD_NONE
2986 * Disables control flow guards checks inside a method and but continue track
2987 * function pointers references by it. */
2988#if defined(_MSC_VER) && !defined(IN_RING0)
2989# define IEM_DECL_MSC_GUARD_NONE __declspec(guard(nocf))
2990#else
2991# define IEM_DECL_MSC_GUARD_NONE
2992#endif
2993
2994
2995/** @def IEM_DECL_IMPL_TYPE
2996 * For typedef'ing an instruction implementation function.
2997 *
2998 * @param a_RetType The return type.
2999 * @param a_Name The name of the type.
3000 * @param a_ArgList The argument list enclosed in parentheses.
3001 */
3002
3003/** @def IEM_DECL_IMPL_DEF
3004 * For defining an instruction implementation function.
3005 *
3006 * @param a_RetType The return type.
3007 * @param a_Name The name of the type.
3008 * @param a_ArgList The argument list enclosed in parentheses.
3009 */
3010
3011#if defined(__GNUC__) && defined(RT_ARCH_X86)
3012# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3013 __attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
3014# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3015 __attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3016# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3017 __attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3018
3019#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3020# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3021 a_RetType (__fastcall a_Name) a_ArgList
3022# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3023 IEM_DECL_MSC_GUARD_IGNORE a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3024# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3025 IEM_DECL_MSC_GUARD_IGNORE a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3026
3027#elif __cplusplus >= 201700 /* P0012R1 support */
3028# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3029 a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
3030# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3031 IEM_DECL_MSC_GUARD_IGNORE DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3032# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3033 IEM_DECL_MSC_GUARD_IGNORE DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3034
3035#else
3036# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3037 a_RetType (VBOXCALL a_Name) a_ArgList
3038# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3039 IEM_DECL_MSC_GUARD_IGNORE DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3040# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3041 IEM_DECL_MSC_GUARD_IGNORE DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3042
3043#endif
3044
3045/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
3046RT_C_DECLS_BEGIN
3047extern uint8_t const g_afParity[256];
3048RT_C_DECLS_END
3049
3050
3051/** @name Arithmetic assignment operations on bytes (binary).
3052 * @{ */
3053typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
3054typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
3055FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
3056FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
3057FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
3058FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
3059FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
3060FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
3061FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
3062/** @} */
3063
3064/** @name Arithmetic assignment operations on words (binary).
3065 * @{ */
3066typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
3067typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
3068FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
3069FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
3070FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
3071FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
3072FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
3073FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
3074FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
3075/** @} */
3076
3077
3078/** @name Arithmetic assignment operations on double words (binary).
3079 * @{ */
3080typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
3081typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
3082FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
3083FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
3084FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
3085FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
3086FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
3087FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
3088FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
3089FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
3090FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
3091FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
3092/** @} */
3093
3094/** @name Arithmetic assignment operations on quad words (binary).
3095 * @{ */
3096typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
3097typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
3098FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
3099FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
3100FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
3101FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
3102FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
3103FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
3104FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
3105FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
3106FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
3107FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
3108/** @} */
3109
3110typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
3111typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
3112typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
3113typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
3114typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
3115typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
3116typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
3117typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
3118
3119/** @name Compare operations (thrown in with the binary ops).
3120 * @{ */
3121FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
3122FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
3123FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
3124FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
3125/** @} */
3126
3127/** @name Test operations (thrown in with the binary ops).
3128 * @{ */
3129FNIEMAIMPLBINROU8 iemAImpl_test_u8;
3130FNIEMAIMPLBINROU16 iemAImpl_test_u16;
3131FNIEMAIMPLBINROU32 iemAImpl_test_u32;
3132FNIEMAIMPLBINROU64 iemAImpl_test_u64;
3133/** @} */
3134
3135/** @name Bit operations operations (thrown in with the binary ops).
3136 * @{ */
3137FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
3138FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
3139FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
3140FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
3141FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
3142FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
3143FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
3144FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
3145FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
3146FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
3147FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
3148FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
3149/** @} */
3150
3151/** @name Arithmetic three operand operations on double words (binary).
3152 * @{ */
3153typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t *pEFlags));
3154typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
3155FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
3156FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
3157FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
3158/** @} */
3159
3160/** @name Arithmetic three operand operations on quad words (binary).
3161 * @{ */
3162typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t *pEFlags));
3163typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
3164FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
3165FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
3166FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
3167/** @} */
3168
3169/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
3170 * @{ */
3171typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
3172typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
3173FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
3174FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
3175FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
3176FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
3177FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
3178FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
3179/** @} */
3180
3181/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
3182 * @{ */
3183typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
3184typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
3185FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
3186FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
3187FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
3188FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
3189FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
3190FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
3191/** @} */
3192
3193/** @name MULX 32-bit and 64-bit.
3194 * @{ */
3195typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t *puDst1, uint32_t *puDst2, uint32_t uSrc1, uint32_t uSrc2));
3196typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
3197FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
3198
3199typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t *puDst1, uint64_t *puDst2, uint64_t uSrc1, uint64_t uSrc2));
3200typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
3201FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
3202/** @} */
3203
3204
3205/** @name Exchange memory with register operations.
3206 * @{ */
3207IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t *pu8Mem, uint8_t *pu8Reg));
3208IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t *pu16Mem, uint16_t *pu16Reg));
3209IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t *pu32Mem, uint32_t *pu32Reg));
3210IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t *pu64Mem, uint64_t *pu64Reg));
3211IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t *pu8Mem, uint8_t *pu8Reg));
3212IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t *pu16Mem, uint16_t *pu16Reg));
3213IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t *pu32Mem, uint32_t *pu32Reg));
3214IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t *pu64Mem, uint64_t *pu64Reg));
3215/** @} */
3216
3217/** @name Exchange and add operations.
3218 * @{ */
3219IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t *pu8Dst, uint8_t *pu8Reg, uint32_t *pEFlags));
3220IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t *pu16Dst, uint16_t *pu16Reg, uint32_t *pEFlags));
3221IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t *pu32Dst, uint32_t *pu32Reg, uint32_t *pEFlags));
3222IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t *pu64Dst, uint64_t *pu64Reg, uint32_t *pEFlags));
3223IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t *pu8Dst, uint8_t *pu8Reg, uint32_t *pEFlags));
3224IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t *pu16Dst, uint16_t *pu16Reg, uint32_t *pEFlags));
3225IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t *pu32Dst, uint32_t *pu32Reg, uint32_t *pEFlags));
3226IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t *pu64Dst, uint64_t *pu64Reg, uint32_t *pEFlags));
3227/** @} */
3228
3229/** @name Compare and exchange.
3230 * @{ */
3231IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3232IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3233IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3234IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3235IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3236IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3237#if ARCH_BITS == 32
3238IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags));
3239IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags));
3240#else
3241IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3242IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3243#endif
3244IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3245 uint32_t *pEFlags));
3246IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3247 uint32_t *pEFlags));
3248IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3249 uint32_t *pEFlags));
3250IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3251 uint32_t *pEFlags));
3252#ifndef RT_ARCH_ARM64
3253IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3254 PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3255#endif
3256/** @} */
3257
3258/** @name Memory ordering
3259 * @{ */
3260typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3261typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3262IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3263IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3264IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3265#ifndef RT_ARCH_ARM64
3266IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3267#endif
3268/** @} */
3269
3270/** @name Double precision shifts
3271 * @{ */
3272typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t *pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t *pEFlags));
3273typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3274typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t *pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t *pEFlags));
3275typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3276typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t *pEFlags));
3277typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3278FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3279FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3280FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3281FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3282FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3283FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3284/** @} */
3285
3286
3287/** @name Bit search operations (thrown in with the binary ops).
3288 * @{ */
3289FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3290FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3291FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3292FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3293FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3294FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3295FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3296FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3297FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3298FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3299FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3300FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3301FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3302FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3303FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3304/** @} */
3305
3306/** @name Signed multiplication operations (thrown in with the binary ops).
3307 * @{ */
3308FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3309FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3310FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3311/** @} */
3312
3313/** @name Arithmetic assignment operations on bytes (unary).
3314 * @{ */
3315typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t *pu8Dst, uint32_t *pEFlags));
3316typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3317FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3318FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3319FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3320FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3321/** @} */
3322
3323/** @name Arithmetic assignment operations on words (unary).
3324 * @{ */
3325typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t *pu16Dst, uint32_t *pEFlags));
3326typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3327FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3328FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3329FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3330FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3331/** @} */
3332
3333/** @name Arithmetic assignment operations on double words (unary).
3334 * @{ */
3335typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t *pu32Dst, uint32_t *pEFlags));
3336typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3337FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3338FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3339FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3340FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3341/** @} */
3342
3343/** @name Arithmetic assignment operations on quad words (unary).
3344 * @{ */
3345typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t *pu64Dst, uint32_t *pEFlags));
3346typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3347FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3348FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3349FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3350FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3351/** @} */
3352
3353
3354/** @name Shift operations on bytes (Group 2).
3355 * @{ */
3356typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3357typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3358FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3359FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3360FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3361FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3362FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3363FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3364FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3365/** @} */
3366
3367/** @name Shift operations on words (Group 2).
3368 * @{ */
3369typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3370typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3371FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3372FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3373FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3374FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3375FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3376FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3377FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3378/** @} */
3379
3380/** @name Shift operations on double words (Group 2).
3381 * @{ */
3382typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3383typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3384FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3385FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3386FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3387FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3388FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3389FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3390FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3391/** @} */
3392
3393/** @name Shift operations on words (Group 2).
3394 * @{ */
3395typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3396typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3397FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3398FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3399FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3400FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3401FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3402FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3403FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3404/** @} */
3405
3406/** @name Multiplication and division operations.
3407 * @{ */
3408typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU8,(uint16_t *pu16AX, uint8_t u8FactorDivisor, uint32_t fEFlags));
3409typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3410FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3411FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3412FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3413FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3414
3415typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU16,(uint16_t *pu16AX, uint16_t *pu16DX, uint16_t u16FactorDivisor, uint32_t fEFlags));
3416typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3417FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3418FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3419FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3420FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3421
3422typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU32,(uint32_t *pu32EAX, uint32_t *pu32EDX, uint32_t u32FactorDivisor, uint32_t fEFlags));
3423typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3424FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3425FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3426FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3427FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3428
3429typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64FactorDivisor, uint32_t fEFlags));
3430typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3431FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3432FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3433FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3434FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3435/** @} */
3436
3437/** @name Byte Swap.
3438 * @{ */
3439IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t *pu32Dst)); /* Yes, 32-bit register access. */
3440IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3441IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3442/** @} */
3443
3444/** @name Misc.
3445 * @{ */
3446FNIEMAIMPLBINU16 iemAImpl_arpl;
3447/** @} */
3448
3449/** @name RDRAND and RDSEED
3450 * @{ */
3451typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t *puDst, uint32_t *pEFlags));
3452typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t *puDst, uint32_t *pEFlags));
3453typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t *puDst, uint32_t *pEFlags));
3454typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3455typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3456typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3457
3458FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3459FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3460FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3461FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3462FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3463FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3464/** @} */
3465
3466/** @name ADOX and ADCX
3467 * @{ */
3468FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3469FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3470FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3471FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3472/** @} */
3473
3474/** @name FPU operations taking a 32-bit float argument
3475 * @{ */
3476typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3477 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3478typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3479
3480typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3481 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3482typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3483
3484FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3485FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3486FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3487FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3488FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3489FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3490FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3491
3492IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3493IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3494 PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3495/** @} */
3496
3497/** @name FPU operations taking a 64-bit float argument
3498 * @{ */
3499typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3500 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3501typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3502
3503typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3504 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3505typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3506
3507FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3508FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3509FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3510FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3511FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3512FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3513FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3514
3515IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3516IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3517 PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3518/** @} */
3519
3520/** @name FPU operations taking a 80-bit float argument
3521 * @{ */
3522typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3523 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3524typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3525FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3526FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3527FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3528FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3529FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3530FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3531FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3532FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3533FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3534
3535FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3536FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3537FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3538
3539typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3540 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3541typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3542FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3543FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3544
3545typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3546 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3547typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3548FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3549FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3550
3551typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3552typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3553FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3554FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3555FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3556FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3557FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3558FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3559FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3560
3561typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3562typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3563FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3564FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3565
3566typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3567typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3568FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3569FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3570FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3571FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3572FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3573FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3574FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3575
3576typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3577 PCRTFLOAT80U pr80Val));
3578typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3579FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3580FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3581FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3582
3583IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3584IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3585 PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3586
3587IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3588IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3589 PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3590
3591/** @} */
3592
3593/** @name FPU operations taking a 16-bit signed integer argument
3594 * @{ */
3595typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3596 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3597typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3598typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3599 int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3600typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3601
3602FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3603FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3604FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3605FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3606FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3607FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3608
3609typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3610 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3611typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3612FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3613
3614IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3615FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3616FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3617/** @} */
3618
3619/** @name FPU operations taking a 32-bit signed integer argument
3620 * @{ */
3621typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3622 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3623typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3624typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3625 int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3626typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3627
3628FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3629FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3630FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3631FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3632FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3633FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3634
3635typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3636 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3637typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3638FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3639
3640IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3641FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3642FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3643/** @} */
3644
3645/** @name FPU operations taking a 64-bit signed integer argument
3646 * @{ */
3647typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3648 int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3649typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3650
3651IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3652FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3653FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3654/** @} */
3655
3656
3657/** Temporary type representing a 256-bit vector register. */
3658typedef struct { uint64_t au64[4]; } IEMVMM256;
3659/** Temporary type pointing to a 256-bit vector register. */
3660typedef IEMVMM256 *PIEMVMM256;
3661/** Temporary type pointing to a const 256-bit vector register. */
3662typedef IEMVMM256 *PCIEMVMM256;
3663
3664
3665/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3666 * @{ */
3667typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t *puDst, uint64_t const *puSrc));
3668typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3669typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
3670typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3671typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc));
3672typedef FNIEMAIMPLMEDIAF2U256 *PFNIEMAIMPLMEDIAF2U256;
3673typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3674typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3675typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3676typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3677typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t *puDst, uint64_t const *puSrc));
3678typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3679typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3680typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3681typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3682typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3683typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3684typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3685typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3686typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3687FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3688FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3689FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3690FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3691FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3692FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3693FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3694FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3695FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3696FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3697FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3698FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3699FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3700FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3701FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3702FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3703FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3704FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3705FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3706FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3707FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3708FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3709FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3710FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3711FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3712FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3713FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3714FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3715FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3716FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3717FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3718FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3719FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3720FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3721FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3722FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3723FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3724FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3725FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3726
3727FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3728FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3729FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3730FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3731FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3732FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3733FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3734FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3735FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3736FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3737FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3738FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3739FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3740FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3741FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3742FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3743FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3744FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3745FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3746FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3747FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3748FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3749FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3750FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3751FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3752FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3753FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3754FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3755FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3756FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3757FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3758FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3759FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3760FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3761FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3762FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3763FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3764FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3765FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3766FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3767FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3768FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3769FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3770FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3771FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3772FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3773FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3774FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3775FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3776FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3777FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3778FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3779FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3780FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3781FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3782FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3783FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3784FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3785
3786FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3787FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3788FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3789FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3790FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3791FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3792FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3793FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3794FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3795FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3796FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3797FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3798FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3799FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3800FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3801FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3802FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3803FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3804FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3805FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3806FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3807FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3808FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3809FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3810FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3811FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3812FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3813FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3814FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3815FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3816FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3817FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3818FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3819FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3820FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3821FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3822FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3823FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3824FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3825FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3826FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3827FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3828FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3829FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3830FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3831FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3832FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3833FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3834FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3835FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3836FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3837FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3838FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3839FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3840FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3841FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3842FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3843FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3844FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3845FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3846FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3847FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3848FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3849FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3850FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3851FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3852FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3853FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3854FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3855FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3856FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3857FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3858FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3859FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3860
3861FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3862FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3863FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3864FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3865
3866FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3867FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3868FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3869FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3870FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3871FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3872FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3873FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3874FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3875FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3876FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3877FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3878FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3879FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3880FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3881FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3882FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3883FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3884FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3885FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3886FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3887FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3888FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3889FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3890FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3891FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3892FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3893FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3894FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3895FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3896FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3897FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3898FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3899FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3900FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3901FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3902FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3903FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3904FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3905FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3906FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3907FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3908FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3909FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3910FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3911FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3912FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3913FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3914FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3915FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3916FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3917FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3918FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3919FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3920FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3921FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3922FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3923FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3924FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3925FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3926FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3927FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3928FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3929FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3930FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3931FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3932FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3933FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3934FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3935FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3936FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3937FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3938FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3939FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3940FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermps_u256, iemAImpl_vpermps_u256_fallback;
3941FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermd_u256, iemAImpl_vpermd_u256_fallback;
3942
3943FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3944FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3945FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3946/** @} */
3947
3948/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3949 * @{ */
3950FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3951FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3952FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3953 iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3954 iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3955 iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3956 iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3957 iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3958 iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3959 iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3960
3961FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3962 iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3963 iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3964 iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3965 iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3966 iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3967 iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3968 iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3969/** @} */
3970
3971/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3972 * @{ */
3973FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3974FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3975FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3976 iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3977 iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3978 iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3979FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3980 iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3981 iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3982 iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3983/** @} */
3984
3985/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3986 * @{ */
3987typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3988typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3989typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3990typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3991IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t *puDst, uint64_t const *puSrc, uint8_t bEvil));
3992FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3993#ifndef IEM_WITHOUT_ASSEMBLY
3994FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3995#endif
3996FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3997/** @} */
3998
3999/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
4000 * @{ */
4001typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
4002typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
4003typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
4004typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
4005typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
4006typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
4007FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
4008FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
4009FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
4010FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
4011FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
4012FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
4013FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
4014/** @} */
4015
4016/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
4017 * @{ */
4018IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t *puMem, uint64_t const *puSrc, uint64_t const *puMsk));
4019IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
4020IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t *pu64Dst, uint64_t const *puSrc));
4021IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
4022#ifndef IEM_WITHOUT_ASSEMBLY
4023IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4024#endif
4025IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4026/** @} */
4027
4028/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
4029 * @{ */
4030typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
4031typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
4032typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
4033typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
4034typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
4035typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
4036
4037FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
4038FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
4039FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
4040FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
4041FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
4042FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
4043
4044FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
4045FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
4046FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
4047FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
4048FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
4049FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
4050
4051FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
4052FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
4053FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
4054FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
4055FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
4056FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
4057/** @} */
4058
4059
4060/** @name Media (SSE/MMX/AVX) operation: Sort this later
4061 * @{ */
4062IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4063IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4064IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4065IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4066IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4067
4068IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4069IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4070IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4071IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4072IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4073
4074IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4075IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4076IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4077IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4078IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4079
4080IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4081IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4082IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4083IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4084IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4085
4086IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4087IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4088IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4089IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4090IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4091
4092IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4093IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4094IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4095IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4096IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4097
4098IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4099IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4100IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4101IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4102IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4103
4104IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4105IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4106IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4107IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4108IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4109
4110IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4111IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4112IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4113IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4114IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4115
4116IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4117IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4118IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4119IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4120IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4121
4122IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4123IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4124IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4125IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4126IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4127
4128IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4129IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4130IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4131IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4132IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4133
4134IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4135IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4136IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4137IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4138IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4139
4140IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4141IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4142IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4143IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4144IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4145
4146IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4147IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4148
4149IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4150IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4151IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4152IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4153IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4154
4155IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4156IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4157IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4158IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4159IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4160
4161
4162typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4163typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
4164typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
4165typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
4166typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4167typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
4168typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4169typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
4170
4171FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
4172FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
4173FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
4174FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
4175
4176FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
4177FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
4178FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
4179FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
4180FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
4181
4182FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
4183FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
4184FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
4185FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
4186FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
4187FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
4188FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
4189
4190FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
4191FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
4192FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
4193FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
4194FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
4195
4196FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
4197FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
4198FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
4199FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
4200FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
4201
4202FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
4203
4204FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
4205
4206FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
4207FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
4208FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
4209FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
4210FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
4211FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
4212IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4213IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4214
4215FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermq_u256, iemAImpl_vpermq_u256_fallback;
4216FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermpd_u256, iemAImpl_vpermpd_u256_fallback;
4217
4218typedef struct IEMPCMPISTRXSRC
4219{
4220 RTUINT128U uSrc1;
4221 RTUINT128U uSrc2;
4222} IEMPCMPISTRXSRC;
4223typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
4224typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
4225
4226typedef struct IEMPCMPESTRXSRC
4227{
4228 RTUINT128U uSrc1;
4229 RTUINT128U uSrc2;
4230 uint64_t u64Rax;
4231 uint64_t u64Rdx;
4232} IEMPCMPESTRXSRC;
4233typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
4234typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
4235
4236typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
4237typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
4238typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t *pu32Ecx, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4239typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
4240
4241typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
4242typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
4243typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4244typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4245
4246FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4247FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4248FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4249FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4250FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_vpcmpistri_u128, iemAImpl_vpcmpistri_u128_fallback;
4251FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_vpcmpestri_u128, iemAImpl_vpcmpestri_u128_fallback;
4252FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_vpcmpistrm_u128, iemAImpl_vpcmpistrm_u128_fallback;
4253FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_vpcmpestrm_u128, iemAImpl_vpcmpestrm_u128_fallback;
4254
4255
4256FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4257FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4258
4259FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4260FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4261FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4262
4263FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4264FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4265FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4266FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4267FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4268FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4269IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4270IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4271IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4272IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4273
4274FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4275FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4276FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4277FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4278
4279FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4280FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4281FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4282FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4283FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4284FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4285IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4286IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4287IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4288IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4289
4290FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4291FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4292FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4293FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4294
4295FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4296FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4297FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4298FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4299
4300FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4301FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4302FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4303FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4304FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4305FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4306FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4307FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4308FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4309FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4310/** @} */
4311
4312/** @name Media Odds and Ends
4313 * @{ */
4314typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4315typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4316typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4317typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4318FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4319FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4320FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4321FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4322
4323typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4324typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4325typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4326typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4327FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4328FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4329FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4330FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4331FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4332FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4333
4334typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */
4335typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4336typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */
4337typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4338typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */
4339typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4340typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */
4341typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4342typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R32,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT32U pr32Src));
4343typedef FNIEMAIMPLSSEF2I32R32 *PFNIEMAIMPLSSEF2I32R32;
4344typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R32,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT32U pr32Src));
4345typedef FNIEMAIMPLSSEF2I64R32 *PFNIEMAIMPLSSEF2I64R32;
4346typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R64,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT64U pr64Src));
4347typedef FNIEMAIMPLSSEF2I32R64 *PFNIEMAIMPLSSEF2I32R64;
4348typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R64,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT64U pr64Src));
4349typedef FNIEMAIMPLSSEF2I64R64 *PFNIEMAIMPLSSEF2I64R64;
4350
4351FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4352FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4353
4354FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4355FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4356
4357FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4358FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4359
4360FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4361FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4362
4363FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttss2si_i32_r32, iemAImpl_vcvttss2si_i32_r32_fallback;
4364FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttss2si_i64_r32, iemAImpl_vcvttss2si_i64_r32_fallback;
4365FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtss2si_i32_r32, iemAImpl_vcvtss2si_i32_r32_fallback;
4366FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtss2si_i64_r32, iemAImpl_vcvtss2si_i64_r32_fallback;
4367
4368FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttss2si_i32_r64, iemAImpl_vcvttss2si_i32_r64_fallback;
4369FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttss2si_i64_r64, iemAImpl_vcvttss2si_i64_r64_fallback;
4370FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtss2si_i32_r64, iemAImpl_vcvtss2si_i32_r64_fallback;
4371FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtss2si_i64_r64, iemAImpl_vcvtss2si_i64_r64_fallback;
4372
4373FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttsd2si_i32_r32, iemAImpl_vcvttsd2si_i32_r32_fallback;
4374FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttsd2si_i64_r32, iemAImpl_vcvttsd2si_i64_r32_fallback;
4375FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtsd2si_i32_r32, iemAImpl_vcvtsd2si_i32_r32_fallback;
4376FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtsd2si_i64_r32, iemAImpl_vcvtsd2si_i64_r32_fallback;
4377
4378FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttsd2si_i32_r64, iemAImpl_vcvttsd2si_i32_r64_fallback;
4379FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttsd2si_i64_r64, iemAImpl_vcvttsd2si_i64_r64_fallback;
4380FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtsd2si_i32_r64, iemAImpl_vcvtsd2si_i32_r64_fallback;
4381FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtsd2si_i64_r64, iemAImpl_vcvtsd2si_i64_r64_fallback;
4382
4383typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4384typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4385typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4386typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4387
4388FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4389FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4390
4391typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI32,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int32_t *pi32Src));
4392typedef FNIEMAIMPLAVXF3XMMI32 *PFNIEMAIMPLAVXF3XMMI32;
4393typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI64,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int64_t *pi64Src));
4394typedef FNIEMAIMPLAVXF3XMMI64 *PFNIEMAIMPLAVXF3XMMI64;
4395
4396FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2ss_u128_i32, iemAImpl_vcvtsi2ss_u128_i32_fallback;
4397FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2ss_u128_i64, iemAImpl_vcvtsi2ss_u128_i64_fallback;
4398
4399
4400typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4401typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4402typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4403typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4404
4405FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4406FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4407
4408FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2sd_u128_i32, iemAImpl_vcvtsi2sd_u128_i32_fallback;
4409FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2sd_u128_i64, iemAImpl_vcvtsi2sd_u128_i64_fallback;
4410
4411IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t *pu64Src)); /* Actually two single precision floating point values. */
4412IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t *pu64Src)); /* Actually two single precision floating point values. */
4413IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4414IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4415
4416
4417IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t *pu64Src)); /* Actually two single precision floating point values. */
4418IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t *pu64Src)); /* Actually two single precision floating point values. */
4419IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4420IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4421
4422
4423typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4424typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4425
4426typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4427typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4428
4429FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4430FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4431
4432FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4433FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4434
4435FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4436FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4437
4438FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4439FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4440
4441
4442typedef struct IEMMEDIAF2XMMSRC
4443{
4444 X86XMMREG uSrc1;
4445 X86XMMREG uSrc2;
4446} IEMMEDIAF2XMMSRC;
4447typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4448typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4449
4450
4451typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4452typedef FNIEMAIMPLMEDIAF3XMMIMM8 *PFNIEMAIMPLMEDIAF3XMMIMM8;
4453
4454
4455typedef struct IEMMEDIAF2YMMSRC
4456{
4457 X86YMMREG uSrc1;
4458 X86YMMREG uSrc2;
4459} IEMMEDIAF2YMMSRC;
4460typedef IEMMEDIAF2YMMSRC *PIEMMEDIAF2YMMSRC;
4461typedef const IEMMEDIAF2YMMSRC *PCIEMMEDIAF2YMMSRC;
4462
4463
4464typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3YMMIMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCIEMMEDIAF2YMMSRC puSrc, uint8_t bEvil));
4465typedef FNIEMAIMPLMEDIAF3YMMIMM8 *PFNIEMAIMPLMEDIAF3YMMIMM8;
4466
4467
4468FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpps_u128;
4469FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmppd_u128;
4470FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpss_u128;
4471FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpsd_u128;
4472
4473FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpps_u128, iemAImpl_vcmpps_u128_fallback;
4474FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmppd_u128, iemAImpl_vcmppd_u128_fallback;
4475FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpss_u128, iemAImpl_vcmpss_u128_fallback;
4476FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpsd_u128, iemAImpl_vcmpsd_u128_fallback;
4477
4478FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmpps_u256, iemAImpl_vcmpps_u256_fallback;
4479FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmppd_u256, iemAImpl_vcmppd_u256_fallback;
4480
4481FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundss_u128;
4482FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundsd_u128;
4483
4484FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4485FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4486
4487
4488typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128IMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, uint8_t bEvil));
4489typedef FNIEMAIMPLMEDIAF2U128IMM8 *PFNIEMAIMPLMEDIAF2U128IMM8;
4490
4491
4492typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256IMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc, uint8_t bEvil));
4493typedef FNIEMAIMPLMEDIAF2U256IMM8 *PFNIEMAIMPLMEDIAF2U256IMM8;
4494
4495
4496FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4497FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4498
4499FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundps_u128, iemAImpl_vroundps_u128_fallback;
4500FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundpd_u128, iemAImpl_vroundpd_u128_fallback;
4501
4502FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundps_u256, iemAImpl_vroundps_u256_fallback;
4503FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundpd_u256, iemAImpl_vroundpd_u256_fallback;
4504
4505FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundss_u128, iemAImpl_vroundss_u128_fallback;
4506FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundsd_u128, iemAImpl_vroundsd_u128_fallback;
4507
4508FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdpps_u128, iemAImpl_vdpps_u128_fallback;
4509FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdppd_u128, iemAImpl_vdppd_u128_fallback;
4510
4511FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vdpps_u256, iemAImpl_vdpps_u256_fallback;
4512
4513
4514typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4515typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4516
4517FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4518FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4519
4520typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4521typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4522
4523FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4524FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4525
4526typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4527typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4528
4529FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4530FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4531
4532/** @} */
4533
4534
4535/** @name Function tables.
4536 * @{
4537 */
4538
4539/**
4540 * Function table for a binary operator providing implementation based on
4541 * operand size.
4542 */
4543typedef struct IEMOPBINSIZES
4544{
4545 PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4546 PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4547 PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4548 PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4549} IEMOPBINSIZES;
4550/** Pointer to a binary operator function table. */
4551typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4552
4553
4554/**
4555 * Function table for a unary operator providing implementation based on
4556 * operand size.
4557 */
4558typedef struct IEMOPUNARYSIZES
4559{
4560 PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4561 PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4562 PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4563 PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4564} IEMOPUNARYSIZES;
4565/** Pointer to a unary operator function table. */
4566typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4567
4568
4569/**
4570 * Function table for a shift operator providing implementation based on
4571 * operand size.
4572 */
4573typedef struct IEMOPSHIFTSIZES
4574{
4575 PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4576 PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4577 PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4578 PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4579} IEMOPSHIFTSIZES;
4580/** Pointer to a shift operator function table. */
4581typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4582
4583
4584/**
4585 * Function table for a multiplication or division operation.
4586 */
4587typedef struct IEMOPMULDIVSIZES
4588{
4589 PFNIEMAIMPLMULDIVU8 pfnU8;
4590 PFNIEMAIMPLMULDIVU16 pfnU16;
4591 PFNIEMAIMPLMULDIVU32 pfnU32;
4592 PFNIEMAIMPLMULDIVU64 pfnU64;
4593} IEMOPMULDIVSIZES;
4594/** Pointer to a multiplication or division operation function table. */
4595typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4596
4597
4598/**
4599 * Function table for a double precision shift operator providing implementation
4600 * based on operand size.
4601 */
4602typedef struct IEMOPSHIFTDBLSIZES
4603{
4604 PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4605 PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4606 PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4607} IEMOPSHIFTDBLSIZES;
4608/** Pointer to a double precision shift function table. */
4609typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4610
4611
4612/**
4613 * Function table for media instruction taking two full sized media source
4614 * registers and one full sized destination register (AVX).
4615 */
4616typedef struct IEMOPMEDIAF3
4617{
4618 PFNIEMAIMPLMEDIAF3U128 pfnU128;
4619 PFNIEMAIMPLMEDIAF3U256 pfnU256;
4620} IEMOPMEDIAF3;
4621/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4622typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4623
4624/** @def IEMOPMEDIAF3_INIT_VARS_EX
4625 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4626 * given functions as initializers. For use in AVX functions where a pair of
4627 * functions are only used once and the function table need not be public. */
4628#ifndef TST_IEM_CHECK_MC
4629# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4630# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4631 static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4632 static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4633# else
4634# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4635 static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4636# endif
4637#else
4638# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4639#endif
4640/** @def IEMOPMEDIAF3_INIT_VARS
4641 * Generate AVX function tables for the @a a_InstrNm instruction.
4642 * @sa IEMOPMEDIAF3_INIT_VARS_EX */
4643#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4644 IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4645 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4646
4647
4648/**
4649 * Function table for media instruction taking one full sized media source
4650 * registers and one full sized destination register (AVX).
4651 */
4652typedef struct IEMOPMEDIAF2
4653{
4654 PFNIEMAIMPLMEDIAF2U128 pfnU128;
4655 PFNIEMAIMPLMEDIAF2U256 pfnU256;
4656} IEMOPMEDIAF2;
4657/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4658typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
4659
4660/** @def IEMOPMEDIAF2_INIT_VARS_EX
4661 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4662 * given functions as initializers. For use in AVX functions where a pair of
4663 * functions are only used once and the function table need not be public. */
4664#ifndef TST_IEM_CHECK_MC
4665# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4666# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4667 static IEMOPMEDIAF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4668 static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4669# else
4670# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4671 static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4672# endif
4673#else
4674# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4675#endif
4676/** @def IEMOPMEDIAF2_INIT_VARS
4677 * Generate AVX function tables for the @a a_InstrNm instruction.
4678 * @sa IEMOPMEDIAF2_INIT_VARS_EX */
4679#define IEMOPMEDIAF2_INIT_VARS(a_InstrNm) \
4680 IEMOPMEDIAF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4681 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4682
4683
4684/**
4685 * Function table for media instruction taking two full sized media source
4686 * registers and one full sized destination register, but no additional state
4687 * (AVX).
4688 */
4689typedef struct IEMOPMEDIAOPTF3
4690{
4691 PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4692 PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4693} IEMOPMEDIAOPTF3;
4694/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4695typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4696
4697/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4698 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4699 * given functions as initializers. For use in AVX functions where a pair of
4700 * functions are only used once and the function table need not be public. */
4701#ifndef TST_IEM_CHECK_MC
4702# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4703# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4704 static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4705 static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4706# else
4707# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4708 static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4709# endif
4710#else
4711# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4712#endif
4713/** @def IEMOPMEDIAOPTF3_INIT_VARS
4714 * Generate AVX function tables for the @a a_InstrNm instruction.
4715 * @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4716#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4717 IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4718 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4719
4720/**
4721 * Function table for media instruction taking one full sized media source
4722 * registers and one full sized destination register, but no additional state
4723 * (AVX).
4724 */
4725typedef struct IEMOPMEDIAOPTF2
4726{
4727 PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4728 PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4729} IEMOPMEDIAOPTF2;
4730/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4731typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4732
4733/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4734 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4735 * given functions as initializers. For use in AVX functions where a pair of
4736 * functions are only used once and the function table need not be public. */
4737#ifndef TST_IEM_CHECK_MC
4738# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4739# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4740 static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4741 static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4742# else
4743# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4744 static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4745# endif
4746#else
4747# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4748#endif
4749/** @def IEMOPMEDIAOPTF2_INIT_VARS
4750 * Generate AVX function tables for the @a a_InstrNm instruction.
4751 * @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4752#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4753 IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4754 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4755
4756
4757/**
4758 * Function table for media instruction taking one full sized media source
4759 * register and one full sized destination register and an 8-bit immediate (AVX).
4760 */
4761typedef struct IEMOPMEDIAF2IMM8
4762{
4763 PFNIEMAIMPLMEDIAF2U128IMM8 pfnU128;
4764 PFNIEMAIMPLMEDIAF2U256IMM8 pfnU256;
4765} IEMOPMEDIAF2IMM8;
4766/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4767typedef IEMOPMEDIAF2IMM8 const *PCIEMOPMEDIAF2IMM8;
4768
4769/** @def IEMOPMEDIAF2IMM8_INIT_VARS_EX
4770 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4771 * given functions as initializers. For use in AVX functions where a pair of
4772 * functions are only used once and the function table need not be public. */
4773#ifndef TST_IEM_CHECK_MC
4774# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4775# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4776 static IEMOPMEDIAF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4777 static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4778# else
4779# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4780 static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4781# endif
4782#else
4783# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4784#endif
4785/** @def IEMOPMEDIAF2IMM8_INIT_VARS
4786 * Generate AVX function tables for the @a a_InstrNm instruction.
4787 * @sa IEMOPMEDIAF2IMM8_INIT_VARS_EX */
4788#define IEMOPMEDIAF2IMM8_INIT_VARS(a_InstrNm) \
4789 IEMOPMEDIAF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4790 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4791
4792
4793/**
4794 * Function table for media instruction taking one full sized media source
4795 * register and one full sized destination register and an 8-bit immediate, but no additional state
4796 * (AVX).
4797 */
4798typedef struct IEMOPMEDIAOPTF2IMM8
4799{
4800 PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4801 PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4802} IEMOPMEDIAOPTF2IMM8;
4803/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4804typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4805
4806/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4807 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4808 * given functions as initializers. For use in AVX functions where a pair of
4809 * functions are only used once and the function table need not be public. */
4810#ifndef TST_IEM_CHECK_MC
4811# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4812# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4813 static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4814 static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4815# else
4816# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4817 static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4818# endif
4819#else
4820# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4821#endif
4822/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4823 * Generate AVX function tables for the @a a_InstrNm instruction.
4824 * @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4825#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4826 IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4827 RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4828
4829/**
4830 * Function table for media instruction taking two full sized media source
4831 * registers and one full sized destination register and an 8-bit immediate, but no additional state
4832 * (AVX).
4833 */
4834typedef struct IEMOPMEDIAOPTF3IMM8
4835{
4836 PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4837 PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4838} IEMOPMEDIAOPTF3IMM8;
4839/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4840typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4841
4842/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4843 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4844 * given functions as initializers. For use in AVX functions where a pair of
4845 * functions are only used once and the function table need not be public. */
4846#ifndef TST_IEM_CHECK_MC
4847# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4848# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4849 static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4850 static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4851# else
4852# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4853 static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4854# endif
4855#else
4856# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4857#endif
4858/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4859 * Generate AVX function tables for the @a a_InstrNm instruction.
4860 * @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4861#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4862 IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4863 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4864/** @} */
4865
4866
4867/**
4868 * Function table for blend type instruction taking three full sized media source
4869 * registers and one full sized destination register, but no additional state
4870 * (AVX).
4871 */
4872typedef struct IEMOPBLENDOP
4873{
4874 PFNIEMAIMPLAVXBLENDU128 pfnU128;
4875 PFNIEMAIMPLAVXBLENDU256 pfnU256;
4876} IEMOPBLENDOP;
4877/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4878typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4879
4880/** @def IEMOPBLENDOP_INIT_VARS_EX
4881 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4882 * given functions as initializers. For use in AVX functions where a pair of
4883 * functions are only used once and the function table need not be public. */
4884#ifndef TST_IEM_CHECK_MC
4885# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4886# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4887 static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4888 static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4889# else
4890# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4891 static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4892# endif
4893#else
4894# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4895#endif
4896/** @def IEMOPBLENDOP_INIT_VARS
4897 * Generate AVX function tables for the @a a_InstrNm instruction.
4898 * @sa IEMOPBLENDOP_INIT_VARS_EX */
4899#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4900 IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4901 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4902
4903
4904/** @name SSE/AVX single/double precision floating point operations.
4905 * @{ */
4906typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4907typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4908typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4909typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4910typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4911typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4912
4913typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4914typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4915typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4916typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4917typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4918typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4919
4920typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4921typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4922
4923FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4924FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4925FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4926FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4927FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4928FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4929FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4930FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4931FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4932FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4933FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4934FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4935FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4936FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4937FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4938FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4939FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4940FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4941FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4942FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4943FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4944FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4945
4946FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4947IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4948
4949FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4950FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4951FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4952FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4953FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4954FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4955
4956FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4957FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4958FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4959FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4960FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4961FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4962FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4963FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4964FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4965FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4966FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4967FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4968FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4969FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4970FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4971FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4972FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4973FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4974
4975FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4976FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4977FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4978FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4979FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4980FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4981FNIEMAIMPLMEDIAF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4982FNIEMAIMPLMEDIAF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4983FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4984FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4985FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4986FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4987FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4988FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4989FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4990FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4991FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4992FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4993FNIEMAIMPLMEDIAF2U128 iemAImpl_vrsqrtps_u128, iemAImpl_vrsqrtps_u128_fallback;
4994FNIEMAIMPLMEDIAF2U128 iemAImpl_vrcpps_u128, iemAImpl_vrcpps_u128_fallback;
4995FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4996FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4997FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtdq2ps_u128, iemAImpl_vcvtdq2ps_u128_fallback;
4998FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtps2dq_u128, iemAImpl_vcvtps2dq_u128_fallback;
4999FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvttps2dq_u128, iemAImpl_vcvttps2dq_u128_fallback;
5000IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5001IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5002IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5003IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5004IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5005IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5006
5007
5008FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
5009FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
5010FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
5011FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
5012FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
5013FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
5014FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
5015FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
5016FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
5017FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
5018FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
5019FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
5020FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
5021FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
5022FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrsqrtss_u128_r32, iemAImpl_vrsqrtss_u128_r32_fallback;
5023FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrcpss_u128_r32, iemAImpl_vrcpss_u128_r32_fallback;
5024FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vcvtss2sd_u128_r32, iemAImpl_vcvtss2sd_u128_r32_fallback;
5025FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vcvtsd2ss_u128_r64, iemAImpl_vcvtsd2ss_u128_r64_fallback;
5026
5027
5028FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
5029FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
5030FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
5031FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
5032FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
5033FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
5034FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
5035FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
5036FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
5037FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
5038FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
5039FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
5040FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
5041FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
5042FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
5043FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
5044FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubps_u256, iemAImpl_vaddsubps_u256_fallback;
5045FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubpd_u256, iemAImpl_vaddsubpd_u256_fallback;
5046FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtps_u256, iemAImpl_vsqrtps_u256_fallback;
5047FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtpd_u256, iemAImpl_vsqrtpd_u256_fallback;
5048FNIEMAIMPLMEDIAF2U256 iemAImpl_vrsqrtps_u256, iemAImpl_vrsqrtps_u256_fallback;
5049FNIEMAIMPLMEDIAF2U256 iemAImpl_vrcpps_u256, iemAImpl_vrcpps_u256_fallback;
5050FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtdq2ps_u256, iemAImpl_vcvtdq2ps_u256_fallback;
5051FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtps2dq_u256, iemAImpl_vcvtps2dq_u256_fallback;
5052FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvttps2dq_u256, iemAImpl_vcvttps2dq_u256_fallback;
5053IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5054IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5055IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5056IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5057IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5058IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5059/** @} */
5060
5061/** @name C instruction implementations for anything slightly complicated.
5062 * @{ */
5063
5064/**
5065 * For typedef'ing or declaring a C instruction implementation function taking
5066 * no extra arguments.
5067 *
5068 * @param a_Name The name of the type.
5069 */
5070# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
5071 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5072/**
5073 * For defining a C instruction implementation function taking no extra
5074 * arguments.
5075 *
5076 * @param a_Name The name of the function
5077 */
5078# define IEM_CIMPL_DEF_0(a_Name) \
5079 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5080/**
5081 * Prototype version of IEM_CIMPL_DEF_0.
5082 */
5083# define IEM_CIMPL_PROTO_0(a_Name) \
5084 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5085/**
5086 * For calling a C instruction implementation function taking no extra
5087 * arguments.
5088 *
5089 * This special call macro adds default arguments to the call and allow us to
5090 * change these later.
5091 *
5092 * @param a_fn The name of the function.
5093 */
5094# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
5095
5096/** Type for a C instruction implementation function taking no extra
5097 * arguments. */
5098typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
5099/** Function pointer type for a C instruction implementation function taking
5100 * no extra arguments. */
5101typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
5102
5103/**
5104 * For typedef'ing or declaring a C instruction implementation function taking
5105 * one extra argument.
5106 *
5107 * @param a_Name The name of the type.
5108 * @param a_Type0 The argument type.
5109 * @param a_Arg0 The argument name.
5110 */
5111# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
5112 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5113/**
5114 * For defining a C instruction implementation function taking one extra
5115 * argument.
5116 *
5117 * @param a_Name The name of the function
5118 * @param a_Type0 The argument type.
5119 * @param a_Arg0 The argument name.
5120 */
5121# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
5122 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5123/**
5124 * Prototype version of IEM_CIMPL_DEF_1.
5125 */
5126# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
5127 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5128/**
5129 * For calling a C instruction implementation function taking one extra
5130 * argument.
5131 *
5132 * This special call macro adds default arguments to the call and allow us to
5133 * change these later.
5134 *
5135 * @param a_fn The name of the function.
5136 * @param a0 The name of the 1st argument.
5137 */
5138# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
5139
5140/**
5141 * For typedef'ing or declaring a C instruction implementation function taking
5142 * two extra arguments.
5143 *
5144 * @param a_Name The name of the type.
5145 * @param a_Type0 The type of the 1st argument
5146 * @param a_Arg0 The name of the 1st argument.
5147 * @param a_Type1 The type of the 2nd argument.
5148 * @param a_Arg1 The name of the 2nd argument.
5149 */
5150# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5151 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5152/**
5153 * For defining a C instruction implementation function taking two extra
5154 * arguments.
5155 *
5156 * @param a_Name The name of the function.
5157 * @param a_Type0 The type of the 1st argument
5158 * @param a_Arg0 The name of the 1st argument.
5159 * @param a_Type1 The type of the 2nd argument.
5160 * @param a_Arg1 The name of the 2nd argument.
5161 */
5162# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5163 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5164/**
5165 * Prototype version of IEM_CIMPL_DEF_2.
5166 */
5167# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5168 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5169/**
5170 * For calling a C instruction implementation function taking two extra
5171 * arguments.
5172 *
5173 * This special call macro adds default arguments to the call and allow us to
5174 * change these later.
5175 *
5176 * @param a_fn The name of the function.
5177 * @param a0 The name of the 1st argument.
5178 * @param a1 The name of the 2nd argument.
5179 */
5180# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
5181
5182/**
5183 * For typedef'ing or declaring a C instruction implementation function taking
5184 * three extra arguments.
5185 *
5186 * @param a_Name The name of the type.
5187 * @param a_Type0 The type of the 1st argument
5188 * @param a_Arg0 The name of the 1st argument.
5189 * @param a_Type1 The type of the 2nd argument.
5190 * @param a_Arg1 The name of the 2nd argument.
5191 * @param a_Type2 The type of the 3rd argument.
5192 * @param a_Arg2 The name of the 3rd argument.
5193 */
5194# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5195 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5196/**
5197 * For defining a C instruction implementation function taking three extra
5198 * arguments.
5199 *
5200 * @param a_Name The name of the function.
5201 * @param a_Type0 The type of the 1st argument
5202 * @param a_Arg0 The name of the 1st argument.
5203 * @param a_Type1 The type of the 2nd argument.
5204 * @param a_Arg1 The name of the 2nd argument.
5205 * @param a_Type2 The type of the 3rd argument.
5206 * @param a_Arg2 The name of the 3rd argument.
5207 */
5208# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5209 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5210/**
5211 * Prototype version of IEM_CIMPL_DEF_3.
5212 */
5213# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5214 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5215/**
5216 * For calling a C instruction implementation function taking three extra
5217 * arguments.
5218 *
5219 * This special call macro adds default arguments to the call and allow us to
5220 * change these later.
5221 *
5222 * @param a_fn The name of the function.
5223 * @param a0 The name of the 1st argument.
5224 * @param a1 The name of the 2nd argument.
5225 * @param a2 The name of the 3rd argument.
5226 */
5227# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
5228
5229
5230/**
5231 * For typedef'ing or declaring a C instruction implementation function taking
5232 * four extra arguments.
5233 *
5234 * @param a_Name The name of the type.
5235 * @param a_Type0 The type of the 1st argument
5236 * @param a_Arg0 The name of the 1st argument.
5237 * @param a_Type1 The type of the 2nd argument.
5238 * @param a_Arg1 The name of the 2nd argument.
5239 * @param a_Type2 The type of the 3rd argument.
5240 * @param a_Arg2 The name of the 3rd argument.
5241 * @param a_Type3 The type of the 4th argument.
5242 * @param a_Arg3 The name of the 4th argument.
5243 */
5244# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5245 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
5246/**
5247 * For defining a C instruction implementation function taking four extra
5248 * arguments.
5249 *
5250 * @param a_Name The name of the function.
5251 * @param a_Type0 The type of the 1st argument
5252 * @param a_Arg0 The name of the 1st argument.
5253 * @param a_Type1 The type of the 2nd argument.
5254 * @param a_Arg1 The name of the 2nd argument.
5255 * @param a_Type2 The type of the 3rd argument.
5256 * @param a_Arg2 The name of the 3rd argument.
5257 * @param a_Type3 The type of the 4th argument.
5258 * @param a_Arg3 The name of the 4th argument.
5259 */
5260# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5261 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5262 a_Type2 a_Arg2, a_Type3 a_Arg3))
5263/**
5264 * Prototype version of IEM_CIMPL_DEF_4.
5265 */
5266# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5267 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5268 a_Type2 a_Arg2, a_Type3 a_Arg3))
5269/**
5270 * For calling a C instruction implementation function taking four extra
5271 * arguments.
5272 *
5273 * This special call macro adds default arguments to the call and allow us to
5274 * change these later.
5275 *
5276 * @param a_fn The name of the function.
5277 * @param a0 The name of the 1st argument.
5278 * @param a1 The name of the 2nd argument.
5279 * @param a2 The name of the 3rd argument.
5280 * @param a3 The name of the 4th argument.
5281 */
5282# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
5283
5284
5285/**
5286 * For typedef'ing or declaring a C instruction implementation function taking
5287 * five extra arguments.
5288 *
5289 * @param a_Name The name of the type.
5290 * @param a_Type0 The type of the 1st argument
5291 * @param a_Arg0 The name of the 1st argument.
5292 * @param a_Type1 The type of the 2nd argument.
5293 * @param a_Arg1 The name of the 2nd argument.
5294 * @param a_Type2 The type of the 3rd argument.
5295 * @param a_Arg2 The name of the 3rd argument.
5296 * @param a_Type3 The type of the 4th argument.
5297 * @param a_Arg3 The name of the 4th argument.
5298 * @param a_Type4 The type of the 5th argument.
5299 * @param a_Arg4 The name of the 5th argument.
5300 */
5301# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5302 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
5303 a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
5304 a_Type3 a_Arg3, a_Type4 a_Arg4))
5305/**
5306 * For defining a C instruction implementation function taking five extra
5307 * arguments.
5308 *
5309 * @param a_Name The name of the function.
5310 * @param a_Type0 The type of the 1st argument
5311 * @param a_Arg0 The name of the 1st argument.
5312 * @param a_Type1 The type of the 2nd argument.
5313 * @param a_Arg1 The name of the 2nd argument.
5314 * @param a_Type2 The type of the 3rd argument.
5315 * @param a_Arg2 The name of the 3rd argument.
5316 * @param a_Type3 The type of the 4th argument.
5317 * @param a_Arg3 The name of the 4th argument.
5318 * @param a_Type4 The type of the 5th argument.
5319 * @param a_Arg4 The name of the 5th argument.
5320 */
5321# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5322 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5323 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5324/**
5325 * Prototype version of IEM_CIMPL_DEF_5.
5326 */
5327# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5328 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5329 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5330/**
5331 * For calling a C instruction implementation function taking five extra
5332 * arguments.
5333 *
5334 * This special call macro adds default arguments to the call and allow us to
5335 * change these later.
5336 *
5337 * @param a_fn The name of the function.
5338 * @param a0 The name of the 1st argument.
5339 * @param a1 The name of the 2nd argument.
5340 * @param a2 The name of the 3rd argument.
5341 * @param a3 The name of the 4th argument.
5342 * @param a4 The name of the 5th argument.
5343 */
5344# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
5345
5346/** @} */
5347
5348
5349/** @name Opcode Decoder Function Types.
5350 * @{ */
5351
5352/** @typedef PFNIEMOP
5353 * Pointer to an opcode decoder function.
5354 */
5355
5356/** @def FNIEMOP_DEF
5357 * Define an opcode decoder function.
5358 *
5359 * We're using macors for this so that adding and removing parameters as well as
5360 * tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
5361 *
5362 * @param a_Name The function name.
5363 */
5364
5365/** @typedef PFNIEMOPRM
5366 * Pointer to an opcode decoder function with RM byte.
5367 */
5368
5369/** @def FNIEMOPRM_DEF
5370 * Define an opcode decoder function with RM byte.
5371 *
5372 * We're using macors for this so that adding and removing parameters as well as
5373 * tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
5374 *
5375 * @param a_Name The function name.
5376 */
5377
5378#if defined(__GNUC__) && defined(RT_ARCH_X86)
5379typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
5380typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5381# define FNIEMOP_DEF(a_Name) \
5382 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
5383# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5384 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5385# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5386 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5387
5388#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
5389typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
5390typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5391# define FNIEMOP_DEF(a_Name) \
5392 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5393# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5394 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5395# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5396 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5397
5398#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5399typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5400typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5401# define FNIEMOP_DEF(a_Name) \
5402 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
5403# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5404 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5405# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5406 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5407
5408#else
5409typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5410typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5411# define FNIEMOP_DEF(a_Name) \
5412 IEM_STATIC IEM_DECL_MSC_GUARD_IGNORE VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5413# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5414 IEM_STATIC IEM_DECL_MSC_GUARD_IGNORE VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5415# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5416 IEM_STATIC IEM_DECL_MSC_GUARD_IGNORE VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5417
5418#endif
5419#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
5420
5421/**
5422 * Call an opcode decoder function.
5423 *
5424 * We're using macors for this so that adding and removing parameters can be
5425 * done as we please. See FNIEMOP_DEF.
5426 */
5427#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
5428
5429/**
5430 * Call a common opcode decoder function taking one extra argument.
5431 *
5432 * We're using macors for this so that adding and removing parameters can be
5433 * done as we please. See FNIEMOP_DEF_1.
5434 */
5435#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
5436
5437/**
5438 * Call a common opcode decoder function taking one extra argument.
5439 *
5440 * We're using macors for this so that adding and removing parameters can be
5441 * done as we please. See FNIEMOP_DEF_1.
5442 */
5443#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
5444/** @} */
5445
5446
5447/** @name Misc Helpers
5448 * @{ */
5449
5450/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5451 * due to GCC lacking knowledge about the value range of a switch. */
5452#if RT_CPLUSPLUS_PREREQ(202000)
5453# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5454#else
5455# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5456#endif
5457
5458/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5459#if RT_CPLUSPLUS_PREREQ(202000)
5460# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5461#else
5462# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5463#endif
5464
5465/**
5466 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5467 * occation.
5468 */
5469#ifdef LOG_ENABLED
5470# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5471 do { \
5472 /*Log*/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5473 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5474 } while (0)
5475#else
5476# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5477 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5478#endif
5479
5480/**
5481 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5482 * occation using the supplied logger statement.
5483 *
5484 * @param a_LoggerArgs What to log on failure.
5485 */
5486#ifdef LOG_ENABLED
5487# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5488 do { \
5489 LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5490 /*LogFunc(a_LoggerArgs);*/ \
5491 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5492 } while (0)
5493#else
5494# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5495 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5496#endif
5497
5498/**
5499 * Gets the CPU mode (from fExec) as a IEMMODE value.
5500 *
5501 * @returns IEMMODE
5502 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5503 */
5504#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5505
5506/**
5507 * Check if we're currently executing in real or virtual 8086 mode.
5508 *
5509 * @returns @c true if it is, @c false if not.
5510 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5511 */
5512#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5513 & (IEM_F_MODE_X86_V86_MASK | IEM_F_MODE_X86_PROT_MASK)) != 0)
5514
5515/**
5516 * Check if we're currently executing in virtual 8086 mode.
5517 *
5518 * @returns @c true if it is, @c false if not.
5519 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5520 */
5521#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5522
5523/**
5524 * Check if we're currently executing in long mode.
5525 *
5526 * @returns @c true if it is, @c false if not.
5527 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5528 */
5529#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5530
5531/**
5532 * Check if we're currently executing in a 16-bit code segment.
5533 *
5534 * @returns @c true if it is, @c false if not.
5535 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5536 */
5537#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5538
5539/**
5540 * Check if we're currently executing in a 32-bit code segment.
5541 *
5542 * @returns @c true if it is, @c false if not.
5543 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5544 */
5545#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5546
5547/**
5548 * Check if we're currently executing in a 64-bit code segment.
5549 *
5550 * @returns @c true if it is, @c false if not.
5551 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5552 */
5553#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5554
5555/**
5556 * Check if we're currently executing in real mode.
5557 *
5558 * @returns @c true if it is, @c false if not.
5559 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5560 */
5561#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5562
5563/**
5564 * Gets the current protection level (CPL).
5565 *
5566 * @returns 0..3
5567 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5568 */
5569#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5570
5571/**
5572 * Sets the current protection level (CPL).
5573 *
5574 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5575 */
5576#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5577 do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) | ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5578
5579/**
5580 * Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5581 * @returns PCCPUMFEATURES
5582 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5583 */
5584#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5585
5586/**
5587 * Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5588 * @returns PCCPUMFEATURES
5589 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5590 */
5591#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5592
5593/**
5594 * Evaluates to true if we're presenting an Intel CPU to the guest.
5595 */
5596#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5597
5598/**
5599 * Evaluates to true if we're presenting an AMD CPU to the guest.
5600 */
5601#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD || (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5602
5603/**
5604 * Check if the address is canonical.
5605 */
5606#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5607
5608/** Checks if the ModR/M byte is in register mode or not. */
5609#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5610/** Checks if the ModR/M byte is in memory mode or not. */
5611#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5612
5613/**
5614 * Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5615 *
5616 * For use during decoding.
5617 */
5618#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | (a_pVCpu)->iem.s.uRexReg )
5619/**
5620 * Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5621 *
5622 * For use during decoding.
5623 */
5624#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) | (a_pVCpu)->iem.s.uRexB )
5625
5626/**
5627 * Gets the register (reg) part of a ModR/M encoding, without REX.R.
5628 *
5629 * For use during decoding.
5630 */
5631#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5632/**
5633 * Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5634 *
5635 * For use during decoding.
5636 */
5637#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5638
5639/**
5640 * Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5641 * register index, with REX.R added in.
5642 *
5643 * For use during decoding.
5644 *
5645 * @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5646 */
5647#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5648 ( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5649 || !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5650 ? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) | 16)
5651/**
5652 * Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5653 * with REX.B added in.
5654 *
5655 * For use during decoding.
5656 *
5657 * @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5658 */
5659#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5660 ( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5661 || !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5662 ? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) | 16)
5663
5664/**
5665 * Combines the prefix REX and ModR/M byte for passing to
5666 * iemOpHlpCalcRmEffAddrThreadedAddr64().
5667 *
5668 * @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5669 * The two bits are part of the REG sub-field, which isn't needed in
5670 * iemOpHlpCalcRmEffAddrThreadedAddr64().
5671 *
5672 * For use during decoding/recompiling.
5673 */
5674#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5675 ( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5676 | (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5677AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5678AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5679
5680/**
5681 * Gets the effective VEX.VVVV value.
5682 *
5683 * The 4th bit is ignored if not 64-bit code.
5684 * @returns effective V-register value.
5685 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5686 */
5687#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5688 (IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5689
5690
5691/**
5692 * Gets the register (reg) part of a the special 4th register byte used by
5693 * vblendvps and vblendvpd.
5694 *
5695 * For use during decoding.
5696 */
5697#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5698 (IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5699
5700
5701/**
5702 * Checks if we're executing inside an AMD-V or VT-x guest.
5703 */
5704#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) || defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5705# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5706#else
5707# define IEM_IS_IN_GUEST(a_pVCpu) false
5708#endif
5709
5710
5711#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5712
5713/**
5714 * Check if the guest has entered VMX root operation.
5715 */
5716# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5717
5718/**
5719 * Check if the guest has entered VMX non-root operation.
5720 */
5721# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX | IEM_F_X86_CTX_IN_GUEST)) \
5722 == (IEM_F_X86_CTX_VMX | IEM_F_X86_CTX_IN_GUEST) )
5723
5724/**
5725 * Check if the nested-guest has the given Pin-based VM-execution control set.
5726 */
5727# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5728
5729/**
5730 * Check if the nested-guest has the given Processor-based VM-execution control set.
5731 */
5732# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5733
5734/**
5735 * Check if the nested-guest has the given Secondary Processor-based VM-execution
5736 * control set.
5737 */
5738# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5739
5740/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5741# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5742
5743/** Whether a shadow VMCS is present for the given VCPU. */
5744# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5745
5746/** Gets the VMXON region pointer. */
5747# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5748
5749/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5750# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5751
5752/** Whether a current VMCS is present for the given VCPU. */
5753# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5754
5755/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5756# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5757 do \
5758 { \
5759 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5760 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5761 } while (0)
5762
5763/** Clears any current VMCS for the given VCPU. */
5764# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5765 do \
5766 { \
5767 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5768 } while (0)
5769
5770/**
5771 * Invokes the VMX VM-exit handler for an instruction intercept.
5772 */
5773# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5774 do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5775
5776/**
5777 * Invokes the VMX VM-exit handler for an instruction intercept where the
5778 * instruction provides additional VM-exit information.
5779 */
5780# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5781 do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5782
5783/**
5784 * Invokes the VMX VM-exit handler for a task switch.
5785 */
5786# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5787 do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5788
5789/**
5790 * Invokes the VMX VM-exit handler for MWAIT.
5791 */
5792# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5793 do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5794
5795/**
5796 * Invokes the VMX VM-exit handler for EPT faults.
5797 */
5798# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5799 do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5800
5801/**
5802 * Invokes the VMX VM-exit handler.
5803 */
5804# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5805 do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5806
5807#else
5808# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5809# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5810# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5811# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5812# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5813# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5814# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5815# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5816# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5817# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5818# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5819
5820#endif
5821
5822#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5823/**
5824 * Checks if we're executing a guest using AMD-V.
5825 */
5826# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM | IEM_F_X86_CTX_IN_GUEST)) \
5827 == (IEM_F_X86_CTX_SVM | IEM_F_X86_CTX_IN_GUEST))
5828/**
5829 * Check if an SVM control/instruction intercept is set.
5830 */
5831# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5832 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5833
5834/**
5835 * Check if an SVM read CRx intercept is set.
5836 */
5837# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5838 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5839
5840/**
5841 * Check if an SVM write CRx intercept is set.
5842 */
5843# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5844 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5845
5846/**
5847 * Check if an SVM read DRx intercept is set.
5848 */
5849# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5850 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5851
5852/**
5853 * Check if an SVM write DRx intercept is set.
5854 */
5855# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5856 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5857
5858/**
5859 * Check if an SVM exception intercept is set.
5860 */
5861# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5862 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5863
5864/**
5865 * Invokes the SVM \#VMEXIT handler for the nested-guest.
5866 */
5867# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5868 do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5869
5870/**
5871 * Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5872 * corresponding decode assist information.
5873 */
5874# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5875 do \
5876 { \
5877 uint64_t uExitInfo1; \
5878 if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5879 && (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5880 uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK | ((a_iGReg) & 7); \
5881 else \
5882 uExitInfo1 = 0; \
5883 IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5884 } while (0)
5885
5886/** Check and handles SVM nested-guest instruction intercept and updates
5887 * NRIP if needed.
5888 */
5889# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5890 do \
5891 { \
5892 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5893 { \
5894 IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5895 IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5896 } \
5897 } while (0)
5898
5899/** Checks and handles SVM nested-guest CR0 read intercept. */
5900# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5901 do \
5902 { \
5903 if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5904 { /* probably likely */ } \
5905 else \
5906 { \
5907 IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5908 IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5909 } \
5910 } while (0)
5911
5912/**
5913 * Updates the NextRIP (NRI) field in the nested-guest VMCB.
5914 */
5915# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5916 do { \
5917 if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5918 CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5919 } while (0)
5920
5921#else
5922# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5923# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5924# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5925# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5926# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5927# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5928# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5929# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5930# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5931 a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5932# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5933# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5934
5935#endif
5936
5937/** @} */
5938
5939uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5940VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5941
5942
5943/**
5944 * Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5945 */
5946typedef union IEMSELDESC
5947{
5948 /** The legacy view. */
5949 X86DESC Legacy;
5950 /** The long mode view. */
5951 X86DESC64 Long;
5952} IEMSELDESC;
5953/** Pointer to a selector descriptor table entry. */
5954typedef IEMSELDESC *PIEMSELDESC;
5955
5956/** @name Raising Exceptions.
5957 * @{ */
5958VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5959 uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5960
5961VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5962 uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5963#ifdef IEM_WITH_SETJMP
5964DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5965 uint32_t fFlags, uint16_t uErr