VirtualBox

source: vbox/trunk/src/VBox/VMM/include/GICInternal.h@ 100594

Last change on this file since 100594 was 100165, checked in by vboxsync, 18 months ago

VMM/GIC: Updates to the emulation, implement interrupt priority support, bugref:10404

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File size: 7.3 KB
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1/* $Id: GICInternal.h 100165 2023-06-13 11:56:42Z vboxsync $ */
2/** @file
3 * GIC - Generic Interrupt Controller Architecture (GICv3).
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_GICInternal_h
29#define VMM_INCLUDED_SRC_include_GICInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/gic.h>
35#include <VBox/vmm/pdmdev.h>
36
37
38/** @defgroup grp_gic_int Internal
39 * @ingroup grp_gic
40 * @internal
41 * @{
42 */
43
44#define VMCPU_TO_GICCPU(a_pVCpu) (&(a_pVCpu)->gic.s)
45#define VM_TO_GIC(a_pVM) (&(a_pVM)->gic.s)
46#define VM_TO_GICDEV(a_pVM) CTX_SUFF(VM_TO_GIC(a_pVM)->pGicDev)
47#ifdef IN_RING3
48# define VMCPU_TO_DEVINS(a_pVCpu) ((a_pVCpu)->pVMR3->gic.s.pDevInsR3)
49#elif defined(IN_RING0)
50# error "Not implemented!"
51#endif
52
53/** Maximum number of SPI interrupts. */
54#define GIC_SPI_MAX 32
55
56/**
57 * GIC PDM instance data (per-VM).
58 */
59typedef struct GICDEV
60{
61 /** The distributor MMIO handle. */
62 IOMMMIOHANDLE hMmioDist;
63 /** The redistributor MMIO handle. */
64 IOMMMIOHANDLE hMmioReDist;
65
66 /** @name SPI distributor register state.
67 * @{ */
68 /** Interrupt Group 0 Register. */
69 volatile uint32_t u32RegIGrp0;
70 /** Interrupt Configuration Register 0. */
71 volatile uint32_t u32RegICfg0;
72 /** Interrupt Configuration Register 1. */
73 volatile uint32_t u32RegICfg1;
74 /** Interrupt enabled bitmap. */
75 volatile uint32_t bmIntEnabled;
76 /** Current interrupt pending state. */
77 volatile uint32_t bmIntPending;
78 /** The current interrupt active state. */
79 volatile uint32_t bmIntActive;
80 /** The interrupt priority for each of the SGI/PPIs */
81 volatile uint8_t abIntPriority[GIC_SPI_MAX];
82
83 /** Flag whether group 0 interrupts are currently enabled. */
84 volatile bool fIrqGrp0Enabled;
85 /** Flag whether group 1 interrupts are currently enabled. */
86 volatile bool fIrqGrp1Enabled;
87 /** @} */
88
89} GICDEV;
90/** Pointer to a GIC device. */
91typedef GICDEV *PGICDEV;
92/** Pointer to a const GIC device. */
93typedef GICDEV const *PCGICDEV;
94
95
96/**
97 * GIC VM Instance data.
98 */
99typedef struct GIC
100{
101 /** The ring-3 device instance. */
102 PPDMDEVINSR3 pDevInsR3;
103} GIC;
104/** Pointer to GIC VM instance data. */
105typedef GIC *PGIC;
106/** Pointer to const GIC VM instance data. */
107typedef GIC const *PCGIC;
108AssertCompileSizeAlignment(GIC, 8);
109
110/**
111 * GIC VMCPU Instance data.
112 */
113typedef struct GICCPU
114{
115 /** @name The per vCPU redistributor data is kept here.
116 * @{ */
117
118 /** @name Physical LPI register state.
119 * @{ */
120 /** @} */
121
122 /** @name SGI and PPI redistributor register state.
123 * @{ */
124 /** Interrupt Group 0 Register. */
125 volatile uint32_t u32RegIGrp0;
126 /** Interrupt Configuration Register 0. */
127 volatile uint32_t u32RegICfg0;
128 /** Interrupt Configuration Register 1. */
129 volatile uint32_t u32RegICfg1;
130 /** Interrupt enabled bitmap. */
131 volatile uint32_t bmIntEnabled;
132 /** Current interrupt pending state. */
133 volatile uint32_t bmIntPending;
134 /** The current interrupt active state. */
135 volatile uint32_t bmIntActive;
136 /** The interrupt priority for each of the SGI/PPIs */
137 volatile uint8_t abIntPriority[GIC_INTID_RANGE_PPI_LAST + 1];
138 /** @} */
139
140 /** @name ICC system register state.
141 * @{ */
142 /** Flag whether group 0 interrupts are currently enabled. */
143 volatile bool fIrqGrp0Enabled;
144 /** Flag whether group 1 interrupts are currently enabled. */
145 volatile bool fIrqGrp1Enabled;
146 /** The current interrupt priority, only interrupts with a higher priority get signalled. */
147 volatile uint8_t bInterruptPriority;
148 /** The interrupt controller Binary Point Register for Group 0 interrupts. */
149 uint8_t bBinaryPointGrp0;
150 /** The interrupt controller Binary Point Register for Group 1 interrupts. */
151 uint8_t bBinaryPointGrp1;
152 /** The running poriorities caused by preemption. */
153 volatile uint8_t abRunningPriorities[256];
154 /** The index to the current running priority. */
155 volatile uint8_t idxRunningPriority;
156 /** @} */
157
158 /** @name Log Max counters
159 * @{ */
160 uint32_t cLogMaxAccessError;
161 uint32_t cLogMaxSetApicBaseAddr;
162 uint32_t cLogMaxGetApicBaseAddr;
163 uint32_t uAlignment4;
164 /** @} */
165
166 /** @name APIC statistics.
167 * @{ */
168#ifdef VBOX_WITH_STATISTICS
169 /** Number of MMIO reads in R3. */
170 STAMCOUNTER StatMmioReadR3;
171 /** Number of MMIO writes in R3. */
172 STAMCOUNTER StatMmioWriteR3;
173 /** Number of MSR reads in R3. */
174 STAMCOUNTER StatSysRegReadR3;
175 /** Number of MSR writes in R3. */
176 STAMCOUNTER StatSysRegWriteR3;
177
178# if 0 /* No R0 for now. */
179 /** Number of MMIO reads in RZ. */
180 STAMCOUNTER StatMmioReadRZ;
181 /** Number of MMIO writes in RZ. */
182 STAMCOUNTER StatMmioWriteRZ;
183 /** Number of MSR reads in RZ. */
184 STAMCOUNTER StatSysRegReadRZ;
185 /** Number of MSR writes in RZ. */
186 STAMCOUNTER StatSysRegWriteRZ;
187# endif
188#endif
189 /** @} */
190} GICCPU;
191/** Pointer to GIC VMCPU instance data. */
192typedef GICCPU *PGICCPU;
193/** Pointer to a const GIC VMCPU instance data. */
194typedef GICCPU const *PCGICCPU;
195
196DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
197DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
198
199DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
200DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
201
202DECLHIDDEN(void) gicResetCpu(PVMCPUCC pVCpu);
203
204DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg);
205DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns);
206DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta);
207DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns);
208
209/** @} */
210
211#endif /* !VMM_INCLUDED_SRC_include_GICInternal_h */
212
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