| 1 | /* $Id: GICInternal.h 109033 2025-04-21 07:01:04Z vboxsync $ */
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| 2 | /** @file
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| 3 | * GIC - Generic Interrupt Controller Architecture (GIC).
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2023-2024 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 | #ifndef VMM_INCLUDED_SRC_include_GICInternal_h
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| 29 | #define VMM_INCLUDED_SRC_include_GICInternal_h
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| 30 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 31 | # pragma once
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| 32 | #endif
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| 33 |
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| 34 | #include <VBox/gic.h>
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| 35 | #include <VBox/vmm/pdmdev.h>
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| 36 | #include <VBox/vmm/pdmgic.h>
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| 37 | #include <VBox/vmm/stam.h>
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| 38 |
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| 39 | #include "GITSInternal.h"
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| 40 |
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| 41 | /** @defgroup grp_gic_int Internal
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| 42 | * @ingroup grp_gic
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| 43 | * @internal
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| 44 | * @{
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| 45 | */
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| 46 |
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| 47 | #ifdef VBOX_INCLUDED_vmm_pdmgic_h
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| 48 | /** The VirtualBox GIC backend. */
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| 49 | extern const PDMGICBACKEND g_GicBackend;
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| 50 | # ifdef RT_OS_DARWIN
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| 51 | /** The Hypervisor.Framework GIC backend. */
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| 52 | extern const PDMGICBACKEND g_GicHvfBackend;
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| 53 | # elif defined(RT_OS_WINDOWS)
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| 54 | /** The Hyper-V GIC backend. */
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| 55 | extern const PDMGICBACKEND g_GicHvBackend;
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| 56 | # elif defined(RT_OS_LINUX)
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| 57 | /** The KVM GIC backend. */
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| 58 | extern const PDMGICBACKEND g_GicKvmBackend;
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| 59 | # endif
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| 60 | #endif
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| 61 |
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| 62 | #define VMCPU_TO_GICCPU(a_pVCpu) (&(a_pVCpu)->gic.s)
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| 63 | #define VM_TO_GIC(a_pVM) (&(a_pVM)->gic.s)
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| 64 | #define VM_TO_GICDEV(a_pVM) CTX_SUFF(VM_TO_GIC(a_pVM)->pGicDev)
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| 65 | #define GICDEV_TO_GITSDEV(a_GicDev) (&(a_GicDev)->Gits)
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| 66 | #ifdef IN_RING3
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| 67 | # define VMCPU_TO_DEVINS(a_pVCpu) ((a_pVCpu)->pVMR3->gic.s.pDevInsR3)
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| 68 | #elif defined(IN_RING0)
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| 69 | # error "Not implemented!"
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| 70 | #endif
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| 71 |
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| 72 | /** Acquire the device critical section. */
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| 73 | #define GIC_CRIT_SECT_ENTER(a_pDevIns) \
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| 74 | do \
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| 75 | { \
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| 76 | int const rcLock_ = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->pCritSectRoR3, VINF_SUCCESS); \
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| 77 | PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), (a_pDevIns)->pCritSectRoR3, rcLock_); \
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| 78 | } while(0)
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| 79 |
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| 80 | /** Release the device critical section. */
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| 81 | #define GIC_CRIT_SECT_LEAVE(a_pDevIns) PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo))
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| 82 |
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| 83 | /** Returns whether the critical section is held. */
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| 84 | #define GIC_CRIT_SECT_IS_OWNER(a_pDevIns) PDMDevHlpCritSectIsOwner((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo))
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| 85 |
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| 86 | /** Returns whether the given register offset is within the specified range. */
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| 87 | #define GIC_IS_REG_IN_RANGE(a_offReg, a_offFirst, a_cbRegion) ((uint32_t)(a_offReg) - (a_offFirst) < (a_cbRegion))
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| 88 |
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| 89 | /** @def GIC_SET_REG_U64_FULL
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| 90 | * Sets a 64-bit GIC register.
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| 91 | * @param a_uReg The 64-bit register to set.
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| 92 | * @param a_uValue The 64-bit value being written.
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| 93 | * @param a_fRwMask The 64-bit mask of valid read-write bits.
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| 94 | */
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| 95 | #define GIC_SET_REG_U64_FULL(a_uReg, a_uValue, a_fRwMask) \
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| 96 | do \
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| 97 | { \
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| 98 | AssertCompile(sizeof(a_uReg) == sizeof(uint64_t)); \
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| 99 | AssertCompile(sizeof(a_fRwMask) == sizeof(uint64_t)); \
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| 100 | (a_uReg) = ((a_uReg) & ~(a_fRwMask)) | ((a_uValue) & (a_fRwMask)); \
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| 101 | } while (0)
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| 102 |
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| 103 | /** @def GIC_SET_REG_U64_LO
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| 104 | * Sets the lower half of a 64-bit GIC register.
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| 105 | * @param a_uReg The lower half of a 64-bit register to set.
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| 106 | * @param a_uValue The value being written (only lower 32-bits are used).
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| 107 | * @param a_fRwMask The 64-bit mask of valid read-write bits.
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| 108 | */
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| 109 | #define GIC_SET_REG_U64_LO(a_uReg, a_uValue, a_fRwMask) \
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| 110 | do \
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| 111 | { \
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| 112 | AssertCompile(sizeof(a_uReg) == sizeof(uint32_t)); \
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| 113 | AssertCompile(sizeof(a_fRwMask) == sizeof(uint64_t)); \
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| 114 | (a_uReg) = ((a_uReg) & ~(RT_LO_U32(a_fRwMask))) | ((uint32_t)(a_uValue) & (RT_LO_U32(a_fRwMask))); \
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| 115 | } while (0)
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| 116 |
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| 117 | /** @def GIC_SET_REG_U64_HI
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| 118 | * Sets the upper half of a 64-bit GIC register.
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| 119 | * @param a_uReg The upper half of the 64-bit register to set.
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| 120 | * @param a_uValue The value being written (only lower 32-bits are used).
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| 121 | * @param a_fRwMask The 64-bit mask of valid read-write bits.
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| 122 | */
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| 123 | #define GIC_SET_REG_U64_HI(a_uReg, a_uValue, a_fRwMask) \
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| 124 | do \
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| 125 | { \
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| 126 | AssertCompile(sizeof(a_uReg) == sizeof(uint32_t)); \
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| 127 | AssertCompile(sizeof(a_fRwMask) == sizeof(uint64_t)); \
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| 128 | (a_uReg) = ((a_uReg) & ~(RT_HI_U32(a_fRwMask))) | ((uint32_t)(a_uValue) & (RT_HI_U32(a_fRwMask))); \
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| 129 | } while (0)
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| 130 |
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| 131 | /** @def GIC_SET_REG_U32
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| 132 | * Sets a 32-bit GIC register.
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| 133 | * @param a_uReg The 32-bit register to set.
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| 134 | * @param a_uValue The 32-bit value being written (only lower 32-bits are
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| 135 | * used).
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| 136 | * @param a_fRwMask The mask of valid read-write bits (only lower 32-bits are
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| 137 | * used).
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| 138 | */
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| 139 | #define GIC_SET_REG_U32(a_uReg, a_uValue, a_fRwMask) \
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| 140 | do \
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| 141 | { \
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| 142 | AssertCompile(sizeof(a_uReg) == sizeof(uint32_t)); \
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| 143 | (a_uReg) = ((a_uReg) & ~(a_fRwMask)) | ((uint32_t)(a_uValue) & (uint32_t)(a_fRwMask)); \
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| 144 | } while (0)
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| 145 |
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| 146 |
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| 147 | /**
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| 148 | * GIC PDM instance data (per-VM).
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| 149 | */
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| 150 | typedef struct GICDEV
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| 151 | {
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| 152 | /** @name Distributor register state.
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| 153 | * @{
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| 154 | */
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| 155 | /** Interrupt group bitmap. */
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| 156 | uint32_t bmIntrGroup[64];
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| 157 | /** Interrupt config bitmap (edge-triggered vs level-sensitive). */
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| 158 | uint32_t bmIntrConfig[128];
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| 159 | /** Interrupt enabled bitmap. */
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| 160 | uint32_t bmIntrEnabled[64];
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| 161 | /** Interrupt pending bitmap. */
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| 162 | uint32_t bmIntrPending[64];
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| 163 | /** Interrupt active bitmap. */
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| 164 | uint32_t bmIntrActive[64];
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| 165 | /** Interrupt priorities. */
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| 166 | uint8_t abIntrPriority[2048];
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| 167 | /** Interrupt routing info. */
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| 168 | uint32_t au32IntrRouting[2048];
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| 169 | /** Interrupt routine mode bitmap. */
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| 170 | uint32_t bmIntrRoutingMode[64];
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| 171 | /** Flag whether group 0 interrupts are enabled. */
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| 172 | bool fIntrGroup0Enabled;
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| 173 | /** Flag whether group 1 interrupts are enabled. */
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| 174 | bool fIntrGroup1Enabled;
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| 175 | /** Flag whether affinity routing is enabled. */
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| 176 | bool fAffRoutingEnabled;
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| 177 | /** @} */
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| 178 |
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| 179 | /** @name Configurables.
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| 180 | * @{ */
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| 181 | /** The GIC architecture revision (GICD_PIDR2.ArchRev and GICR_PIDR2.ArchRev). */
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| 182 | uint8_t uArchRev;
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| 183 | /** The GIC architecture minor revision (currently 1 as we only support GICv3.1). */
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| 184 | uint8_t uArchRevMinor;
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| 185 | /** The maximum SPI supported (GICD_TYPER.ItLinesNumber). */
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| 186 | uint8_t uMaxSpi;
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| 187 | /** Whether extended SPIs are supported (GICD_ESPI). */
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| 188 | bool fExtSpi;
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| 189 | /** The maximum extended SPI supported (GICD_TYPER.ESPI_range). */
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| 190 | uint8_t uMaxExtSpi;
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| 191 | /** Whether extended PPIs are supported. */
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| 192 | bool fExtPpi;
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| 193 | /** The maximum extended PPI supported (GICR_TYPER.PPInum). */
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| 194 | uint8_t uMaxExtPpi;
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| 195 | /** Whether range-selector is supported (GICD_TYPER.RSS and ICC_CTLR_EL1.RSS). */
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| 196 | bool fRangeSel;
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| 197 | /** Whether NMIs are supported (GICD_TYPER.NMI). */
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| 198 | bool fNmi;
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| 199 | /** Whether message-based interrupts are supported (GICD_TYPER.MBIS). */
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| 200 | bool fMbi;
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| 201 | /** Whether non-zero affinity 3 levels are supported (GICD_TYPER.A3V) and
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| 202 | * (ICC_CTLR.A3V). */
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| 203 | bool fAff3Levels;
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| 204 | /** Whether LPIs are supported (GICD_TYPER.PLPIS). */
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| 205 | bool fLpi;
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| 206 | /** The maximum LPI supported (GICD_TYPER.num_LPI). */
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| 207 | uint8_t uMaxLpi;
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| 208 | /** @} */
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| 209 |
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| 210 | /** @name GITS device data and LPIs.
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| 211 | * @{ */
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| 212 | /** Whether LPIs are enabled (GICR_CTLR.EnableLpis of all redistributors). */
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| 213 | bool fEnableLpis;
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| 214 | /** Padding. */
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| 215 | bool afPadding1[3];
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| 216 | /** ITS device state. */
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| 217 | GITSDEV Gits;
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| 218 | /** LPI config table. */
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| 219 | uint8_t abLpiConfig[4096];
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| 220 | /** The LPI config table base register (GICR_PROPBASER). */
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| 221 | RTUINT64U uLpiConfigBaseReg;
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| 222 | /** The LPI pending table base register (GICR_PENDBASER). */
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| 223 | RTUINT64U uLpiPendingBaseReg;
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| 224 | /** @} */
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| 225 |
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| 226 | /** @name MMIO data.
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| 227 | * @{ */
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| 228 | /** The distributor MMIO handle. */
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| 229 | IOMMMIOHANDLE hMmioDist;
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| 230 | /** The redistributor MMIO handle. */
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| 231 | IOMMMIOHANDLE hMmioReDist;
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| 232 | /** The interrupt translation service MMIO handle. */
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| 233 | IOMMMIOHANDLE hMmioGits;
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| 234 | /** @} */
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| 235 | } GICDEV;
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| 236 | /** Pointer to a GIC device. */
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| 237 | typedef GICDEV *PGICDEV;
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| 238 | /** Pointer to a const GIC device. */
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| 239 | typedef GICDEV const *PCGICDEV;
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| 240 | AssertCompileMemberSizeAlignment(GICDEV, Gits, 8);
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| 241 | AssertCompileMemberAlignment(GICDEV, abLpiConfig, 8);
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| 242 | AssertCompileMemberAlignment(GICDEV, hMmioDist, 8);
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| 243 |
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| 244 | /**
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| 245 | * GIC VM Instance data.
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| 246 | */
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| 247 | typedef struct GIC
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| 248 | {
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| 249 | /** The ring-3 device instance. */
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| 250 | PPDMDEVINSR3 pDevInsR3;
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| 251 | } GIC;
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| 252 | /** Pointer to GIC VM instance data. */
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| 253 | typedef GIC *PGIC;
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| 254 | /** Pointer to const GIC VM instance data. */
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| 255 | typedef GIC const *PCGIC;
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| 256 | AssertCompileSizeAlignment(GIC, 8);
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| 257 |
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| 258 | /**
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| 259 | * GIC VMCPU Instance data.
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| 260 | */
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| 261 | typedef struct GICCPU
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| 262 | {
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| 263 | /** @name Redistributor register state.
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| 264 | * @{ */
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| 265 | /** Interrupt group bitmap. */
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| 266 | uint32_t bmIntrGroup[3];
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| 267 | /** Interrupt config bitmap (edge-triggered vs level-sensitive). */
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| 268 | uint32_t bmIntrConfig[6];
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| 269 | /** Interrupt enabled bitmap. */
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| 270 | uint32_t bmIntrEnabled[3];
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| 271 | /** Interrupt pending bitmap. */
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| 272 | uint32_t bmIntrPending[3];
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| 273 | /** Interrupt active bitmap. */
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| 274 | uint32_t bmIntrActive[3];
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| 275 | /** Interrupt priorities. */
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| 276 | uint8_t abIntrPriority[96];
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| 277 | /** @} */
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| 278 |
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| 279 | /** @name ICC system register state.
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| 280 | * @{ */
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| 281 | /** The control register (ICC_CTLR_EL1). */
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| 282 | uint64_t uIccCtlr;
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| 283 | /** The interrupt priority mask of the CPU interface (ICC_PMR_EL1). */
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| 284 | uint8_t bIntrPriorityMask;
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| 285 | /** The index to the current running priority. */
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| 286 | uint8_t idxRunningPriority;
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| 287 | /** The running priorities caused by preemption. */
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| 288 | uint8_t abRunningPriorities[256];
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| 289 | /** The active priorities group 0 bitmap. */
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| 290 | uint32_t bmActivePriorityGroup0[4];
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| 291 | /** The active priorities group 0 bitmap. */
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| 292 | uint32_t bmActivePriorityGroup1[4];
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| 293 | /** The binary point register for group 0 interrupts. */
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| 294 | uint8_t bBinaryPtGroup0;
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| 295 | /** The binary point register for group 1 interrupts. */
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| 296 | uint8_t bBinaryPtGroup1;
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| 297 | /** Flag whether group 0 interrupts are enabled. */
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| 298 | bool fIntrGroup0Enabled;
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| 299 | /** Flag whether group 1 interrupts are enabled. */
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| 300 | bool fIntrGroup1Enabled;
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| 301 | /** @} */
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| 302 |
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| 303 | /** @name LPIs.
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| 304 | * @{ */
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| 305 | /** LPI pending bitmap. */
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| 306 | uint64_t bmLpiPending[64];
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| 307 | /** @} */
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| 308 |
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| 309 | /** @name Statistics.
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| 310 | * @{ */
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| 311 | #ifdef VBOX_WITH_STATISTICS
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| 312 | /** Number of MMIO reads. */
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| 313 | STAMCOUNTER StatMmioRead;
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| 314 | /** Number of MMIO writes. */
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| 315 | STAMCOUNTER StatMmioWrite;
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| 316 | /** Number of MSR reads. */
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| 317 | STAMCOUNTER StatSysRegRead;
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| 318 | /** Number of MSR writes. */
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| 319 | STAMCOUNTER StatSysRegWrite;
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| 320 | /** Number of set SPI callbacks. */
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| 321 | STAMCOUNTER StatSetSpi;
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| 322 | /** Number of set PPI callbacks. */
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| 323 | STAMCOUNTER StatSetPpi;
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| 324 | /** Number of SGIs generated. */
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| 325 | STAMCOUNTER StatSetSgi;
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| 326 |
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| 327 | /** Profiling of interrupt acknowledge (IAR). */
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| 328 | STAMPROFILE StatProfIntrAck;
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| 329 | /** Profiling of set SPI callback. */
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| 330 | STAMPROFILE StatProfSetSpi;
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| 331 | /** Profiling of set PPI callback. */
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| 332 | STAMPROFILE StatProfSetPpi;
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| 333 | /** Profiling of set SGI function. */
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| 334 | STAMPROFILE StatProfSetSgi;
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| 335 | #endif
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| 336 | /** @} */
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| 337 | } GICCPU;
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| 338 | /** Pointer to GIC VMCPU instance data. */
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| 339 | typedef GICCPU *PGICCPU;
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| 340 | /** Pointer to a const GIC VMCPU instance data. */
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| 341 | typedef GICCPU const *PCGICCPU;
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| 342 | /* Ensure the LPI pending bitmap's capacity is sufficient for the number of LPIs we support. */
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| 343 | AssertCompileMemberSize(GICCPU, bmLpiPending, RT_ELEMENTS(GICDEV::abLpiConfig) / 8);
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| 344 | AssertCompileMemberAlignment(GICCPU, bmLpiPending, 8);
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| 345 |
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| 346 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
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| 347 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
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| 348 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
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| 349 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
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| 350 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicItsMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
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| 351 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicItsMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
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| 352 |
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| 353 | DECLHIDDEN(void) gicDistReadLpiConfigTableFromMem(PPDMDEVINS pDevIns);
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| 354 |
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| 355 | DECLHIDDEN(void) gicResetCpu(PPDMDEVINS pDevIns, PVMCPUCC pVCpu);
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| 356 | DECLHIDDEN(void) gicReset(PPDMDEVINS pDevIns);
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| 357 | DECLHIDDEN(uint16_t) gicReDistGetIntIdFromIndex(uint16_t idxIntr);
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| 358 | DECLHIDDEN(uint16_t) gicDistGetIntIdFromIndex(uint16_t idxIntr);
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| 359 |
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| 360 | DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg);
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| 361 | DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns);
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| 362 | DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns);
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| 363 |
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| 364 | /** @} */
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| 365 |
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| 366 | #endif /* !VMM_INCLUDED_SRC_include_GICInternal_h */
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| 367 |
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