VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 87351

Last change on this file since 87351 was 87351, checked in by vboxsync, 4 years ago

VMM/CPUM: Slapped a @todo on CPUM_CHANGED_XXX / CPUMCPU::fChanged.
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  • Property svn:keywords set to Id Revision
File size: 18.4 KB
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1/* $Id: CPUMInternal.h 87351 2021-01-21 14:28:30Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
19#define VMM_INCLUDED_SRC_include_CPUMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#ifndef VBOX_FOR_DTRACE_LIB
25# include <VBox/cdefs.h>
26# include <VBox/types.h>
27# include <VBox/vmm/stam.h>
28# include <iprt/x86.h>
29# include <VBox/vmm/pgm.h>
30#else
31# pragma D depends_on library x86.d
32# pragma D depends_on library cpumctx.d
33# pragma D depends_on library cpum.d
34
35/* Some fudging. */
36typedef uint64_t STAMCOUNTER;
37#endif
38
39
40
41
42/** @defgroup grp_cpum_int Internals
43 * @ingroup grp_cpum
44 * @internal
45 * @{
46 */
47
48/** Flags and types for CPUM fault handlers
49 * @{ */
50/** Type: Load DS */
51#define CPUM_HANDLER_DS 1
52/** Type: Load ES */
53#define CPUM_HANDLER_ES 2
54/** Type: Load FS */
55#define CPUM_HANDLER_FS 3
56/** Type: Load GS */
57#define CPUM_HANDLER_GS 4
58/** Type: IRET */
59#define CPUM_HANDLER_IRET 5
60/** Type mask. */
61#define CPUM_HANDLER_TYPEMASK 0xff
62/** If set EBP points to the CPUMCTXCORE that's being used. */
63#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
64/** @} */
65
66
67/** Use flags (CPUM::fUseFlags).
68 * (Don't forget to sync this with CPUMInternal.mac !)
69 * @note Part of saved state.
70 * @{ */
71/** Indicates that we've saved the host FPU, SSE, whatever state and that it
72 * needs to be restored. */
73#define CPUM_USED_FPU_HOST RT_BIT(0)
74/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
75 * needs to be saved. */
76#define CPUM_USED_FPU_GUEST RT_BIT(10)
77/** Used the guest FPU, SSE or such stuff since last we were in REM.
78 * REM syncing is clearing this, lazy FPU is setting it. */
79#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
80/** The XMM state was manually restored. (AMD only) */
81#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
82
83/** Host OS is using SYSENTER and we must NULL the CS. */
84#define CPUM_USE_SYSENTER RT_BIT(3)
85/** Host OS is using SYSENTER and we must NULL the CS. */
86#define CPUM_USE_SYSCALL RT_BIT(4)
87
88/** Debug registers are used by host and that DR7 and DR6 must be saved and
89 * disabled when switching to raw-mode. */
90#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
91/** Records that we've saved the host DRx registers.
92 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
93 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
94#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
95/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
96 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
97#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
98/** Used in ring-0 to indicate that we have loaded the hypervisor debug
99 * registers. */
100#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
101/** Used in ring-0 to indicate that we have loaded the guest debug
102 * registers (DR0-3 and maybe DR6) for direct use by the guest.
103 * DR7 (and AMD-V DR6) are handled via the VMCB. */
104#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
105
106/** Host CPU requires fxsave/fxrstor leaky bit handling. */
107#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
108/** Set if the VM supports long-mode. */
109#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
110/** @} */
111
112
113/** @name CPUM Saved State Version.
114 * @{ */
115/** The current saved state version. */
116#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM
117/** The saved state version including VMX hardware virtualization state (IEM only
118 * execution). */
119#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM 19
120/** The saved state version including SVM hardware virtualization state. */
121#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
122/** The saved state version including XSAVE state. */
123#define CPUM_SAVED_STATE_VERSION_XSAVE 17
124/** The saved state version with good CPUID leaf count. */
125#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
126/** CPUID changes with explode forgetting to update the leaf count on
127 * restore, resulting in garbage being saved restoring+saving old states). */
128#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
129/** The saved state version before the CPUIDs changes. */
130#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
131/** The saved state version before using SSMR3PutStruct. */
132#define CPUM_SAVED_STATE_VERSION_MEM 13
133/** The saved state version before introducing the MSR size field. */
134#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
135/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
136 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
137#define CPUM_SAVED_STATE_VERSION_VER3_2 11
138/** The saved state version of 3.0 and 3.1 trunk before the teleportation
139 * changes. */
140#define CPUM_SAVED_STATE_VERSION_VER3_0 10
141/** The saved state version for the 2.1 trunk before the MSR changes. */
142#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
143/** The saved state version of 2.0, used for backwards compatibility. */
144#define CPUM_SAVED_STATE_VERSION_VER2_0 8
145/** The saved state version of 1.6, used for backwards compatibility. */
146#define CPUM_SAVED_STATE_VERSION_VER1_6 6
147/** @} */
148
149
150/**
151 * CPU info
152 */
153typedef struct CPUMINFO
154{
155 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
156 uint32_t cMsrRanges;
157 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
158 * instruction. Older hardware has been observed to ignore higher bits. */
159 uint32_t fMsrMask;
160
161 /** MXCSR mask. */
162 uint32_t fMxCsrMask;
163
164 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
165 uint32_t cCpuIdLeaves;
166 /** The index of the first extended CPUID leaf in the array.
167 * Set to cCpuIdLeaves if none present. */
168 uint32_t iFirstExtCpuIdLeaf;
169 /** How to handle unknown CPUID leaves. */
170 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
171 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
172 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
173 CPUMCPUID DefCpuId;
174
175 /** Scalable bus frequency used for reporting other frequencies. */
176 uint64_t uScalableBusFreq;
177
178 /** Pointer to the MSR ranges (ring-0 pointer). */
179 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
180 /** Pointer to the CPUID leaves (ring-0 pointer). */
181 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
182
183 /** Pointer to the MSR ranges (ring-3 pointer). */
184 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
185 /** Pointer to the CPUID leaves (ring-3 pointer). */
186 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
187} CPUMINFO;
188/** Pointer to a CPU info structure. */
189typedef CPUMINFO *PCPUMINFO;
190/** Pointer to a const CPU info structure. */
191typedef CPUMINFO const *CPCPUMINFO;
192
193
194/**
195 * The saved host CPU state.
196 */
197typedef struct CPUMHOSTCTX
198{
199 /** General purpose register, selectors, flags and more
200 * @{ */
201 /** General purpose register ++
202 * { */
203 /*uint64_t rax; - scratch*/
204 uint64_t rbx;
205 /*uint64_t rcx; - scratch*/
206 /*uint64_t rdx; - scratch*/
207 uint64_t rdi;
208 uint64_t rsi;
209 uint64_t rbp;
210 uint64_t rsp;
211 /*uint64_t r8; - scratch*/
212 /*uint64_t r9; - scratch*/
213 uint64_t r10;
214 uint64_t r11;
215 uint64_t r12;
216 uint64_t r13;
217 uint64_t r14;
218 uint64_t r15;
219 /*uint64_t rip; - scratch*/
220 uint64_t rflags;
221 /** @} */
222
223 /** Selector registers
224 * @{ */
225 RTSEL ss;
226 RTSEL ssPadding;
227 RTSEL gs;
228 RTSEL gsPadding;
229 RTSEL fs;
230 RTSEL fsPadding;
231 RTSEL es;
232 RTSEL esPadding;
233 RTSEL ds;
234 RTSEL dsPadding;
235 RTSEL cs;
236 RTSEL csPadding;
237 /** @} */
238
239 /** Control registers.
240 * @{ */
241 /** The CR0 FPU state in HM mode. */
242 uint64_t cr0;
243 /*uint64_t cr2; - scratch*/
244 uint64_t cr3;
245 uint64_t cr4;
246 uint64_t cr8;
247 /** @} */
248
249 /** Debug registers.
250 * @{ */
251 uint64_t dr0;
252 uint64_t dr1;
253 uint64_t dr2;
254 uint64_t dr3;
255 uint64_t dr6;
256 uint64_t dr7;
257 /** @} */
258
259 /** Global Descriptor Table register. */
260 X86XDTR64 gdtr;
261 uint16_t gdtrPadding;
262 /** Interrupt Descriptor Table register. */
263 X86XDTR64 idtr;
264 uint16_t idtrPadding;
265 /** The task register. */
266 RTSEL ldtr;
267 RTSEL ldtrPadding;
268 /** The task register. */
269 RTSEL tr;
270 RTSEL trPadding;
271
272 /** MSRs
273 * @{ */
274 CPUMSYSENTER SysEnter;
275 uint64_t FSbase;
276 uint64_t GSbase;
277 uint64_t efer;
278 /** @} */
279
280 /* padding to get 64byte aligned size */
281 uint8_t auPadding[8];
282
283#if HC_ARCH_BITS != 64
284# error HC_ARCH_BITS not defined or unsupported
285#endif
286
287 /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
288 R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
289 /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
290 R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
291 /** The XCR0 register. */
292 uint64_t xcr0;
293 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
294 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
295 uint64_t fXStateMask;
296} CPUMHOSTCTX;
297#ifndef VBOX_FOR_DTRACE_LIB
298AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
299#endif
300/** Pointer to the saved host CPU state. */
301typedef CPUMHOSTCTX *PCPUMHOSTCTX;
302
303
304/**
305 * The hypervisor context CPU state (just DRx left now).
306 */
307typedef struct CPUMHYPERCTX
308{
309 /** Debug registers.
310 * @remarks DR4 and DR5 should not be used since they are aliases for
311 * DR6 and DR7 respectively on both AMD and Intel CPUs.
312 * @remarks DR8-15 are currently not supported by AMD or Intel, so
313 * neither do we.
314 */
315 uint64_t dr[8];
316 /** @todo eliminiate the rest. */
317 uint64_t cr3;
318 uint64_t au64Padding[7];
319} CPUMHYPERCTX;
320#ifndef VBOX_FOR_DTRACE_LIB
321AssertCompileSizeAlignment(CPUMHYPERCTX, 64);
322#endif
323/** Pointer to the hypervisor context CPU state. */
324typedef CPUMHYPERCTX *PCPUMHYPERCTX;
325
326
327/**
328 * CPUM Data (part of VM)
329 */
330typedef struct CPUM
331{
332 /** Use flags.
333 * These flags indicates which CPU features the host uses.
334 */
335 uint32_t fHostUseFlags;
336
337 /** CR4 mask
338 * @todo obsolete? */
339 struct
340 {
341 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
342 uint32_t OrMask;
343 } CR4;
344
345 /** The (more) portable CPUID level. */
346 uint8_t u8PortableCpuIdLevel;
347 /** Indicates that a state restore is pending.
348 * This is used to verify load order dependencies (PGM). */
349 bool fPendingRestore;
350 uint8_t abPadding0[2];
351
352 /** XSAVE/XRTOR components we can expose to the guest mask. */
353 uint64_t fXStateGuestMask;
354 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
355 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
356 uint64_t fXStateHostMask;
357
358 /** The host MXCSR mask (determined at init). */
359 uint32_t fHostMxCsrMask;
360 /** Nested VMX: Whether to expose VMX-preemption timer to the guest. */
361 bool fNestedVmxPreemptTimer;
362 uint8_t abPadding1[3];
363
364 /** Align to 64-byte boundary. */
365 uint8_t abPadding2[20+4];
366
367 /** Host CPU feature information.
368 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
369 CPUMFEATURES HostFeatures;
370 /** Guest CPU feature information.
371 * Externaly visible via that VM structure, aligned with HostFeatures. */
372 CPUMFEATURES GuestFeatures;
373 /** Guest CPU info. */
374 CPUMINFO GuestInfo;
375
376 /** The standard set of CpuId leaves. */
377 CPUMCPUID aGuestCpuIdPatmStd[6];
378 /** The extended set of CpuId leaves. */
379 CPUMCPUID aGuestCpuIdPatmExt[10];
380 /** The centaur set of CpuId leaves. */
381 CPUMCPUID aGuestCpuIdPatmCentaur[4];
382
383 /** @name MSR statistics.
384 * @{ */
385 STAMCOUNTER cMsrWrites;
386 STAMCOUNTER cMsrWritesToIgnoredBits;
387 STAMCOUNTER cMsrWritesRaiseGp;
388 STAMCOUNTER cMsrWritesUnknown;
389 STAMCOUNTER cMsrReads;
390 STAMCOUNTER cMsrReadsRaiseGp;
391 STAMCOUNTER cMsrReadsUnknown;
392 /** @} */
393} CPUM;
394#ifndef VBOX_FOR_DTRACE_LIB
395AssertCompileMemberOffset(CPUM, HostFeatures, 64);
396AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
397#endif
398/** Pointer to the CPUM instance data residing in the shared VM structure. */
399typedef CPUM *PCPUM;
400
401/**
402 * CPUM Data (part of VMCPU)
403 */
404typedef struct CPUMCPU
405{
406 /**
407 * Guest context.
408 * Aligned on a 64-byte boundary.
409 */
410 CPUMCTX Guest;
411
412 /**
413 * Guest context - misc MSRs
414 * Aligned on a 64-byte boundary.
415 */
416 CPUMCTXMSRS GuestMsrs;
417
418 /** Nested VMX: VMX-preemption timer - R0 ptr. */
419 PTMTIMERR0 pNestedVmxPreemptTimerR0;
420 /** Nested VMX: VMX-preemption timer - R3 ptr. */
421 PTMTIMERR3 pNestedVmxPreemptTimerR3;
422
423 /** Use flags.
424 * These flags indicates both what is to be used and what has been used.
425 */
426 uint32_t fUseFlags;
427
428 /** Changed flags.
429 * These flags indicates to REM (and others) which important guest
430 * registers which has been changed since last time the flags were cleared.
431 * See the CPUM_CHANGED_* defines for what we keep track of.
432 *
433 * @todo Obsolete, but will probably refactored so keep it for reference. */
434 uint32_t fChanged;
435
436 /** Temporary storage for the return code of the function called in the
437 * 32-64 switcher. */
438 uint32_t u32RetCode;
439
440#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
441 /** Used by the world switcher code to store which vectors needs restoring on
442 * the way back. */
443 uint32_t fApicDisVectors;
444 /** The address of the APIC mapping, NULL if no APIC.
445 * Call CPUMR0SetLApic to update this before doing a world switch. */
446 RTHCPTR pvApicBase;
447 /** Set if the CPU has the X2APIC mode enabled.
448 * Call CPUMR0SetLApic to update this before doing a world switch. */
449 bool fX2Apic;
450#else
451 uint8_t abPadding3[4 + sizeof(RTHCPTR) + 1];
452#endif
453
454 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
455 * (?) bits are visible or not. (The APIC is responsible for setting this
456 * when loading state, so we won't save it.) */
457 bool fCpuIdApicFeatureVisible;
458
459 /** Align the next member on a 64-byte boundary. */
460 uint8_t abPadding2[64 - (16 + 12 + 4 + 8 + 1 + 1)];
461
462 /** Saved host context. Only valid while inside RC or HM contexts.
463 * Must be aligned on a 64-byte boundary. */
464 CPUMHOSTCTX Host;
465 /** Old hypervisor context, only used for combined DRx values now.
466 * Must be aligned on a 64-byte boundary. */
467 CPUMHYPERCTX Hyper;
468
469#ifdef VBOX_WITH_CRASHDUMP_MAGIC
470 uint8_t aMagic[56];
471 uint64_t uMagic;
472#endif
473} CPUMCPU;
474/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
475typedef CPUMCPU *PCPUMCPU;
476
477#ifndef VBOX_FOR_DTRACE_LIB
478RT_C_DECLS_BEGIN
479
480PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
481PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
482
483# ifdef IN_RING3
484int cpumR3DbgInit(PVM pVM);
485int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures);
486int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
487void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs);
488void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
489int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
490int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
491DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
492
493int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
494int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
495int cpumR3MsrReconcileWithCpuId(PVM pVM);
496int cpumR3MsrApplyFudge(PVM pVM);
497int cpumR3MsrRegStats(PVM pVM);
498int cpumR3MsrStrictInitChecks(void);
499PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
500# endif
501
502# ifdef IN_RC
503DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
504# endif
505
506# ifdef IN_RING0
507DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
508DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
509# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
510DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
511# endif
512# endif
513
514# if defined(IN_RC) || defined(IN_RING0)
515DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
516DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
517DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
518DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
519# endif
520
521RT_C_DECLS_END
522#endif /* !VBOX_FOR_DTRACE_LIB */
523
524/** @} */
525
526#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
527
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