VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 100594

Last change on this file since 100594 was 99163, checked in by vboxsync, 21 months ago

VMM/CPUM: Nested VMX: bugref:10318 Adjust virtual VMCS for saving/restoring non-zero secondary processor-based execution VM-controls when the 'activate secondary controls' bit is not set.

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1/* $Id: CPUMInternal.h 99163 2023-03-24 06:19:19Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
29#define VMM_INCLUDED_SRC_include_CPUMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_FOR_DTRACE_LIB
35# include <VBox/cdefs.h>
36# include <VBox/types.h>
37# include <VBox/vmm/stam.h>
38# include <iprt/x86.h>
39# include <VBox/vmm/pgm.h>
40#else
41# pragma D depends_on library x86.d
42# pragma D depends_on library cpumctx.d
43# pragma D depends_on library cpum.d
44
45/* Some fudging. */
46typedef uint64_t STAMCOUNTER;
47#endif
48
49
50
51
52/** @defgroup grp_cpum_int Internals
53 * @ingroup grp_cpum
54 * @internal
55 * @{
56 */
57
58/** Use flags (CPUM::fUseFlags).
59 * (Don't forget to sync this with CPUMInternal.mac !)
60 * @note Was part of saved state (6.1 and earlier).
61 * @{ */
62/** Indicates that we've saved the host FPU, SSE, whatever state and that it
63 * needs to be restored. */
64#define CPUM_USED_FPU_HOST RT_BIT(0)
65/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
66 * needs to be saved.
67 * @note Mirrored in CPUMCTX::fUsedFpuGuest for the HM switcher code. */
68#define CPUM_USED_FPU_GUEST RT_BIT(10)
69/** Used the guest FPU, SSE or such stuff since last we were in REM.
70 * REM syncing is clearing this, lazy FPU is setting it. */
71#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
72/** The XMM state was manually restored. (AMD only) */
73#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
74
75/** Host OS is using SYSENTER and we must NULL the CS. */
76#define CPUM_USE_SYSENTER RT_BIT(3)
77/** Host OS is using SYSENTER and we must NULL the CS. */
78#define CPUM_USE_SYSCALL RT_BIT(4)
79
80/** Debug registers are used by host and that DR7 and DR6 must be saved and
81 * disabled when switching to raw-mode. */
82#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
83/** Records that we've saved the host DRx registers.
84 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
85 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
86#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
87/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
88 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
89#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
90/** Used in ring-0 to indicate that we have loaded the hypervisor debug
91 * registers. */
92#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
93/** Used in ring-0 to indicate that we have loaded the guest debug
94 * registers (DR0-3 and maybe DR6) for direct use by the guest.
95 * DR7 (and AMD-V DR6) are handled via the VMCB. */
96#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
97
98/** Host CPU requires fxsave/fxrstor leaky bit handling. */
99#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
100/** Set if the VM supports long-mode. */
101#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
102/** @} */
103
104
105/** @name CPUM Saved State Version.
106 * @{ */
107/** The current saved state version. */
108#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4
109/** The saved state version with u32RestoreProcCtls2 for Nested Microsoft
110 * Hyper-V. */
111#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4 23
112/** The saved state version with more virtual VMCS fields (HLAT prefix size,
113 * PCONFIG-exiting bitmap, HLAT ptr, VM-exit ctls2) and a CPUMCTX field (VM-exit
114 * ctls2 MSR). */
115#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3 22
116/** The saved state version with PAE PDPEs added. */
117#define CPUM_SAVED_STATE_VERSION_PAE_PDPES 21
118/** The saved state version with more virtual VMCS fields and CPUMCTX VMX fields. */
119#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2 20
120/** The saved state version including VMX hardware virtualization state. */
121#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX 19
122/** The saved state version including SVM hardware virtualization state. */
123#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
124/** The saved state version including XSAVE state. */
125#define CPUM_SAVED_STATE_VERSION_XSAVE 17
126/** The saved state version with good CPUID leaf count. */
127#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
128/** CPUID changes with explode forgetting to update the leaf count on
129 * restore, resulting in garbage being saved restoring+saving old states). */
130#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
131/** The saved state version before the CPUIDs changes. */
132#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
133/** The saved state version before using SSMR3PutStruct. */
134#define CPUM_SAVED_STATE_VERSION_MEM 13
135/** The saved state version before introducing the MSR size field. */
136#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
137/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
138 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
139#define CPUM_SAVED_STATE_VERSION_VER3_2 11
140/** The saved state version of 3.0 and 3.1 trunk before the teleportation
141 * changes. */
142#define CPUM_SAVED_STATE_VERSION_VER3_0 10
143/** The saved state version for the 2.1 trunk before the MSR changes. */
144#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
145/** The saved state version of 2.0, used for backwards compatibility. */
146#define CPUM_SAVED_STATE_VERSION_VER2_0 8
147/** The saved state version of 1.6, used for backwards compatibility. */
148#define CPUM_SAVED_STATE_VERSION_VER1_6 6
149/** @} */
150
151
152/** @name XSAVE limits.
153 * @{ */
154/** Max size we accept for the XSAVE area.
155 * @see CPUMCTX::abXSave */
156#define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
157/* Min size we accept for the XSAVE area. */
158#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
159/** @} */
160
161
162/**
163 * CPU info
164 */
165typedef struct CPUMINFO
166{
167 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
168 uint32_t cMsrRanges;
169 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
170 * instruction. Older hardware has been observed to ignore higher bits. */
171 uint32_t fMsrMask;
172
173 /** MXCSR mask. */
174 uint32_t fMxCsrMask;
175
176 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
177 uint32_t cCpuIdLeaves;
178 /** The index of the first extended CPUID leaf in the array.
179 * Set to cCpuIdLeaves if none present. */
180 uint32_t iFirstExtCpuIdLeaf;
181 /** How to handle unknown CPUID leaves. */
182 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
183 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
184 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
185 CPUMCPUID DefCpuId;
186
187 /** Scalable bus frequency used for reporting other frequencies. */
188 uint64_t uScalableBusFreq;
189
190 /** Pointer to the MSR ranges (for compatibility with old hyper heap code). */
191 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
192 /** Pointer to the CPUID leaves (for compatibility with old hyper heap code). */
193 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
194
195 /** CPUID leaves. */
196 CPUMCPUIDLEAF aCpuIdLeaves[256];
197 /** MSR ranges.
198 * @todo This is insane, so might want to move this into a separate
199 * allocation. The insanity is mainly for more recent AMD CPUs. */
200 CPUMMSRRANGE aMsrRanges[8192];
201} CPUMINFO;
202/** Pointer to a CPU info structure. */
203typedef CPUMINFO *PCPUMINFO;
204/** Pointer to a const CPU info structure. */
205typedef CPUMINFO const *CPCPUMINFO;
206
207
208/**
209 * The saved host CPU state.
210 */
211typedef struct CPUMHOSTCTX
212{
213 /** The extended state (FPU/SSE/AVX/AVX-2/XXXX). Must be aligned on 64 bytes. */
214 union /* no tag */
215 {
216 X86XSAVEAREA XState;
217 /** Byte view for simple indexing and space allocation.
218 * @note Must match or exceed the size of CPUMCTX::abXState. */
219 uint8_t abXState[0x4000 - 0x300];
220 } CPUM_UNION_NM(u);
221
222 /** General purpose register, selectors, flags and more
223 * @{ */
224 /** General purpose register ++
225 * { */
226 /*uint64_t rax; - scratch*/
227 uint64_t rbx;
228 /*uint64_t rcx; - scratch*/
229 /*uint64_t rdx; - scratch*/
230 uint64_t rdi;
231 uint64_t rsi;
232 uint64_t rbp;
233 uint64_t rsp;
234 /*uint64_t r8; - scratch*/
235 /*uint64_t r9; - scratch*/
236 uint64_t r10;
237 uint64_t r11;
238 uint64_t r12;
239 uint64_t r13;
240 uint64_t r14;
241 uint64_t r15;
242 /*uint64_t rip; - scratch*/
243 uint64_t rflags;
244 /** @} */
245
246 /** Selector registers
247 * @{ */
248 RTSEL ss;
249 RTSEL ssPadding;
250 RTSEL gs;
251 RTSEL gsPadding;
252 RTSEL fs;
253 RTSEL fsPadding;
254 RTSEL es;
255 RTSEL esPadding;
256 RTSEL ds;
257 RTSEL dsPadding;
258 RTSEL cs;
259 RTSEL csPadding;
260 /** @} */
261
262 /** Control registers.
263 * @{ */
264 /** The CR0 FPU state in HM mode. */
265 uint64_t cr0;
266 /*uint64_t cr2; - scratch*/
267 uint64_t cr3;
268 uint64_t cr4;
269 uint64_t cr8;
270 /** @} */
271
272 /** Debug registers.
273 * @{ */
274 uint64_t dr0;
275 uint64_t dr1;
276 uint64_t dr2;
277 uint64_t dr3;
278 uint64_t dr6;
279 uint64_t dr7;
280 /** @} */
281
282 /** Global Descriptor Table register. */
283 X86XDTR64 gdtr;
284 uint16_t gdtrPadding;
285 /** Interrupt Descriptor Table register. */
286 X86XDTR64 idtr;
287 uint16_t idtrPadding;
288 /** The task register. */
289 RTSEL ldtr;
290 RTSEL ldtrPadding;
291 /** The task register. */
292 RTSEL tr;
293 RTSEL trPadding;
294
295 /** MSRs
296 * @{ */
297 CPUMSYSENTER SysEnter;
298 uint64_t FSbase;
299 uint64_t GSbase;
300 uint64_t efer;
301 /** @} */
302
303 /** The XCR0 register. */
304 uint64_t xcr0;
305 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
306 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
307 uint64_t fXStateMask;
308
309 /* padding to get 64byte aligned size */
310 uint8_t auPadding[24];
311#if HC_ARCH_BITS != 64
312# error HC_ARCH_BITS not defined or unsupported
313#endif
314} CPUMHOSTCTX;
315#ifndef VBOX_FOR_DTRACE_LIB
316AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
317#endif
318/** Pointer to the saved host CPU state. */
319typedef CPUMHOSTCTX *PCPUMHOSTCTX;
320
321
322/**
323 * The hypervisor context CPU state (just DRx left now).
324 */
325typedef struct CPUMHYPERCTX
326{
327 /** Debug registers.
328 * @remarks DR4 and DR5 should not be used since they are aliases for
329 * DR6 and DR7 respectively on both AMD and Intel CPUs.
330 * @remarks DR8-15 are currently not supported by AMD or Intel, so
331 * neither do we.
332 */
333 uint64_t dr[8];
334 /** @todo eliminiate the rest. */
335 uint64_t cr3;
336 uint64_t au64Padding[7];
337} CPUMHYPERCTX;
338#ifndef VBOX_FOR_DTRACE_LIB
339AssertCompileSizeAlignment(CPUMHYPERCTX, 64);
340#endif
341/** Pointer to the hypervisor context CPU state. */
342typedef CPUMHYPERCTX *PCPUMHYPERCTX;
343
344
345/**
346 * CPUM Data (part of VM)
347 */
348typedef struct CPUM
349{
350 /** Use flags.
351 * These flags indicates which CPU features the host uses.
352 */
353 uint32_t fHostUseFlags;
354
355 /** CR4 mask
356 * @todo obsolete? */
357 struct
358 {
359 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
360 uint32_t OrMask;
361 } CR4;
362
363 /** The (more) portable CPUID level. */
364 uint8_t u8PortableCpuIdLevel;
365 /** Indicates that a state restore is pending.
366 * This is used to verify load order dependencies (PGM). */
367 bool fPendingRestore;
368 uint8_t abPadding0[2];
369
370 /** XSAVE/XRTOR components we can expose to the guest mask. */
371 uint64_t fXStateGuestMask;
372 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
373 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
374 uint64_t fXStateHostMask;
375
376#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
377 /** The host MXCSR mask (determined at init). */
378 uint32_t fHostMxCsrMask;
379#else
380 uint32_t u32UnusedOnNonX86;
381#endif
382 uint8_t abPadding1[4];
383
384 /** Random value we store in the reserved RFLAGS bits we don't use ourselves so
385 * we can detect corruption. */
386 uint64_t fReservedRFlagsCookie;
387
388 /** Align to 64-byte boundary. */
389 uint8_t abPadding2[16];
390
391 /** Host CPU feature information.
392 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
393 CPUMFEATURES HostFeatures;
394 /** Guest CPU feature information.
395 * Externaly visible via that VM structure, aligned with HostFeatures. */
396 CPUMFEATURES GuestFeatures;
397 /** Guest CPU info. */
398 CPUMINFO GuestInfo;
399
400 /** The standard set of CpuId leaves. */
401 CPUMCPUID aGuestCpuIdPatmStd[6];
402 /** The extended set of CpuId leaves. */
403 CPUMCPUID aGuestCpuIdPatmExt[10];
404 /** The centaur set of CpuId leaves. */
405 CPUMCPUID aGuestCpuIdPatmCentaur[4];
406
407 /** @name MSR statistics.
408 * @{ */
409 STAMCOUNTER cMsrWrites;
410 STAMCOUNTER cMsrWritesToIgnoredBits;
411 STAMCOUNTER cMsrWritesRaiseGp;
412 STAMCOUNTER cMsrWritesUnknown;
413 STAMCOUNTER cMsrReads;
414 STAMCOUNTER cMsrReadsRaiseGp;
415 STAMCOUNTER cMsrReadsUnknown;
416 /** @} */
417} CPUM;
418#ifndef VBOX_FOR_DTRACE_LIB
419AssertCompileMemberOffset(CPUM, HostFeatures, 64);
420AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
421#endif
422/** Pointer to the CPUM instance data residing in the shared VM structure. */
423typedef CPUM *PCPUM;
424
425/**
426 * CPUM Data (part of VMCPU)
427 */
428typedef struct CPUMCPU
429{
430 /** Guest context.
431 * Aligned on a 64-byte boundary. */
432 CPUMCTX Guest;
433 /** Guest context - misc MSRs
434 * Aligned on a 64-byte boundary. */
435 CPUMCTXMSRS GuestMsrs;
436
437 /** Nested VMX: VMX-preemption timer. */
438 TMTIMERHANDLE hNestedVmxPreemptTimer;
439
440 /** Use flags.
441 * These flags indicates both what is to be used and what has been used. */
442 uint32_t fUseFlags;
443
444 /** Changed flags.
445 * These flags indicates to REM (and others) which important guest
446 * registers which has been changed since last time the flags were cleared.
447 * See the CPUM_CHANGED_* defines for what we keep track of.
448 *
449 * @todo Obsolete, but will probably be refactored so keep it for reference. */
450 uint32_t fChanged;
451
452 /** Temporary storage for the return code of the function called in the
453 * 32-64 switcher. */
454 uint32_t u32RetCode;
455
456 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
457 * (?) bits are visible or not. (The APIC is responsible for setting this
458 * when loading state, so we won't save it.) */
459 bool fCpuIdApicFeatureVisible;
460
461 /** Align the next member on a 64-byte boundary. */
462 uint8_t abPadding2[64 - 8 - 4*3 - 1];
463
464 /** Saved host context. Only valid while inside RC or HM contexts.
465 * Must be aligned on a 64-byte boundary. */
466 CPUMHOSTCTX Host;
467 /** Old hypervisor context, only used for combined DRx values now.
468 * Must be aligned on a 64-byte boundary. */
469 CPUMHYPERCTX Hyper;
470
471#ifdef VBOX_WITH_CRASHDUMP_MAGIC
472 uint8_t aMagic[56];
473 uint64_t uMagic;
474#endif
475} CPUMCPU;
476#ifndef VBOX_FOR_DTRACE_LIB
477AssertCompileMemberAlignment(CPUMCPU, Host, 64);
478#endif
479/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
480typedef CPUMCPU *PCPUMCPU;
481
482#ifndef VBOX_FOR_DTRACE_LIB
483RT_C_DECLS_BEGIN
484
485PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
486PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
487PCPUMCPUIDLEAF cpumCpuIdGetLeafInt(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
488PCPUMCPUIDLEAF cpumCpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves);
489# ifdef VBOX_STRICT
490void cpumCpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves);
491# endif
492int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs,
493 PCPUMFEATURES pFeatures);
494
495# ifdef IN_RING3
496int cpumR3DbgInit(PVM pVM);
497int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
498void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCFGMNODE pCpumCfg, PCVMXMSRS pHostVmxMsrs,
499 PVMXMSRS pGuestVmxMsrs);
500void cpumR3CpuIdRing3InitDone(PVM pVM);
501void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
502int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
503int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
504DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
505
506int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
507int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
508int cpumR3MsrReconcileWithCpuId(PVM pVM);
509int cpumR3MsrApplyFudge(PVM pVM);
510int cpumR3MsrRegStats(PVM pVM);
511int cpumR3MsrStrictInitChecks(void);
512PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
513# endif
514
515# ifdef IN_RC
516DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
517# endif
518
519# ifdef IN_RING0
520DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
521DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
522# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
523DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
524# endif
525# endif
526
527# if defined(IN_RC) || defined(IN_RING0)
528DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
529DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
530DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
531DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
532# endif
533
534RT_C_DECLS_END
535#endif /* !VBOX_FOR_DTRACE_LIB */
536
537/** @} */
538
539#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
540
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