VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMTests.cpp@ 28800

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1/* $Id: VMMTests.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core, Tests.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18//#define NO_SUPCALLR0VMM
19
20/*******************************************************************************
21* Header Files *
22*******************************************************************************/
23#define LOG_GROUP LOG_GROUP_VMM
24#include <VBox/vmm.h>
25#include <VBox/pdmapi.h>
26#include <VBox/cpum.h>
27#include <VBox/dbg.h>
28#include <VBox/mm.h>
29#include <VBox/trpm.h>
30#include <VBox/selm.h>
31#include "VMMInternal.h"
32#include <VBox/vm.h>
33#include <VBox/err.h>
34#include <VBox/param.h>
35#include <VBox/x86.h>
36#include <VBox/hwaccm.h>
37
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/time.h>
41#include <iprt/stream.h>
42#include <iprt/string.h>
43
44
45/**
46 * Performs a testcase.
47 *
48 * @returns return value from the test.
49 * @param pVM The VM handle.
50 * @param enmTestcase The testcase operation to perform.
51 * @param uVariation The testcase variation id.
52 */
53static int vmmR3DoGCTest(PVM pVM, VMMGCOPERATION enmTestcase, unsigned uVariation)
54{
55 PVMCPU pVCpu = &pVM->aCpus[0];
56
57 RTRCPTR RCPtrEP;
58 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
59 if (RT_FAILURE(rc))
60 return rc;
61
62 CPUMHyperSetCtxCore(pVCpu, NULL);
63 memset(pVCpu->vmm.s.pbEMTStackR3, 0xaa, VMM_STACK_SIZE);
64 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
65 CPUMPushHyper(pVCpu, uVariation);
66 CPUMPushHyper(pVCpu, enmTestcase);
67 CPUMPushHyper(pVCpu, pVM->pVMRC);
68 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
69 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
70 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
71 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
72 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
73 if (RT_LIKELY(rc == VINF_SUCCESS))
74 rc = pVCpu->vmm.s.iLastGZRc;
75 return rc;
76}
77
78
79/**
80 * Performs a trap test.
81 *
82 * @returns Return value from the trap test.
83 * @param pVM The VM handle.
84 * @param u8Trap The trap number to test.
85 * @param uVariation The testcase variation.
86 * @param rcExpect The expected result.
87 * @param u32Eax The expected eax value.
88 * @param pszFaultEIP The fault address. Pass NULL if this isn't available or doesn't apply.
89 * @param pszDesc The test description.
90 */
91static int vmmR3DoTrapTest(PVM pVM, uint8_t u8Trap, unsigned uVariation, int rcExpect, uint32_t u32Eax, const char *pszFaultEIP, const char *pszDesc)
92{
93 PVMCPU pVCpu = &pVM->aCpus[0];
94
95 RTPrintf("VMM: testing 0%x / %d - %s\n", u8Trap, uVariation, pszDesc);
96
97 RTRCPTR RCPtrEP;
98 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
99 if (RT_FAILURE(rc))
100 return rc;
101
102 CPUMHyperSetCtxCore(pVCpu, NULL);
103 memset(pVCpu->vmm.s.pbEMTStackR3, 0xaa, VMM_STACK_SIZE);
104 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
105 CPUMPushHyper(pVCpu, uVariation);
106 CPUMPushHyper(pVCpu, u8Trap + VMMGC_DO_TESTCASE_TRAP_FIRST);
107 CPUMPushHyper(pVCpu, pVM->pVMRC);
108 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
109 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
110 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
111 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
112 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
113 if (RT_LIKELY(rc == VINF_SUCCESS))
114 rc = pVCpu->vmm.s.iLastGZRc;
115 bool fDump = false;
116 if (rc != rcExpect)
117 {
118 RTPrintf("VMM: FAILURE - rc=%Rrc expected %Rrc\n", rc, rcExpect);
119 if (rc != VERR_NOT_IMPLEMENTED)
120 fDump = true;
121 }
122 else if ( rcExpect != VINF_SUCCESS
123 && u8Trap != 8 /* double fault doesn't dare set TrapNo. */
124 && u8Trap != 3 /* guest only, we're not in guest. */
125 && u8Trap != 1 /* guest only, we're not in guest. */
126 && u8Trap != TRPMGetTrapNo(pVCpu))
127 {
128 RTPrintf("VMM: FAILURE - Trap %#x expected %#x\n", TRPMGetTrapNo(pVCpu), u8Trap);
129 fDump = true;
130 }
131 else if (pszFaultEIP)
132 {
133 RTRCPTR RCPtrFault;
134 int rc2 = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, pszFaultEIP, &RCPtrFault);
135 if (RT_FAILURE(rc2))
136 RTPrintf("VMM: FAILURE - Failed to resolve symbol '%s', %Rrc!\n", pszFaultEIP, rc);
137 else if (RCPtrFault != CPUMGetHyperEIP(pVCpu))
138 {
139 RTPrintf("VMM: FAILURE - EIP=%08RX32 expected %RRv (%s)\n", CPUMGetHyperEIP(pVCpu), RCPtrFault, pszFaultEIP);
140 fDump = true;
141 }
142 }
143 else if (rcExpect != VINF_SUCCESS)
144 {
145 if (CPUMGetHyperSS(pVCpu) == SELMGetHyperDS(pVM))
146 RTPrintf("VMM: FAILURE - ss=%x expected %x\n", CPUMGetHyperSS(pVCpu), SELMGetHyperDS(pVM));
147 if (CPUMGetHyperES(pVCpu) == SELMGetHyperDS(pVM))
148 RTPrintf("VMM: FAILURE - es=%x expected %x\n", CPUMGetHyperES(pVCpu), SELMGetHyperDS(pVM));
149 if (CPUMGetHyperDS(pVCpu) == SELMGetHyperDS(pVM))
150 RTPrintf("VMM: FAILURE - ds=%x expected %x\n", CPUMGetHyperDS(pVCpu), SELMGetHyperDS(pVM));
151 if (CPUMGetHyperFS(pVCpu) == SELMGetHyperDS(pVM))
152 RTPrintf("VMM: FAILURE - fs=%x expected %x\n", CPUMGetHyperFS(pVCpu), SELMGetHyperDS(pVM));
153 if (CPUMGetHyperGS(pVCpu) == SELMGetHyperDS(pVM))
154 RTPrintf("VMM: FAILURE - gs=%x expected %x\n", CPUMGetHyperGS(pVCpu), SELMGetHyperDS(pVM));
155 if (CPUMGetHyperEDI(pVCpu) == 0x01234567)
156 RTPrintf("VMM: FAILURE - edi=%x expected %x\n", CPUMGetHyperEDI(pVCpu), 0x01234567);
157 if (CPUMGetHyperESI(pVCpu) == 0x42000042)
158 RTPrintf("VMM: FAILURE - esi=%x expected %x\n", CPUMGetHyperESI(pVCpu), 0x42000042);
159 if (CPUMGetHyperEBP(pVCpu) == 0xffeeddcc)
160 RTPrintf("VMM: FAILURE - ebp=%x expected %x\n", CPUMGetHyperEBP(pVCpu), 0xffeeddcc);
161 if (CPUMGetHyperEBX(pVCpu) == 0x89abcdef)
162 RTPrintf("VMM: FAILURE - ebx=%x expected %x\n", CPUMGetHyperEBX(pVCpu), 0x89abcdef);
163 if (CPUMGetHyperECX(pVCpu) == 0xffffaaaa)
164 RTPrintf("VMM: FAILURE - ecx=%x expected %x\n", CPUMGetHyperECX(pVCpu), 0xffffaaaa);
165 if (CPUMGetHyperEDX(pVCpu) == 0x77778888)
166 RTPrintf("VMM: FAILURE - edx=%x expected %x\n", CPUMGetHyperEDX(pVCpu), 0x77778888);
167 if (CPUMGetHyperEAX(pVCpu) == u32Eax)
168 RTPrintf("VMM: FAILURE - eax=%x expected %x\n", CPUMGetHyperEAX(pVCpu), u32Eax);
169 }
170 if (fDump)
171 VMMR3FatalDump(pVM, pVCpu, rc);
172 return rc;
173}
174
175
176/* execute the switch. */
177VMMR3DECL(int) VMMDoTest(PVM pVM)
178{
179#if 1
180 PVMCPU pVCpu = &pVM->aCpus[0];
181
182#ifdef NO_SUPCALLR0VMM
183 RTPrintf("NO_SUPCALLR0VMM\n");
184 return VINF_SUCCESS;
185#endif
186
187 /*
188 * Setup stack for calling VMMGCEntry().
189 */
190 RTRCPTR RCPtrEP;
191 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
192 if (RT_SUCCESS(rc))
193 {
194 RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
195
196 /*
197 * Test various crashes which we must be able to recover from.
198 */
199 vmmR3DoTrapTest(pVM, 0x3, 0, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3");
200 vmmR3DoTrapTest(pVM, 0x3, 1, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3 WP");
201
202#if defined(DEBUG_bird) /* guess most people would like to skip these since they write to com1. */
203 vmmR3DoTrapTest(pVM, 0x8, 0, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG]");
204 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
205 bool f;
206 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "DoubleFault", &f);
207#if !defined(DEBUG_bird)
208 if (RT_SUCCESS(rc) && f)
209#endif
210 {
211 /* see tripple fault warnings in SELM and VMMGC.cpp. */
212 vmmR3DoTrapTest(pVM, 0x8, 1, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG] WP");
213 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
214 }
215#endif
216
217 vmmR3DoTrapTest(pVM, 0xd, 0, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP");
218 ///@todo find a better \#GP case, on intel ltr will \#PF (busy update?) and not \#GP.
219 //vmmR3DoTrapTest(pVM, 0xd, 1, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP WP");
220
221 vmmR3DoTrapTest(pVM, 0xe, 0, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL)");
222 vmmR3DoTrapTest(pVM, 0xe, 1, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL) WP");
223 vmmR3DoTrapTest(pVM, 0xe, 2, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler");
224 vmmR3DoTrapTest(pVM, 0xe, 4, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler and bad fs");
225
226 /*
227 * Set a debug register and perform a context switch.
228 */
229 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
230 if (rc != VINF_SUCCESS)
231 {
232 RTPrintf("VMM: Nop test failed, rc=%Rrc not VINF_SUCCESS\n", rc);
233 return rc;
234 }
235
236 /* a harmless breakpoint */
237 RTPrintf("VMM: testing hardware bp at 0x10000 (not hit)\n");
238 DBGFADDRESS Addr;
239 DBGFR3AddrFromFlat(pVM, &Addr, 0x10000);
240 RTUINT iBp0;
241 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp0);
242 AssertReleaseRC(rc);
243 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
244 if (rc != VINF_SUCCESS)
245 {
246 RTPrintf("VMM: DR0=0x10000 test failed with rc=%Rrc!\n", rc);
247 return rc;
248 }
249
250 /* a bad one at VMMGCEntry */
251 RTPrintf("VMM: testing hardware bp at VMMGCEntry (hit)\n");
252 DBGFR3AddrFromFlat(pVM, &Addr, RCPtrEP);
253 RTUINT iBp1;
254 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp1);
255 AssertReleaseRC(rc);
256 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
257 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
258 {
259 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
260 return rc;
261 }
262
263 /* resume the breakpoint */
264 RTPrintf("VMM: resuming hyper after breakpoint\n");
265 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF);
266 rc = VMMR3ResumeHyper(pVM, pVCpu);
267 if (rc != VINF_SUCCESS)
268 {
269 RTPrintf("VMM: failed to resume on hyper breakpoint, rc=%Rrc\n", rc);
270 return rc;
271 }
272
273 /* engage the breakpoint again and try single stepping. */
274 RTPrintf("VMM: testing hardware bp at VMMGCEntry + stepping\n");
275 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
276 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
277 {
278 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
279 return rc;
280 }
281
282 RTGCUINTREG OldPc = CPUMGetHyperEIP(pVCpu);
283 RTPrintf("%RGr=>", OldPc);
284 unsigned i;
285 for (i = 0; i < 8; i++)
286 {
287 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
288 rc = VMMR3ResumeHyper(pVM, pVCpu);
289 if (rc != VINF_EM_DBG_HYPER_STEPPED)
290 {
291 RTPrintf("\nVMM: failed to step on hyper breakpoint, rc=%Rrc\n", rc);
292 return rc;
293 }
294 RTGCUINTREG Pc = CPUMGetHyperEIP(pVCpu);
295 RTPrintf("%RGr=>", Pc);
296 if (Pc == OldPc)
297 {
298 RTPrintf("\nVMM: step failed, PC: %RGr -> %RGr\n", OldPc, Pc);
299 return VERR_GENERAL_FAILURE;
300 }
301 OldPc = Pc;
302 }
303 RTPrintf("ok\n");
304
305 /* done, clear it */
306 if ( RT_FAILURE(DBGFR3BpClear(pVM, iBp0))
307 || RT_FAILURE(DBGFR3BpClear(pVM, iBp1)))
308 {
309 RTPrintf("VMM: Failed to clear breakpoints!\n");
310 return VERR_GENERAL_FAILURE;
311 }
312 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
313 if (rc != VINF_SUCCESS)
314 {
315 RTPrintf("VMM: NOP failed, rc=%Rrc\n", rc);
316 return rc;
317 }
318
319 /*
320 * Interrupt masking.
321 */
322 RTPrintf("VMM: interrupt masking...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
323 for (i = 0; i < 10000; i++)
324 {
325 uint64_t StartTick = ASMReadTSC();
326 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_INTERRUPT_MASKING, 0);
327 if (rc != VINF_SUCCESS)
328 {
329 RTPrintf("VMM: Interrupt masking failed: rc=%Rrc\n", rc);
330 return rc;
331 }
332 uint64_t Ticks = ASMReadTSC() - StartTick;
333 if (Ticks < (SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000))
334 RTPrintf("Warning: Ticks=%RU64 (< %RU64)\n", Ticks, SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000);
335 }
336
337 /*
338 * Interrupt forwarding.
339 */
340 CPUMHyperSetCtxCore(pVCpu, NULL);
341 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
342 CPUMPushHyper(pVCpu, 0);
343 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HYPER_INTERRUPT);
344 CPUMPushHyper(pVCpu, pVM->pVMRC);
345 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
346 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
347 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
348 Log(("trampoline=%x\n", pVM->vmm.s.pfnCallTrampolineRC));
349
350 /*
351 * Switch and do da thing.
352 */
353 RTPrintf("VMM: interrupt forwarding...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
354 i = 0;
355 uint64_t tsBegin = RTTimeNanoTS();
356 uint64_t TickStart = ASMReadTSC();
357 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
358 do
359 {
360 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
361 if (RT_LIKELY(rc == VINF_SUCCESS))
362 rc = pVCpu->vmm.s.iLastGZRc;
363 if (RT_FAILURE(rc))
364 {
365 Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
366 VMMR3FatalDump(pVM, pVCpu, rc);
367 return rc;
368 }
369 i++;
370 if (!(i % 32))
371 Log(("VMM: iteration %d, esi=%08x edi=%08x ebx=%08x\n",
372 i, CPUMGetHyperESI(pVCpu), CPUMGetHyperEDI(pVCpu), CPUMGetHyperEBX(pVCpu)));
373 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
374 uint64_t TickEnd = ASMReadTSC();
375 uint64_t tsEnd = RTTimeNanoTS();
376
377 uint64_t Elapsed = tsEnd - tsBegin;
378 uint64_t PerIteration = Elapsed / (uint64_t)i;
379 uint64_t cTicksElapsed = TickEnd - TickStart;
380 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
381
382 RTPrintf("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
383 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration);
384 Log(("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
385 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration));
386
387 /*
388 * These forced actions are not necessary for the test and trigger breakpoints too.
389 */
390 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
391 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
392
393 /*
394 * Profile switching.
395 */
396 RTPrintf("VMM: profiling switcher...\n");
397 Log(("VMM: profiling switcher...\n"));
398 uint64_t TickMin = ~0;
399 tsBegin = RTTimeNanoTS();
400 TickStart = ASMReadTSC();
401 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
402 for (i = 0; i < 1000000; i++)
403 {
404 CPUMHyperSetCtxCore(pVCpu, NULL);
405 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
406 CPUMPushHyper(pVCpu, 0);
407 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_NOP);
408 CPUMPushHyper(pVCpu, pVM->pVMRC);
409 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
410 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
411 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
412
413 uint64_t TickThisStart = ASMReadTSC();
414 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
415 if (RT_LIKELY(rc == VINF_SUCCESS))
416 rc = pVCpu->vmm.s.iLastGZRc;
417 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
418 if (RT_FAILURE(rc))
419 {
420 Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
421 VMMR3FatalDump(pVM, pVCpu, rc);
422 return rc;
423 }
424 if (TickThisElapsed < TickMin)
425 TickMin = TickThisElapsed;
426 }
427 TickEnd = ASMReadTSC();
428 tsEnd = RTTimeNanoTS();
429
430 Elapsed = tsEnd - tsBegin;
431 PerIteration = Elapsed / (uint64_t)i;
432 cTicksElapsed = TickEnd - TickStart;
433 cTicksPerIteration = cTicksElapsed / (uint64_t)i;
434
435 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
436 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
437 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
438 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
439
440 rc = VINF_SUCCESS;
441 }
442 else
443 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
444#endif
445 return rc;
446}
447
448#define SYNC_SEL(pHyperCtx, reg) \
449 if (pHyperCtx->reg) \
450 { \
451 DBGFSELINFO selInfo; \
452 int rc2 = SELMR3GetShadowSelectorInfo(pVM, pHyperCtx->reg, &selInfo); \
453 AssertRC(rc2); \
454 \
455 pHyperCtx->reg##Hid.u64Base = selInfo.GCPtrBase; \
456 pHyperCtx->reg##Hid.u32Limit = selInfo.cbLimit; \
457 pHyperCtx->reg##Hid.Attr.n.u1Present = selInfo.u.Raw.Gen.u1Present; \
458 pHyperCtx->reg##Hid.Attr.n.u1DefBig = selInfo.u.Raw.Gen.u1DefBig; \
459 pHyperCtx->reg##Hid.Attr.n.u1Granularity = selInfo.u.Raw.Gen.u1Granularity; \
460 pHyperCtx->reg##Hid.Attr.n.u4Type = selInfo.u.Raw.Gen.u4Type; \
461 pHyperCtx->reg##Hid.Attr.n.u2Dpl = selInfo.u.Raw.Gen.u2Dpl; \
462 pHyperCtx->reg##Hid.Attr.n.u1DescType = selInfo.u.Raw.Gen.u1DescType; \
463 pHyperCtx->reg##Hid.Attr.n.u1Long = selInfo.u.Raw.Gen.u1Long; \
464 }
465
466/* execute the switch. */
467VMMR3DECL(int) VMMDoHwAccmTest(PVM pVM)
468{
469 uint32_t i;
470 int rc;
471 PCPUMCTX pHyperCtx, pGuestCtx;
472 RTGCPHYS CR3Phys = 0x0; /* fake address */
473 PVMCPU pVCpu = &pVM->aCpus[0];
474
475 if (!HWACCMR3IsAllowed(pVM))
476 {
477 RTPrintf("VMM: Hardware accelerated test not available!\n");
478 return VERR_ACCESS_DENIED;
479 }
480
481 /*
482 * These forced actions are not necessary for the test and trigger breakpoints too.
483 */
484 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
485 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
486
487 /* Enable mapping of the hypervisor into the shadow page table. */
488 uint32_t cb;
489 rc = PGMR3MappingsSize(pVM, &cb);
490 AssertRCReturn(rc, rc);
491
492 /* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
493 rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
494 AssertRCReturn(rc, rc);
495
496 CPUMQueryHyperCtxPtr(pVCpu, &pHyperCtx);
497
498 pHyperCtx->cr0 = X86_CR0_PE | X86_CR0_WP | X86_CR0_PG | X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
499 pHyperCtx->cr4 = X86_CR4_PGE | X86_CR4_OSFSXR | X86_CR4_OSXMMEEXCPT;
500 PGMChangeMode(pVCpu, pHyperCtx->cr0, pHyperCtx->cr4, pHyperCtx->msrEFER);
501 PGMSyncCR3(pVCpu, pHyperCtx->cr0, CR3Phys, pHyperCtx->cr4, true);
502
503 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
504 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
505 VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
506 VM_FF_CLEAR(pVM, VM_FF_REQUEST);
507
508 /*
509 * Setup stack for calling VMMGCEntry().
510 */
511 RTRCPTR RCPtrEP;
512 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
513 if (RT_SUCCESS(rc))
514 {
515 RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
516
517 CPUMQueryHyperCtxPtr(pVCpu, &pHyperCtx);
518
519 /* Fill in hidden selector registers for the hypervisor state. */
520 SYNC_SEL(pHyperCtx, cs);
521 SYNC_SEL(pHyperCtx, ds);
522 SYNC_SEL(pHyperCtx, es);
523 SYNC_SEL(pHyperCtx, fs);
524 SYNC_SEL(pHyperCtx, gs);
525 SYNC_SEL(pHyperCtx, ss);
526 SYNC_SEL(pHyperCtx, tr);
527
528 /*
529 * Profile switching.
530 */
531 RTPrintf("VMM: profiling switcher...\n");
532 Log(("VMM: profiling switcher...\n"));
533 uint64_t TickMin = ~0;
534 uint64_t tsBegin = RTTimeNanoTS();
535 uint64_t TickStart = ASMReadTSC();
536 for (i = 0; i < 1000000; i++)
537 {
538 CPUMHyperSetCtxCore(pVCpu, NULL);
539
540 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
541 CPUMPushHyper(pVCpu, 0);
542 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HWACCM_NOP);
543 CPUMPushHyper(pVCpu, pVM->pVMRC);
544 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
545 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
546 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
547
548 CPUMQueryHyperCtxPtr(pVCpu, &pHyperCtx);
549 pGuestCtx = CPUMQueryGuestCtxPtr(pVCpu);
550
551 /* Copy the hypervisor context to make sure we have a valid guest context. */
552 *pGuestCtx = *pHyperCtx;
553 pGuestCtx->cr3 = CR3Phys;
554
555 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
556 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
557 VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
558
559 uint64_t TickThisStart = ASMReadTSC();
560 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN, 0);
561 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
562 if (RT_FAILURE(rc))
563 {
564 Log(("VMM: R0 returned fatal %Rrc in iteration %d\n", rc, i));
565 VMMR3FatalDump(pVM, pVCpu, rc);
566 return rc;
567 }
568 if (TickThisElapsed < TickMin)
569 TickMin = TickThisElapsed;
570 }
571 uint64_t TickEnd = ASMReadTSC();
572 uint64_t tsEnd = RTTimeNanoTS();
573
574 uint64_t Elapsed = tsEnd - tsBegin;
575 uint64_t PerIteration = Elapsed / (uint64_t)i;
576 uint64_t cTicksElapsed = TickEnd - TickStart;
577 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
578
579 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
580 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
581 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
582 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
583
584 rc = VINF_SUCCESS;
585 }
586 else
587 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
588
589 return rc;
590}
591
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