VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMSwitcher.cpp@ 28800

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1/* $Id: VMMSwitcher.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor, World Switcher(s).
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_VMM
22#include <VBox/vmm.h>
23#include <VBox/pgm.h>
24#include <VBox/selm.h>
25#include <VBox/mm.h>
26#include <VBox/sup.h>
27#include "VMMInternal.h"
28#include "VMMSwitcher/VMMSwitcher.h"
29#include <VBox/vm.h>
30#include <VBox/dis.h>
31
32#include <VBox/err.h>
33#include <VBox/param.h>
34#include <iprt/assert.h>
35#include <iprt/alloc.h>
36#include <iprt/asm.h>
37#include <iprt/string.h>
38#include <iprt/ctype.h>
39
40
41/*******************************************************************************
42* Global Variables *
43*******************************************************************************/
44/** Array of switcher defininitions.
45 * The type and index shall match!
46 */
47static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
48{
49 NULL, /* invalid entry */
50#ifdef VBOX_WITH_RAW_MODE
51# ifndef RT_ARCH_AMD64
52 &vmmR3Switcher32BitTo32Bit_Def,
53 &vmmR3Switcher32BitToPAE_Def,
54 &vmmR3Switcher32BitToAMD64_Def,
55 &vmmR3SwitcherPAETo32Bit_Def,
56 &vmmR3SwitcherPAEToPAE_Def,
57 &vmmR3SwitcherPAEToAMD64_Def,
58 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
59# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
60 &vmmR3SwitcherAMD64ToPAE_Def,
61# else
62 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
63# endif
64 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
65# else /* RT_ARCH_AMD64 */
66 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
67 NULL, //&vmmR3Switcher32BitToPAE_Def,
68 NULL, //&vmmR3Switcher32BitToAMD64_Def,
69 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
70 NULL, //&vmmR3SwitcherPAEToPAE_Def,
71 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
72 &vmmR3SwitcherAMD64To32Bit_Def,
73 &vmmR3SwitcherAMD64ToPAE_Def,
74 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
75# endif /* RT_ARCH_AMD64 */
76#else /* !VBOX_WITH_RAW_MODE */
77 NULL,
78 NULL,
79 NULL,
80 NULL,
81 NULL,
82 NULL,
83 NULL,
84 NULL,
85 NULL
86#endif /* !VBOX_WITH_RAW_MODE */
87};
88
89
90/**
91 * VMMR3Init worker that initiates the switcher code (aka core code).
92 *
93 * This is core per VM code which might need fixups and/or for ease of use are
94 * put on linear contiguous backing.
95 *
96 * @returns VBox status code.
97 * @param pVM Pointer to the shared VM structure.
98 */
99int vmmR3SwitcherInit(PVM pVM)
100{
101#ifndef VBOX_WITH_RAW_MODE
102 return VINF_SUCCESS;
103#else
104 /*
105 * Calc the size.
106 */
107 unsigned cbCoreCode = 0;
108 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
109 {
110 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
111 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
112 if (pSwitcher)
113 {
114 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
115 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
116 }
117 }
118
119 /*
120 * Allocate continguous pages for switchers and deal with
121 * conflicts in the intermediate mapping of the code.
122 */
123 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
124 pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
125 int rc = VERR_NO_MEMORY;
126 if (pVM->vmm.s.pvCoreCodeR3)
127 {
128 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
129 if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
130 {
131 /* try more allocations - Solaris, Linux. */
132 const unsigned cTries = 8234;
133 struct VMMInitBadTry
134 {
135 RTR0PTR pvR0;
136 void *pvR3;
137 RTHCPHYS HCPhys;
138 RTUINT cb;
139 } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
140 AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
141 unsigned i = 0;
142 do
143 {
144 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
145 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
146 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
147 i++;
148 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
149 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
150 pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
151 if (!pVM->vmm.s.pvCoreCodeR3)
152 break;
153 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
154 } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
155 && i < cTries - 1);
156
157 /* cleanup */
158 if (RT_FAILURE(rc))
159 {
160 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
161 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
162 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
163 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
164 i++;
165 LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
166 }
167 while (i-- > 0)
168 {
169 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
170 i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
171 SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
172 }
173 RTMemTmpFree(paBadTries);
174 }
175 }
176 if (RT_SUCCESS(rc))
177 {
178 /*
179 * copy the code.
180 */
181 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
182 {
183 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
184 if (pSwitcher)
185 memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
186 pSwitcher->pvCode, pSwitcher->cbCode);
187 }
188
189 /*
190 * Map the code into the GC address space.
191 */
192 RTGCPTR GCPtr;
193 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
194 cbCoreCode, "Core Code", &GCPtr);
195 if (RT_SUCCESS(rc))
196 {
197 pVM->vmm.s.pvCoreCodeRC = GCPtr;
198 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
199 LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
200 pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
201
202 /*
203 * Finally, PGM probably has selected a switcher already but we need
204 * to get the routine addresses, so we'll reselect it.
205 * This may legally fail so, we're ignoring the rc.
206 */
207 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
208 return rc;
209 }
210
211 /* shit */
212 AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
213 SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
214 }
215 else
216 VMSetError(pVM, rc, RT_SRC_POS,
217 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
218 cbCoreCode);
219
220 pVM->vmm.s.pvCoreCodeR3 = NULL;
221 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
222 pVM->vmm.s.pvCoreCodeRC = 0;
223 return rc;
224#endif
225}
226
227/**
228 * Relocate the switchers, called by VMMR#Relocate.
229 *
230 * @param pVM Pointer to the shared VM structure.
231 * @param offDelta The relocation delta.
232 */
233void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
234{
235#ifdef VBOX_WITH_RAW_MODE
236 /*
237 * Relocate all the switchers.
238 */
239 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
240 {
241 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
242 if (pSwitcher && pSwitcher->pfnRelocate)
243 {
244 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
245 pSwitcher->pfnRelocate(pVM,
246 pSwitcher,
247 pVM->vmm.s.pvCoreCodeR0 + off,
248 (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
249 pVM->vmm.s.pvCoreCodeRC + off,
250 pVM->vmm.s.HCPhysCoreCode + off);
251 }
252 }
253
254 /*
255 * Recalc the RC address for the current switcher.
256 */
257 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
258 RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
259 pVM->vmm.s.pfnGuestToHostRC = RCPtr + pSwitcher->offGCGuestToHost;
260 pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offGCCallTrampoline;
261 pVM->pfnVMMGCGuestToHostAsm = RCPtr + pSwitcher->offGCGuestToHostAsm;
262 pVM->pfnVMMGCGuestToHostAsmHyperCtx = RCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
263 pVM->pfnVMMGCGuestToHostAsmGuestCtx = RCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
264
265// AssertFailed();
266#endif
267}
268
269
270/**
271 * Generic switcher code relocator.
272 *
273 * @param pVM The VM handle.
274 * @param pSwitcher The switcher definition.
275 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
276 * @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
277 * @param GCPtrCode The guest context address corresponding to pu8Code.
278 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
279 * @param SelCS The hypervisor CS selector.
280 * @param SelDS The hypervisor DS selector.
281 * @param SelTSS The hypervisor TSS selector.
282 * @param GCPtrGDT The GC address of the hypervisor GDT.
283 * @param SelCS64 The 64-bit mode hypervisor CS selector.
284 */
285static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
286 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
287{
288 union
289 {
290 const uint8_t *pu8;
291 const uint16_t *pu16;
292 const uint32_t *pu32;
293 const uint64_t *pu64;
294 const void *pv;
295 uintptr_t u;
296 } u;
297 u.pv = pSwitcher->pvFixups;
298
299 /*
300 * Process fixups.
301 */
302 uint8_t u8;
303 while ((u8 = *u.pu8++) != FIX_THE_END)
304 {
305 /*
306 * Get the source (where to write the fixup).
307 */
308 uint32_t offSrc = *u.pu32++;
309 Assert(offSrc < pSwitcher->cbCode);
310 union
311 {
312 uint8_t *pu8;
313 uint16_t *pu16;
314 uint32_t *pu32;
315 uint64_t *pu64;
316 uintptr_t u;
317 } uSrc;
318 uSrc.pu8 = pu8CodeR3 + offSrc;
319
320 /* The fixup target and method depends on the type. */
321 switch (u8)
322 {
323 /*
324 * 32-bit relative, source in HC and target in GC.
325 */
326 case FIX_HC_2_GC_NEAR_REL:
327 {
328 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
329 uint32_t offTrg = *u.pu32++;
330 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
331 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
332 break;
333 }
334
335 /*
336 * 32-bit relative, source in HC and target in ID.
337 */
338 case FIX_HC_2_ID_NEAR_REL:
339 {
340 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
341 uint32_t offTrg = *u.pu32++;
342 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
343 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
344 break;
345 }
346
347 /*
348 * 32-bit relative, source in GC and target in HC.
349 */
350 case FIX_GC_2_HC_NEAR_REL:
351 {
352 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
353 uint32_t offTrg = *u.pu32++;
354 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
355 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
356 break;
357 }
358
359 /*
360 * 32-bit relative, source in GC and target in ID.
361 */
362 case FIX_GC_2_ID_NEAR_REL:
363 {
364 AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
365 uint32_t offTrg = *u.pu32++;
366 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
367 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
368 break;
369 }
370
371 /*
372 * 32-bit relative, source in ID and target in HC.
373 */
374 case FIX_ID_2_HC_NEAR_REL:
375 {
376 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
377 uint32_t offTrg = *u.pu32++;
378 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
379 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
380 break;
381 }
382
383 /*
384 * 32-bit relative, source in ID and target in HC.
385 */
386 case FIX_ID_2_GC_NEAR_REL:
387 {
388 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
389 uint32_t offTrg = *u.pu32++;
390 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
391 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
392 break;
393 }
394
395 /*
396 * 16:32 far jump, target in GC.
397 */
398 case FIX_GC_FAR32:
399 {
400 uint32_t offTrg = *u.pu32++;
401 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
402 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
403 *uSrc.pu16++ = SelCS;
404 break;
405 }
406
407 /*
408 * Make 32-bit GC pointer given CPUM offset.
409 */
410 case FIX_GC_CPUM_OFF:
411 {
412 uint32_t offCPUM = *u.pu32++;
413 Assert(offCPUM < sizeof(pVM->cpum));
414 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
415 break;
416 }
417
418 /*
419 * Make 32-bit GC pointer given CPUMCPU offset.
420 */
421 case FIX_GC_CPUMCPU_OFF:
422 {
423 uint32_t offCPUM = *u.pu32++;
424 Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
425 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
426 break;
427 }
428
429 /*
430 * Make 32-bit GC pointer given VM offset.
431 */
432 case FIX_GC_VM_OFF:
433 {
434 uint32_t offVM = *u.pu32++;
435 Assert(offVM < sizeof(VM));
436 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
437 break;
438 }
439
440 /*
441 * Make 32-bit HC pointer given CPUM offset.
442 */
443 case FIX_HC_CPUM_OFF:
444 {
445 uint32_t offCPUM = *u.pu32++;
446 Assert(offCPUM < sizeof(pVM->cpum));
447 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
448 break;
449 }
450
451 /*
452 * Make 32-bit R0 pointer given VM offset.
453 */
454 case FIX_HC_VM_OFF:
455 {
456 uint32_t offVM = *u.pu32++;
457 Assert(offVM < sizeof(VM));
458 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
459 break;
460 }
461
462 /*
463 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
464 */
465 case FIX_INTER_32BIT_CR3:
466 {
467
468 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
469 break;
470 }
471
472 /*
473 * Store the PAE CR3 (32-bit) for the intermediate memory context.
474 */
475 case FIX_INTER_PAE_CR3:
476 {
477
478 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
479 break;
480 }
481
482 /*
483 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
484 */
485 case FIX_INTER_AMD64_CR3:
486 {
487
488 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
489 break;
490 }
491
492 /*
493 * Store Hypervisor CS (16-bit).
494 */
495 case FIX_HYPER_CS:
496 {
497 *uSrc.pu16 = SelCS;
498 break;
499 }
500
501 /*
502 * Store Hypervisor DS (16-bit).
503 */
504 case FIX_HYPER_DS:
505 {
506 *uSrc.pu16 = SelDS;
507 break;
508 }
509
510 /*
511 * Store Hypervisor TSS (16-bit).
512 */
513 case FIX_HYPER_TSS:
514 {
515 *uSrc.pu16 = SelTSS;
516 break;
517 }
518
519 /*
520 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
521 */
522 case FIX_GC_TSS_GDTE_DW2:
523 {
524 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
525 *uSrc.pu32 = (uint32_t)GCPtr;
526 break;
527 }
528
529
530 ///@todo case FIX_CR4_MASK:
531 ///@todo case FIX_CR4_OSFSXR:
532
533 /*
534 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
535 */
536 case FIX_NO_FXSAVE_JMP:
537 {
538 uint32_t offTrg = *u.pu32++;
539 Assert(offTrg < pSwitcher->cbCode);
540 if (!CPUMSupportsFXSR(pVM))
541 {
542 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
543 *uSrc.pu32++ = offTrg - (offSrc + 5);
544 }
545 else
546 {
547 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
548 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
549 }
550 break;
551 }
552
553 /*
554 * Insert relative jump to specified target it SYSENTER isn't used by the host.
555 */
556 case FIX_NO_SYSENTER_JMP:
557 {
558 uint32_t offTrg = *u.pu32++;
559 Assert(offTrg < pSwitcher->cbCode);
560 if (!CPUMIsHostUsingSysEnter(pVM))
561 {
562 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
563 *uSrc.pu32++ = offTrg - (offSrc + 5);
564 }
565 else
566 {
567 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
568 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
569 }
570 break;
571 }
572
573 /*
574 * Insert relative jump to specified target it SYSCALL isn't used by the host.
575 */
576 case FIX_NO_SYSCALL_JMP:
577 {
578 uint32_t offTrg = *u.pu32++;
579 Assert(offTrg < pSwitcher->cbCode);
580 if (!CPUMIsHostUsingSysCall(pVM))
581 {
582 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
583 *uSrc.pu32++ = offTrg - (offSrc + 5);
584 }
585 else
586 {
587 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
588 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
589 }
590 break;
591 }
592
593 /*
594 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
595 */
596 case FIX_HC_32BIT:
597 {
598 uint32_t offTrg = *u.pu32++;
599 Assert(offSrc < pSwitcher->cbCode);
600 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
601 *uSrc.pu32 = R0PtrCode + offTrg;
602 break;
603 }
604
605#if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
606 /*
607 * 64-bit HC Code Selector (no argument).
608 */
609 case FIX_HC_64BIT_CS:
610 {
611 Assert(offSrc < pSwitcher->cbCode);
612# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
613 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
614# else
615 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
616# endif
617 break;
618 }
619
620 /*
621 * 64-bit HC pointer to the CPUM instance data (no argument).
622 */
623 case FIX_HC_64BIT_CPUM:
624 {
625 Assert(offSrc < pSwitcher->cbCode);
626 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
627 break;
628 }
629#endif
630 /*
631 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
632 */
633 case FIX_HC_64BIT:
634 {
635 uint32_t offTrg = *u.pu32++;
636 Assert(offSrc < pSwitcher->cbCode);
637 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
638 *uSrc.pu64 = R0PtrCode + offTrg;
639 break;
640 }
641
642#ifdef RT_ARCH_X86
643 case FIX_GC_64_BIT_CPUM_OFF:
644 {
645 uint32_t offCPUM = *u.pu32++;
646 Assert(offCPUM < sizeof(pVM->cpum));
647 *uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
648 break;
649 }
650#endif
651
652 /*
653 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
654 */
655 case FIX_ID_32BIT:
656 {
657 uint32_t offTrg = *u.pu32++;
658 Assert(offSrc < pSwitcher->cbCode);
659 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
660 *uSrc.pu32 = u32IDCode + offTrg;
661 break;
662 }
663
664 /*
665 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
666 */
667 case FIX_ID_64BIT:
668 case FIX_HC_64BIT_NOCHECK:
669 {
670 uint32_t offTrg = *u.pu32++;
671 Assert(offSrc < pSwitcher->cbCode);
672 Assert(u8 == FIX_HC_64BIT_NOCHECK || offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
673 *uSrc.pu64 = u32IDCode + offTrg;
674 break;
675 }
676
677 /*
678 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
679 */
680 case FIX_ID_FAR32_TO_64BIT_MODE:
681 {
682 uint32_t offTrg = *u.pu32++;
683 Assert(offSrc < pSwitcher->cbCode);
684 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
685 *uSrc.pu32++ = u32IDCode + offTrg;
686 *uSrc.pu16 = SelCS64;
687 AssertRelease(SelCS64);
688 break;
689 }
690
691#ifdef VBOX_WITH_NMI
692 /*
693 * 32-bit address to the APIC base.
694 */
695 case FIX_GC_APIC_BASE_32BIT:
696 {
697 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
698 break;
699 }
700#endif
701
702 default:
703 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
704 break;
705 }
706 }
707
708#ifdef LOG_ENABLED
709 /*
710 * If Log2 is enabled disassemble the switcher code.
711 *
712 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
713 */
714 if (LogIs2Enabled())
715 {
716 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
717 " R0PtrCode = %p\n"
718 " pu8CodeR3 = %p\n"
719 " GCPtrCode = %RGv\n"
720 " u32IDCode = %08x\n"
721 " pVMRC = %RRv\n"
722 " pCPUMRC = %RRv\n"
723 " pVMR3 = %p\n"
724 " pCPUMR3 = %p\n"
725 " GCPtrGDT = %RGv\n"
726 " InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
727 " HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
728 " SelCS = %04x\n"
729 " SelDS = %04x\n"
730 " SelCS64 = %04x\n"
731 " SelTSS = %04x\n",
732 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
733 R0PtrCode,
734 pu8CodeR3,
735 GCPtrCode,
736 u32IDCode,
737 VM_RC_ADDR(pVM, pVM),
738 VM_RC_ADDR(pVM, &pVM->cpum),
739 pVM,
740 &pVM->cpum,
741 GCPtrGDT,
742 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
743 PGMGetHyperCR3(VMMGetCpu(pVM)),
744 SelCS, SelDS, SelCS64, SelTSS);
745
746 uint32_t offCode = 0;
747 while (offCode < pSwitcher->cbCode)
748 {
749 /*
750 * Figure out where this is.
751 */
752 const char *pszDesc = NULL;
753 RTUINTPTR uBase;
754 uint32_t cbCode;
755 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
756 {
757 pszDesc = "HCCode0";
758 uBase = R0PtrCode;
759 offCode = pSwitcher->offHCCode0;
760 cbCode = pSwitcher->cbHCCode0;
761 }
762 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
763 {
764 pszDesc = "HCCode1";
765 uBase = R0PtrCode;
766 offCode = pSwitcher->offHCCode1;
767 cbCode = pSwitcher->cbHCCode1;
768 }
769 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
770 {
771 pszDesc = "GCCode";
772 uBase = GCPtrCode;
773 offCode = pSwitcher->offGCCode;
774 cbCode = pSwitcher->cbGCCode;
775 }
776 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
777 {
778 pszDesc = "IDCode0";
779 uBase = u32IDCode;
780 offCode = pSwitcher->offIDCode0;
781 cbCode = pSwitcher->cbIDCode0;
782 }
783 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
784 {
785 pszDesc = "IDCode1";
786 uBase = u32IDCode;
787 offCode = pSwitcher->offIDCode1;
788 cbCode = pSwitcher->cbIDCode1;
789 }
790 else
791 {
792 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
793 offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
794 offCode++;
795 continue;
796 }
797
798 /*
799 * Disassemble it.
800 */
801 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
802 DISCPUSTATE Cpu;
803
804 memset(&Cpu, 0, sizeof(Cpu));
805 Cpu.mode = CPUMODE_32BIT;
806 while (cbCode > 0)
807 {
808 /* try label it */
809 if (pSwitcher->offR0HostToGuest == offCode)
810 RTLogPrintf(" *R0HostToGuest:\n");
811 if (pSwitcher->offGCGuestToHost == offCode)
812 RTLogPrintf(" *GCGuestToHost:\n");
813 if (pSwitcher->offGCCallTrampoline == offCode)
814 RTLogPrintf(" *GCCallTrampoline:\n");
815 if (pSwitcher->offGCGuestToHostAsm == offCode)
816 RTLogPrintf(" *GCGuestToHostAsm:\n");
817 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
818 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
819 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
820 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
821
822 /* disas */
823 uint32_t cbInstr = 0;
824 char szDisas[256];
825 if (RT_SUCCESS(DISInstr(&Cpu, (uintptr_t)pu8CodeR3 + offCode, uBase - (uintptr_t)pu8CodeR3, &cbInstr, szDisas)))
826 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
827 else
828 {
829 RTLogPrintf(" %04x: %02x '%c'\n",
830 offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
831 cbInstr = 1;
832 }
833 offCode += cbInstr;
834 cbCode -= RT_MIN(cbInstr, cbCode);
835 }
836 }
837 }
838#endif
839}
840
841
842/**
843 * Relocator for the 32-Bit to 32-Bit world switcher.
844 */
845DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
846{
847 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
848 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
849}
850
851
852/**
853 * Relocator for the 32-Bit to PAE world switcher.
854 */
855DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
856{
857 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
858 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
859}
860
861
862/**
863 * Relocator for the 32-Bit to AMD64 world switcher.
864 */
865DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
866{
867 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
868 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
869}
870
871
872/**
873 * Relocator for the PAE to 32-Bit world switcher.
874 */
875DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
876{
877 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
878 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
879}
880
881
882/**
883 * Relocator for the PAE to PAE world switcher.
884 */
885DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
886{
887 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
888 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
889}
890
891/**
892 * Relocator for the PAE to AMD64 world switcher.
893 */
894DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
895{
896 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
897 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
898}
899
900
901/**
902 * Relocator for the AMD64 to 32-bit world switcher.
903 */
904DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
905{
906 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
907 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
908}
909
910
911/**
912 * Relocator for the AMD64 to PAE world switcher.
913 */
914DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
915{
916 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
917 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
918}
919
920
921/**
922 * Selects the switcher to be used for switching to GC.
923 *
924 * @returns VBox status code.
925 * @param pVM VM handle.
926 * @param enmSwitcher The new switcher.
927 * @remark This function may be called before the VMM is initialized.
928 */
929VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
930{
931 /*
932 * Validate input.
933 */
934 if ( enmSwitcher < VMMSWITCHER_INVALID
935 || enmSwitcher >= VMMSWITCHER_MAX)
936 {
937 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
938 return VERR_INVALID_PARAMETER;
939 }
940
941 /* Do nothing if the switcher is disabled. */
942 if (pVM->vmm.s.fSwitcherDisabled)
943 return VINF_SUCCESS;
944
945 /*
946 * Select the new switcher.
947 */
948 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
949 if (pSwitcher)
950 {
951 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
952 pVM->vmm.s.enmSwitcher = enmSwitcher;
953
954 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
955 pVM->vmm.s.pfnHostToGuestR0 = pbCodeR0 + pSwitcher->offR0HostToGuest;
956
957 RTGCPTR GCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
958 pVM->vmm.s.pfnGuestToHostRC = GCPtr + pSwitcher->offGCGuestToHost;
959 pVM->vmm.s.pfnCallTrampolineRC = GCPtr + pSwitcher->offGCCallTrampoline;
960 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
961 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
962 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
963 return VINF_SUCCESS;
964 }
965
966 return VERR_NOT_IMPLEMENTED;
967}
968
969
970/**
971 * Disable the switcher logic permanently.
972 *
973 * @returns VBox status code.
974 * @param pVM VM handle.
975 */
976VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
977{
978/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
979 * @code
980 * mov eax, VERR_INTERNAL_ERROR
981 * ret
982 * @endcode
983 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
984 */
985 pVM->vmm.s.fSwitcherDisabled = true;
986 return VINF_SUCCESS;
987}
988
989
990/**
991 * Gets the switcher to be used for switching to GC.
992 *
993 * @returns host to guest ring 0 switcher entrypoint
994 * @param pVM VM handle.
995 * @param enmSwitcher The new switcher.
996 */
997VMMR3DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
998{
999 /*
1000 * Validate input.
1001 */
1002 if ( enmSwitcher < VMMSWITCHER_INVALID
1003 || enmSwitcher >= VMMSWITCHER_MAX)
1004 {
1005 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1006 return NIL_RTR0PTR;
1007 }
1008
1009 /*
1010 * Select the new switcher.
1011 */
1012 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1013 if (pSwitcher)
1014 {
1015 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1016 return pbCodeR0 + pSwitcher->offR0HostToGuest;
1017 }
1018 return NIL_RTR0PTR;
1019}
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