| 1 | ; $Id: CPUMRCA.asm 69221 2017-10-24 15:07:46Z vboxsync $
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| 2 | ;; @file
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| 3 | ; CPUM - Raw-mode Context Assembly Routines.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2006-2017 Oracle Corporation
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 |
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| 18 | ;*******************************************************************************
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| 19 | ;* Header Files *
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| 20 | ;*******************************************************************************
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| 21 | %include "VMMRC.mac"
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| 22 | %include "VBox/vmm/vm.mac"
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| 23 | %include "VBox/err.mac"
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| 24 | %include "VBox/vmm/stam.mac"
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| 25 | %include "CPUMInternal.mac"
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| 26 | %include "iprt/x86.mac"
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| 27 | %include "VBox/vmm/cpum.mac"
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| 28 |
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| 29 |
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| 30 | ;*******************************************************************************
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| 31 | ;* External Symbols *
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| 32 | ;*******************************************************************************
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| 33 | extern IMPNAME(g_CPUM) ; VMM GC Builtin import
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| 34 | extern IMPNAME(g_VM) ; VMM GC Builtin import
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| 35 | extern NAME(cpumRCHandleNPAndGP) ; CPUMGC.cpp
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| 36 | extern NAME(CPUMRCAssertPreExecutionSanity)
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| 37 |
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| 38 |
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| 39 | ;
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| 40 | ; Enables write protection of Hypervisor memory pages.
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| 41 | ; !note! Must be commented out for Trap8 debug handler.
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| 42 | ;
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| 43 | %define ENABLE_WRITE_PROTECTION 1
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| 44 |
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| 45 | BEGINCODE
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| 46 |
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| 47 |
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| 48 | ;;
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| 49 | ; Handles lazy FPU saving and restoring.
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| 50 | ;
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| 51 | ; This handler will implement lazy fpu (sse/mmx/stuff) saving.
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| 52 | ; Two actions may be taken in this handler since the Guest OS may
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| 53 | ; be doing lazy fpu switching. So, we'll have to generate those
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| 54 | ; traps which the Guest CPU CTX shall have according to the
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| 55 | ; its CR0 flags. If no traps for the Guest OS, we'll save the host
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| 56 | ; context and restore the guest context.
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| 57 | ;
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| 58 | ; @returns 0 if caller should continue execution.
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| 59 | ; @returns VINF_EM_RAW_GUEST_TRAP if a guest trap should be generated.
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| 60 | ; @param pCpumCpu [ebp+8] Pointer to the CPUMCPU.
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| 61 | ;
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| 62 | align 16
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| 63 | BEGINPROC cpumHandleLazyFPUAsm
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| 64 | push ebp
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| 65 | mov ebp, esp
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| 66 | push ebx
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| 67 | push esi
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| 68 | mov ebx, [ebp + 8]
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| 69 | %define pCpumCpu ebx
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| 70 | %define pXState esi
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| 71 |
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| 72 | ;
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| 73 | ; Figure out what to do.
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| 74 | ;
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| 75 | ; There are two basic actions:
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| 76 | ; 1. Save host fpu and restore guest fpu.
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| 77 | ; 2. Generate guest trap.
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| 78 | ;
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| 79 | ; When entering the hypervisor we'll always enable MP (for proper wait
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| 80 | ; trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
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| 81 | ; is taken from the guest OS in order to get proper SSE handling.
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| 82 | ;
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| 83 | ;
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| 84 | ; Actions taken depending on the guest CR0 flags:
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| 85 | ;
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| 86 | ; 3 2 1
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| 87 | ; TS | EM | MP | FPUInstr | WAIT :: VMM Action
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| 88 | ; ------------------------------------------------------------------------
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| 89 | ; 0 | 0 | 0 | Exec | Exec :: Clear TS & MP, Save HC, Load GC.
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| 90 | ; 0 | 0 | 1 | Exec | Exec :: Clear TS, Save HC, Load GC.
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| 91 | ; 0 | 1 | 0 | #NM | Exec :: Clear TS & MP, Save HC, Load GC;
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| 92 | ; 0 | 1 | 1 | #NM | Exec :: Clear TS, Save HC, Load GC.
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| 93 | ; 1 | 0 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
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| 94 | ; 1 | 0 | 1 | #NM | #NM :: Go to host taking trap there.
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| 95 | ; 1 | 1 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
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| 96 | ; 1 | 1 | 1 | #NM | #NM :: Go to host taking trap there.
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| 97 |
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| 98 | ;
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| 99 | ; Before taking any of these actions we're checking if we have already
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| 100 | ; loaded the GC FPU. Because if we have, this is an trap for the guest - raw ring-3.
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| 101 | ;
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| 102 | test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USED_FPU_GUEST
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| 103 | jz hlfpua_not_loaded
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| 104 | jmp hlfpua_guest_trap
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| 105 |
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| 106 | ;
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| 107 | ; Take action.
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| 108 | ;
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| 109 | align 16
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| 110 | hlfpua_not_loaded:
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| 111 | mov eax, [pCpumCpu + CPUMCPU.Guest.cr0]
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| 112 | and eax, X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
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| 113 | jmp dword [eax*2 + hlfpuajmp1]
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| 114 | align 16
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| 115 | ;; jump table using fpu related cr0 flags as index.
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| 116 | hlfpuajmp1:
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| 117 | RTCCPTR_DEF hlfpua_switch_fpu_ctx
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| 118 | RTCCPTR_DEF hlfpua_switch_fpu_ctx
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| 119 | RTCCPTR_DEF hlfpua_switch_fpu_ctx
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| 120 | RTCCPTR_DEF hlfpua_switch_fpu_ctx
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| 121 | RTCCPTR_DEF hlfpua_switch_fpu_ctx
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| 122 | RTCCPTR_DEF hlfpua_guest_trap
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| 123 | RTCCPTR_DEF hlfpua_switch_fpu_ctx
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| 124 | RTCCPTR_DEF hlfpua_guest_trap
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| 125 | ;; and mask for cr0.
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| 126 | hlfpu_afFlags:
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| 127 | RTCCPTR_DEF ~(X86_CR0_TS | X86_CR0_MP)
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| 128 | RTCCPTR_DEF ~(X86_CR0_TS)
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| 129 | RTCCPTR_DEF ~(X86_CR0_TS | X86_CR0_MP)
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| 130 | RTCCPTR_DEF ~(X86_CR0_TS)
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| 131 | RTCCPTR_DEF ~(X86_CR0_MP)
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| 132 | RTCCPTR_DEF 0
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| 133 | RTCCPTR_DEF ~(X86_CR0_MP)
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| 134 | RTCCPTR_DEF 0
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| 135 |
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| 136 | ;
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| 137 | ; Action - switch FPU context and change cr0 flags.
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| 138 | ;
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| 139 | align 16
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| 140 | hlfpua_switch_fpu_ctx:
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| 141 | mov ecx, cr0
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| 142 | mov edx, ecx
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| 143 | and ecx, [eax*2 + hlfpu_afFlags] ; Calc the new cr0 flags. Do NOT use ECX until we restore it!
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| 144 | and edx, ~(X86_CR0_TS | X86_CR0_EM)
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| 145 | mov cr0, edx ; Clear flags so we don't trap here.
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| 146 |
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| 147 | test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USED_FPU_HOST
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| 148 | jnz hlfpua_host_done
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| 149 |
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| 150 | mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
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| 151 | mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateRC]
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| 152 | or eax, eax
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| 153 | jz hlfpua_host_fxsave
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| 154 | mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
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| 155 | xsave [pXState]
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| 156 | jmp hlfpua_host_done
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| 157 | hlfpua_host_fxsave:
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| 158 | fxsave [pXState]
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| 159 | hlfpua_host_done:
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| 160 |
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| 161 | mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
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| 162 | mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateRC]
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| 163 | or eax, eax
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| 164 | jz hlfpua_guest_fxrstor
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| 165 | mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
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| 166 | xrstor [pXState]
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| 167 | jmp hlfpua_guest_done
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| 168 | hlfpua_guest_fxrstor:
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| 169 | fxrstor [pXState]
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| 170 | hlfpua_guest_done:
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| 171 |
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| 172 | hlfpua_finished_switch:
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| 173 | or dword [pCpumCpu + CPUMCPU.fUseFlags], (CPUM_USED_FPU_HOST | CPUM_USED_FPU_GUEST | CPUM_USED_FPU_SINCE_REM)
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| 174 |
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| 175 | ; Load new CR0 value.
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| 176 | mov cr0, ecx ; load the new cr0 flags.
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| 177 |
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| 178 | ; return continue execution.
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| 179 | pop esi
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| 180 | pop ebx
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| 181 | xor eax, eax
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| 182 | leave
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| 183 | ret
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| 184 |
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| 185 | ;
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| 186 | ; Action - Generate Guest trap.
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| 187 | ;
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| 188 | hlfpua_action_4:
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| 189 | hlfpua_guest_trap:
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| 190 | pop esi
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| 191 | pop ebx
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| 192 | mov eax, VINF_EM_RAW_GUEST_TRAP
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| 193 | leave
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| 194 | ret
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| 195 | ENDPROC cpumHandleLazyFPUAsm
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| 196 |
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| 197 |
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| 198 | ;;
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| 199 | ; Calls a guest trap/interrupt handler directly
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| 200 | ; Assumes a trap stack frame has already been setup on the guest's stack!
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| 201 | ;
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| 202 | ; @param pRegFrame [esp + 4] Original trap/interrupt context
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| 203 | ; @param selCS [esp + 8] Code selector of handler
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| 204 | ; @param pHandler [esp + 12] GC virtual address of handler
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| 205 | ; @param eflags [esp + 16] Callee's EFLAGS
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| 206 | ; @param selSS [esp + 20] Stack selector for handler
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| 207 | ; @param pEsp [esp + 24] Stack address for handler
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| 208 | ;
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| 209 | ; @remark This call never returns!
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| 210 | ;
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| 211 | ; VMMRCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
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| 212 | align 16
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| 213 | BEGINPROC_EXPORTED CPUMGCCallGuestTrapHandler
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| 214 | mov ebp, esp
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| 215 |
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| 216 | ; construct iret stack frame
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| 217 | push dword [ebp + 20] ; SS
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| 218 | push dword [ebp + 24] ; ESP
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| 219 | push dword [ebp + 16] ; EFLAGS
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| 220 | push dword [ebp + 8] ; CS
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| 221 | push dword [ebp + 12] ; EIP
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| 222 |
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| 223 | ;
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| 224 | ; enable WP
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| 225 | ;
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| 226 | %ifdef ENABLE_WRITE_PROTECTION
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| 227 | mov eax, cr0
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| 228 | or eax, X86_CR0_WRITE_PROTECT
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| 229 | mov cr0, eax
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| 230 | %endif
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| 231 |
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| 232 | ; restore CPU context (all except cs, eip, ss, esp & eflags; which are restored or overwritten by iret)
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| 233 | mov ebp, [ebp + 4] ; pRegFrame
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| 234 | mov ebx, [ebp + CPUMCTXCORE.ebx]
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| 235 | mov ecx, [ebp + CPUMCTXCORE.ecx]
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| 236 | mov edx, [ebp + CPUMCTXCORE.edx]
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| 237 | mov esi, [ebp + CPUMCTXCORE.esi]
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| 238 | mov edi, [ebp + CPUMCTXCORE.edi]
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| 239 |
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| 240 | ;; @todo load segment registers *before* enabling WP.
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| 241 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_GS | CPUM_HANDLER_CTXCORE_IN_EBP
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| 242 | mov gs, [ebp + CPUMCTXCORE.gs.Sel]
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| 243 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_FS | CPUM_HANDLER_CTXCORE_IN_EBP
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| 244 | mov fs, [ebp + CPUMCTXCORE.fs.Sel]
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| 245 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_ES | CPUM_HANDLER_CTXCORE_IN_EBP
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| 246 | mov es, [ebp + CPUMCTXCORE.es.Sel]
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| 247 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_DS | CPUM_HANDLER_CTXCORE_IN_EBP
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| 248 | mov ds, [ebp + CPUMCTXCORE.ds.Sel]
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| 249 |
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| 250 | mov eax, [ebp + CPUMCTXCORE.eax]
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| 251 | mov ebp, [ebp + CPUMCTXCORE.ebp]
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| 252 |
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| 253 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_IRET
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| 254 | iret
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| 255 | ENDPROC CPUMGCCallGuestTrapHandler
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| 256 |
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| 257 |
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| 258 | ;;
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| 259 | ; Performs an iret to V86 code
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| 260 | ; Assumes a trap stack frame has already been setup on the guest's stack!
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| 261 | ;
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| 262 | ; @param pRegFrame Original trap/interrupt context
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| 263 | ;
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| 264 | ; This function does not return!
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| 265 | ;
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| 266 | ;VMMRCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
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| 267 | align 16
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| 268 | BEGINPROC CPUMGCCallV86Code
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| 269 | push ebp
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| 270 | mov ebp, esp
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| 271 | mov ebx, [ebp + 8] ; pRegFrame
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| 272 |
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| 273 | ; Construct iret stack frame.
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| 274 | push dword [ebx + CPUMCTXCORE.gs.Sel]
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| 275 | push dword [ebx + CPUMCTXCORE.fs.Sel]
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| 276 | push dword [ebx + CPUMCTXCORE.ds.Sel]
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| 277 | push dword [ebx + CPUMCTXCORE.es.Sel]
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| 278 | push dword [ebx + CPUMCTXCORE.ss.Sel]
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| 279 | push dword [ebx + CPUMCTXCORE.esp]
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| 280 | push dword [ebx + CPUMCTXCORE.eflags]
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| 281 | push dword [ebx + CPUMCTXCORE.cs.Sel]
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| 282 | push dword [ebx + CPUMCTXCORE.eip]
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| 283 |
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| 284 | ; Invalidate all segment registers.
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| 285 | mov al, ~CPUMSELREG_FLAGS_VALID
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| 286 | and [ebx + CPUMCTXCORE.fs.fFlags], al
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| 287 | and [ebx + CPUMCTXCORE.ds.fFlags], al
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| 288 | and [ebx + CPUMCTXCORE.es.fFlags], al
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| 289 | and [ebx + CPUMCTXCORE.ss.fFlags], al
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| 290 | and [ebx + CPUMCTXCORE.gs.fFlags], al
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| 291 | and [ebx + CPUMCTXCORE.cs.fFlags], al
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| 292 |
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| 293 | ;
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| 294 | ; enable WP
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| 295 | ;
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| 296 | %ifdef ENABLE_WRITE_PROTECTION
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| 297 | mov eax, cr0
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| 298 | or eax, X86_CR0_WRITE_PROTECT
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| 299 | mov cr0, eax
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| 300 | %endif
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| 301 |
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| 302 | ; restore CPU context (all except cs, eip, ss, esp, eflags, ds, es, fs & gs; which are restored or overwritten by iret)
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| 303 | mov eax, [ebx + CPUMCTXCORE.eax]
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| 304 | mov ecx, [ebx + CPUMCTXCORE.ecx]
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| 305 | mov edx, [ebx + CPUMCTXCORE.edx]
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| 306 | mov esi, [ebx + CPUMCTXCORE.esi]
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| 307 | mov edi, [ebx + CPUMCTXCORE.edi]
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| 308 | mov ebp, [ebx + CPUMCTXCORE.ebp]
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| 309 | mov ebx, [ebx + CPUMCTXCORE.ebx]
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| 310 |
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| 311 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_IRET
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| 312 | iret
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| 313 | ENDPROC CPUMGCCallV86Code
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| 314 |
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| 315 |
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| 316 | ;;
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| 317 | ; This is a main entry point for resuming (or starting) guest
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| 318 | ; code execution.
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| 319 | ;
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| 320 | ; We get here directly from VMMSwitcher.asm (jmp at the end
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| 321 | ; of VMMSwitcher_HostToGuest).
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| 322 | ;
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| 323 | ; This call never returns!
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| 324 | ;
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| 325 | ; @param edx Pointer to CPUMCPU structure.
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| 326 | ;
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| 327 | align 16
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| 328 | BEGINPROC_EXPORTED CPUMGCResumeGuest
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| 329 | %ifdef VBOX_STRICT
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| 330 | ; Call CPUM to check sanity.
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| 331 | push edx
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| 332 | mov edx, IMP(g_VM)
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| 333 | push edx
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| 334 | call NAME(CPUMRCAssertPreExecutionSanity)
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| 335 | add esp, 4
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| 336 | pop edx
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| 337 | %endif
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| 338 |
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| 339 | ;
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| 340 | ; Setup iretd
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| 341 | ;
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| 342 | push dword [edx + CPUMCPU.Guest.ss.Sel]
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| 343 | push dword [edx + CPUMCPU.Guest.esp]
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| 344 | push dword [edx + CPUMCPU.Guest.eflags]
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| 345 | push dword [edx + CPUMCPU.Guest.cs.Sel]
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| 346 | push dword [edx + CPUMCPU.Guest.eip]
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| 347 |
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| 348 | ;
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| 349 | ; Restore registers.
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| 350 | ;
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| 351 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_ES
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| 352 | mov es, [edx + CPUMCPU.Guest.es.Sel]
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| 353 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_FS
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| 354 | mov fs, [edx + CPUMCPU.Guest.fs.Sel]
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| 355 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_GS
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| 356 | mov gs, [edx + CPUMCPU.Guest.gs.Sel]
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| 357 |
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| 358 | %ifdef VBOX_WITH_STATISTICS
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| 359 | ;
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| 360 | ; Statistics.
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| 361 | ;
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| 362 | push edx
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| 363 | mov edx, IMP(g_VM)
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| 364 | lea edx, [edx + VM.StatTotalQemuToGC]
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| 365 | STAM_PROFILE_ADV_STOP edx
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| 366 |
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| 367 | mov edx, IMP(g_VM)
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| 368 | lea edx, [edx + VM.StatTotalInGC]
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| 369 | STAM_PROFILE_ADV_START edx
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| 370 | pop edx
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| 371 | %endif
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| 372 |
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| 373 | ;
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| 374 | ; enable WP
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| 375 | ;
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| 376 | %ifdef ENABLE_WRITE_PROTECTION
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| 377 | mov eax, cr0
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| 378 | or eax, X86_CR0_WRITE_PROTECT
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| 379 | mov cr0, eax
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| 380 | %endif
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| 381 |
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| 382 | ;
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| 383 | ; Continue restore.
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| 384 | ;
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| 385 | mov esi, [edx + CPUMCPU.Guest.esi]
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| 386 | mov edi, [edx + CPUMCPU.Guest.edi]
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| 387 | mov ebp, [edx + CPUMCPU.Guest.ebp]
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| 388 | mov ebx, [edx + CPUMCPU.Guest.ebx]
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| 389 | mov ecx, [edx + CPUMCPU.Guest.ecx]
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| 390 | mov eax, [edx + CPUMCPU.Guest.eax]
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| 391 | push dword [edx + CPUMCPU.Guest.ds.Sel]
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| 392 | mov edx, [edx + CPUMCPU.Guest.edx]
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| 393 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_DS
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| 394 | pop ds
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| 395 |
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| 396 | ; restart execution.
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| 397 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_IRET
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| 398 | iretd
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| 399 | ENDPROC CPUMGCResumeGuest
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| 400 |
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| 401 |
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| 402 | ;;
|
|---|
| 403 | ; This is a main entry point for resuming (or starting) guest
|
|---|
| 404 | ; code execution for raw V86 mode
|
|---|
| 405 | ;
|
|---|
| 406 | ; We get here directly from VMMSwitcher.asm (jmp at the end
|
|---|
| 407 | ; of VMMSwitcher_HostToGuest).
|
|---|
| 408 | ;
|
|---|
| 409 | ; This call never returns!
|
|---|
| 410 | ;
|
|---|
| 411 | ; @param edx Pointer to CPUMCPU structure.
|
|---|
| 412 | ;
|
|---|
| 413 | align 16
|
|---|
| 414 | BEGINPROC_EXPORTED CPUMGCResumeGuestV86
|
|---|
| 415 | %ifdef VBOX_STRICT
|
|---|
| 416 | ; Call CPUM to check sanity.
|
|---|
| 417 | push edx
|
|---|
| 418 | mov edx, IMP(g_VM)
|
|---|
| 419 | push edx
|
|---|
| 420 | call NAME(CPUMRCAssertPreExecutionSanity)
|
|---|
| 421 | add esp, 4
|
|---|
| 422 | pop edx
|
|---|
| 423 | %endif
|
|---|
| 424 |
|
|---|
| 425 | ;
|
|---|
| 426 | ; Setup iretd
|
|---|
| 427 | ;
|
|---|
| 428 | push dword [edx + CPUMCPU.Guest.gs.Sel]
|
|---|
| 429 | push dword [edx + CPUMCPU.Guest.fs.Sel]
|
|---|
| 430 | push dword [edx + CPUMCPU.Guest.ds.Sel]
|
|---|
| 431 | push dword [edx + CPUMCPU.Guest.es.Sel]
|
|---|
| 432 |
|
|---|
| 433 | push dword [edx + CPUMCPU.Guest.ss.Sel]
|
|---|
| 434 | push dword [edx + CPUMCPU.Guest.esp]
|
|---|
| 435 |
|
|---|
| 436 | push dword [edx + CPUMCPU.Guest.eflags]
|
|---|
| 437 | push dword [edx + CPUMCPU.Guest.cs.Sel]
|
|---|
| 438 | push dword [edx + CPUMCPU.Guest.eip]
|
|---|
| 439 |
|
|---|
| 440 | ;
|
|---|
| 441 | ; Restore registers.
|
|---|
| 442 | ;
|
|---|
| 443 |
|
|---|
| 444 | %ifdef VBOX_WITH_STATISTICS
|
|---|
| 445 | ;
|
|---|
| 446 | ; Statistics.
|
|---|
| 447 | ;
|
|---|
| 448 | push edx
|
|---|
| 449 | mov edx, IMP(g_VM)
|
|---|
| 450 | lea edx, [edx + VM.StatTotalQemuToGC]
|
|---|
| 451 | STAM_PROFILE_ADV_STOP edx
|
|---|
| 452 |
|
|---|
| 453 | mov edx, IMP(g_VM)
|
|---|
| 454 | lea edx, [edx + VM.StatTotalInGC]
|
|---|
| 455 | STAM_PROFILE_ADV_START edx
|
|---|
| 456 | pop edx
|
|---|
| 457 | %endif
|
|---|
| 458 |
|
|---|
| 459 | ;
|
|---|
| 460 | ; enable WP
|
|---|
| 461 | ;
|
|---|
| 462 | %ifdef ENABLE_WRITE_PROTECTION
|
|---|
| 463 | mov eax, cr0
|
|---|
| 464 | or eax, X86_CR0_WRITE_PROTECT
|
|---|
| 465 | mov cr0, eax
|
|---|
| 466 | %endif
|
|---|
| 467 |
|
|---|
| 468 | ;
|
|---|
| 469 | ; Continue restore.
|
|---|
| 470 | ;
|
|---|
| 471 | mov esi, [edx + CPUMCPU.Guest.esi]
|
|---|
| 472 | mov edi, [edx + CPUMCPU.Guest.edi]
|
|---|
| 473 | mov ebp, [edx + CPUMCPU.Guest.ebp]
|
|---|
| 474 | mov ecx, [edx + CPUMCPU.Guest.ecx]
|
|---|
| 475 | mov ebx, [edx + CPUMCPU.Guest.ebx]
|
|---|
| 476 | mov eax, [edx + CPUMCPU.Guest.eax]
|
|---|
| 477 | mov edx, [edx + CPUMCPU.Guest.edx]
|
|---|
| 478 |
|
|---|
| 479 | ; restart execution.
|
|---|
| 480 | TRPM_NP_GP_HANDLER NAME(cpumRCHandleNPAndGP), CPUM_HANDLER_IRET
|
|---|
| 481 | iretd
|
|---|
| 482 | ENDPROC CPUMGCResumeGuestV86
|
|---|
| 483 |
|
|---|
