1 | /* $Id: ARM_Qualcomm_Snapdragon_X.h 109063 2025-04-23 13:17:46Z vboxsync $ */
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2 | /** @file
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3 | * CPU database entry "Qualcomm Snapdragon X".
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4 | * Generated at 2025-04-21T11:23:38Z by VBoxCpuReport v7.1.97r168566 on win.arm64.
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5 | */
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6 |
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7 | /*
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8 | * Copyright (C) 2013-2025 Oracle and/or its affiliates.
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9 | *
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10 | * This file is part of VirtualBox base platform packages, as
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11 | * available from https://www.virtualbox.org.
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12 | *
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13 | * This program is free software; you can redistribute it and/or
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14 | * modify it under the terms of the GNU General Public License
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15 | * as published by the Free Software Foundation, in version 3 of the
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16 | * License.
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17 | *
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18 | * This program is distributed in the hope that it will be useful, but
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19 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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21 | * General Public License for more details.
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22 | *
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23 | * You should have received a copy of the GNU General Public License
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24 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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25 | *
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26 | * SPDX-License-Identifier: GPL-3.0-only
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27 | */
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28 |
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29 | #ifndef VBOX_CPUDB_ARM_Qualcomm_Snapdragon_X_h
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30 | #define VBOX_CPUDB_ARM_Qualcomm_Snapdragon_X_h
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31 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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32 | # pragma once
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33 | #endif
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34 |
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35 |
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36 | /**
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37 | * Common system register values for Snapdragon(R) X Elite - X1E80100 - Qualcomm(R) Oryon(TM) CPU.
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38 | */
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39 | static SUPARMSYSREGVAL const g_aCmnSysRegVals_ARM_Qualcomm_Snapdragon_X[] =
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40 | {
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41 | { UINT64_C(0x0000000080000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5), 0x1 }, /* MPIDR_EL1 */
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42 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6), 0x0 }, /* REVIDR_EL1 */
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43 | { UINT64_C(0x1101201021111111), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0), 0x0 }, /* ID_AA64PFR0_EL1 */
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44 | { UINT64_C(0x0000000000000020), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1), 0x0 }, /* ID_AA64PFR1_EL1 */
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45 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 2), 0x0 },
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46 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 3), 0x0 },
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47 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4), 0x0 }, /* ID_AA64ZFR0_EL1 */
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48 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5), 0x0 }, /* ID_AA64SMFR0_EL1 */
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49 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 6), 0x0 },
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50 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 7), 0x0 },
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51 | { UINT64_C(0x000000f010305709), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0), 0x0 }, /* ID_AA64DFR0_EL1 */
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52 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1), 0x0 }, /* ID_AA64DFR1_EL1 */
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53 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 2), 0x0 },
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54 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 3), 0x0 },
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55 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4), 0x0 }, /* ID_AA64AFR0_EL1 */
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56 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5), 0x0 }, /* ID_AA64AFR1_EL1 */
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57 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 6), 0x0 },
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58 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 7), 0x0 },
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59 | { UINT64_C(0x1221111110212120), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0), 0x0 }, /* ID_AA64ISAR0_EL1 */
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60 | { UINT64_C(0x0010111101211052), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1), 0x0 }, /* ID_AA64ISAR1_EL1 */
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61 | { UINT64_C(0x0000000010000010), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2), 0x0 }, /* ID_AA64ISAR2_EL1 */
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62 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 3), 0x0 }, /* ID_AA64ISAR3_EL1 */
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63 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 4), 0x0 },
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64 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 5), 0x0 },
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65 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 6), 0x0 },
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66 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 7), 0x0 },
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67 | { UINT64_C(0x0000111100001024), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0), 0x0 }, /* ID_AA64MMFR0_EL1 */
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68 | { UINT64_C(0x0000101001201000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1), 0x0 }, /* ID_AA64MMFR1_EL1 */
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69 | { UINT64_C(0x1000001100101011), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2), 0x0 }, /* ID_AA64MMFR2_EL1 */
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70 | { UINT64_C(0x1000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 3), 0x0 }, /* ID_AA64MMFR3_EL1 */
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71 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 4), 0x0 }, /* ID_AA64MMFR4_EL1 */
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72 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 5), 0x0 },
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73 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 6), 0x0 },
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74 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 7), 0x0 },
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75 | { UINT64_C(0x0000000000000003), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0), 0x0 }, /* ERRIDR_EL1 */
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76 | { UINT64_C(0x00003fff0000005a), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 1, 0, 0, 0), 0x0 }, /* CCSIDR_EL1 */
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77 | { UINT64_C(0x0000000002000023), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 1, 0, 0, 1), 0x0 }, /* CLIDR_EL1 */
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78 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 1, 0, 0, 2), 0x0 }, /* CCSIDR2_EL1 */
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79 | { UINT64_C(0x0000000000000000), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 1, 0, 0, 7), 0x0 }, /* AIDR_EL1 */
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80 | { UINT64_C(0x0000000000000004), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 0, 0, 7), 0x0 }, /* DCZID_EL0 */
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81 | { UINT64_C(0x000000000124f800), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3,14, 0, 0), 0x0 }, /* CNTFRQ_EL0 */
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82 | };
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83 |
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84 |
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85 | /**
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86 | * System register values for Qualcomm Snapdragon X (Oryon var 2), variation #0.
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87 | * 4 CPUs shares this variant: 0, 1, 2, 3
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88 | */
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89 | static SUPARMSYSREGVAL const g_aVar0SysRegVals_ARM_Qualcomm_Snapdragon_X[] =
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90 | {
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91 | { UINT64_C(0x00000000512f0011), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0), 0x0 }, /* MIDR_EL1 */
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92 | };
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93 |
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94 |
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95 | /**
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96 | * System register values for Qualcomm Snapdragon X (Oryon var 1), variation #1.
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97 | * 8 CPUs shares this variant: 4, 5, 6, 7, 8, 9, 10, 11
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98 | */
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99 | static SUPARMSYSREGVAL const g_aVar1SysRegVals_ARM_Qualcomm_Snapdragon_X[] =
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100 | {
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101 | { UINT64_C(0x00000000511f0011), ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0), 0x0 }, /* MIDR_EL1 */
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102 | };
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103 |
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104 |
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105 | /**
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106 | * Database entry for Snapdragon(R) X Elite - X1E80100 - Qualcomm(R) Oryon(TM) CPU.
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107 | */
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108 | static CPUMDBENTRYARM const g_Entry_ARM_Qualcomm_Snapdragon_X =
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109 | {
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110 | {
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111 | /*.pszName = */ "Qualcomm Snapdragon X",
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112 | /*.pszFullName = */ "Snapdragon(R) X Elite - X1E80100 - Qualcomm(R) Oryon(TM) CPU",
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113 | /*.enmVendor = */ CPUMCPUVENDOR_QUALCOMM,
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114 | /*.enmMicroarch = */ kCpumMicroarch_Qualcomm_Oryon,
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115 | /*.fFlags = */ 0,
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116 | },
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117 | /*.paSysRegCmnVals = */ NULL_ALONE(g_aCmnSysRegVals_ARM_Qualcomm_Snapdragon_X),
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118 | /*.cSysRegCmnVals = */ ZERO_ALONE(RT_ELEMENTS(g_aCmnSysRegVals_ARM_Qualcomm_Snapdragon_X)),
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119 | /*.cVariants = */ 2,
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120 | /*.aVariants = */
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121 | {
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122 | /*.Variants[0] = */
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123 | {
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124 | /*.pszName = */ "Qualcomm Snapdragon X (Oryon var 2)",
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125 | /*.Midr = */
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126 | {
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127 | /*Midr.s = */
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128 | {
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129 | /*.u4Revision = */ 0x1,
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130 | /*.u12PartNum = */ 0x001,
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131 | /*.u4Arch = */ 0xf,
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132 | /*.u4Variant = */ 0x2,
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133 | /*.u4Implementer = */ 0x51,
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134 | }
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135 | },
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136 | /*.enmCoreType = */ kCpumCoreType_Unknown,
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137 | /*.cSysRegVals = */ ZERO_ALONE(RT_ELEMENTS(g_aVar0SysRegVals_ARM_Qualcomm_Snapdragon_X)),
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138 | /*.paSysRegVals = */ NULL_ALONE(g_aVar0SysRegVals_ARM_Qualcomm_Snapdragon_X)
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139 | },
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140 | /*.Variants[1] = */
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141 | {
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142 | /*.pszName = */ "Qualcomm Snapdragon X (Oryon var 1)",
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143 | /*.Midr = */
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144 | {
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145 | /*Midr.s = */
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146 | {
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147 | /*.u4Revision = */ 0x1,
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148 | /*.u12PartNum = */ 0x001,
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149 | /*.u4Arch = */ 0xf,
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150 | /*.u4Variant = */ 0x1,
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151 | /*.u4Implementer = */ 0x51,
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152 | }
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153 | },
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154 | /*.enmCoreType = */ kCpumCoreType_Unknown,
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155 | /*.cSysRegVals = */ ZERO_ALONE(RT_ELEMENTS(g_aVar1SysRegVals_ARM_Qualcomm_Snapdragon_X)),
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156 | /*.paSysRegVals = */ NULL_ALONE(g_aVar1SysRegVals_ARM_Qualcomm_Snapdragon_X)
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157 | },
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158 | }
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159 | };
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160 |
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161 | #endif /* !VBOX_CPUDB_ARM_Qualcomm_Snapdragon_X_h */
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162 |
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