VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp@ 50653

Last change on this file since 50653 was 48221, checked in by vboxsync, 11 years ago

VMM: Adding a debugging aid for 64-on-32 that tries to catch exceptions on the otherwordly context. Set VBOX_WITH_64ON32_IDT in LocalConfig.kmk to enable.
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File size: 43.0 KB
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1/* $Id: VMMSwitcher.cpp 48221 2013-09-01 23:27:56Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor, World Switcher(s).
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_VMM
23#include <VBox/vmm/vmm.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/hm.h>
26#include <VBox/vmm/selm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/sup.h>
29#include "VMMInternal.h"
30#include "VMMSwitcher.h"
31#include <VBox/vmm/vm.h>
32#include <VBox/dis.h>
33
34#include <VBox/err.h>
35#include <VBox/param.h>
36#include <iprt/assert.h>
37#include <iprt/alloc.h>
38#include <iprt/asm.h>
39#include <iprt/asm-amd64-x86.h>
40#include <iprt/string.h>
41#include <iprt/ctype.h>
42
43
44/*******************************************************************************
45* Global Variables *
46*******************************************************************************/
47/** Array of switcher definitions.
48 * The type and index shall match!
49 */
50static PVMMSWITCHERDEF g_apRawModeSwitchers[VMMSWITCHER_MAX] =
51{
52 NULL, /* invalid entry */
53#ifdef VBOX_WITH_RAW_MODE
54# ifndef RT_ARCH_AMD64
55 &vmmR3Switcher32BitTo32Bit_Def,
56 &vmmR3Switcher32BitToPAE_Def,
57 NULL, //&vmmR3Switcher32BitToAMD64_Def,
58 &vmmR3SwitcherPAETo32Bit_Def,
59 &vmmR3SwitcherPAEToPAE_Def,
60 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
61 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
62# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
63 &vmmR3SwitcherAMD64ToPAE_Def,
64# else
65 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
66# endif
67 NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
68# else /* RT_ARCH_AMD64 */
69 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
70 NULL, //&vmmR3Switcher32BitToPAE_Def,
71 NULL, //&vmmR3Switcher32BitToAMD64_Def,
72 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
73 NULL, //&vmmR3SwitcherPAEToPAE_Def,
74 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
75 &vmmR3SwitcherAMD64To32Bit_Def,
76 &vmmR3SwitcherAMD64ToPAE_Def,
77 NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
78# endif /* RT_ARCH_AMD64 */
79#else /* !VBOX_WITH_RAW_MODE */
80 NULL,
81 NULL,
82 NULL,
83 NULL,
84 NULL,
85 NULL,
86 NULL,
87 NULL,
88 NULL,
89#endif /* !VBOX_WITH_RAW_MODE */
90#ifndef RT_ARCH_AMD64
91 &vmmR3SwitcherX86Stub_Def,
92 NULL,
93#else
94 NULL,
95 &vmmR3SwitcherAMD64Stub_Def,
96#endif
97};
98
99/** Array of switcher definitions.
100 * The type and index shall match!
101 */
102static PVMMSWITCHERDEF g_apHmSwitchers[VMMSWITCHER_MAX] =
103{
104 NULL, /* invalid entry */
105#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
106 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
107 NULL, //&vmmR3Switcher32BitToPAE_Def,
108 &vmmR3Switcher32BitToAMD64_Def,
109 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
110 NULL, //&vmmR3SwitcherPAEToPAE_Def,
111 &vmmR3SwitcherPAEToAMD64_Def,
112 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
113 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
114 NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
115#else /* !VBOX_WITH_RAW_MODE */
116 NULL,
117 NULL,
118 NULL,
119 NULL,
120 NULL,
121 NULL,
122 NULL,
123 NULL,
124 NULL,
125#endif /* !VBOX_WITH_RAW_MODE */
126#ifndef RT_ARCH_AMD64
127 &vmmR3SwitcherX86Stub_Def,
128 NULL,
129#else
130 NULL,
131 &vmmR3SwitcherAMD64Stub_Def,
132#endif
133};
134
135
136# ifdef VBOX_WITH_64ON32_IDT
137/**
138 * Initializes the 64-bit IDT for 64-bit guest on 32-bit host switchers.
139 *
140 * This is only used as a debugging aid when we cannot find out why something
141 * goes haywire in the intermediate context.
142 *
143 * @param pVM The cross context VM structure.
144 * @param pSwitcher The switcher descriptor.
145 * @param pbDst Where the switcher code was just copied.
146 * @param HCPhysDst The host physical address corresponding to @a pbDst.
147 */
148static void vmmR3Switcher32On64IdtInit(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pbDst, RTHCPHYS HCPhysDst)
149{
150 AssertRelease(pSwitcher->offGCCode > 0 && pSwitcher->offGCCode < pSwitcher->cbCode);
151 AssertRelease(pSwitcher->cbCode < _64K);
152 RTSEL uCs64 = SELMGetHyperCS64(pVM);
153
154 PX86DESC64GATE paIdt = (PX86DESC64GATE)(pbDst + pSwitcher->offGCCode);
155 for (uint32_t i = 0 ; i < 256; i++)
156 {
157 AssertRelease(((uint64_t *)&paIdt[i])[0] < pSwitcher->cbCode);
158 AssertRelease(((uint64_t *)&paIdt[i])[1] == 0);
159 uint64_t uHandler = HCPhysDst + paIdt[i].u16OffsetLow;
160 paIdt[i].u16OffsetLow = (uint16_t)uHandler;
161 paIdt[i].u16Sel = uCs64;
162 paIdt[i].u3IST = 0;
163 paIdt[i].u5Reserved = 0;
164 paIdt[i].u4Type = AMD64_SEL_TYPE_SYS_INT_GATE;
165 paIdt[i].u1DescType = 0 /* system */;
166 paIdt[i].u2Dpl = 3;
167 paIdt[i].u1Present = 1;
168 paIdt[i].u16OffsetHigh = (uint16_t)(uHandler >> 16);
169 paIdt[i].u32Reserved = (uint32_t)(uHandler >> 32);
170 }
171
172 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
173 {
174 uint64_t uIdtr = HCPhysDst + pSwitcher->offGCCode; AssertRelease(uIdtr < UINT32_MAX);
175 CPUMSetHyperIDTR(&pVM->aCpus[iCpu], uIdtr, 16*256 + iCpu);
176 }
177}
178
179
180/**
181 * Relocates the 64-bit IDT for 64-bit guest on 32-bit host switchers.
182 *
183 * @param pVM The cross context VM structure.
184 * @param pSwitcher The switcher descriptor.
185 * @param pbDst Where the switcher code was just copied.
186 * @param HCPhysDst The host physical address corresponding to @a pbDst.
187 */
188static void vmmR3Switcher32On64IdtRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pbDst, RTHCPHYS HCPhysDst)
189{
190 AssertRelease(pSwitcher->offGCCode > 0 && pSwitcher->offGCCode < pSwitcher->cbCode && pSwitcher->cbCode < _64K);
191
192 /* The intermediate context doesn't move, but the CS may. */
193 RTSEL uCs64 = SELMGetHyperCS64(pVM);
194 PX86DESC64GATE paIdt = (PX86DESC64GATE)(pbDst + pSwitcher->offGCCode);
195 for (uint32_t i = 0 ; i < 256; i++)
196 paIdt[i].u16Sel = uCs64;
197
198 /* Just in case... */
199 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
200 {
201 uint64_t uIdtr = HCPhysDst + pSwitcher->offGCCode; AssertRelease(uIdtr < UINT32_MAX);
202 CPUMSetHyperIDTR(&pVM->aCpus[iCpu], uIdtr, 16*256 + iCpu);
203 }
204}
205# endif /* VBOX_WITH_64ON32_IDT */
206
207
208/**
209 * VMMR3Init worker that initiates the switcher code (aka core code).
210 *
211 * This is core per VM code which might need fixups and/or for ease of use are
212 * put on linear contiguous backing.
213 *
214 * @returns VBox status code.
215 * @param pVM Pointer to the VM.
216 */
217int vmmR3SwitcherInit(PVM pVM)
218{
219#if !defined(VBOX_WITH_RAW_MODE) && (HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL))
220 return VINF_SUCCESS;
221#else
222
223 /*
224 * Calc the size.
225 */
226 const PVMMSWITCHERDEF *papSwitchers = HMIsEnabled(pVM) ? g_apHmSwitchers : g_apRawModeSwitchers;
227 unsigned cbCoreCode = 0;
228 for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
229 {
230 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
231 PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
232 if (pSwitcher)
233 {
234 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
235 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
236 }
237 }
238
239 /*
240 * Allocate contiguous pages for switchers and deal with
241 * conflicts in the intermediate mapping of the code.
242 */
243 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
244 pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
245 int rc = VERR_NO_MEMORY;
246 if (pVM->vmm.s.pvCoreCodeR3)
247 {
248 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
249 if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
250 {
251 /* try more allocations - Solaris, Linux. */
252 const unsigned cTries = 8234;
253 struct VMMInitBadTry
254 {
255 RTR0PTR pvR0;
256 void *pvR3;
257 RTHCPHYS HCPhys;
258 RTUINT cb;
259 } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
260 AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
261 unsigned i = 0;
262 do
263 {
264 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
265 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
266 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
267 i++;
268 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
269 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
270 pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
271 if (!pVM->vmm.s.pvCoreCodeR3)
272 break;
273 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
274 } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
275 && i < cTries - 1);
276
277 /* cleanup */
278 if (RT_FAILURE(rc))
279 {
280 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
281 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
282 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
283 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
284 i++;
285 LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
286 }
287 while (i-- > 0)
288 {
289 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
290 i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
291 SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
292 }
293 RTMemTmpFree(paBadTries);
294 }
295 }
296 if (RT_SUCCESS(rc))
297 {
298 /*
299 * Copy the code.
300 */
301 for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
302 {
303 PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
304 if (pSwitcher)
305 {
306 uint8_t *pbDst = (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher];
307 memcpy(pbDst, pSwitcher->pvCode, pSwitcher->cbCode);
308# ifdef VBOX_WITH_64ON32_IDT
309 if ( pSwitcher->enmType == VMMSWITCHER_32_TO_AMD64
310 || pSwitcher->enmType == VMMSWITCHER_PAE_TO_AMD64)
311 vmmR3Switcher32On64IdtInit(pVM, pSwitcher, pbDst,
312 pVM->vmm.s.HCPhysCoreCode + pVM->vmm.s.aoffSwitchers[iSwitcher]);
313# endif
314 }
315 }
316
317 /*
318 * Map the code into the GC address space.
319 */
320 RTGCPTR GCPtr;
321 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
322 cbCoreCode, "Core Code", &GCPtr);
323 if (RT_SUCCESS(rc))
324 {
325 pVM->vmm.s.pvCoreCodeRC = GCPtr;
326 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
327 LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
328 pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
329
330 /*
331 * Finally, PGM probably has selected a switcher already but we need
332 * to get the routine addresses, so we'll reselect it.
333 * This may legally fail so, we're ignoring the rc.
334 * Note! See HMIsEnabled hack in selector function.
335 */
336 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
337 return rc;
338 }
339
340 /* shit */
341 AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
342 SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
343 }
344 else
345 VMSetError(pVM, rc, RT_SRC_POS,
346 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
347 cbCoreCode);
348
349 pVM->vmm.s.pvCoreCodeR3 = NULL;
350 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
351 pVM->vmm.s.pvCoreCodeRC = 0;
352 return rc;
353#endif
354}
355
356/**
357 * Relocate the switchers, called by VMMR#Relocate.
358 *
359 * @param pVM Pointer to the VM.
360 * @param offDelta The relocation delta.
361 */
362void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
363{
364#if defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL))
365 /*
366 * Relocate all the switchers.
367 */
368 const PVMMSWITCHERDEF *papSwitchers = HMIsEnabled(pVM) ? g_apHmSwitchers : g_apRawModeSwitchers;
369 for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
370 {
371 PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
372 if (pSwitcher && pSwitcher->pfnRelocate)
373 {
374 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
375 pSwitcher->pfnRelocate(pVM,
376 pSwitcher,
377 pVM->vmm.s.pvCoreCodeR0 + off,
378 (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
379 pVM->vmm.s.pvCoreCodeRC + off,
380 pVM->vmm.s.HCPhysCoreCode + off);
381# ifdef VBOX_WITH_64ON32_IDT
382 if ( pSwitcher->enmType == VMMSWITCHER_32_TO_AMD64
383 || pSwitcher->enmType == VMMSWITCHER_PAE_TO_AMD64)
384 vmmR3Switcher32On64IdtRelocate(pVM, pSwitcher,
385 (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
386 pVM->vmm.s.HCPhysCoreCode + off);
387# endif
388 }
389 }
390
391 /*
392 * Recalc the RC address for the current switcher.
393 */
394 PVMMSWITCHERDEF pSwitcher = papSwitchers[pVM->vmm.s.enmSwitcher];
395 if (pSwitcher)
396 {
397 RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
398 pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
399 pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
400 pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
401 pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
402 }
403 else
404 AssertRelease(HMIsEnabled(pVM));
405
406#else
407 NOREF(pVM);
408#endif
409 NOREF(offDelta);
410}
411
412
413#if defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL))
414
415/**
416 * Generic switcher code relocator.
417 *
418 * @param pVM Pointer to the VM.
419 * @param pSwitcher The switcher definition.
420 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
421 * @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
422 * @param GCPtrCode The guest context address corresponding to pu8Code.
423 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
424 * @param SelCS The hypervisor CS selector.
425 * @param SelDS The hypervisor DS selector.
426 * @param SelTSS The hypervisor TSS selector.
427 * @param GCPtrGDT The GC address of the hypervisor GDT.
428 * @param SelCS64 The 64-bit mode hypervisor CS selector.
429 */
430static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher,
431 RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
432 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
433{
434 union
435 {
436 const uint8_t *pu8;
437 const uint16_t *pu16;
438 const uint32_t *pu32;
439 const uint64_t *pu64;
440 const void *pv;
441 uintptr_t u;
442 } u;
443 u.pv = pSwitcher->pvFixups;
444
445 /*
446 * Process fixups.
447 */
448 uint8_t u8;
449 while ((u8 = *u.pu8++) != FIX_THE_END)
450 {
451 /*
452 * Get the source (where to write the fixup).
453 */
454 uint32_t offSrc = *u.pu32++;
455 Assert(offSrc < pSwitcher->cbCode);
456 union
457 {
458 uint8_t *pu8;
459 uint16_t *pu16;
460 uint32_t *pu32;
461 uint64_t *pu64;
462 uintptr_t u;
463 } uSrc;
464 uSrc.pu8 = pu8CodeR3 + offSrc;
465
466 /* The fixup target and method depends on the type. */
467 switch (u8)
468 {
469 /*
470 * 32-bit relative, source in HC and target in GC.
471 */
472 case FIX_HC_2_GC_NEAR_REL:
473 {
474 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
475 uint32_t offTrg = *u.pu32++;
476 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
477 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
478 break;
479 }
480
481 /*
482 * 32-bit relative, source in HC and target in ID.
483 */
484 case FIX_HC_2_ID_NEAR_REL:
485 {
486 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
487 uint32_t offTrg = *u.pu32++;
488 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
489 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
490 break;
491 }
492
493 /*
494 * 32-bit relative, source in GC and target in HC.
495 */
496 case FIX_GC_2_HC_NEAR_REL:
497 {
498 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
499 uint32_t offTrg = *u.pu32++;
500 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
501 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
502 break;
503 }
504
505 /*
506 * 32-bit relative, source in GC and target in ID.
507 */
508 case FIX_GC_2_ID_NEAR_REL:
509 {
510 AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
511 uint32_t offTrg = *u.pu32++;
512 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
513 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
514 break;
515 }
516
517 /*
518 * 32-bit relative, source in ID and target in HC.
519 */
520 case FIX_ID_2_HC_NEAR_REL:
521 {
522 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
523 uint32_t offTrg = *u.pu32++;
524 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
525 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
526 break;
527 }
528
529 /*
530 * 32-bit relative, source in ID and target in HC.
531 */
532 case FIX_ID_2_GC_NEAR_REL:
533 {
534 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
535 uint32_t offTrg = *u.pu32++;
536 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
537 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
538 break;
539 }
540
541 /*
542 * 16:32 far jump, target in GC.
543 */
544 case FIX_GC_FAR32:
545 {
546 uint32_t offTrg = *u.pu32++;
547 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
548 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
549 *uSrc.pu16++ = SelCS;
550 break;
551 }
552
553 /*
554 * Make 32-bit GC pointer given CPUM offset.
555 */
556 case FIX_GC_CPUM_OFF:
557 {
558 uint32_t offCPUM = *u.pu32++;
559 Assert(offCPUM < sizeof(pVM->cpum));
560 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
561 break;
562 }
563
564 /*
565 * Make 32-bit GC pointer given CPUMCPU offset.
566 */
567 case FIX_GC_CPUMCPU_OFF:
568 {
569 uint32_t offCPUM = *u.pu32++;
570 Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
571 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
572 break;
573 }
574
575 /*
576 * Make 32-bit GC pointer given VM offset.
577 */
578 case FIX_GC_VM_OFF:
579 {
580 uint32_t offVM = *u.pu32++;
581 Assert(offVM < sizeof(VM));
582 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
583 break;
584 }
585
586 /*
587 * Make 32-bit HC pointer given CPUM offset.
588 */
589 case FIX_HC_CPUM_OFF:
590 {
591 uint32_t offCPUM = *u.pu32++;
592 Assert(offCPUM < sizeof(pVM->cpum));
593 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
594 break;
595 }
596
597 /*
598 * Make 32-bit R0 pointer given VM offset.
599 */
600 case FIX_HC_VM_OFF:
601 {
602 uint32_t offVM = *u.pu32++;
603 Assert(offVM < sizeof(VM));
604 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
605 break;
606 }
607
608 /*
609 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
610 */
611 case FIX_INTER_32BIT_CR3:
612 {
613
614 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
615 break;
616 }
617
618 /*
619 * Store the PAE CR3 (32-bit) for the intermediate memory context.
620 */
621 case FIX_INTER_PAE_CR3:
622 {
623
624 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
625 break;
626 }
627
628 /*
629 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
630 */
631 case FIX_INTER_AMD64_CR3:
632 {
633
634 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
635 break;
636 }
637
638 /*
639 * Store Hypervisor CS (16-bit).
640 */
641 case FIX_HYPER_CS:
642 {
643 *uSrc.pu16 = SelCS;
644 break;
645 }
646
647 /*
648 * Store Hypervisor DS (16-bit).
649 */
650 case FIX_HYPER_DS:
651 {
652 *uSrc.pu16 = SelDS;
653 break;
654 }
655
656 /*
657 * Store Hypervisor TSS (16-bit).
658 */
659 case FIX_HYPER_TSS:
660 {
661 *uSrc.pu16 = SelTSS;
662 break;
663 }
664
665 /*
666 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
667 */
668 case FIX_GC_TSS_GDTE_DW2:
669 {
670 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
671 *uSrc.pu32 = (uint32_t)GCPtr;
672 break;
673 }
674
675 /*
676 * Store the EFER or mask for the 32->64 bit switcher.
677 */
678 case FIX_EFER_OR_MASK:
679 {
680 uint32_t u32OrMask = MSR_K6_EFER_LME | MSR_K6_EFER_SCE;
681 /*
682 * We don't care if cpuid 0x8000001 isn't supported as that implies
683 * long mode isn't supported either, so this switched would never be used.
684 */
685 if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
686 u32OrMask |= MSR_K6_EFER_NXE;
687
688 *uSrc.pu32 = u32OrMask;
689 break;
690 }
691
692 /*
693 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
694 */
695 case FIX_NO_FXSAVE_JMP:
696 {
697 uint32_t offTrg = *u.pu32++;
698 Assert(offTrg < pSwitcher->cbCode);
699 if (!CPUMSupportsFXSR(pVM))
700 {
701 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
702 *uSrc.pu32++ = offTrg - (offSrc + 5);
703 }
704 else
705 {
706 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
707 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
708 }
709 break;
710 }
711
712 /*
713 * Insert relative jump to specified target it SYSENTER isn't used by the host.
714 */
715 case FIX_NO_SYSENTER_JMP:
716 {
717 uint32_t offTrg = *u.pu32++;
718 Assert(offTrg < pSwitcher->cbCode);
719 if (!CPUMIsHostUsingSysEnter(pVM))
720 {
721 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
722 *uSrc.pu32++ = offTrg - (offSrc + 5);
723 }
724 else
725 {
726 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
727 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
728 }
729 break;
730 }
731
732 /*
733 * Insert relative jump to specified target it SYSCALL isn't used by the host.
734 */
735 case FIX_NO_SYSCALL_JMP:
736 {
737 uint32_t offTrg = *u.pu32++;
738 Assert(offTrg < pSwitcher->cbCode);
739 if (!CPUMIsHostUsingSysCall(pVM))
740 {
741 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
742 *uSrc.pu32++ = offTrg - (offSrc + 5);
743 }
744 else
745 {
746 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
747 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
748 }
749 break;
750 }
751
752 /*
753 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
754 */
755 case FIX_HC_32BIT:
756 {
757 uint32_t offTrg = *u.pu32++;
758 Assert(offSrc < pSwitcher->cbCode);
759 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
760 *uSrc.pu32 = R0PtrCode + offTrg;
761 break;
762 }
763
764# if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
765 /*
766 * 64-bit HC Code Selector (no argument).
767 */
768 case FIX_HC_64BIT_CS:
769 {
770 Assert(offSrc < pSwitcher->cbCode);
771# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
772 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
773# else
774 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
775# endif
776 break;
777 }
778
779 /*
780 * 64-bit HC pointer to the CPUM instance data (no argument).
781 */
782 case FIX_HC_64BIT_CPUM:
783 {
784 Assert(offSrc < pSwitcher->cbCode);
785 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
786 break;
787 }
788# endif
789 /*
790 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
791 */
792 case FIX_HC_64BIT:
793 {
794 uint32_t offTrg = *u.pu32++;
795 Assert(offSrc < pSwitcher->cbCode);
796 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
797 *uSrc.pu64 = R0PtrCode + offTrg;
798 break;
799 }
800
801# ifdef RT_ARCH_X86
802 case FIX_GC_64_BIT_CPUM_OFF:
803 {
804 uint32_t offCPUM = *u.pu32++;
805 Assert(offCPUM < sizeof(pVM->cpum));
806 *uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
807 break;
808 }
809# endif
810
811 /*
812 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
813 */
814 case FIX_ID_32BIT:
815 {
816 uint32_t offTrg = *u.pu32++;
817 Assert(offSrc < pSwitcher->cbCode);
818 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
819 *uSrc.pu32 = u32IDCode + offTrg;
820 break;
821 }
822
823 /*
824 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
825 */
826 case FIX_ID_64BIT:
827 case FIX_HC_64BIT_NOCHECK:
828 {
829 uint32_t offTrg = *u.pu32++;
830 Assert(offSrc < pSwitcher->cbCode);
831 Assert(u8 == FIX_HC_64BIT_NOCHECK || offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
832 *uSrc.pu64 = u32IDCode + offTrg;
833 break;
834 }
835
836 /*
837 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
838 */
839 case FIX_ID_FAR32_TO_64BIT_MODE:
840 {
841 uint32_t offTrg = *u.pu32++;
842 Assert(offSrc < pSwitcher->cbCode);
843 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
844 *uSrc.pu32++ = u32IDCode + offTrg;
845 *uSrc.pu16 = SelCS64;
846 AssertRelease(SelCS64);
847 break;
848 }
849
850# ifdef VBOX_WITH_NMI
851 /*
852 * 32-bit address to the APIC base.
853 */
854 case FIX_GC_APIC_BASE_32BIT:
855 {
856 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
857 break;
858 }
859# endif
860
861 default:
862 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
863 break;
864 }
865 }
866
867# ifdef LOG_ENABLED
868 /*
869 * If Log2 is enabled disassemble the switcher code.
870 *
871 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
872 */
873 if (LogIs2Enabled())
874 {
875 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
876 " R0PtrCode = %p\n"
877 " pu8CodeR3 = %p\n"
878 " GCPtrCode = %RGv\n"
879 " u32IDCode = %08x\n"
880 " pVMRC = %RRv\n"
881 " pCPUMRC = %RRv\n"
882 " pVMR3 = %p\n"
883 " pCPUMR3 = %p\n"
884 " GCPtrGDT = %RGv\n"
885 " InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
886 " HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
887 " SelCS = %04x\n"
888 " SelDS = %04x\n"
889 " SelCS64 = %04x\n"
890 " SelTSS = %04x\n",
891 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
892 R0PtrCode,
893 pu8CodeR3,
894 GCPtrCode,
895 u32IDCode,
896 VM_RC_ADDR(pVM, pVM),
897 VM_RC_ADDR(pVM, &pVM->cpum),
898 pVM,
899 &pVM->cpum,
900 GCPtrGDT,
901 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
902 PGMGetHyperCR3(VMMGetCpu(pVM)),
903 SelCS, SelDS, SelCS64, SelTSS);
904
905 uint32_t offCode = 0;
906 while (offCode < pSwitcher->cbCode)
907 {
908 /*
909 * Figure out where this is.
910 */
911 const char *pszDesc = NULL;
912 RTUINTPTR uBase;
913 uint32_t cbCode;
914 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
915 {
916 pszDesc = "HCCode0";
917 uBase = R0PtrCode;
918 offCode = pSwitcher->offHCCode0;
919 cbCode = pSwitcher->cbHCCode0;
920 }
921 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
922 {
923 pszDesc = "HCCode1";
924 uBase = R0PtrCode;
925 offCode = pSwitcher->offHCCode1;
926 cbCode = pSwitcher->cbHCCode1;
927 }
928 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
929 {
930 pszDesc = "GCCode";
931 uBase = GCPtrCode;
932 offCode = pSwitcher->offGCCode;
933 cbCode = pSwitcher->cbGCCode;
934 }
935 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
936 {
937 pszDesc = "IDCode0";
938 uBase = u32IDCode;
939 offCode = pSwitcher->offIDCode0;
940 cbCode = pSwitcher->cbIDCode0;
941 }
942 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
943 {
944 pszDesc = "IDCode1";
945 uBase = u32IDCode;
946 offCode = pSwitcher->offIDCode1;
947 cbCode = pSwitcher->cbIDCode1;
948 }
949 else
950 {
951 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
952 offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
953 offCode++;
954 continue;
955 }
956
957 /*
958 * Disassemble it.
959 */
960 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
961
962 while (cbCode > 0)
963 {
964 /* try label it */
965 if (pSwitcher->offR0ToRawMode == offCode)
966 RTLogPrintf(" *R0ToRawMode:\n");
967 if (pSwitcher->offRCToHost == offCode)
968 RTLogPrintf(" *RCToHost:\n");
969 if (pSwitcher->offRCCallTrampoline == offCode)
970 RTLogPrintf(" *RCCallTrampoline:\n");
971 if (pSwitcher->offRCToHostAsm == offCode)
972 RTLogPrintf(" *RCToHostAsm:\n");
973 if (pSwitcher->offRCToHostAsmNoReturn == offCode)
974 RTLogPrintf(" *RCToHostAsmNoReturn:\n");
975
976 /* disas */
977 uint32_t cbInstr = 0;
978 DISCPUSTATE Cpu;
979 char szDisas[256];
980 int rc = DISInstr(pu8CodeR3 + offCode, DISCPUMODE_32BIT, &Cpu, &cbInstr);
981 if (RT_SUCCESS(rc))
982 {
983 Cpu.uInstrAddr += uBase - (uintptr_t)pu8CodeR3;
984 DISFormatYasmEx(&Cpu, szDisas, sizeof(szDisas),
985 DIS_FMT_FLAGS_ADDR_LEFT | DIS_FMT_FLAGS_BYTES_LEFT | DIS_FMT_FLAGS_BYTES_SPACED
986 | DIS_FMT_FLAGS_RELATIVE_BRANCH,
987 NULL, NULL);
988 }
989 if (RT_SUCCESS(rc))
990 RTLogPrintf(" %04x: %s\n", offCode, szDisas);
991 else
992 {
993 RTLogPrintf(" %04x: %02x '%c' (rc=%Rrc\n",
994 offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ', rc);
995 cbInstr = 1;
996 }
997 offCode += cbInstr;
998 cbCode -= RT_MIN(cbInstr, cbCode);
999 }
1000 }
1001 }
1002# endif
1003}
1004
1005/**
1006 * Wrapper around SELMGetHyperGDT() that avoids calling it when raw-mode context
1007 * is not initialized.
1008 *
1009 * @returns Raw-mode contet GDT address. Null pointer if not applicable.
1010 * @param pVM The cross context VM structure.
1011 */
1012static RTRCPTR vmmR3SwitcherGetHyperGDT(PVM pVM)
1013{
1014 if (HMIsRawModeCtxNeeded(pVM))
1015 return SELMGetHyperGDT(pVM);
1016# if HC_ARCH_BITS != 32 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1017 AssertFailed(); /* This path is only applicable to some 32-bit hosts. */
1018# endif
1019 return NIL_RTRCPTR;
1020}
1021
1022/**
1023 * Relocator for the 32-Bit to 32-Bit world switcher.
1024 */
1025DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1026{
1027 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1028 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1029}
1030
1031
1032/**
1033 * Relocator for the 32-Bit to PAE world switcher.
1034 */
1035DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1036{
1037 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1038 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1039}
1040
1041
1042/**
1043 * Relocator for the 32-Bit to AMD64 world switcher.
1044 */
1045DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1046{
1047 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1048 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), vmmR3SwitcherGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1049}
1050
1051
1052/**
1053 * Relocator for the PAE to 32-Bit world switcher.
1054 */
1055DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1056{
1057 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1058 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1059}
1060
1061
1062/**
1063 * Relocator for the PAE to PAE world switcher.
1064 */
1065DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1066{
1067 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1068 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1069}
1070
1071/**
1072 * Relocator for the PAE to AMD64 world switcher.
1073 */
1074DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1075{
1076 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1077 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), vmmR3SwitcherGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1078}
1079
1080
1081/**
1082 * Relocator for the AMD64 to 32-bit world switcher.
1083 */
1084DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1085{
1086 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1087 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1088}
1089
1090
1091/**
1092 * Relocator for the AMD64 to PAE world switcher.
1093 */
1094DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1095{
1096 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1097 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1098}
1099
1100
1101/**
1102 * Selects the switcher to be used for switching to raw-mode context.
1103 *
1104 * @returns VBox status code.
1105 * @param pVM Pointer to the VM.
1106 * @param enmSwitcher The new switcher.
1107 * @remark This function may be called before the VMM is initialized.
1108 */
1109VMMR3_INT_DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1110{
1111 /*
1112 * Validate input.
1113 */
1114 if ( enmSwitcher < VMMSWITCHER_INVALID
1115 || enmSwitcher >= VMMSWITCHER_MAX)
1116 {
1117 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1118 return VERR_INVALID_PARAMETER;
1119 }
1120
1121 /*
1122 * Override it if HM is active.
1123 */
1124 if (HMIsEnabled(pVM))
1125 pVM->vmm.s.enmSwitcher = HC_ARCH_BITS == 64 ? VMMSWITCHER_AMD64_STUB : VMMSWITCHER_X86_STUB;
1126
1127 /*
1128 * Select the new switcher.
1129 */
1130 const PVMMSWITCHERDEF *papSwitchers = HMIsEnabled(pVM) ? g_apHmSwitchers : g_apRawModeSwitchers;
1131 PVMMSWITCHERDEF pSwitcher = papSwitchers[enmSwitcher];
1132 if (pSwitcher)
1133 {
1134 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1135 pVM->vmm.s.enmSwitcher = enmSwitcher;
1136
1137 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1138 pVM->vmm.s.pfnR0ToRawMode = pbCodeR0 + pSwitcher->offR0ToRawMode;
1139
1140 RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1141 pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
1142 pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
1143 pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
1144 pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
1145 return VINF_SUCCESS;
1146 }
1147
1148 return VERR_NOT_IMPLEMENTED;
1149}
1150
1151#endif /* #defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)) */
1152
1153
1154/**
1155 * Gets the switcher to be used for switching to GC.
1156 *
1157 * @returns host to guest ring 0 switcher entrypoint
1158 * @param pVM Pointer to the VM.
1159 * @param enmSwitcher The new switcher.
1160 */
1161VMMR3_INT_DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1162{
1163 /*
1164 * Validate input.
1165 */
1166 AssertMsgReturn( enmSwitcher == VMMSWITCHER_32_TO_AMD64
1167 || enmSwitcher == VMMSWITCHER_PAE_TO_AMD64,
1168 ("%d\n", enmSwitcher),
1169 NIL_RTR0PTR);
1170 AssertReturn(HMIsEnabled(pVM), NIL_RTR0PTR);
1171
1172 /*
1173 * Select the new switcher.
1174 */
1175 const PVMMSWITCHERDEF *papSwitchers = g_apHmSwitchers;
1176 PVMMSWITCHERDEF pSwitcher = papSwitchers[enmSwitcher];
1177 if (pSwitcher)
1178 {
1179 /** @todo fix the pvCoreCodeR0 type */
1180 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1181 return pbCodeR0 + pSwitcher->offR0ToRawMode;
1182 }
1183 return NIL_RTR0PTR;
1184}
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