VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp@ 76553

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[23]1/* $Id: VMMSwitcher.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
[1]2/** @file
[13798]3 * VMM - The Virtual Machine Monitor, World Switcher(s).
[1]4 */
5
6/*
[76553]7 * Copyright (C) 2006-2019 Oracle Corporation
[1]8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
[5999]12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
[1]16 */
17
[45701]18
[57358]19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
[1]22#define LOG_GROUP LOG_GROUP_VMM
[35346]23#include <VBox/vmm/vmm.h>
24#include <VBox/vmm/pgm.h>
[45701]25#include <VBox/vmm/hm.h>
[35346]26#include <VBox/vmm/selm.h>
27#include <VBox/vmm/mm.h>
[1]28#include <VBox/sup.h>
29#include "VMMInternal.h"
[35333]30#include "VMMSwitcher.h"
[35346]31#include <VBox/vmm/vm.h>
[13813]32#include <VBox/dis.h>
[13695]33
[1]34#include <VBox/err.h>
35#include <VBox/param.h>
36#include <iprt/assert.h>
37#include <iprt/alloc.h>
38#include <iprt/asm.h>
[30148]39#include <iprt/asm-amd64-x86.h>
[1]40#include <iprt/string.h>
41#include <iprt/ctype.h>
42
43
[57358]44/*********************************************************************************************************************************
45* Global Variables *
46*********************************************************************************************************************************/
[70949]47#if defined(VBOX_WITH_RAW_MODE) || HC_ARCH_BITS != 64
48
[33540]49/** Array of switcher definitions.
[1]50 * The type and index shall match!
51 */
[45701]52static PVMMSWITCHERDEF g_apRawModeSwitchers[VMMSWITCHER_MAX] =
[1]53{
54 NULL, /* invalid entry */
[63429]55# ifdef VBOX_WITH_RAW_MODE
56# ifndef RT_ARCH_AMD64
[1]57 &vmmR3Switcher32BitTo32Bit_Def,
58 &vmmR3Switcher32BitToPAE_Def,
[45746]59 NULL, //&vmmR3Switcher32BitToAMD64_Def,
[1]60 &vmmR3SwitcherPAETo32Bit_Def,
61 &vmmR3SwitcherPAEToPAE_Def,
[45746]62 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
[14167]63 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
[1]64 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
[45713]65 NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
[63429]66# else /* RT_ARCH_AMD64 */
[1]67 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
68 NULL, //&vmmR3Switcher32BitToPAE_Def,
[14136]69 NULL, //&vmmR3Switcher32BitToAMD64_Def,
[1]70 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
71 NULL, //&vmmR3SwitcherPAEToPAE_Def,
72 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
[14167]73 &vmmR3SwitcherAMD64To32Bit_Def,
[1]74 &vmmR3SwitcherAMD64ToPAE_Def,
[45701]75 NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
[63429]76# endif /* RT_ARCH_AMD64 */
77# else /* !VBOX_WITH_RAW_MODE */
[25946]78 NULL,
79 NULL,
80 NULL,
81 NULL,
82 NULL,
83 NULL,
84 NULL,
85 NULL,
[45701]86 NULL,
[63429]87# endif /* !VBOX_WITH_RAW_MODE */
88# ifndef RT_ARCH_AMD64
[45707]89 &vmmR3SwitcherX86Stub_Def,
[45701]90 NULL,
[63429]91# else
[45701]92 NULL,
93 &vmmR3SwitcherAMD64Stub_Def,
[63429]94# endif
[1]95};
96
[45701]97/** Array of switcher definitions.
98 * The type and index shall match!
99 */
100static PVMMSWITCHERDEF g_apHmSwitchers[VMMSWITCHER_MAX] =
101{
102 NULL, /* invalid entry */
[70949]103# if HC_ARCH_BITS == 32
[45701]104 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
105 NULL, //&vmmR3Switcher32BitToPAE_Def,
106 &vmmR3Switcher32BitToAMD64_Def,
107 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
108 NULL, //&vmmR3SwitcherPAEToPAE_Def,
109 &vmmR3SwitcherPAEToAMD64_Def,
110 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
111 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
112 NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
[70949]113# else /* !VBOX_WITH_RAW_MODE */
[45701]114 NULL,
115 NULL,
116 NULL,
117 NULL,
118 NULL,
119 NULL,
120 NULL,
121 NULL,
122 NULL,
[70949]123# endif /* !VBOX_WITH_RAW_MODE */
124# ifndef RT_ARCH_AMD64
[45707]125 &vmmR3SwitcherX86Stub_Def,
[45701]126 NULL,
[70949]127# else
[45701]128 NULL,
129 &vmmR3SwitcherAMD64Stub_Def,
[70949]130# endif
[45701]131};
[1]132
[70949]133#endif /* VBOX_WITH_RAW_MODE || HC_ARCH_BITS != 64 */
[45701]134
[70949]135
[48221]136# ifdef VBOX_WITH_64ON32_IDT
[1]137/**
[48221]138 * Initializes the 64-bit IDT for 64-bit guest on 32-bit host switchers.
139 *
140 * This is only used as a debugging aid when we cannot find out why something
141 * goes haywire in the intermediate context.
142 *
[58122]143 * @param pVM The cross context VM structure.
[48221]144 * @param pSwitcher The switcher descriptor.
145 * @param pbDst Where the switcher code was just copied.
146 * @param HCPhysDst The host physical address corresponding to @a pbDst.
147 */
148static void vmmR3Switcher32On64IdtInit(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pbDst, RTHCPHYS HCPhysDst)
149{
150 AssertRelease(pSwitcher->offGCCode > 0 && pSwitcher->offGCCode < pSwitcher->cbCode);
151 AssertRelease(pSwitcher->cbCode < _64K);
152 RTSEL uCs64 = SELMGetHyperCS64(pVM);
153
154 PX86DESC64GATE paIdt = (PX86DESC64GATE)(pbDst + pSwitcher->offGCCode);
155 for (uint32_t i = 0 ; i < 256; i++)
156 {
157 AssertRelease(((uint64_t *)&paIdt[i])[0] < pSwitcher->cbCode);
158 AssertRelease(((uint64_t *)&paIdt[i])[1] == 0);
159 uint64_t uHandler = HCPhysDst + paIdt[i].u16OffsetLow;
160 paIdt[i].u16OffsetLow = (uint16_t)uHandler;
161 paIdt[i].u16Sel = uCs64;
162 paIdt[i].u3IST = 0;
163 paIdt[i].u5Reserved = 0;
164 paIdt[i].u4Type = AMD64_SEL_TYPE_SYS_INT_GATE;
165 paIdt[i].u1DescType = 0 /* system */;
166 paIdt[i].u2Dpl = 3;
167 paIdt[i].u1Present = 1;
168 paIdt[i].u16OffsetHigh = (uint16_t)(uHandler >> 16);
169 paIdt[i].u32Reserved = (uint32_t)(uHandler >> 32);
170 }
171
172 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
173 {
174 uint64_t uIdtr = HCPhysDst + pSwitcher->offGCCode; AssertRelease(uIdtr < UINT32_MAX);
175 CPUMSetHyperIDTR(&pVM->aCpus[iCpu], uIdtr, 16*256 + iCpu);
176 }
177}
178
179
180/**
181 * Relocates the 64-bit IDT for 64-bit guest on 32-bit host switchers.
182 *
[58122]183 * @param pVM The cross context VM structure.
[48221]184 * @param pSwitcher The switcher descriptor.
185 * @param pbDst Where the switcher code was just copied.
186 * @param HCPhysDst The host physical address corresponding to @a pbDst.
187 */
188static void vmmR3Switcher32On64IdtRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pbDst, RTHCPHYS HCPhysDst)
189{
190 AssertRelease(pSwitcher->offGCCode > 0 && pSwitcher->offGCCode < pSwitcher->cbCode && pSwitcher->cbCode < _64K);
191
192 /* The intermediate context doesn't move, but the CS may. */
193 RTSEL uCs64 = SELMGetHyperCS64(pVM);
194 PX86DESC64GATE paIdt = (PX86DESC64GATE)(pbDst + pSwitcher->offGCCode);
195 for (uint32_t i = 0 ; i < 256; i++)
196 paIdt[i].u16Sel = uCs64;
197
198 /* Just in case... */
199 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
200 {
201 uint64_t uIdtr = HCPhysDst + pSwitcher->offGCCode; AssertRelease(uIdtr < UINT32_MAX);
202 CPUMSetHyperIDTR(&pVM->aCpus[iCpu], uIdtr, 16*256 + iCpu);
203 }
204}
205# endif /* VBOX_WITH_64ON32_IDT */
206
207
208/**
[13798]209 * VMMR3Init worker that initiates the switcher code (aka core code).
[1]210 *
[13697]211 * This is core per VM code which might need fixups and/or for ease of use are
212 * put on linear contiguous backing.
213 *
214 * @returns VBox status code.
[58122]215 * @param pVM The cross context VM structure.
[13697]216 */
[13798]217int vmmR3SwitcherInit(PVM pVM)
[13697]218{
[57429]219#if !defined(VBOX_WITH_RAW_MODE) && (HC_ARCH_BITS == 64)
[63429]220 RT_NOREF(pVM);
[26437]221 return VINF_SUCCESS;
222#else
[45786]223
[13697]224 /*
225 * Calc the size.
226 */
[70948]227 const PVMMSWITCHERDEF *papSwitchers = VM_IS_RAW_MODE_ENABLED(pVM) ? g_apRawModeSwitchers : g_apHmSwitchers;
[13697]228 unsigned cbCoreCode = 0;
[45701]229 for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
[13697]230 {
231 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
[45701]232 PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
[13697]233 if (pSwitcher)
234 {
235 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
236 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
237 }
238 }
239
240 /*
[33540]241 * Allocate contiguous pages for switchers and deal with
[13697]242 * conflicts in the intermediate mapping of the code.
243 */
244 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
[20864]245 pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
[13697]246 int rc = VERR_NO_MEMORY;
[13714]247 if (pVM->vmm.s.pvCoreCodeR3)
[13697]248 {
[13714]249 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
[13697]250 if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
251 {
252 /* try more allocations - Solaris, Linux. */
253 const unsigned cTries = 8234;
254 struct VMMInitBadTry
255 {
256 RTR0PTR pvR0;
257 void *pvR3;
258 RTHCPHYS HCPhys;
259 RTUINT cb;
260 } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
261 AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
262 unsigned i = 0;
263 do
264 {
[13714]265 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
266 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
[13697]267 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
268 i++;
[13714]269 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
[13697]270 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
[20864]271 pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
[13714]272 if (!pVM->vmm.s.pvCoreCodeR3)
[13697]273 break;
[13714]274 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
[13697]275 } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
276 && i < cTries - 1);
277
278 /* cleanup */
[13816]279 if (RT_FAILURE(rc))
[13697]280 {
[13714]281 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
282 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
[13697]283 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
284 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
285 i++;
[55177]286 LogRel(("VMM: Failed to allocated and map core code: rc=%Rrc\n", rc));
[13697]287 }
288 while (i-- > 0)
289 {
[66288]290 LogRel(("VMM: Core code alloc attempt #%d: pvR3=%p pvR0=%RKv HCPhys=%RHp\n",
[13697]291 i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
[20864]292 SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
[13697]293 }
294 RTMemTmpFree(paBadTries);
295 }
296 }
[13816]297 if (RT_SUCCESS(rc))
[13697]298 {
299 /*
[48221]300 * Copy the code.
[13697]301 */
[45701]302 for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
[13697]303 {
[45701]304 PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
[13697]305 if (pSwitcher)
[48221]306 {
307 uint8_t *pbDst = (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher];
308 memcpy(pbDst, pSwitcher->pvCode, pSwitcher->cbCode);
309# ifdef VBOX_WITH_64ON32_IDT
310 if ( pSwitcher->enmType == VMMSWITCHER_32_TO_AMD64
311 || pSwitcher->enmType == VMMSWITCHER_PAE_TO_AMD64)
312 vmmR3Switcher32On64IdtInit(pVM, pSwitcher, pbDst,
313 pVM->vmm.s.HCPhysCoreCode + pVM->vmm.s.aoffSwitchers[iSwitcher]);
314# endif
315 }
[13697]316 }
317
318 /*
319 * Map the code into the GC address space.
320 */
321 RTGCPTR GCPtr;
[14597]322 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
323 cbCoreCode, "Core Code", &GCPtr);
[13816]324 if (RT_SUCCESS(rc))
[13697]325 {
[13714]326 pVM->vmm.s.pvCoreCodeRC = GCPtr;
[13697]327 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
[66288]328 LogRel(("VMM: CoreCode: R3=%RHv R0=%RKv RC=%RRv Phys=%RHp cb=%#x\n",
[13714]329 pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
[13697]330
331 /*
[14716]332 * Finally, PGM probably has selected a switcher already but we need
[13697]333 * to get the routine addresses, so we'll reselect it.
334 * This may legally fail so, we're ignoring the rc.
[45701]335 * Note! See HMIsEnabled hack in selector function.
[13697]336 */
337 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
338 return rc;
339 }
340
341 /* shit */
[13820]342 AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
[20864]343 SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
[13697]344 }
345 else
346 VMSetError(pVM, rc, RT_SRC_POS,
347 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
348 cbCoreCode);
349
[13714]350 pVM->vmm.s.pvCoreCodeR3 = NULL;
351 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
352 pVM->vmm.s.pvCoreCodeRC = 0;
[13697]353 return rc;
[26437]354#endif
[13697]355}
356
357/**
[13798]358 * Relocate the switchers, called by VMMR#Relocate.
[13714]359 *
[58122]360 * @param pVM The cross context VM structure.
[1]361 * @param offDelta The relocation delta.
362 */
[13798]363void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
[1]364{
[57429]365#if defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64)
[1]366 /*
[13798]367 * Relocate all the switchers.
[1]368 */
[70948]369 const PVMMSWITCHERDEF *papSwitchers = VM_IS_RAW_MODE_ENABLED(pVM) ? g_apRawModeSwitchers : g_apHmSwitchers;
[45701]370 for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
[1]371 {
[45701]372 PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
[1]373 if (pSwitcher && pSwitcher->pfnRelocate)
374 {
375 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
[23]376 pSwitcher->pfnRelocate(pVM,
[1]377 pSwitcher,
[13717]378 pVM->vmm.s.pvCoreCodeR0 + off,
[13714]379 (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
380 pVM->vmm.s.pvCoreCodeRC + off,
[1]381 pVM->vmm.s.HCPhysCoreCode + off);
[48221]382# ifdef VBOX_WITH_64ON32_IDT
383 if ( pSwitcher->enmType == VMMSWITCHER_32_TO_AMD64
384 || pSwitcher->enmType == VMMSWITCHER_PAE_TO_AMD64)
385 vmmR3Switcher32On64IdtRelocate(pVM, pSwitcher,
386 (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
387 pVM->vmm.s.HCPhysCoreCode + off);
388# endif
[1]389 }
390 }
391
392 /*
[13717]393 * Recalc the RC address for the current switcher.
[1]394 */
[45701]395 PVMMSWITCHERDEF pSwitcher = papSwitchers[pVM->vmm.s.enmSwitcher];
396 if (pSwitcher)
397 {
398 RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
399 pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
400 pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
401 pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
402 pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
403 }
404 else
[70948]405 AssertRelease(!VM_IS_RAW_MODE_ENABLED(pVM));
[1]406
[39078]407#else
408 NOREF(pVM);
[26437]409#endif
[39078]410 NOREF(offDelta);
[1]411}
412
413
[57429]414#if defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64)
[43864]415
[1]416/**
[13798]417 * Generic switcher code relocator.
[1]418 *
[58122]419 * @param pVM The cross context VM structure.
[1]420 * @param pSwitcher The switcher definition.
421 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
[13717]422 * @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
[1]423 * @param GCPtrCode The guest context address corresponding to pu8Code.
424 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
425 * @param SelCS The hypervisor CS selector.
426 * @param SelDS The hypervisor DS selector.
427 * @param SelTSS The hypervisor TSS selector.
428 * @param GCPtrGDT The GC address of the hypervisor GDT.
429 * @param SelCS64 The 64-bit mode hypervisor CS selector.
430 */
[44168]431static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher,
432 RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
[1]433 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
434{
435 union
436 {
437 const uint8_t *pu8;
438 const uint16_t *pu16;
439 const uint32_t *pu32;
440 const uint64_t *pu64;
441 const void *pv;
442 uintptr_t u;
443 } u;
444 u.pv = pSwitcher->pvFixups;
445
446 /*
447 * Process fixups.
448 */
449 uint8_t u8;
450 while ((u8 = *u.pu8++) != FIX_THE_END)
451 {
452 /*
453 * Get the source (where to write the fixup).
454 */
455 uint32_t offSrc = *u.pu32++;
456 Assert(offSrc < pSwitcher->cbCode);
457 union
458 {
459 uint8_t *pu8;
460 uint16_t *pu16;
461 uint32_t *pu32;
462 uint64_t *pu64;
463 uintptr_t u;
464 } uSrc;
465 uSrc.pu8 = pu8CodeR3 + offSrc;
466
467 /* The fixup target and method depends on the type. */
468 switch (u8)
469 {
470 /*
471 * 32-bit relative, source in HC and target in GC.
472 */
473 case FIX_HC_2_GC_NEAR_REL:
474 {
475 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
476 uint32_t offTrg = *u.pu32++;
477 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
478 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
479 break;
480 }
481
482 /*
483 * 32-bit relative, source in HC and target in ID.
484 */
485 case FIX_HC_2_ID_NEAR_REL:
486 {
487 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
488 uint32_t offTrg = *u.pu32++;
489 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
[13717]490 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
[1]491 break;
492 }
493
494 /*
495 * 32-bit relative, source in GC and target in HC.
496 */
497 case FIX_GC_2_HC_NEAR_REL:
498 {
499 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
500 uint32_t offTrg = *u.pu32++;
501 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
[13717]502 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
[1]503 break;
504 }
505
506 /*
507 * 32-bit relative, source in GC and target in ID.
508 */
509 case FIX_GC_2_ID_NEAR_REL:
510 {
[14771]511 AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
[1]512 uint32_t offTrg = *u.pu32++;
513 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
514 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
515 break;
516 }
517
518 /*
519 * 32-bit relative, source in ID and target in HC.
520 */
521 case FIX_ID_2_HC_NEAR_REL:
522 {
523 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
524 uint32_t offTrg = *u.pu32++;
525 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
[13717]526 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
[1]527 break;
528 }
529
530 /*
531 * 32-bit relative, source in ID and target in HC.
532 */
533 case FIX_ID_2_GC_NEAR_REL:
534 {
535 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
536 uint32_t offTrg = *u.pu32++;
537 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
538 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
539 break;
540 }
541
542 /*
543 * 16:32 far jump, target in GC.
544 */
545 case FIX_GC_FAR32:
546 {
547 uint32_t offTrg = *u.pu32++;
548 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
549 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
550 *uSrc.pu16++ = SelCS;
551 break;
552 }
553
554 /*
555 * Make 32-bit GC pointer given CPUM offset.
556 */
557 case FIX_GC_CPUM_OFF:
558 {
559 uint32_t offCPUM = *u.pu32++;
560 Assert(offCPUM < sizeof(pVM->cpum));
[13830]561 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
[1]562 break;
563 }
564
565 /*
[18927]566 * Make 32-bit GC pointer given CPUMCPU offset.
567 */
568 case FIX_GC_CPUMCPU_OFF:
569 {
570 uint32_t offCPUM = *u.pu32++;
571 Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
572 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
573 break;
574 }
575
576 /*
[1]577 * Make 32-bit GC pointer given VM offset.
578 */
579 case FIX_GC_VM_OFF:
580 {
581 uint32_t offVM = *u.pu32++;
582 Assert(offVM < sizeof(VM));
[13830]583 *uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
[1]584 break;
585 }
586
587 /*
588 * Make 32-bit HC pointer given CPUM offset.
589 */
590 case FIX_HC_CPUM_OFF:
591 {
592 uint32_t offCPUM = *u.pu32++;
593 Assert(offCPUM < sizeof(pVM->cpum));
[73097]594 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_UOFFSETOF(VM, cpum) + offCPUM;
[1]595 break;
596 }
597
598 /*
[914]599 * Make 32-bit R0 pointer given VM offset.
[1]600 */
601 case FIX_HC_VM_OFF:
602 {
603 uint32_t offVM = *u.pu32++;
604 Assert(offVM < sizeof(VM));
[914]605 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
[1]606 break;
607 }
608
609 /*
610 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
611 */
612 case FIX_INTER_32BIT_CR3:
613 {
614
615 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
616 break;
617 }
618
619 /*
620 * Store the PAE CR3 (32-bit) for the intermediate memory context.
621 */
622 case FIX_INTER_PAE_CR3:
623 {
624
625 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
626 break;
627 }
628
629 /*
630 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
631 */
632 case FIX_INTER_AMD64_CR3:
633 {
634
635 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
636 break;
637 }
638
639 /*
640 * Store Hypervisor CS (16-bit).
641 */
642 case FIX_HYPER_CS:
643 {
644 *uSrc.pu16 = SelCS;
645 break;
646 }
647
648 /*
649 * Store Hypervisor DS (16-bit).
650 */
651 case FIX_HYPER_DS:
652 {
653 *uSrc.pu16 = SelDS;
654 break;
655 }
656
657 /*
658 * Store Hypervisor TSS (16-bit).
659 */
660 case FIX_HYPER_TSS:
661 {
662 *uSrc.pu16 = SelTSS;
663 break;
664 }
665
666 /*
667 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
668 */
669 case FIX_GC_TSS_GDTE_DW2:
670 {
671 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
672 *uSrc.pu32 = (uint32_t)GCPtr;
673 break;
674 }
675
[30145]676 /*
677 * Store the EFER or mask for the 32->64 bit switcher.
678 */
679 case FIX_EFER_OR_MASK:
680 {
681 uint32_t u32OrMask = MSR_K6_EFER_LME | MSR_K6_EFER_SCE;
[42024]682 /*
683 * We don't care if cpuid 0x8000001 isn't supported as that implies
684 * long mode isn't supported either, so this switched would never be used.
685 */
686 if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
[30145]687 u32OrMask |= MSR_K6_EFER_NXE;
[1]688
[30145]689 *uSrc.pu32 = u32OrMask;
690 break;
691 }
[1]692
[55054]693#if 0 /* Reusable for XSAVE. */
[1]694 /*
695 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
696 */
697 case FIX_NO_FXSAVE_JMP:
698 {
699 uint32_t offTrg = *u.pu32++;
700 Assert(offTrg < pSwitcher->cbCode);
[55062]701 if (!CPUMSupportsXSave(pVM))
[1]702 {
703 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
704 *uSrc.pu32++ = offTrg - (offSrc + 5);
705 }
706 else
707 {
708 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
709 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
710 }
711 break;
712 }
[55054]713#endif
[1]714
715 /*
716 * Insert relative jump to specified target it SYSENTER isn't used by the host.
717 */
718 case FIX_NO_SYSENTER_JMP:
719 {
720 uint32_t offTrg = *u.pu32++;
721 Assert(offTrg < pSwitcher->cbCode);
722 if (!CPUMIsHostUsingSysEnter(pVM))
723 {
724 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
725 *uSrc.pu32++ = offTrg - (offSrc + 5);
726 }
727 else
728 {
729 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
730 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
731 }
732 break;
733 }
734
735 /*
[21942]736 * Insert relative jump to specified target it SYSCALL isn't used by the host.
[1]737 */
738 case FIX_NO_SYSCALL_JMP:
739 {
740 uint32_t offTrg = *u.pu32++;
741 Assert(offTrg < pSwitcher->cbCode);
[21942]742 if (!CPUMIsHostUsingSysCall(pVM))
[1]743 {
744 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
745 *uSrc.pu32++ = offTrg - (offSrc + 5);
746 }
747 else
748 {
749 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
750 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
751 }
752 break;
753 }
754
755 /*
[1283]756 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
757 */
758 case FIX_HC_32BIT:
759 {
760 uint32_t offTrg = *u.pu32++;
761 Assert(offSrc < pSwitcher->cbCode);
762 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
[13717]763 *uSrc.pu32 = R0PtrCode + offTrg;
[1283]764 break;
765 }
766
[57429]767# if defined(RT_ARCH_AMD64)
[1283]768 /*
769 * 64-bit HC Code Selector (no argument).
770 */
771 case FIX_HC_64BIT_CS:
772 {
773 Assert(offSrc < pSwitcher->cbCode);
[1286]774 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
[1283]775 break;
776 }
[14979]777
778 /*
779 * 64-bit HC pointer to the CPUM instance data (no argument).
780 */
781 case FIX_HC_64BIT_CPUM:
782 {
783 Assert(offSrc < pSwitcher->cbCode);
[73097]784 *uSrc.pu64 = pVM->pVMR0 + RT_UOFFSETOF(VM, cpum);
[14979]785 break;
786 }
[45786]787# endif
[1283]788 /*
[14771]789 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
790 */
791 case FIX_HC_64BIT:
792 {
793 uint32_t offTrg = *u.pu32++;
794 Assert(offSrc < pSwitcher->cbCode);
795 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
796 *uSrc.pu64 = R0PtrCode + offTrg;
797 break;
798 }
799
[45786]800# ifdef RT_ARCH_X86
[14979]801 case FIX_GC_64_BIT_CPUM_OFF:
[1]802 {
[14979]803 uint32_t offCPUM = *u.pu32++;
804 Assert(offCPUM < sizeof(pVM->cpum));
805 *uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
[1]806 break;
807 }
[45786]808# endif
[1]809
810 /*
811 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
812 */
813 case FIX_ID_32BIT:
814 {
815 uint32_t offTrg = *u.pu32++;
816 Assert(offSrc < pSwitcher->cbCode);
817 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
818 *uSrc.pu32 = u32IDCode + offTrg;
819 break;
820 }
821
822 /*
823 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
824 */
825 case FIX_ID_64BIT:
[14771]826 case FIX_HC_64BIT_NOCHECK:
[1]827 {
828 uint32_t offTrg = *u.pu32++;
829 Assert(offSrc < pSwitcher->cbCode);
[14771]830 Assert(u8 == FIX_HC_64BIT_NOCHECK || offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
[1]831 *uSrc.pu64 = u32IDCode + offTrg;
832 break;
833 }
834
835 /*
836 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
837 */
838 case FIX_ID_FAR32_TO_64BIT_MODE:
839 {
840 uint32_t offTrg = *u.pu32++;
841 Assert(offSrc < pSwitcher->cbCode);
842 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
843 *uSrc.pu32++ = u32IDCode + offTrg;
844 *uSrc.pu16 = SelCS64;
845 AssertRelease(SelCS64);
846 break;
847 }
848
[45786]849# ifdef VBOX_WITH_NMI
[1]850 /*
851 * 32-bit address to the APIC base.
852 */
853 case FIX_GC_APIC_BASE_32BIT:
854 {
855 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
856 break;
857 }
[45786]858# endif
[1]859
860 default:
861 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
862 break;
863 }
864 }
865
[45786]866# ifdef LOG_ENABLED
[1]867 /*
868 * If Log2 is enabled disassemble the switcher code.
869 *
870 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
871 */
872 if (LogIs2Enabled())
873 {
874 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
[13717]875 " R0PtrCode = %p\n"
[1]876 " pu8CodeR3 = %p\n"
[13823]877 " GCPtrCode = %RGv\n"
[1]878 " u32IDCode = %08x\n"
[13820]879 " pVMRC = %RRv\n"
880 " pCPUMRC = %RRv\n"
881 " pVMR3 = %p\n"
882 " pCPUMR3 = %p\n"
[13823]883 " GCPtrGDT = %RGv\n"
[13820]884 " InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
[18927]885 " HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
[1]886 " SelCS = %04x\n"
887 " SelDS = %04x\n"
888 " SelCS64 = %04x\n"
889 " SelTSS = %04x\n",
890 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
[13820]891 R0PtrCode,
892 pu8CodeR3,
893 GCPtrCode,
894 u32IDCode,
895 VM_RC_ADDR(pVM, pVM),
896 VM_RC_ADDR(pVM, &pVM->cpum),
897 pVM,
898 &pVM->cpum,
[1]899 GCPtrGDT,
[13820]900 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
[18927]901 PGMGetHyperCR3(VMMGetCpu(pVM)),
[1]902 SelCS, SelDS, SelCS64, SelTSS);
903
904 uint32_t offCode = 0;
905 while (offCode < pSwitcher->cbCode)
906 {
907 /*
908 * Figure out where this is.
909 */
910 const char *pszDesc = NULL;
911 RTUINTPTR uBase;
912 uint32_t cbCode;
913 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
914 {
915 pszDesc = "HCCode0";
[13717]916 uBase = R0PtrCode;
[1]917 offCode = pSwitcher->offHCCode0;
918 cbCode = pSwitcher->cbHCCode0;
919 }
920 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
921 {
922 pszDesc = "HCCode1";
[13717]923 uBase = R0PtrCode;
[1]924 offCode = pSwitcher->offHCCode1;
925 cbCode = pSwitcher->cbHCCode1;
926 }
927 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
928 {
929 pszDesc = "GCCode";
930 uBase = GCPtrCode;
931 offCode = pSwitcher->offGCCode;
932 cbCode = pSwitcher->cbGCCode;
933 }
934 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
935 {
936 pszDesc = "IDCode0";
937 uBase = u32IDCode;
938 offCode = pSwitcher->offIDCode0;
939 cbCode = pSwitcher->cbIDCode0;
940 }
941 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
942 {
943 pszDesc = "IDCode1";
944 uBase = u32IDCode;
945 offCode = pSwitcher->offIDCode1;
946 cbCode = pSwitcher->cbIDCode1;
947 }
948 else
949 {
950 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
[24009]951 offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
[1]952 offCode++;
953 continue;
954 }
955
956 /*
957 * Disassemble it.
958 */
959 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
[7015]960
[1]961 while (cbCode > 0)
962 {
963 /* try label it */
[41976]964 if (pSwitcher->offR0ToRawMode == offCode)
965 RTLogPrintf(" *R0ToRawMode:\n");
966 if (pSwitcher->offRCToHost == offCode)
967 RTLogPrintf(" *RCToHost:\n");
968 if (pSwitcher->offRCCallTrampoline == offCode)
969 RTLogPrintf(" *RCCallTrampoline:\n");
970 if (pSwitcher->offRCToHostAsm == offCode)
971 RTLogPrintf(" *RCToHostAsm:\n");
972 if (pSwitcher->offRCToHostAsmNoReturn == offCode)
973 RTLogPrintf(" *RCToHostAsmNoReturn:\n");
[1]974
975 /* disas */
[41671]976 uint32_t cbInstr = 0;
977 DISCPUSTATE Cpu;
978 char szDisas[256];
[41675]979 int rc = DISInstr(pu8CodeR3 + offCode, DISCPUMODE_32BIT, &Cpu, &cbInstr);
[41671]980 if (RT_SUCCESS(rc))
981 {
982 Cpu.uInstrAddr += uBase - (uintptr_t)pu8CodeR3;
[41679]983 DISFormatYasmEx(&Cpu, szDisas, sizeof(szDisas),
984 DIS_FMT_FLAGS_ADDR_LEFT | DIS_FMT_FLAGS_BYTES_LEFT | DIS_FMT_FLAGS_BYTES_SPACED
985 | DIS_FMT_FLAGS_RELATIVE_BRANCH,
986 NULL, NULL);
[41671]987 }
988 if (RT_SUCCESS(rc))
989 RTLogPrintf(" %04x: %s\n", offCode, szDisas);
[1]990 else
991 {
[41671]992 RTLogPrintf(" %04x: %02x '%c' (rc=%Rrc\n",
993 offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ', rc);
[1]994 cbInstr = 1;
995 }
996 offCode += cbInstr;
997 cbCode -= RT_MIN(cbInstr, cbCode);
998 }
999 }
1000 }
[45786]1001# endif
[1]1002}
1003
1004/**
[45750]1005 * Wrapper around SELMGetHyperGDT() that avoids calling it when raw-mode context
1006 * is not initialized.
1007 *
1008 * @returns Raw-mode contet GDT address. Null pointer if not applicable.
[58122]1009 * @param pVM The cross context VM structure.
[45750]1010 */
1011static RTRCPTR vmmR3SwitcherGetHyperGDT(PVM pVM)
1012{
[73324]1013 if (VM_IS_RAW_MODE_ENABLED(pVM) || HMIsRawModeCtxNeeded(pVM))
[45750]1014 return SELMGetHyperGDT(pVM);
[57429]1015# if HC_ARCH_BITS != 32
[45750]1016 AssertFailed(); /* This path is only applicable to some 32-bit hosts. */
[45786]1017# endif
[45750]1018 return NIL_RTRCPTR;
1019}
1020
1021/**
[1]1022 * Relocator for the 32-Bit to 32-Bit world switcher.
1023 */
[13717]1024DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
[1]1025{
[13717]1026 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
[1]1027 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1028}
1029
1030
1031/**
1032 * Relocator for the 32-Bit to PAE world switcher.
1033 */
[13717]1034DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
[1]1035{
[13717]1036 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
[1]1037 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1038}
1039
1040
1041/**
[14138]1042 * Relocator for the 32-Bit to AMD64 world switcher.
1043 */
[14139]1044DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
[14138]1045{
1046 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
[45750]1047 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), vmmR3SwitcherGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
[14138]1048}
1049
1050
1051/**
[1]1052 * Relocator for the PAE to 32-Bit world switcher.
1053 */
[13717]1054DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
[1]1055{
[13717]1056 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
[1]1057 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1058}
1059
1060
1061/**
1062 * Relocator for the PAE to PAE world switcher.
1063 */
[13717]1064DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
[1]1065{
[13717]1066 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
[1]1067 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1068}
1069
[14771]1070/**
1071 * Relocator for the PAE to AMD64 world switcher.
1072 */
1073DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1074{
1075 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
[45750]1076 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), vmmR3SwitcherGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
[14771]1077}
[1]1078
[14771]1079
[1]1080/**
[14167]1081 * Relocator for the AMD64 to 32-bit world switcher.
1082 */
1083DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1084{
1085 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1086 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1087}
1088
1089
1090/**
[1]1091 * Relocator for the AMD64 to PAE world switcher.
1092 */
[13717]1093DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
[1]1094{
[13717]1095 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
[1]1096 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1097}
1098
1099
1100/**
[36415]1101 * Selects the switcher to be used for switching to raw-mode context.
[1]1102 *
1103 * @returns VBox status code.
[58122]1104 * @param pVM The cross context VM structure.
[1]1105 * @param enmSwitcher The new switcher.
1106 * @remark This function may be called before the VMM is initialized.
1107 */
[34322]1108VMMR3_INT_DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
[1]1109{
1110 /*
1111 * Validate input.
1112 */
1113 if ( enmSwitcher < VMMSWITCHER_INVALID
1114 || enmSwitcher >= VMMSWITCHER_MAX)
1115 {
1116 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1117 return VERR_INVALID_PARAMETER;
1118 }
1119
[45701]1120 /*
1121 * Override it if HM is active.
1122 */
[70948]1123 if (!VM_IS_RAW_MODE_ENABLED(pVM))
[45701]1124 pVM->vmm.s.enmSwitcher = HC_ARCH_BITS == 64 ? VMMSWITCHER_AMD64_STUB : VMMSWITCHER_X86_STUB;
[9539]1125
[1]1126 /*
1127 * Select the new switcher.
1128 */
[70948]1129 const PVMMSWITCHERDEF *papSwitchers = VM_IS_RAW_MODE_ENABLED(pVM) ? g_apRawModeSwitchers : g_apHmSwitchers;
[45701]1130 PVMMSWITCHERDEF pSwitcher = papSwitchers[enmSwitcher];
[1]1131 if (pSwitcher)
1132 {
1133 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1134 pVM->vmm.s.enmSwitcher = enmSwitcher;
1135
[13714]1136 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
[41976]1137 pVM->vmm.s.pfnR0ToRawMode = pbCodeR0 + pSwitcher->offR0ToRawMode;
[1]1138
[41933]1139 RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
[41976]1140 pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
1141 pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
1142 pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
1143 pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
[1]1144 return VINF_SUCCESS;
1145 }
[13798]1146
[1]1147 return VERR_NOT_IMPLEMENTED;
1148}
1149
[57429]1150#endif /* #defined(VBOX_WITH_RAW_MODE) || (HC_ARCH_BITS != 64) */
[13798]1151
[43864]1152
[70950]1153#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
[1]1154/**
[14845]1155 * Gets the switcher to be used for switching to GC.
1156 *
[70948]1157 * This is for 64-on-32 with HM. Caller is HMR3Relocate().
1158 *
[14845]1159 * @returns host to guest ring 0 switcher entrypoint
[58122]1160 * @param pVM The cross context VM structure.
[14845]1161 * @param enmSwitcher The new switcher.
1162 */
[34322]1163VMMR3_INT_DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
[14845]1164{
1165 /*
1166 * Validate input.
1167 */
[45750]1168 AssertMsgReturn( enmSwitcher == VMMSWITCHER_32_TO_AMD64
1169 || enmSwitcher == VMMSWITCHER_PAE_TO_AMD64,
1170 ("%d\n", enmSwitcher),
1171 NIL_RTR0PTR);
1172 AssertReturn(HMIsEnabled(pVM), NIL_RTR0PTR);
[14845]1173
1174 /*
1175 * Select the new switcher.
1176 */
[45750]1177 const PVMMSWITCHERDEF *papSwitchers = g_apHmSwitchers;
[45701]1178 PVMMSWITCHERDEF pSwitcher = papSwitchers[enmSwitcher];
[14845]1179 if (pSwitcher)
1180 {
[45750]1181 /** @todo fix the pvCoreCodeR0 type */
1182 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher];
[41976]1183 return pbCodeR0 + pSwitcher->offR0ToRawMode;
[14845]1184 }
[20557]1185 return NIL_RTR0PTR;
[14845]1186}
[70948]1187#endif
1188
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