VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 50653

Last change on this file since 50653 was 46420, checked in by vboxsync, 11 years ago

VMM, recompiler: Purge deprecated macros.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 77.8 KB
Line 
1/* $Id: TRPM.cpp 46420 2013-06-06 16:27:25Z vboxsync $ */
2/** @file
3 * TRPM - The Trap Monitor.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_trpm TRPM - The Trap Monitor
19 *
20 * The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21 * the VMM. It plays a major role in raw-mode execution and a lesser one in the
22 * hardware assisted mode.
23 *
24 * Note first, the following will use trap as a collective term for faults,
25 * aborts and traps.
26 *
27 * @see grp_trpm
28 *
29 *
30 * @section sec_trpm_rc Raw-Mode Context
31 *
32 * When executing in the raw-mode context, TRPM will be managing the IDT and
33 * processing all traps and interrupts. It will also monitor the guest IDT
34 * because CSAM wishes to know about changes to it (trap/interrupt/syscall
35 * handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36 * considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37 *
38 * External interrupts will be forwarded to the host context by the quickest
39 * possible route where they will be reasserted. The other events will be
40 * categorized into virtualization traps, genuine guest traps and hypervisor
41 * traps. The latter group may be recoverable depending on when they happen and
42 * whether there is a handler for it, otherwise it will cause a guru meditation.
43 *
44 * TRPM distinguishes the between the first two (virt and guest traps) and the
45 * latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46 * it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47 * dispatcher tables, one ad-hoc for one time traps registered via
48 * TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49 * The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50 *
51 * The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52 * part), will call up the other VMM sub-systems depending on what it things
53 * happens. The two most busy traps are page faults (\#PF) and general
54 * protection fault/trap (\#GP).
55 *
56 * Before resuming guest code after having taken a virtualization trap or
57 * injected a guest trap, TRPM will check for pending forced action and
58 * every now and again let TM check for timed out timers. This allows code that
59 * is being executed as part of virtualization traps to signal ring-3 exits,
60 * page table resyncs and similar without necessarily using the status code. It
61 * also make sure we're more responsive to timers and requests from other
62 * threads (necessarily running on some different core/cpu in most cases).
63 *
64 *
65 * @section sec_trpm_all All Contexts
66 *
67 * TRPM will also dispatch / inject interrupts and traps to the guest, both when
68 * in raw-mode and when in hardware assisted mode. See TRPMInject().
69 *
70 */
71
72/*******************************************************************************
73* Header Files *
74*******************************************************************************/
75#define LOG_GROUP LOG_GROUP_TRPM
76#include <VBox/vmm/trpm.h>
77#include <VBox/vmm/cpum.h>
78#include <VBox/vmm/selm.h>
79#include <VBox/vmm/ssm.h>
80#include <VBox/vmm/pdmapi.h>
81#include <VBox/vmm/em.h>
82#include <VBox/vmm/pgm.h>
83#include "internal/pgm.h"
84#include <VBox/vmm/dbgf.h>
85#include <VBox/vmm/mm.h>
86#include <VBox/vmm/stam.h>
87#include <VBox/vmm/csam.h>
88#include <VBox/vmm/patm.h>
89#include "TRPMInternal.h"
90#include <VBox/vmm/vm.h>
91#include <VBox/vmm/em.h>
92#ifdef VBOX_WITH_REM
93# include <VBox/vmm/rem.h>
94#endif
95#include <VBox/vmm/hm.h>
96
97#include <VBox/err.h>
98#include <VBox/param.h>
99#include <VBox/log.h>
100#include <iprt/assert.h>
101#include <iprt/asm.h>
102#include <iprt/string.h>
103#include <iprt/alloc.h>
104
105
106/*******************************************************************************
107* Structures and Typedefs *
108*******************************************************************************/
109/**
110 * Trap handler function.
111 * @todo need to specialize this as we go along.
112 */
113typedef enum TRPMHANDLER
114{
115 /** Generic Interrupt handler. */
116 TRPM_HANDLER_INT = 0,
117 /** Generic Trap handler. */
118 TRPM_HANDLER_TRAP,
119 /** Trap 8 (\#DF) handler. */
120 TRPM_HANDLER_TRAP_08,
121 /** Trap 12 (\#MC) handler. */
122 TRPM_HANDLER_TRAP_12,
123 /** Max. */
124 TRPM_HANDLER_MAX
125} TRPMHANDLER, *PTRPMHANDLER;
126
127
128/*******************************************************************************
129* Global Variables *
130*******************************************************************************/
131/** Preinitialized IDT.
132 * The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
133 * will use to pick the right address. The u16SegSel is always VMM CS.
134 */
135static VBOXIDTE_GENERIC g_aIdt[256] =
136{
137/* special trap handler - still, this is an interrupt gate not a trap gate... */
138#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
139/* generic trap handler. */
140#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
141/* special interrupt handler. */
142#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
143/* generic interrupt handler. */
144#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
145/* special task gate IDT entry (for critical exceptions like #DF). */
146#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
147/* draft, fixme later when the handler is written. */
148#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
149
150 /* N - M M - T - C - D i */
151 /* o - n o - y - o - e p */
152 /* - e n - p - d - s t */
153 /* - i - e - e - c . */
154 /* - c - - - r */
155 /* ============================================================= */
156 IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
157 IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
158#ifdef VBOX_WITH_NMI
159 IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
160#else
161 IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
162#endif
163 IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
164 IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
165 IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
166 IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
167 IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
168 IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
169 IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
170 IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
171 IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
172 IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
173 IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
174 IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
175 IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
176 IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
177 IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
178 IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
179 IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
180 IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
181 IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
182 IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
183 IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
184 IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
185 IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
186 IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
187 IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
188 IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
189 IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
190 IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
191 IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
192 IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
193 IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
194 IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
195 IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
196 IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
197 IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
198 IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
199 IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
200 IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
201 IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
202 IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
203 IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
204 IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
205 IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
206 IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
207 IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
208 IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
209 IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
210 IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
211 IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
212 IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
213 IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
214 IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
215 IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
216 IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
217 IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
218 IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
219 IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
220 IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
221 IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
222 IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
223 IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
224 IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
225 IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
226 IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
227 IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
228 IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
229 IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
230 IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
231 IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
232 IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
233 IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
234 IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
235 IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
236 IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
237 IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
238 IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
239 IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
240 IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
241 IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
242 IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
243 IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
244 IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
245 IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
246 IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
247 IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
248 IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
249 IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
250 IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
251 IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
252 IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
253 IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
254 IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
255 IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
256 IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
257 IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
258 IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
259 IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
260 IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
261 IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
262 IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
263 IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
264 IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
265 IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
266 IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
267 IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
268 IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
269 IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
270 IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
271 IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
272 IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
273 IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
274 IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
275 IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
276 IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
277 IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
278 IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
279 IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
280 IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
281 IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
282 IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
283 IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
284 IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
285 IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
286 IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
287 IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
288 IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
289 IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
290 IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
291 IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
292 IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
293 IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
294 IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
295 IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
296 IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
297 IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
298 IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
299 IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
300 IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
301 IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
302 IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
303 IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
304 IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
305 IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
306 IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
307 IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
308 IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
309 IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
310 IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
311 IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
312 IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
313 IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
314 IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
315 IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
316 IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
317 IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
318 IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
319 IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
320 IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
321 IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
322 IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
323 IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
324 IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
325 IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
326 IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
327 IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
328 IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
329 IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
330 IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
331 IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
332 IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
333 IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
334 IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
335 IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
336 IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
337 IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
338 IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
339 IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
340 IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
341 IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
342 IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
343 IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
344 IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
345 IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
346 IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
347 IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
348 IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
349 IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
350 IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
351 IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
352 IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
353 IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
354 IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
355 IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
356 IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
357 IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
358 IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
359 IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
360 IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
361 IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
362 IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
363 IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
364 IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
365 IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
366 IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
367 IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
368 IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
369 IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
370 IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
371 IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
372 IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
373 IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
374 IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
375 IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
376 IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
377 IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
378 IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
379 IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
380 IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
381 IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
382 IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
383 IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
384 IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
385 IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
386 IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
387 IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
388 IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
389 IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
390 IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
391 IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
392 IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
393 IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
394 IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
395 IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
396 IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
397 IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
398 IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
399 IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
400 IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
401 IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
402 IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
403 IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
404 IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
405 IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
406 IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
407 IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
408 IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
409 IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
410 IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
411 IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
412 IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
413 IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
414 IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
415 IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
416#undef IDTE_TRAP
417#undef IDTE_TRAP_GEN
418#undef IDTE_INT
419#undef IDTE_INT_GEN
420#undef IDTE_TASK
421#undef IDTE_UNUSED
422#undef IDTE_RESERVED
423};
424
425
426#ifdef VBOX_WITH_RAW_MODE
427/** Enable or disable tracking of Guest's IDT. */
428# define TRPM_TRACK_GUEST_IDT_CHANGES
429/** Enable or disable tracking of Shadow IDT. */
430# define TRPM_TRACK_SHADOW_IDT_CHANGES
431#endif
432
433/** TRPM saved state version. */
434#define TRPM_SAVED_STATE_VERSION 9
435#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
436
437
438/*******************************************************************************
439* Internal Functions *
440*******************************************************************************/
441static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
442static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
443#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
444static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
445#endif
446
447
448/**
449 * Initializes the Trap Manager
450 *
451 * @returns VBox status code.
452 * @param pVM Pointer to the VM.
453 */
454VMMR3DECL(int) TRPMR3Init(PVM pVM)
455{
456 LogFlow(("TRPMR3Init\n"));
457
458 /*
459 * Assert sizes and alignments.
460 */
461 AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
462 AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
463 AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
464 AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
465
466 /*
467 * Initialize members.
468 */
469 pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
470 pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
471
472 for (VMCPUID i = 0; i < pVM->cCpus; i++)
473 {
474 PVMCPU pVCpu = &pVM->aCpus[i];
475
476 pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
477 pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
478 pVCpu->trpm.s.uActiveVector = ~0U;
479 }
480
481 pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
482 pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
483 pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
484
485 /*
486 * Read the configuration (if any).
487 */
488 PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
489 if (pTRPMNode)
490 {
491 bool f;
492 int rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
493 if (RT_SUCCESS(rc))
494 pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
495 }
496
497 /* write config summary to log */
498 if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
499 LogRel(("TRPM: Dropping Guest IDT Monitoring.\n"));
500
501 /*
502 * Initialize the IDT.
503 * The handler addresses will be set in the TRPMR3Relocate() function.
504 */
505 Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
506 memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
507
508 /*
509 * Register the saved state data unit.
510 */
511 int rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
512 NULL, NULL, NULL,
513 NULL, trpmR3Save, NULL,
514 NULL, trpmR3Load, NULL);
515 if (RT_FAILURE(rc))
516 return rc;
517
518 /*
519 * Statistics.
520 */
521#ifdef VBOX_WITH_RAW_MODE
522 if (!HMIsEnabled(pVM))
523 {
524 STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
525 STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
526 STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
527
528 /* traps */
529 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
530 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
531 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
532 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
533 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
534 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
535 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
536 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
537 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
538 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
539 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
540 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
541 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
542 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
543 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
544 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
545 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
546 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
547 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
548 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
549 }
550#endif
551
552# ifdef VBOX_WITH_STATISTICS
553 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
554 AssertRCReturn(rc, rc);
555 pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
556 for (unsigned i = 0; i < 256; i++)
557 STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
558 i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
559
560# ifdef VBOX_WITH_RAW_MODE
561 if (!HMIsEnabled(pVM))
562 {
563 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
564 AssertRCReturn(rc, rc);
565 pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
566 for (unsigned i = 0; i < 256; i++)
567 STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
568 "Host interrupts.", "/TRPM/HostIRQs/%02x", i);
569 }
570# endif
571# endif
572
573#ifdef VBOX_WITH_RAW_MODE
574 if (!HMIsEnabled(pVM))
575 {
576 STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
577 STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
578 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
579 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
580 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
581 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
582
583 STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
584 STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
585 }
586#endif
587
588#ifdef VBOX_WITH_RAW_MODE
589 /*
590 * Default action when entering raw mode for the first time
591 */
592 if (!HMIsEnabled(pVM))
593 {
594 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
595 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
596 }
597#endif
598 return 0;
599}
600
601
602/**
603 * Applies relocations to data and code managed by this component.
604 *
605 * This function will be called at init and whenever the VMM need
606 * to relocate itself inside the GC.
607 *
608 * @param pVM Pointer to the VM.
609 * @param offDelta Relocation delta relative to old location.
610 */
611VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
612{
613#ifdef VBOX_WITH_RAW_MODE
614 if (HMIsEnabled(pVM))
615 return;
616
617 /* Only applies to raw mode which supports only 1 VCPU. */
618 PVMCPU pVCpu = &pVM->aCpus[0];
619 LogFlow(("TRPMR3Relocate\n"));
620
621 /*
622 * Get the trap handler addresses.
623 *
624 * If VMMGC.gc is screwed, so are we. We'll assert here since it elsewise
625 * would make init order impossible if we should assert the presence of these
626 * exports in TRPMR3Init().
627 */
628 RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
629 RT_ZERO(aRCPtrs);
630 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
631 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
632
633 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
634 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMGC.gc!\n"));
635
636 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
637 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMGC.gc!\n"));
638
639 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
640 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMGC.gc!\n"));
641
642 RTSEL SelCS = CPUMGetHyperCS(pVCpu);
643
644 /*
645 * Iterate the idt and set the addresses.
646 */
647 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
648 PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
649 for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
650 {
651 if ( pIdte->Gen.u1Present
652 && !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
653 )
654 {
655 Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
656 RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
657 switch (pIdteTemplate->u16OffsetLow)
658 {
659 /*
660 * Generic handlers have different entrypoints for each possible
661 * vector number. These entrypoints makes a sort of an array with
662 * 8 byte entries where the vector number is the index.
663 * See TRPMGCHandlersA.asm for details.
664 */
665 case TRPM_HANDLER_INT:
666 case TRPM_HANDLER_TRAP:
667 Offset += i * 8;
668 break;
669 case TRPM_HANDLER_TRAP_12:
670 break;
671 case TRPM_HANDLER_TRAP_08:
672 /* Handle #DF Task Gate in special way. */
673 pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
674 pIdte->Gen.u16OffsetLow = 0;
675 pIdte->Gen.u16OffsetHigh = 0;
676 SELMSetTrap8EIP(pVM, Offset);
677 continue;
678 }
679 /* (non-task gates only ) */
680 pIdte->Gen.u16OffsetLow = Offset & 0xffff;
681 pIdte->Gen.u16OffsetHigh = Offset >> 16;
682 pIdte->Gen.u16SegSel = SelCS;
683 }
684 }
685
686 /*
687 * Update IDTR (limit is including!).
688 */
689 CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
690
691# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
692 if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
693 {
694 rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
695 AssertRC(rc);
696 }
697 pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
698 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
699 0, 0, "trpmRCShadowIDTWriteHandler", 0, "Shadow IDT write access handler");
700 AssertRC(rc);
701# endif
702
703 /* Relocate IDT handlers for forwarding guest traps/interrupts. */
704 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
705 {
706 if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
707 {
708 Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
709 pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
710 }
711
712 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
713 {
714 PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
715 RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
716
717 Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
718 pHandler += offDelta;
719
720 pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
721 pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
722 }
723 }
724
725# ifdef VBOX_WITH_STATISTICS
726 pVM->trpm.s.paStatForwardedIRQRC += offDelta;
727 pVM->trpm.s.paStatHostIrqRC += offDelta;
728# endif
729#endif /* VBOX_WITH_RAW_MODE */
730}
731
732
733/**
734 * Terminates the Trap Manager
735 *
736 * @returns VBox status code.
737 * @param pVM Pointer to the VM.
738 */
739VMMR3DECL(int) TRPMR3Term(PVM pVM)
740{
741 NOREF(pVM);
742 return VINF_SUCCESS;
743}
744
745
746/**
747 * Resets a virtual CPU.
748 *
749 * Used by TRPMR3Reset and CPU hot plugging.
750 *
751 * @param pVCpu Pointer to the VMCPU.
752 */
753VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
754{
755 pVCpu->trpm.s.uActiveVector = ~0U;
756}
757
758
759/**
760 * The VM is being reset.
761 *
762 * For the TRPM component this means that any IDT write monitors
763 * needs to be removed, any pending trap cleared, and the IDT reset.
764 *
765 * @param pVM Pointer to the VM.
766 */
767VMMR3DECL(void) TRPMR3Reset(PVM pVM)
768{
769 /*
770 * Deregister any virtual handlers.
771 */
772#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
773 if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
774 {
775 if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
776 {
777 int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
778 AssertRC(rc);
779 }
780 pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
781 }
782 pVM->trpm.s.GuestIdtr.cbIdt = 0;
783#endif
784
785 /*
786 * Reinitialize other members calling the relocator to get things right.
787 */
788 for (VMCPUID i = 0; i < pVM->cCpus; i++)
789 TRPMR3ResetCpu(&pVM->aCpus[i]);
790 memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
791 memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
792 TRPMR3Relocate(pVM, 0);
793
794#ifdef VBOX_WITH_RAW_MODE
795 /*
796 * Default action when entering raw mode for the first time
797 */
798 if (!HMIsEnabled(pVM))
799 {
800 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
801 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
802 }
803#endif
804}
805
806
807# ifdef VBOX_WITH_RAW_MODE
808/**
809 * Resolve a builtin RC symbol.
810 *
811 * Called by PDM when loading or relocating RC modules.
812 *
813 * @returns VBox status
814 * @param pVM Pointer to the VM.
815 * @param pszSymbol Symbol to resolv
816 * @param pRCPtrValue Where to store the symbol value.
817 *
818 * @remark This has to work before VMMR3Relocate() is called.
819 */
820VMMR3_INT_DECL(int) TRPMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
821{
822 if (!strcmp(pszSymbol, "g_TRPM"))
823 *pRCPtrValue = VM_RC_ADDR(pVM, &pVM->trpm);
824 else if (!strcmp(pszSymbol, "g_TRPMCPU"))
825 *pRCPtrValue = VM_RC_ADDR(pVM, &pVM->aCpus[0].trpm);
826 else if (!strcmp(pszSymbol, "g_trpmGuestCtxCore"))
827 {
828 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
829 *pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
830 }
831 else if (!strcmp(pszSymbol, "g_trpmHyperCtxCore"))
832 {
833 PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
834 *pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
835 }
836 else
837 return VERR_SYMBOL_NOT_FOUND;
838 return VINF_SUCCESS;
839}
840#endif /* VBOX_WITH_RAW_MODE */
841
842
843/**
844 * Execute state save operation.
845 *
846 * @returns VBox status code.
847 * @param pVM Pointer to the VM.
848 * @param pSSM SSM operation handle.
849 */
850static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
851{
852 PTRPM pTrpm = &pVM->trpm.s;
853 LogFlow(("trpmR3Save:\n"));
854
855 /*
856 * Active and saved traps.
857 */
858 for (VMCPUID i = 0; i < pVM->cCpus; i++)
859 {
860 PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
861 SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
862 SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
863 SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
864 SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
865 SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
866 SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
867 SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
868 SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
869 SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
870 }
871 SSMR3PutBool(pSSM, HMIsEnabled(pVM));
872 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
873 SSMR3PutUInt(pSSM, VM_WHEN_RAW_MODE(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT), 0));
874 SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
875 SSMR3PutU32(pSSM, ~0); /* separator. */
876
877 /*
878 * Save any trampoline gates.
879 */
880 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
881 {
882 if (pTrpm->aGuestTrapHandler[iTrap])
883 {
884 SSMR3PutU32(pSSM, iTrap);
885 SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
886 SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
887 }
888 }
889
890 return SSMR3PutU32(pSSM, ~0); /* terminator */
891}
892
893
894/**
895 * Execute state load operation.
896 *
897 * @returns VBox status code.
898 * @param pVM Pointer to the VM.
899 * @param pSSM SSM operation handle.
900 * @param uVersion Data layout version.
901 * @param uPass The data pass.
902 */
903static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
904{
905 LogFlow(("trpmR3Load:\n"));
906 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
907
908 /*
909 * Validate version.
910 */
911 if ( uVersion != TRPM_SAVED_STATE_VERSION
912 && uVersion != TRPM_SAVED_STATE_VERSION_UNI)
913 {
914 AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
915 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
916 }
917
918 /*
919 * Call the reset function to kick out any handled gates and other potential trouble.
920 */
921 TRPMR3Reset(pVM);
922
923 /*
924 * Active and saved traps.
925 */
926 PTRPM pTrpm = &pVM->trpm.s;
927
928 if (uVersion == TRPM_SAVED_STATE_VERSION)
929 {
930 for (VMCPUID i = 0; i < pVM->cCpus; i++)
931 {
932 PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
933 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
934 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
935 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
936 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
937 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
938 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
939 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
940 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
941 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
942 }
943
944 bool fIgnored;
945 SSMR3GetBool(pSSM, &fIgnored);
946 }
947 else
948 {
949 PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
950 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
951 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
952 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
953 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
954 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
955 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
956 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
957 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
958 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
959
960 RTGCUINT fIgnored;
961 SSMR3GetGCUInt(pSSM, &fIgnored);
962 }
963
964 RTUINT fSyncIDT;
965 int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
966 if (RT_FAILURE(rc))
967 return rc;
968 if (fSyncIDT & ~1)
969 {
970 AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
971 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
972 }
973#ifdef VBOX_WITH_RAW_MODE
974 if (fSyncIDT)
975 {
976 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
977 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
978 }
979 /* else: cleared by reset call above. */
980#endif
981
982 SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
983
984 /* check the separator */
985 uint32_t u32Sep;
986 rc = SSMR3GetU32(pSSM, &u32Sep);
987 if (RT_FAILURE(rc))
988 return rc;
989 if (u32Sep != (uint32_t)~0)
990 {
991 AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
992 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
993 }
994
995 /*
996 * Restore any trampoline gates.
997 */
998 for (;;)
999 {
1000 /* gate number / terminator */
1001 uint32_t iTrap;
1002 rc = SSMR3GetU32(pSSM, &iTrap);
1003 if (RT_FAILURE(rc))
1004 return rc;
1005 if (iTrap == (uint32_t)~0)
1006 break;
1007 if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
1008 || pTrpm->aGuestTrapHandler[iTrap])
1009 {
1010 AssertMsgFailed(("iTrap=%#x\n", iTrap));
1011 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1012 }
1013
1014 /* restore the IDT entry. */
1015 RTGCPTR GCPtrHandler;
1016 SSMR3GetGCPtr(pSSM, &GCPtrHandler);
1017 VBOXIDTE Idte;
1018 rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
1019 if (RT_FAILURE(rc))
1020 return rc;
1021 Assert(GCPtrHandler);
1022 pTrpm->aIdt[iTrap] = Idte;
1023 }
1024
1025 return VINF_SUCCESS;
1026}
1027
1028#ifdef VBOX_WITH_RAW_MODE
1029
1030/**
1031 * Check if gate handlers were updated
1032 * (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
1033 *
1034 * @returns VBox status code.
1035 * @param pVM Pointer to the VM.
1036 * @param pVCpu Pointer to the VMCPU.
1037 */
1038VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
1039{
1040 STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
1041 const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
1042 int rc;
1043
1044 AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1045
1046 if (fRawRing0 && CSAMIsEnabled(pVM))
1047 {
1048 /* Clear all handlers */
1049 Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
1050 /** @todo inefficient, but simple */
1051 for (unsigned iGate = 0; iGate < 256; iGate++)
1052 trpmClearGuestTrapHandler(pVM, iGate);
1053
1054 /* Scan them all (only the first time) */
1055 CSAMR3CheckGates(pVM, 0, 256);
1056 }
1057
1058 /*
1059 * Get the IDTR.
1060 */
1061 VBOXIDTR IDTR;
1062 IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
1063 if (!IDTR.cbIdt)
1064 {
1065 Log(("No IDT entries...\n"));
1066 return DBGFSTOP(pVM);
1067 }
1068
1069# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1070 /*
1071 * Check if Guest's IDTR has changed.
1072 */
1073 if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1074 || IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1075 {
1076 Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1077 if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1078 {
1079 /*
1080 * [Re]Register write virtual handler for guest's IDT.
1081 */
1082 if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1083 {
1084 rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1085 AssertRCReturn(rc, rc);
1086 }
1087 /* limit is including */
1088 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1089 0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1090
1091 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1092 {
1093 /* Could be a conflict with CSAM */
1094 CSAMR3RemovePage(pVM, IDTR.pIdt);
1095 if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1096 CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1097
1098 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1099 0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1100 }
1101
1102 AssertRCReturn(rc, rc);
1103 }
1104
1105 /* Update saved Guest IDTR. */
1106 pVM->trpm.s.GuestIdtr = IDTR;
1107 }
1108# endif
1109
1110 /*
1111 * Sync the interrupt gate.
1112 * Should probably check/sync the others too, but for now we'll handle that in #GP.
1113 */
1114 X86DESC Idte3;
1115 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1116 if (RT_FAILURE(rc))
1117 {
1118 AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1119 return DBGFSTOP(pVM);
1120 }
1121 AssertRCReturn(rc, rc);
1122 if (fRawRing0)
1123 pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1124 else
1125 pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1126
1127 /*
1128 * Clear the FF and we're done.
1129 */
1130 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1131 STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1132 return VINF_SUCCESS;
1133}
1134
1135
1136# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1137/**
1138 * \#PF Handler callback for virtual access handler ranges.
1139 *
1140 * Important to realize that a physical page in a range can have aliases, and
1141 * for ALL and WRITE handlers these will also trigger.
1142 *
1143 * @returns VINF_SUCCESS if the handler have carried out the operation.
1144 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1145 * @param pVM Pointer to the VM.
1146 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1147 * @param pvPtr The HC mapping of that address.
1148 * @param pvBuf What the guest is reading/writing.
1149 * @param cbBuf How much it's reading/writing.
1150 * @param enmAccessType The access type.
1151 * @param pvUser User argument.
1152 */
1153static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf,
1154 PGMACCESSTYPE enmAccessType, void *pvUser)
1155{
1156 Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1157 Log(("trpmR3GuestIDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1158 NOREF(pvPtr); NOREF(pvUser); NOREF(pvBuf);
1159 Assert(!HMIsEnabled(pVM));
1160
1161 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TRPM_SYNC_IDT);
1162 return VINF_PGM_HANDLER_DO_DEFAULT;
1163}
1164# endif /* TRPM_TRACK_GUEST_IDT_CHANGES */
1165
1166
1167/**
1168 * Clear passthrough interrupt gate handler (reset to default handler)
1169 *
1170 * @returns VBox status code.
1171 * @param pVM Pointer to the VM.
1172 * @param iTrap Trap/interrupt gate number.
1173 */
1174int trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1175{
1176 /* Only applies to raw mode which supports only 1 VCPU. */
1177 PVMCPU pVCpu = &pVM->aCpus[0];
1178 Assert(!HMIsEnabled(pVM));
1179
1180 /** @todo cleanup trpmR3ClearPassThroughHandler()! */
1181 RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1182 int rc;
1183
1184 memset(aGCPtrs, 0, sizeof(aGCPtrs));
1185
1186 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1187 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
1188
1189 if ( iTrap < TRPM_HANDLER_INT_BASE
1190 || iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1191 {
1192 AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1193 return VERR_INVALID_PARAMETER;
1194 }
1195 memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1196
1197 /* Unmark it for relocation purposes. */
1198 ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1199
1200 RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1201 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1202 PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1203 if (pIdte->Gen.u1Present)
1204 {
1205 Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1206 Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1207 RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1208
1209 /*
1210 * Generic handlers have different entrypoints for each possible
1211 * vector number. These entrypoints make a sort of an array with
1212 * 8 byte entries where the vector number is the index.
1213 * See TRPMGCHandlersA.asm for details.
1214 */
1215 Offset += iTrap * 8;
1216
1217 if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1218 {
1219 pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1220 pIdte->Gen.u16OffsetHigh = Offset >> 16;
1221 pIdte->Gen.u16SegSel = SelCS;
1222 }
1223 }
1224
1225 return VINF_SUCCESS;
1226}
1227
1228
1229/**
1230 * Check if address is a gate handler (interrupt or trap).
1231 *
1232 * @returns gate nr or ~0 is not found
1233 *
1234 * @param pVM Pointer to the VM.
1235 * @param GCPtr GC address to check.
1236 */
1237VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1238{
1239 AssertReturn(!HMIsEnabled(pVM), ~0U);
1240
1241 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1242 {
1243 if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1244 return iTrap;
1245
1246 /* redundant */
1247 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1248 {
1249 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1250 RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1251
1252 if (pHandler == GCPtr)
1253 return iTrap;
1254 }
1255 }
1256 return ~0;
1257}
1258
1259
1260/**
1261 * Get guest trap/interrupt gate handler
1262 *
1263 * @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1264 * @param pVM Pointer to the VM.
1265 * @param iTrap Interrupt/trap number.
1266 */
1267VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1268{
1269 AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1270 AssertReturn(!HMIsEnabled(pVM), TRPM_INVALID_HANDLER);
1271
1272 return pVM->trpm.s.aGuestTrapHandler[iTrap];
1273}
1274
1275
1276/**
1277 * Set guest trap/interrupt gate handler
1278 * Used for setting up trap gates used for kernel calls.
1279 *
1280 * @returns VBox status code.
1281 * @param pVM Pointer to the VM.
1282 * @param iTrap Interrupt/trap number.
1283 * @param pHandler GC handler pointer
1284 */
1285VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1286{
1287 /* Only valid in raw mode which implies 1 VCPU */
1288 Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1289 AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1290 PVMCPU pVCpu = &pVM->aCpus[0];
1291
1292 /*
1293 * Validate.
1294 */
1295 if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1296 {
1297 AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1298 return VERR_INVALID_PARAMETER;
1299 }
1300
1301 AssertReturn(pHandler == TRPM_INVALID_HANDLER || PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1302
1303 uint16_t cbIDT;
1304 RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1305 if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1306 return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1307
1308 if (pHandler == TRPM_INVALID_HANDLER)
1309 {
1310 /* clear trap handler */
1311 Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1312 return trpmClearGuestTrapHandler(pVM, iTrap);
1313 }
1314
1315 /*
1316 * Read the guest IDT entry.
1317 */
1318 VBOXIDTE GuestIdte;
1319 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1320 if (RT_FAILURE(rc))
1321 {
1322 AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1323 return rc;
1324 }
1325
1326 if ( EMIsRawRing0Enabled(pVM)
1327 && !EMIsRawRing1Enabled(pVM)) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */
1328 {
1329 /*
1330 * Only replace handlers for which we are 100% certain there won't be
1331 * any host interrupts.
1332 *
1333 * 0x2E is safe on Windows because it's the system service interrupt gate. Not
1334 * quite certain if this is safe or not on 64-bit Vista, it probably is.
1335 *
1336 * 0x80 is safe on Linux because it's the syscall vector and is part of the
1337 * 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1338 * and will therefor never assign hardware interrupts to 0x80.
1339 *
1340 * Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1341 * to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1342 * Booting Linux/BSD guest will cause system lockups on most of the computers.
1343 * -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1344 * @bugref{3604}.
1345 *
1346 * PORTME - Check if your host keeps any of these gates free from hw ints.
1347 *
1348 * Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1349 */
1350 /** @todo handle those dependencies better! */
1351 /** @todo Solve this in a proper manner. see @bugref{1186} */
1352#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1353 if (iTrap == 0x2E)
1354#elif defined(RT_OS_LINUX)
1355 if (iTrap == 0x80)
1356#else
1357 if (0)
1358#endif
1359 {
1360 if ( GuestIdte.Gen.u1Present
1361 && ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1362 || GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1363 && GuestIdte.Gen.u2DPL == 3)
1364 {
1365 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1366
1367 GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1368 GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1369 GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1370 GuestIdte.Gen.u16SegSel |= 1; //ring 1
1371 *pIdte = GuestIdte;
1372
1373 /* Mark it for relocation purposes. */
1374 ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1375
1376 /* Also store it in our guest trap array. */
1377 pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1378
1379 Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1380 return VINF_SUCCESS;
1381 }
1382 /* ok, let's try to install a trampoline handler then. */
1383 }
1384 }
1385
1386 if ( GuestIdte.Gen.u1Present
1387 && ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1388 || GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1389 && (GuestIdte.Gen.u2DPL == 3 || GuestIdte.Gen.u2DPL == 0))
1390 {
1391 /*
1392 * Save handler which can be used for a trampoline call inside the GC
1393 */
1394 Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1395 pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1396 return VINF_SUCCESS;
1397 }
1398 return VERR_INVALID_PARAMETER;
1399}
1400
1401
1402/**
1403 * Check if address is a gate handler (interrupt/trap/task/anything).
1404 *
1405 * @returns True is gate handler, false if not.
1406 *
1407 * @param pVM Pointer to the VM.
1408 * @param GCPtr GC address to check.
1409 */
1410VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1411{
1412 /* Only valid in raw mode which implies 1 VCPU */
1413 Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1414 PVMCPU pVCpu = &pVM->aCpus[0];
1415
1416 /*
1417 * Read IDTR and calc last entry.
1418 */
1419 uint16_t cbIDT;
1420 RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1421 unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1422 if (!cEntries)
1423 return false;
1424 RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1425
1426 /*
1427 * Outer loop: iterate pages.
1428 */
1429 while (GCPtrIDTE <= GCPtrIDTELast)
1430 {
1431 /*
1432 * Convert this page to a HC address.
1433 * (This function checks for not-present pages.)
1434 */
1435 PCVBOXIDTE pIDTE;
1436 PGMPAGEMAPLOCK Lock;
1437 int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1438 if (RT_SUCCESS(rc))
1439 {
1440 /*
1441 * Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1442 * N.B. Member of the Flat Earth Society...
1443 */
1444 while (GCPtrIDTE <= GCPtrIDTELast)
1445 {
1446 if (pIDTE->Gen.u1Present)
1447 {
1448 RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1449 if (GCPtr == GCPtrHandler)
1450 {
1451 PGMPhysReleasePageMappingLock(pVM, &Lock);
1452 return true;
1453 }
1454 }
1455
1456 /* next entry */
1457 if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1458 {
1459 AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1460 ("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1461 GCPtrIDTE += sizeof(VBOXIDTE);
1462 break;
1463 }
1464 GCPtrIDTE += sizeof(VBOXIDTE);
1465 pIDTE++;
1466 }
1467 PGMPhysReleasePageMappingLock(pVM, &Lock);
1468 }
1469 else
1470 {
1471 /* Skip to the next page (if any). Take care not to wrap around the address space. */
1472 if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1473 return false;
1474 GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1475 }
1476 }
1477 return false;
1478}
1479
1480#endif /* VBOX_WITH_RAW_MODE */
1481
1482/**
1483 * Inject event (such as external irq or trap)
1484 *
1485 * @returns VBox status code.
1486 * @param pVM Pointer to the VM.
1487 * @param pVCpu Pointer to the VMCPU.
1488 * @param enmEvent Trpm event type
1489 */
1490VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1491{
1492 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1493#ifdef VBOX_WITH_RAW_MODE
1494 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1495#endif
1496 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1497
1498 /* Currently only useful for external hardware interrupts. */
1499 Assert(enmEvent == TRPM_HARDWARE_INT);
1500
1501 if ( !EMIsSupervisorCodeRecompiled(pVM)
1502#ifdef VBOX_WITH_REM
1503 && REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ
1504#endif
1505 )
1506 {
1507#ifdef TRPM_FORWARD_TRAPS_IN_GC
1508
1509# ifdef LOG_ENABLED
1510 DBGFR3_INFO_LOG(pVM, "cpumguest", "TRPMInject");
1511 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "TRPMInject");
1512# endif
1513
1514 uint8_t u8Interrupt;
1515 int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1516 Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1517 if (RT_SUCCESS(rc))
1518 {
1519# ifndef IEM_VERIFICATION_MODE
1520 if (HMIsEnabled(pVM))
1521# endif
1522 {
1523 rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1524 AssertRC(rc);
1525 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1526 return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1527 }
1528 /* If the guest gate is not patched, then we will check (again) if we can patch it. */
1529 if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1530 {
1531 CSAMR3CheckGates(pVM, u8Interrupt, 1);
1532 Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1533 }
1534
1535 if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1536 {
1537 /* Must check pending forced actions as our IDT or GDT might be out of sync */
1538 rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1539 if (rc == VINF_SUCCESS)
1540 {
1541 /* There's a handler -> let's execute it in raw mode */
1542 rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1543 if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1544 {
1545 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));
1546
1547 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1548 return VINF_EM_RESCHEDULE_RAW;
1549 }
1550 }
1551 }
1552 else
1553 STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1554# ifdef VBOX_WITH_REM
1555 REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1556# endif
1557 }
1558 else
1559 {
1560 AssertRC(rc);
1561 return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1562 }
1563#else /* !TRPM_FORWARD_TRAPS_IN_GC */
1564 if (HMR3IsActive(pVCpu))
1565 {
1566 uint8_t u8Interrupt;
1567 int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1568 Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1569 if (RT_SUCCESS(rc))
1570 {
1571 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
1572 AssertRC(rc);
1573 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1574 return VINF_EM_RESCHEDULE_HM;
1575 }
1576 }
1577#endif /* !TRPM_FORWARD_TRAPS_IN_GC */
1578 }
1579 /** @todo check if it's safe to translate the patch address to the original guest address.
1580 * this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1581 */
1582 /* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1583
1584 /* Fall back to the recompiler */
1585 return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1586}
1587
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use