VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 74795

Last change on this file since 74795 was 73322, checked in by vboxsync, 6 years ago

HM,SELM: Redefined HMIsRawModeCtxNeeded as accessor for VM::fHMNeedRawModeCtx, i.e. dropping old fashioned raw-mode from it's definition. bugref:9044
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File size: 107.5 KB
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1/* $Id: SELM.cpp 73322 2018-07-23 14:04:59Z vboxsync $ */
2/** @file
3 * SELM - The Selector Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_selm SELM - The Selector Manager
19 *
20 * SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21 * of a few hyper selector for the raw-mode context. In the hardware assisted
22 * virtualization mode its only task is to decode entries in the guest GDT or
23 * LDT once in a while.
24 *
25 * @see grp_selm
26 *
27 *
28 * @section seg_selm_shadowing Shadowing
29 *
30 * SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31 * work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32 * The idea is to do it in a more on-demand fashion when we get time. There
33 * also a whole bunch of issues with the current synchronization of all three
34 * tables, see notes and todos in the code.
35 *
36 * When the guest makes changes to the GDT we will try update the shadow copy
37 * without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38 *
39 * When the guest make LDT changes we'll trigger a full resync of the LDT
40 * (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41 *
42 * The TSS shadowing is limited to the fields we need to care about, namely SS0
43 * and ESP0. The Patch Manager makes use of these. We monitor updates to the
44 * guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45 * rather than go the SELMR3SyncTSS() route.
46 *
47 * When in raw-mode SELM also injects a few extra GDT selectors which are used
48 * by the raw-mode (hyper) context. These start their life at the high end of
49 * the table and will be relocated when the guest tries to make use of them...
50 * Well, that was that idea at least, only the code isn't quite there yet which
51 * is why we have trouble with guests which actually have a full sized GDT.
52 *
53 * So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54 * lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55 *
56 */
57
58
59/*********************************************************************************************************************************
60* Header Files *
61*********************************************************************************************************************************/
62#define LOG_GROUP LOG_GROUP_SELM
63#include <VBox/vmm/selm.h>
64#include <VBox/vmm/cpum.h>
65#include <VBox/vmm/stam.h>
66#include <VBox/vmm/em.h>
67#include <VBox/vmm/hm.h>
68#include <VBox/vmm/mm.h>
69#include <VBox/vmm/ssm.h>
70#include <VBox/vmm/pgm.h>
71#include <VBox/vmm/trpm.h>
72#include <VBox/vmm/dbgf.h>
73#include "SELMInternal.h"
74#include <VBox/vmm/vm.h>
75#include <VBox/err.h>
76#include <VBox/param.h>
77
78#include <iprt/assert.h>
79#include <VBox/log.h>
80#include <iprt/asm.h>
81#include <iprt/string.h>
82#include <iprt/thread.h>
83#include <iprt/string.h>
84
85#include "SELMInline.h"
86
87
88/** SELM saved state version. */
89#define SELM_SAVED_STATE_VERSION 5
90
91
92/*********************************************************************************************************************************
93* Internal Functions *
94*********************************************************************************************************************************/
95static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
96static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
97static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
98static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
99static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
100static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104
105
106/*********************************************************************************************************************************
107* Global Variables *
108*********************************************************************************************************************************/
109#if defined(VBOX_WITH_RAW_MODE) && defined(LOG_ENABLED)
110/** Segment register names. */
111static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
112#endif
113
114
115/**
116 * Initializes the SELM.
117 *
118 * @returns VBox status code.
119 * @param pVM The cross context VM structure.
120 */
121VMMR3DECL(int) SELMR3Init(PVM pVM)
122{
123 int rc;
124 LogFlow(("SELMR3Init\n"));
125
126 /*
127 * Assert alignment and sizes.
128 * (The TSS block requires contiguous back.)
129 */
130 AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
131 AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_UOFFSETOF(VM, selm.s) & 31));
132#if 0 /* doesn't work */
133 AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
134 AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
135#endif
136 AssertRelease((RT_UOFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
137 AssertRelease((RT_UOFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
138 AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
139
140 /*
141 * Init the structure.
142 */
143 pVM->selm.s.offVM = RT_UOFFSETOF(VM, selm);
144 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
145 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
146 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
147 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
148 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
149
150 if (VM_IS_RAW_MODE_ENABLED(pVM) || HMIsRawModeCtxNeeded(pVM))
151 {
152 /*
153 * Allocate GDT table.
154 */
155 rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
156 PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
157 AssertRCReturn(rc, rc);
158
159 /*
160 * Allocate LDT area.
161 */
162 rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
163 AssertRCReturn(rc, rc);
164 }
165
166 /*
167 * Init Guest's and Shadow GDT, LDT, TSS changes control variables.
168 */
169 pVM->selm.s.cbEffGuestGdtLimit = 0;
170 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
171 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
172 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
173
174 pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
175 pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
176 pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
177 pVM->selm.s.GCSelTss = RTSEL_MAX;
178
179 pVM->selm.s.fSyncTSSRing0Stack = false;
180
181 /* The I/O bitmap starts right after the virtual interrupt redirection
182 bitmap. Outside the TSS on purpose; the CPU will not check it for
183 I/O operations. */
184 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
185 /* bit set to 1 means no redirection */
186 memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
187
188 /*
189 * Register the virtual access handlers.
190 */
191 pVM->selm.s.hShadowGdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
192 pVM->selm.s.hShadowLdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
193 pVM->selm.s.hShadowTssWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
194 pVM->selm.s.hGuestGdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
195 pVM->selm.s.hGuestLdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
196 pVM->selm.s.hGuestTssWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
197#ifdef VBOX_WITH_RAW_MODE
198 if (VM_IS_RAW_MODE_ENABLED(pVM))
199 {
200# ifdef SELM_TRACK_SHADOW_GDT_CHANGES
201 rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /*fRelocUserRC*/,
202 NULL /*pfnInvalidateR3*/, NULL /*pfnHandlerR3*/,
203 NULL /*pszHandlerRC*/, "selmRCShadowGDTWritePfHandler",
204 "Shadow GDT write access handler", &pVM->selm.s.hShadowGdtWriteHandlerType);
205 AssertRCReturn(rc, rc);
206# endif
207# ifdef SELM_TRACK_SHADOW_TSS_CHANGES
208 rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /*fRelocUserRC*/,
209 NULL /*pfnInvalidateR3*/, NULL /*pfnHandlerR3*/,
210 NULL /*pszHandlerRC*/, "selmRCShadowTSSWritePfHandler",
211 "Shadow TSS write access handler", &pVM->selm.s.hShadowTssWriteHandlerType);
212 AssertRCReturn(rc, rc);
213# endif
214# ifdef SELM_TRACK_SHADOW_LDT_CHANGES
215 rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /*fRelocUserRC*/,
216 NULL /*pfnInvalidateR3*/, NULL /*pfnHandlerR3*/,
217 NULL /*pszHandlerRC*/, "selmRCShadowLDTWritePfHandler",
218 "Shadow LDT write access handler", &pVM->selm.s.hShadowLdtWriteHandlerType);
219 AssertRCReturn(rc, rc);
220# endif
221 rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /*fRelocUserRC*/,
222 NULL /*pfnInvalidateR3*/, selmGuestGDTWriteHandler,
223 "selmGuestGDTWriteHandler", "selmRCGuestGDTWritePfHandler",
224 "Guest GDT write access handler", &pVM->selm.s.hGuestGdtWriteHandlerType);
225 AssertRCReturn(rc, rc);
226 rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /*fRelocUserRC*/,
227 NULL /*pfnInvalidateR3*/, selmGuestLDTWriteHandler,
228 "selmGuestLDTWriteHandler", "selmRCGuestLDTWritePfHandler",
229 "Guest LDT write access handler", &pVM->selm.s.hGuestLdtWriteHandlerType);
230 AssertRCReturn(rc, rc);
231 rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /*fRelocUserRC*/,
232 NULL /*pfnInvalidateR3*/, selmGuestTSSWriteHandler,
233 "selmGuestTSSWriteHandler", "selmRCGuestTSSWritePfHandler",
234 "Guest TSS write access handler", &pVM->selm.s.hGuestTssWriteHandlerType);
235 AssertRCReturn(rc, rc);
236 }
237#endif /* VBOX_WITH_RAW_MODE */
238
239 /*
240 * Register the saved state data unit.
241 */
242 rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
243 NULL, NULL, NULL,
244 NULL, selmR3Save, NULL,
245 NULL, selmR3Load, selmR3LoadDone);
246 if (RT_FAILURE(rc))
247 return rc;
248
249 /*
250 * Statistics.
251 */
252 if (VM_IS_RAW_MODE_ENABLED(pVM))
253 {
254 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
255 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
256 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
257 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
258 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
259 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
260 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
261 STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
262 STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
263
264 STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
265 STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
266
267 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleES", STAMUNIT_OCCURENCES, "Stale ES was detected in UpdateFromCPUM.");
268 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleCS", STAMUNIT_OCCURENCES, "Stale CS was detected in UpdateFromCPUM.");
269 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleSS", STAMUNIT_OCCURENCES, "Stale SS was detected in UpdateFromCPUM.");
270 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleDS", STAMUNIT_OCCURENCES, "Stale DS was detected in UpdateFromCPUM.");
271 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleFS", STAMUNIT_OCCURENCES, "Stale FS was detected in UpdateFromCPUM.");
272 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleGS", STAMUNIT_OCCURENCES, "Stale GS was detected in UpdateFromCPUM.");
273
274 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleES", STAMUNIT_OCCURENCES, "Already stale ES in UpdateFromCPUM.");
275 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleCS", STAMUNIT_OCCURENCES, "Already stale CS in UpdateFromCPUM.");
276 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleSS", STAMUNIT_OCCURENCES, "Already stale SS in UpdateFromCPUM.");
277 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleDS", STAMUNIT_OCCURENCES, "Already stale DS in UpdateFromCPUM.");
278 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleFS", STAMUNIT_OCCURENCES, "Already stale FS in UpdateFromCPUM.");
279 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleGS", STAMUNIT_OCCURENCES, "Already stale GS in UpdateFromCPUM.");
280
281 STAM_REL_REG(pVM, &pVM->selm.s.StatStaleToUnstaleSReg, STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/StaleToUnstale", STAMUNIT_OCCURENCES, "Transitions from stale to unstale UpdateFromCPUM.");
282
283 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedES", STAMUNIT_OCCURENCES, "Updated hidden ES values in UpdateFromCPUM.");
284 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedCS", STAMUNIT_OCCURENCES, "Updated hidden CS values in UpdateFromCPUM.");
285 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedSS", STAMUNIT_OCCURENCES, "Updated hidden SS values in UpdateFromCPUM.");
286 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedDS", STAMUNIT_OCCURENCES, "Updated hidden DS values in UpdateFromCPUM.");
287 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedFS", STAMUNIT_OCCURENCES, "Updated hidden FS values in UpdateFromCPUM.");
288 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedGS", STAMUNIT_OCCURENCES, "Updated hidden GS values in UpdateFromCPUM.");
289 }
290
291 STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelGst, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from guest tables.");
292 STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelShw, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedShadow", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from shadow tables.");
293 STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelReadErrors, STAMTYPE_COUNTER, "/SELM/LoadHidSel/GstReadErrors", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Guest table read errors.");
294 STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelGstNoGood, STAMTYPE_COUNTER, "/SELM/LoadHidSel/NoGoodGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: No good guest table entry.");
295
296#ifdef VBOX_WITH_RAW_MODE
297 /*
298 * Default action when entering raw mode for the first time
299 */
300 if (VM_IS_RAW_MODE_ENABLED(pVM))
301 {
302 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
303 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
304 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
305 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
306 }
307#endif
308
309 /*
310 * Register info handlers.
311 */
312 if (VM_IS_RAW_MODE_ENABLED(pVM) || HMIsRawModeCtxNeeded(pVM))
313 {
314 DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
315 DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
316 //DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
317 }
318 DBGFR3InfoRegisterInternalEx(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest, DBGFINFO_FLAGS_RUN_ON_EMT);
319 DBGFR3InfoRegisterInternalEx(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest, DBGFINFO_FLAGS_RUN_ON_EMT);
320 //DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest, DBGFINFO_FLAGS_RUN_ON_EMT);
321
322 return rc;
323}
324
325
326/**
327 * Finalizes HMA page attributes.
328 *
329 * @returns VBox status code.
330 * @param pVM The cross context VM structure.
331 */
332VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
333{
334#ifdef VBOX_WITH_RAW_MODE
335 /** @cfgm{/DoubleFault,bool,false}
336 * Enables catching of double faults in the raw-mode context VMM code. This can
337 * be used when the triple faults or hangs occur and one suspect an unhandled
338 * double fault. This is not enabled by default because it means making the
339 * hyper selectors writeable for all supervisor code, including the guest's.
340 * The double fault is a task switch and thus requires write access to the GDT
341 * of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
342 * 8 TSS for the back link.
343 */
344 bool f;
345# if defined(DEBUG_bird)
346 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
347# else
348 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
349# endif
350 AssertLogRelRCReturn(rc, rc);
351 if (f && (VM_IS_RAW_MODE_ENABLED(pVM) || HMIsRawModeCtxNeeded(pVM)))
352 {
353 PX86DESC paGdt = pVM->selm.s.paGdtR3;
354 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
355 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
356 AssertRC(rc);
357 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
358 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
359 AssertRC(rc);
360 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
361 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
362 AssertRC(rc);
363 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
364 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
365 AssertRC(rc);
366 }
367#else /* !VBOX_WITH_RAW_MODE */
368 RT_NOREF(pVM);
369#endif /* !VBOX_WITH_RAW_MODE */
370 return VINF_SUCCESS;
371}
372
373
374/**
375 * Setup the hypervisor GDT selectors in our shadow table
376 *
377 * @param pVM The cross context VM structure.
378 */
379static void selmR3SetupHyperGDTSelectors(PVM pVM)
380{
381 PX86DESC paGdt = pVM->selm.s.paGdtR3;
382
383 /*
384 * Set up global code and data descriptors for use in the guest context.
385 * Both are wide open (base 0, limit 4GB)
386 */
387 PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
388 pDesc->Gen.u16LimitLow = 0xffff;
389 pDesc->Gen.u4LimitHigh = 0xf;
390 pDesc->Gen.u16BaseLow = 0;
391 pDesc->Gen.u8BaseHigh1 = 0;
392 pDesc->Gen.u8BaseHigh2 = 0;
393 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
394 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
395 pDesc->Gen.u2Dpl = 0; /* supervisor */
396 pDesc->Gen.u1Present = 1;
397 pDesc->Gen.u1Available = 0;
398 pDesc->Gen.u1Long = 0;
399 pDesc->Gen.u1DefBig = 1; /* def 32 bit */
400 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
401
402 /* data */
403 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
404 pDesc->Gen.u16LimitLow = 0xffff;
405 pDesc->Gen.u4LimitHigh = 0xf;
406 pDesc->Gen.u16BaseLow = 0;
407 pDesc->Gen.u8BaseHigh1 = 0;
408 pDesc->Gen.u8BaseHigh2 = 0;
409 pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
410 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
411 pDesc->Gen.u2Dpl = 0; /* supervisor */
412 pDesc->Gen.u1Present = 1;
413 pDesc->Gen.u1Available = 0;
414 pDesc->Gen.u1Long = 0;
415 pDesc->Gen.u1DefBig = 1; /* big */
416 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
417
418 /* 64-bit mode code (& data?) */
419 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
420 pDesc->Gen.u16LimitLow = 0xffff;
421 pDesc->Gen.u4LimitHigh = 0xf;
422 pDesc->Gen.u16BaseLow = 0;
423 pDesc->Gen.u8BaseHigh1 = 0;
424 pDesc->Gen.u8BaseHigh2 = 0;
425 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
426 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
427 pDesc->Gen.u2Dpl = 0; /* supervisor */
428 pDesc->Gen.u1Present = 1;
429 pDesc->Gen.u1Available = 0;
430 pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
431 pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
432 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
433
434 /*
435 * TSS descriptor
436 */
437 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
438 RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
439 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
440 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
441 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
442 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
443 pDesc->Gen.u4LimitHigh = 0;
444 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
445 pDesc->Gen.u1DescType = 0; /* system */
446 pDesc->Gen.u2Dpl = 0; /* supervisor */
447 pDesc->Gen.u1Present = 1;
448 pDesc->Gen.u1Available = 0;
449 pDesc->Gen.u1Long = 0;
450 pDesc->Gen.u1DefBig = 0;
451 pDesc->Gen.u1Granularity = 0; /* byte limit */
452
453 /*
454 * TSS descriptor for trap 08
455 */
456 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
457 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
458 pDesc->Gen.u4LimitHigh = 0;
459 RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
460 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
461 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
462 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
463 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
464 pDesc->Gen.u1DescType = 0; /* system */
465 pDesc->Gen.u2Dpl = 0; /* supervisor */
466 pDesc->Gen.u1Present = 1;
467 pDesc->Gen.u1Available = 0;
468 pDesc->Gen.u1Long = 0;
469 pDesc->Gen.u1DefBig = 0;
470 pDesc->Gen.u1Granularity = 0; /* byte limit */
471}
472
473/**
474 * Applies relocations to data and code managed by this
475 * component. This function will be called at init and
476 * whenever the VMM need to relocate it self inside the GC.
477 *
478 * @param pVM The cross context VM structure.
479 */
480VMMR3DECL(void) SELMR3Relocate(PVM pVM)
481{
482 PX86DESC paGdt = pVM->selm.s.paGdtR3;
483 LogFlow(("SELMR3Relocate\n"));
484
485 if (VM_IS_RAW_MODE_ENABLED(pVM) || HMIsRawModeCtxNeeded(pVM))
486 {
487 for (VMCPUID i = 0; i < pVM->cCpus; i++)
488 {
489 PVMCPU pVCpu = &pVM->aCpus[i];
490
491 /*
492 * Update GDTR and selector.
493 */
494 CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
495
496 /** @todo selector relocations should be a separate operation? */
497 CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
498 CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
499 CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
500 CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
501 CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
502 }
503
504 selmR3SetupHyperGDTSelectors(pVM);
505
506/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
507/** @todo PGM knows the proper CR3 values these days, not CPUM. */
508 /*
509 * Update the TSSes.
510 */
511 /* Only applies to raw mode which supports only 1 VCPU */
512 PVMCPU pVCpu = &pVM->aCpus[0];
513
514 /* Current TSS */
515 pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
516 pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
517 pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
518 pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
519 pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
520 pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
521 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
522
523 /* trap 08 */
524 pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
525 pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
526 pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
527 pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
528 pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
529 pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
530 pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
531 pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
532 pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
533 pVM->selm.s.TssTrap08.fs = 0;
534 pVM->selm.s.TssTrap08.gs = 0;
535 pVM->selm.s.TssTrap08.selLdt = 0;
536 pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
537 pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
538 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
539 pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
540 pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
541 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
542 pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
543 pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
544 /* TRPM will be updating the eip */
545 }
546
547 if (VM_IS_RAW_MODE_ENABLED(pVM))
548 {
549 /*
550 * Update shadow GDT/LDT/TSS write access handlers.
551 */
552 PVMCPU pVCpu = VMMGetCpu(pVM); NOREF(pVCpu);
553 int rc; NOREF(rc);
554#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
555 if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
556 {
557 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.paGdtRC, true /*fHypervisor*/);
558 AssertRC(rc);
559 }
560 pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
561 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hShadowGdtWriteHandlerType,
562 pVM->selm.s.paGdtRC,
563 pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
564 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
565 AssertRC(rc);
566#endif
567#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
568 if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
569 {
570 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.pvMonShwTssRC, true /*fHypervisor*/);
571 AssertRC(rc);
572 }
573 pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
574 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hShadowTssWriteHandlerType,
575 pVM->selm.s.pvMonShwTssRC,
576 pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
577 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
578 AssertRC(rc);
579#endif
580
581 /*
582 * Update the GC LDT region handler and address.
583 */
584#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
585 if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
586 {
587 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.pvLdtRC, true /*fHypervisor*/);
588 AssertRC(rc);
589 }
590#endif
591 pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
592#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
593 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hShadowLdtWriteHandlerType,
594 pVM->selm.s.pvLdtRC,
595 pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
596 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
597 AssertRC(rc);
598#endif
599 }
600}
601
602
603/**
604 * Terminates the SELM.
605 *
606 * Termination means cleaning up and freeing all resources,
607 * the VM it self is at this point powered off or suspended.
608 *
609 * @returns VBox status code.
610 * @param pVM The cross context VM structure.
611 */
612VMMR3DECL(int) SELMR3Term(PVM pVM)
613{
614 NOREF(pVM);
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * The VM is being reset.
621 *
622 * For the SELM component this means that any GDT/LDT/TSS monitors
623 * needs to be removed.
624 *
625 * @param pVM The cross context VM structure.
626 */
627VMMR3DECL(void) SELMR3Reset(PVM pVM)
628{
629 LogFlow(("SELMR3Reset:\n"));
630 VM_ASSERT_EMT(pVM);
631
632 /*
633 * Uninstall guest GDT/LDT/TSS write access handlers.
634 */
635 PVMCPU pVCpu = VMMGetCpu(pVM); NOREF(pVCpu);
636 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
637 {
638#ifdef SELM_TRACK_GUEST_GDT_CHANGES
639 int rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GuestGdtr.pGdt, false /*fHypervisor*/);
640 AssertRC(rc);
641#endif
642 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
643 pVM->selm.s.GuestGdtr.cbGdt = 0;
644 }
645 pVM->selm.s.fGDTRangeRegistered = false;
646 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
647 {
648#ifdef SELM_TRACK_GUEST_LDT_CHANGES
649 int rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /*fHypervisor*/);
650 AssertRC(rc);
651#endif
652 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
653 }
654 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
655 {
656#ifdef SELM_TRACK_GUEST_TSS_CHANGES
657 int rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestTss, false /*fHypervisor*/);
658 AssertRC(rc);
659#endif
660 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
661 pVM->selm.s.GCSelTss = RTSEL_MAX;
662 }
663
664 /*
665 * Re-initialize other members.
666 */
667 pVM->selm.s.cbLdtLimit = 0;
668 pVM->selm.s.offLdtHyper = 0;
669 pVM->selm.s.cbMonitoredGuestTss = 0;
670
671 pVM->selm.s.fSyncTSSRing0Stack = false;
672
673#ifdef VBOX_WITH_RAW_MODE
674 if (VM_IS_RAW_MODE_ENABLED(pVM))
675 {
676 /*
677 * Default action when entering raw mode for the first time
678 */
679 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
680 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
681 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
682 }
683#endif
684}
685
686
687/**
688 * Execute state save operation.
689 *
690 * @returns VBox status code.
691 * @param pVM The cross context VM structure.
692 * @param pSSM SSM operation handle.
693 */
694static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
695{
696 LogFlow(("selmR3Save:\n"));
697
698 /*
699 * Save the basic bits - fortunately all the other things can be resynced on load.
700 */
701 PSELM pSelm = &pVM->selm.s;
702
703 SSMR3PutBool(pSSM, !VM_IS_RAW_MODE_ENABLED(pVM));
704 SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
705 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
706 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
707 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
708 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
709 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
710 return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
711}
712
713
714/**
715 * Execute state load operation.
716 *
717 * @returns VBox status code.
718 * @param pVM The cross context VM structure.
719 * @param pSSM SSM operation handle.
720 * @param uVersion Data layout version.
721 * @param uPass The data pass.
722 */
723static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
724{
725 LogFlow(("selmR3Load:\n"));
726 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
727
728 /*
729 * Validate version.
730 */
731 if (uVersion != SELM_SAVED_STATE_VERSION)
732 {
733 AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
734 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
735 }
736
737 /*
738 * Do a reset.
739 */
740 SELMR3Reset(pVM);
741
742 /* Get the monitoring flag. */
743 bool fIgnored;
744 SSMR3GetBool(pSSM, &fIgnored);
745
746 /* Get the TSS state flag. */
747 SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
748
749 /*
750 * Get the selectors.
751 */
752 RTSEL SelCS;
753 SSMR3GetSel(pSSM, &SelCS);
754 RTSEL SelDS;
755 SSMR3GetSel(pSSM, &SelDS);
756 RTSEL SelCS64;
757 SSMR3GetSel(pSSM, &SelCS64);
758 RTSEL SelDS64;
759 SSMR3GetSel(pSSM, &SelDS64);
760 RTSEL SelTSS;
761 SSMR3GetSel(pSSM, &SelTSS);
762 RTSEL SelTSSTrap08;
763 SSMR3GetSel(pSSM, &SelTSSTrap08);
764
765 /* Copy the selectors; they will be checked during relocation. */
766 PSELM pSelm = &pVM->selm.s;
767 pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
768 pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
769 pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
770 pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
771 pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
772
773 return VINF_SUCCESS;
774}
775
776
777/**
778 * Sync the GDT, LDT and TSS after loading the state.
779 *
780 * Just to play save, we set the FFs to force syncing before
781 * executing GC code.
782 *
783 * @returns VBox status code.
784 * @param pVM The cross context VM structure.
785 * @param pSSM SSM operation handle.
786 */
787static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
788{
789#ifdef VBOX_WITH_RAW_MODE
790 if (VM_IS_RAW_MODE_ENABLED(pVM))
791 {
792 PVMCPU pVCpu = VMMGetCpu(pVM);
793
794 LogFlow(("selmR3LoadDone:\n"));
795
796 /*
797 * Don't do anything if it's a load failure.
798 */
799 int rc = SSMR3HandleGetStatus(pSSM);
800 if (RT_FAILURE(rc))
801 return VINF_SUCCESS;
802
803 /*
804 * Do the syncing if we're in protected mode and using raw-mode.
805 */
806 if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
807 {
808 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
809 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
810 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
811 SELMR3UpdateFromCPUM(pVM, pVCpu);
812 }
813
814 /*
815 * Flag everything for resync on next raw mode entry.
816 */
817 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
818 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
819 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
820 }
821
822#else /* !VBOX_WITH_RAW_MODE */
823 RT_NOREF(pVM, pSSM);
824#endif /* !VBOX_WITH_RAW_MODE */
825 return VINF_SUCCESS;
826}
827
828#ifdef VBOX_WITH_RAW_MODE
829
830/**
831 * Updates (syncs) the shadow GDT.
832 *
833 * @returns VBox status code.
834 * @param pVM The cross context VM structure.
835 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
836 */
837static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
838{
839 LogFlow(("selmR3UpdateShadowGdt\n"));
840 Assert(VM_IS_RAW_MODE_ENABLED(pVM));
841
842 /*
843 * Always assume the best...
844 */
845 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
846
847 /* If the GDT was changed, then make sure the LDT is checked too */
848 /** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
849 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
850 /* Same goes for the TSS selector */
851 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
852
853 /*
854 * Get the GDTR and check if there is anything to do (there usually is).
855 */
856 VBOXGDTR GDTR;
857 CPUMGetGuestGDTR(pVCpu, &GDTR);
858 if (GDTR.cbGdt < sizeof(X86DESC))
859 {
860 Log(("No GDT entries...\n"));
861 return VINF_SUCCESS;
862 }
863
864 /*
865 * Read the Guest GDT.
866 * ASSUMES that the entire GDT is in memory.
867 */
868 RTUINT cbEffLimit = GDTR.cbGdt;
869 PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
870 int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
871 if (RT_FAILURE(rc))
872 {
873 /*
874 * Read it page by page.
875 *
876 * Keep track of the last valid page and delay memsets and
877 * adjust cbEffLimit to reflect the effective size. The latter
878 * is something we do in the belief that the guest will probably
879 * never actually commit the last page, thus allowing us to keep
880 * our selectors in the high end of the GDT.
881 */
882 RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
883 RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
884 uint8_t *pu8Dst = (uint8_t *)&pVM->selm.s.paGdtR3[1];
885 uint8_t *pu8DstInvalid = pu8Dst;
886
887 while (cbLeft)
888 {
889 RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
890 cb = RT_MIN(cb, cbLeft);
891 rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
892 if (RT_SUCCESS(rc))
893 {
894 if (pu8DstInvalid != pu8Dst)
895 RT_BZERO(pu8DstInvalid, pu8Dst - pu8DstInvalid);
896 GCPtrSrc += cb;
897 pu8Dst += cb;
898 pu8DstInvalid = pu8Dst;
899 }
900 else if ( rc == VERR_PAGE_NOT_PRESENT
901 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
902 {
903 GCPtrSrc += cb;
904 pu8Dst += cb;
905 }
906 else
907 {
908 AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
909 return VERR_SELM_GDT_READ_ERROR;
910 }
911 cbLeft -= cb;
912 }
913
914 /* any invalid pages at the end? */
915 if (pu8DstInvalid != pu8Dst)
916 {
917 cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
918 /* If any GDTEs was invalidated, zero them. */
919 if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
920 RT_BZERO(pu8DstInvalid + cbEffLimit + 1, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
921 }
922
923 /* keep track of the effective limit. */
924 if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
925 {
926 Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
927 pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
928 pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
929 }
930 }
931
932 /*
933 * Check if the Guest GDT intrudes on our GDT entries.
934 */
935 /** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
936 RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
937 if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
938 {
939 PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
940 PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
941 int iGDT = 0;
942
943 Log(("Internal SELM GDT conflict: use non-present entries\n"));
944 STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
945 while ((uintptr_t)pGDTECur > (uintptr_t)pGDTEStart)
946 {
947 /* We can reuse non-present entries */
948 if (!pGDTECur->Gen.u1Present)
949 {
950 aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
951 aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
952 Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
953 iGDT++;
954 if (iGDT >= SELM_HYPER_SEL_MAX)
955 break;
956 }
957
958 pGDTECur--;
959 }
960 if (iGDT != SELM_HYPER_SEL_MAX)
961 {
962 AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
963 return VERR_SELM_GDT_TOO_FULL;
964 }
965 }
966 else
967 {
968 aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
969 aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
970 aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
971 aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
972 aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
973 }
974
975# ifdef VBOX_WITH_SAFE_STR
976 /* Use the guest's TR selector to plug the str virtualization hole. */
977 if (CPUMGetGuestTR(pVCpu, NULL) != 0)
978 {
979 Log(("SELM: Use guest TSS selector %x\n", CPUMGetGuestTR(pVCpu, NULL)));
980 aHyperSel[SELM_HYPER_SEL_TSS] = CPUMGetGuestTR(pVCpu, NULL);
981 }
982# endif
983
984 /*
985 * Work thru the copied GDT entries adjusting them for correct virtualization.
986 */
987 PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
988 while (pGDTE < pGDTEEnd)
989 {
990 if (pGDTE->Gen.u1Present)
991 selmGuestToShadowDesc(pVM, pGDTE);
992
993 /* Next GDT entry. */
994 pGDTE++;
995 }
996
997 /*
998 * Check if our hypervisor selectors were changed.
999 */
1000 if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
1001 || aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
1002 || aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
1003 || aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
1004 || aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
1005 {
1006 /* Reinitialize our hypervisor GDTs */
1007 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
1008 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
1009 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
1010 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
1011 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1012
1013 STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
1014
1015 /*
1016 * Do the relocation callbacks to let everyone update their hyper selector dependencies.
1017 * (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
1018 */
1019 VMR3Relocate(pVM, 0);
1020 }
1021# ifdef VBOX_WITH_SAFE_STR
1022 else if ( cbEffLimit >= SELM_HYPER_DEFAULT_BASE
1023 || CPUMGetGuestTR(pVCpu, NULL) != 0) /* Our shadow TR entry was overwritten when we synced the guest's GDT. */
1024# else
1025 else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
1026# endif
1027 /* We overwrote all entries above, so we have to save them again. */
1028 selmR3SetupHyperGDTSelectors(pVM);
1029
1030 /*
1031 * Adjust the cached GDT limit.
1032 * Any GDT entries which have been removed must be cleared.
1033 */
1034 if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1035 {
1036 if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1037 RT_BZERO(pGDTE, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1038 }
1039
1040 /*
1041 * Check if Guest's GDTR is changed.
1042 */
1043 if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1044 || GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1045 {
1046 Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1047
1048# ifdef SELM_TRACK_GUEST_GDT_CHANGES
1049 /*
1050 * [Re]Register write virtual handler for guest's GDT.
1051 */
1052 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1053 {
1054 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GuestGdtr.pGdt, false /*fHypervisor*/);
1055 AssertRC(rc);
1056 }
1057 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestGdtWriteHandlerType,
1058 GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1059 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
1060# ifdef VBOX_WITH_RAW_RING1
1061 /** @todo !HACK ALERT!
1062 * Some guest OSes (QNX) share code and the GDT on the same page;
1063 * PGMR3HandlerVirtualRegister doesn't support more than one handler,
1064 * so we kick out the PATM handler as this one is more important. Fix this
1065 * properly in PGMR3HandlerVirtualRegister?
1066 */
1067 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1068 {
1069 LogRel(("selmR3UpdateShadowGdt: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority GDT page monitor\n", GDTR.pGdt));
1070 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, GDTR.pGdt & PAGE_BASE_GC_MASK, false /*fHypervisor*/);
1071 AssertRC(rc);
1072 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestGdtWriteHandlerType,
1073 GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1074 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
1075 }
1076# endif
1077 if (RT_FAILURE(rc))
1078 return rc;
1079# endif /* SELM_TRACK_GUEST_GDT_CHANGES */
1080
1081 /* Update saved Guest GDTR. */
1082 pVM->selm.s.GuestGdtr = GDTR;
1083 pVM->selm.s.fGDTRangeRegistered = true;
1084 }
1085
1086 return VINF_SUCCESS;
1087}
1088
1089
1090/**
1091 * Updates (syncs) the shadow LDT.
1092 *
1093 * @returns VBox status code.
1094 * @param pVM The cross context VM structure.
1095 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1096 */
1097static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1098{
1099 LogFlow(("selmR3UpdateShadowLdt\n"));
1100 int rc = VINF_SUCCESS;
1101 Assert(VM_IS_RAW_MODE_ENABLED(pVM));
1102
1103 /*
1104 * Always assume the best...
1105 */
1106 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1107
1108 /*
1109 * LDT handling is done similarly to the GDT handling with a shadow
1110 * array. However, since the LDT is expected to be swappable (at least
1111 * some ancient OSes makes it swappable) it must be floating and
1112 * synced on a per-page basis.
1113 *
1114 * Eventually we will change this to be fully on demand. Meaning that
1115 * we will only sync pages containing LDT selectors actually used and
1116 * let the #PF handler lazily sync pages as they are used.
1117 * (This applies to GDT too, when we start making OS/2 fast.)
1118 */
1119
1120 /*
1121 * First, determine the current LDT selector.
1122 */
1123 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1124 if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
1125 {
1126 /* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1127 CPUMSetHyperLDTR(pVCpu, 0);
1128 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1129 {
1130 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /*fHypervisor*/);
1131 AssertRC(rc);
1132 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1133 }
1134 pVM->selm.s.cbLdtLimit = 0;
1135 return VINF_SUCCESS;
1136 }
1137
1138 /*
1139 * Get the LDT selector.
1140 */
1141/** @todo this is wrong, use CPUMGetGuestLdtrEx */
1142 PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1143 RTGCPTR GCPtrLdt = X86DESC_BASE(pDesc);
1144 uint32_t cbLdt = X86DESC_LIMIT_G(pDesc);
1145
1146 /*
1147 * Validate it.
1148 */
1149 if ( !cbLdt
1150 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1151 || pDesc->Gen.u1DescType
1152 || pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1153 {
1154 AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1155
1156 /* cbLdt > 0:
1157 * This is quite impossible, so we do as most people do when faced with
1158 * the impossible, we simply ignore it.
1159 */
1160 CPUMSetHyperLDTR(pVCpu, 0);
1161 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1162 {
1163 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /*fHypervisor*/);
1164 AssertRC(rc);
1165 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1166 }
1167 return VINF_SUCCESS;
1168 }
1169 /** @todo check what intel does about odd limits. */
1170 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1171
1172 /*
1173 * Use the cached guest ldt address if the descriptor has already been modified (see below)
1174 * (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1175 */
1176 if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1177 GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1178
1179
1180 /** @todo Handle only present LDT segments. */
1181// if (pDesc->Gen.u1Present)
1182 {
1183 /*
1184 * Check if Guest's LDT address/limit is changed.
1185 */
1186 if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1187 || cbLdt != pVM->selm.s.cbLdtLimit)
1188 {
1189 Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1190 pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1191
1192# ifdef SELM_TRACK_GUEST_LDT_CHANGES
1193 /*
1194 * [Re]Register write virtual handler for guest's GDT.
1195 * In the event of LDT overlapping something, don't install it just assume it's being updated.
1196 */
1197 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1198 {
1199 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /*fHypervisor*/);
1200 AssertRC(rc);
1201 }
1202# ifdef LOG_ENABLED
1203 if (pDesc->Gen.u1Present)
1204 Log(("LDT selector marked not present!!\n"));
1205# endif
1206 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestLdtWriteHandlerType,
1207 GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1208 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
1209 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1210 {
1211 /** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1212 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1213 Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1214 GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1215 }
1216 else if (RT_SUCCESS(rc))
1217 pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1218 else
1219 {
1220 CPUMSetHyperLDTR(pVCpu, 0);
1221 return rc;
1222 }
1223# else
1224 pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1225# endif
1226 pVM->selm.s.cbLdtLimit = cbLdt;
1227 }
1228 }
1229
1230 /*
1231 * Calc Shadow LDT base.
1232 */
1233 unsigned off;
1234 pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1235 RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1236 PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1237
1238 /*
1239 * Enable the LDT selector in the shadow GDT.
1240 */
1241 pDesc->Gen.u1Present = 1;
1242 pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1243 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1244 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1245 pDesc->Gen.u1Available = 0;
1246 pDesc->Gen.u1Long = 0;
1247 if (cbLdt > 0xffff)
1248 {
1249 cbLdt = 0xffff;
1250 pDesc->Gen.u4LimitHigh = 0;
1251 pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1252 }
1253
1254 /*
1255 * Set Hyper LDTR and notify TRPM.
1256 */
1257 CPUMSetHyperLDTR(pVCpu, SelLdt);
1258 LogFlow(("selmR3UpdateShadowLdt: Hyper LDTR %#x\n", SelLdt));
1259
1260 /*
1261 * Loop synchronising the LDT page by page.
1262 */
1263 /** @todo investigate how intel handle various operations on half present cross page entries. */
1264 off = GCPtrLdt & (sizeof(X86DESC) - 1);
1265 AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1266
1267 /* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1268 unsigned cbLeft = cbLdt + 1;
1269 PX86DESC pLDTE = pShadowLDT;
1270 while (cbLeft)
1271 {
1272 /*
1273 * Read a chunk.
1274 */
1275 unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1276 if (cbChunk > cbLeft)
1277 cbChunk = cbLeft;
1278 rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1279 if (RT_SUCCESS(rc))
1280 {
1281 /*
1282 * Mark page
1283 */
1284 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D);
1285 AssertRC(rc);
1286
1287 /*
1288 * Loop thru the available LDT entries.
1289 * Figure out where to start and end and the potential cross pageness of
1290 * things adds a little complexity. pLDTE is updated there and not in the
1291 * 'next' part of the loop. The pLDTEEnd is inclusive.
1292 */
1293 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1294 if (pLDTE + 1 < pShadowLDT)
1295 pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1296 while (pLDTE <= pLDTEEnd)
1297 {
1298 if (pLDTE->Gen.u1Present)
1299 selmGuestToShadowDesc(pVM, pLDTE);
1300
1301 /* Next LDT entry. */
1302 pLDTE++;
1303 }
1304 }
1305 else
1306 {
1307 RT_BZERO(pShadowLDT, cbChunk);
1308 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1309 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1310 AssertRC(rc);
1311 }
1312
1313 /*
1314 * Advance to the next page.
1315 */
1316 cbLeft -= cbChunk;
1317 GCPtrShadowLDT += cbChunk;
1318 pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1319 GCPtrLdt += cbChunk;
1320 }
1321
1322 return VINF_SUCCESS;
1323}
1324
1325
1326/**
1327 * Checks and updates segment selector registers.
1328 *
1329 * @returns VBox strict status code.
1330 * @retval VINF_EM_RESCHEDULE_REM if a stale register was found.
1331 *
1332 * @param pVM The cross context VM structure.
1333 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1334 */
1335static VBOXSTRICTRC selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu)
1336{
1337 Assert(CPUMIsGuestInProtectedMode(pVCpu));
1338 Assert(VM_IS_RAW_MODE_ENABLED(pVM));
1339
1340 /*
1341 * No stale selectors in V8086 mode.
1342 */
1343 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1344 if (pCtx->eflags.Bits.u1VM)
1345 return VINF_SUCCESS;
1346
1347 /*
1348 * Check for stale selectors and load hidden register bits where they
1349 * are missing.
1350 */
1351 uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
1352 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1353 PCPUMSELREG paSReg = CPUMCTX_FIRST_SREG(pCtx);
1354 for (uint32_t iSReg = 0; iSReg < X86_SREG_COUNT; iSReg++)
1355 {
1356 RTSEL const Sel = paSReg[iSReg].Sel;
1357 if (Sel & X86_SEL_MASK_OFF_RPL)
1358 {
1359 /* Get the shadow descriptor entry corresponding to this. */
1360 static X86DESC const s_NotPresentDesc = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } };
1361 PCX86DESC pDesc;
1362 if (!(Sel & X86_SEL_LDT))
1363 {
1364 if ((Sel | (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt)
1365 pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
1366 else
1367 pDesc = &s_NotPresentDesc;
1368 }
1369 else
1370 {
1371 if ((Sel | (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit)
1372 pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT];
1373 else
1374 pDesc = &s_NotPresentDesc;
1375 }
1376
1377 /* Check the segment register. */
1378 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &paSReg[iSReg]))
1379 {
1380 if (!(paSReg[iSReg].fFlags & CPUMSELREG_FLAGS_STALE))
1381 {
1382 /* Did it go stale? */
1383 if (selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1384 {
1385 Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel));
1386 STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1387 paSReg[iSReg].fFlags |= CPUMSELREG_FLAGS_STALE;
1388 rcStrict = VINF_EM_RESCHEDULE_REM;
1389 }
1390 }
1391 else
1392 {
1393 /* Did it stop being stale? I.e. did the guest change it things
1394 back to the way they were? */
1395 if (!selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1396 {
1397 STAM_REL_COUNTER_INC(&pVM->selm.s.StatStaleToUnstaleSReg);
1398 paSReg[iSReg].fFlags &= CPUMSELREG_FLAGS_STALE;
1399 }
1400 else
1401 {
1402 Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel));
1403 STAM_REL_COUNTER_INC(&pVM->selm.s.aStatAlreadyStaleSReg[iSReg]);
1404 rcStrict = VINF_EM_RESCHEDULE_REM;
1405 }
1406 }
1407 }
1408 /* Load the hidden registers if it's a valid descriptor for the
1409 current segment register. */
1410 else if (selmIsShwDescGoodForSReg(&paSReg[iSReg], pDesc, iSReg, uCpl))
1411 {
1412 selmLoadHiddenSRegFromShadowDesc(&paSReg[iSReg], pDesc);
1413 STAM_COUNTER_INC(&pVM->selm.s.aStatUpdatedSReg[iSReg]);
1414 }
1415 /* It's stale. */
1416 else
1417 {
1418 Log2(("SELM: Detected stale %s=%#x (wasn't valid)\n", g_aszSRegNms[iSReg], Sel));
1419 STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1420 paSReg[iSReg].fFlags = CPUMSELREG_FLAGS_STALE;
1421 rcStrict = VINF_EM_RESCHEDULE_REM;
1422 }
1423 }
1424 /* else: 0 selector, ignore. */
1425 }
1426
1427 return rcStrict;
1428}
1429
1430
1431/**
1432 * Updates the Guest GDT & LDT virtualization based on current CPU state.
1433 *
1434 * @returns VBox status code.
1435 * @param pVM The cross context VM structure.
1436 * @param pVCpu The cross context virtual CPU structure.
1437 */
1438VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1439{
1440 STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1441 AssertReturn(VM_IS_RAW_MODE_ENABLED(pVM), VERR_SELM_HM_IPE);
1442
1443 /*
1444 * GDT sync
1445 */
1446 int rc;
1447 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1448 {
1449 rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1450 if (RT_FAILURE(rc))
1451 return rc; /* We're toast, so forget the profiling. */
1452 AssertRCSuccess(rc);
1453 }
1454
1455 /*
1456 * TSS sync
1457 */
1458 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1459 {
1460 rc = SELMR3SyncTSS(pVM, pVCpu);
1461 if (RT_FAILURE(rc))
1462 return rc;
1463 AssertRCSuccess(rc);
1464 }
1465
1466 /*
1467 * LDT sync
1468 */
1469 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1470 {
1471 rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1472 if (RT_FAILURE(rc))
1473 return rc;
1474 AssertRCSuccess(rc);
1475 }
1476
1477 /*
1478 * Check selector registers.
1479 */
1480 VBOXSTRICTRC rcStrict = selmR3UpdateSegmentRegisters(pVM, pVCpu);
1481
1482 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1483 return rcStrict;
1484}
1485
1486
1487/**
1488 * Synchronize the shadowed fields in the TSS.
1489 *
1490 * At present we're shadowing the ring-0 stack selector & pointer, and the
1491 * interrupt redirection bitmap (if present). We take the lazy approach wrt to
1492 * REM and this function is called both if REM made any changes to the TSS or
1493 * loaded TR.
1494 *
1495 * @returns VBox status code.
1496 * @param pVM The cross context VM structure.
1497 * @param pVCpu The cross context virtual CPU structure.
1498 */
1499VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1500{
1501 LogFlow(("SELMR3SyncTSS\n"));
1502 int rc;
1503 AssertReturnStmt(VM_IS_RAW_MODE_ENABLED(pVM), VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS), VINF_SUCCESS);
1504
1505 STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1506 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1507
1508 /*
1509 * Get TR and extract and store the basic info.
1510 *
1511 * Note! The TSS limit is not checked by the LTR code, so we
1512 * have to be a bit careful with it. We make sure cbTss
1513 * won't be zero if TR is valid and if it's NULL we'll
1514 * make sure cbTss is 0.
1515 */
1516/** @todo use the hidden bits, not shadow GDT. */
1517 CPUMSELREGHID trHid;
1518 RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1519 RTGCPTR GCPtrTss = trHid.u64Base;
1520 uint32_t cbTss = trHid.u32Limit;
1521 Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1522 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1523 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1524 if (SelTss & X86_SEL_MASK_OFF_RPL)
1525 {
1526 Assert(!(SelTss & X86_SEL_LDT));
1527 Assert(trHid.Attr.n.u1DescType == 0);
1528 Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1529 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1530 if (!++cbTss)
1531 cbTss = UINT32_MAX;
1532 }
1533 else
1534 {
1535 Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1536 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1537 cbTss = 0; /* the reset case. */
1538 }
1539 pVM->selm.s.cbGuestTss = cbTss;
1540 pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1541 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1542
1543 /*
1544 * Figure out the size of what need to monitor.
1545 */
1546 /* We're not interested in any 16-bit TSSes. */
1547 uint32_t cbMonitoredTss = cbTss;
1548 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1549 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1550 cbMonitoredTss = 0;
1551
1552 pVM->selm.s.offGuestIoBitmap = 0;
1553 bool fNoRing1Stack = true;
1554 if (cbMonitoredTss)
1555 {
1556 /*
1557 * 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1558 * If VME is enabled we also want to keep an eye on the interrupt
1559 * redirection bitmap.
1560 */
1561 VBOXTSS Tss;
1562 uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1563 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_UOFFSETOF(VBOXTSS, IntRedirBitmap));
1564 if ( !(cr4 & X86_CR4_VME)
1565 || ( RT_SUCCESS(rc)
1566 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1567 && Tss.offIoBitmap > cbTss) /* beyond the end */ /** @todo not sure how the partial case is handled; probably not allowed. */
1568 )
1569 /* No interrupt redirection bitmap, just ESP0 and SS0. */
1570 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1571 else if (RT_SUCCESS(rc))
1572 {
1573 /*
1574 * Everything up to and including the interrupt redirection bitmap. Unfortunately
1575 * this can be quite a large chunk. We use to skip it earlier and just hope it
1576 * was kind of static...
1577 *
1578 * Update the virtual interrupt redirection bitmap while we're here.
1579 * (It is located in the 32 bytes before TR:offIoBitmap.)
1580 */
1581 cbMonitoredTss = Tss.offIoBitmap;
1582 pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1583
1584 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1585 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1586 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1587 AssertRC(rc);
1588 /** @todo memset the bitmap on failure? */
1589 Log2(("Redirection bitmap:\n"));
1590 Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1591 }
1592 else
1593 {
1594 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, IntRedirBitmap);
1595 pVM->selm.s.offGuestIoBitmap = 0;
1596 /** @todo memset the bitmap? */
1597 }
1598
1599 /*
1600 * Update the ring 0 stack selector and base address.
1601 */
1602 if (RT_SUCCESS(rc))
1603 {
1604# ifdef LOG_ENABLED
1605 if (LogIsEnabled())
1606 {
1607 uint32_t ssr0, espr0;
1608 SELMGetRing1Stack(pVM, &ssr0, &espr0);
1609 if ((ssr0 & ~1) != Tss.ss0 || espr0 != Tss.esp0)
1610 {
1611 RTGCPHYS GCPhys = NIL_RTGCPHYS;
1612 rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1613 Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1614 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1615 AssertMsg(ssr0 != Tss.ss0,
1616 ("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1617 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1618 }
1619 Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1620 }
1621# endif /* LOG_ENABLED */
1622 AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1623
1624 /* Update our TSS structure for the guest's ring 1 stack */
1625 selmSetRing1Stack(pVM, Tss.ss0 | 1, Tss.esp0);
1626 pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1627
1628# ifdef VBOX_WITH_RAW_RING1
1629 /* Update our TSS structure for the guest's ring 2 stack */
1630 if (EMIsRawRing1Enabled(pVM))
1631 {
1632 if ( (pVM->selm.s.Tss.ss2 != ((Tss.ss1 & ~2) | 1))
1633 || pVM->selm.s.Tss.esp2 != Tss.esp1)
1634 Log(("SELMR3SyncTSS: Updating TSS ring 1 stack to %04X:%08X from %04X:%08X\n", Tss.ss1, Tss.esp1, (pVM->selm.s.Tss.ss2 & ~2) | 1, pVM->selm.s.Tss.esp2));
1635 selmSetRing2Stack(pVM, (Tss.ss1 & ~1) | 2, Tss.esp1);
1636 }
1637# endif
1638 }
1639 }
1640
1641 /*
1642 * Flush the ring-1 stack and the direct syscall dispatching if we
1643 * cannot obtain SS0:ESP0.
1644 */
1645 if (fNoRing1Stack)
1646 {
1647 selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1648 pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1649
1650 /** @todo handle these dependencies better! */
1651 TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1652 TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1653 }
1654
1655 /*
1656 * Check for monitor changes and apply them.
1657 */
1658 if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1659 || cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1660 {
1661 Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1662 GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1663
1664 /* Release the old range first. */
1665 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1666 {
1667 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestTss, false /*fHypervisor*/);
1668 AssertRC(rc);
1669 }
1670
1671 /* Register the write handler if TS != 0. */
1672 if (cbMonitoredTss != 0)
1673 {
1674# ifdef SELM_TRACK_GUEST_TSS_CHANGES
1675 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestTssWriteHandlerType,
1676 GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1677 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
1678 if (RT_FAILURE(rc))
1679 {
1680# ifdef VBOX_WITH_RAW_RING1
1681 /** @todo !HACK ALERT!
1682 * Some guest OSes (QNX) share code and the TSS on the same page;
1683 * PGMR3HandlerVirtualRegister doesn't support more than one
1684 * handler, so we kick out the PATM handler as this one is more
1685 * important. Fix this properly in PGMR3HandlerVirtualRegister?
1686 */
1687 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1688 {
1689 LogRel(("SELMR3SyncTSS: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority TSS page monitor\n", GCPtrTss));
1690 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, GCPtrTss & PAGE_BASE_GC_MASK, false /*fHypervisor*/);
1691 AssertRC(rc);
1692
1693 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestTssWriteHandlerType,
1694 GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1695 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
1696 if (RT_FAILURE(rc))
1697 {
1698 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1699 return rc;
1700 }
1701 }
1702# else
1703 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1704 return rc;
1705# endif
1706 }
1707# endif /* SELM_TRACK_GUEST_TSS_CHANGES */
1708
1709 /* Update saved Guest TSS info. */
1710 pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1711 pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1712 pVM->selm.s.GCSelTss = SelTss;
1713 }
1714 else
1715 {
1716 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1717 pVM->selm.s.cbMonitoredGuestTss = 0;
1718 pVM->selm.s.GCSelTss = 0;
1719 }
1720 }
1721
1722 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1723
1724 STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1725 return VINF_SUCCESS;
1726}
1727
1728
1729/**
1730 * Compares the Guest GDT and LDT with the shadow tables.
1731 * This is a VBOX_STRICT only function.
1732 *
1733 * @returns VBox status code.
1734 * @param pVM The cross context VM structure.
1735 */
1736VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1737{
1738# ifdef VBOX_STRICT
1739 PVMCPU pVCpu = VMMGetCpu(pVM);
1740 AssertReturn(VM_IS_RAW_MODE_ENABLED(pVM), VERR_SELM_HM_IPE);
1741
1742 /*
1743 * Get GDTR and check for conflict.
1744 */
1745 VBOXGDTR GDTR;
1746 CPUMGetGuestGDTR(pVCpu, &GDTR);
1747 if (GDTR.cbGdt == 0)
1748 return VINF_SUCCESS;
1749
1750 if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1751 Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1752
1753 if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1754 Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1755
1756 /*
1757 * Loop thru the GDT checking each entry.
1758 */
1759 RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1760 PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1761 PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1762 while (pGDTE < pGDTEEnd)
1763 {
1764 X86DESC GDTEGuest;
1765 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1766 if (RT_SUCCESS(rc))
1767 {
1768 if (pGDTE->Gen.u1DescType || pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1769 {
1770 if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1771 || pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1772 || pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1773 || pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1774 || pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1775 || pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1776 || pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1777 {
1778 unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1779 SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1780 SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1781 }
1782 }
1783 }
1784
1785 /* Advance to the next descriptor. */
1786 GCPtrGDTEGuest += sizeof(X86DESC);
1787 pGDTE++;
1788 }
1789
1790
1791 /*
1792 * LDT?
1793 */
1794 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1795 if ((SelLdt & X86_SEL_MASK_OFF_RPL) == 0)
1796 return VINF_SUCCESS;
1797 Assert(!(SelLdt & X86_SEL_LDT));
1798 if (SelLdt > GDTR.cbGdt)
1799 {
1800 Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1801 return VERR_SELM_LDT_OUT_OF_BOUNDS;
1802 }
1803 X86DESC LDTDesc;
1804 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1805 if (RT_FAILURE(rc))
1806 {
1807 Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1808 return rc;
1809 }
1810 RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(&LDTDesc);
1811 uint32_t cbLdt = X86DESC_LIMIT_G(&LDTDesc);
1812
1813 /*
1814 * Validate it.
1815 */
1816 if (!cbLdt)
1817 return VINF_SUCCESS;
1818 /** @todo check what intel does about odd limits. */
1819 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1820 if ( LDTDesc.Gen.u1DescType
1821 || LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1822 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1823 {
1824 Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1825 return VERR_SELM_INVALID_LDT;
1826 }
1827
1828 /*
1829 * Loop thru the LDT checking each entry.
1830 */
1831 unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1832 PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1833 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1834 while (pLDTE < pLDTEEnd)
1835 {
1836 X86DESC LDTEGuest;
1837 rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1838 if (RT_SUCCESS(rc))
1839 {
1840 if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1841 || pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1842 || pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1843 || pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1844 || pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1845 || pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1846 || pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1847 {
1848 unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1849 SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1850 SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1851 }
1852 }
1853
1854 /* Advance to the next descriptor. */
1855 GCPtrLDTEGuest += sizeof(X86DESC);
1856 pLDTE++;
1857 }
1858
1859# else /* !VBOX_STRICT */
1860 NOREF(pVM);
1861# endif /* !VBOX_STRICT */
1862
1863 return VINF_SUCCESS;
1864}
1865
1866
1867/**
1868 * Validates the RawR0 TSS values against the one in the Guest TSS.
1869 *
1870 * @returns true if it matches.
1871 * @returns false and assertions on mismatch..
1872 * @param pVM The cross context VM structure.
1873 */
1874VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1875{
1876# if defined(VBOX_STRICT) && defined(SELM_TRACK_GUEST_TSS_CHANGES)
1877 PVMCPU pVCpu = VMMGetCpu(pVM);
1878
1879 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1880 return true;
1881
1882 /*
1883 * Get TR and extract the basic info.
1884 */
1885 CPUMSELREGHID trHid;
1886 RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1887 RTGCPTR GCPtrTss = trHid.u64Base;
1888 uint32_t cbTss = trHid.u32Limit;
1889 Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1890 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1891 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1892 if (SelTss & X86_SEL_MASK_OFF_RPL)
1893 {
1894 AssertReturn(!(SelTss & X86_SEL_LDT), false);
1895 AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1896 AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1897 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1898 false);
1899 if (!++cbTss)
1900 cbTss = UINT32_MAX;
1901 }
1902 else
1903 {
1904 AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1905 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
1906 false);
1907 cbTss = 0; /* the reset case. */
1908 }
1909 AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1910 AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1911 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1912 ("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1913 false);
1914 AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1915 || (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1916 ("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1917 false);
1918 AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1919 || (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1920 ("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1921 false);
1922
1923
1924 /*
1925 * Figure out the size of what need to monitor.
1926 */
1927 /* We're not interested in any 16-bit TSSes. */
1928 uint32_t cbMonitoredTss = cbTss;
1929 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1930 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1931 cbMonitoredTss = 0;
1932 if (cbMonitoredTss)
1933 {
1934 VBOXTSS Tss;
1935 uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1936 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_UOFFSETOF(VBOXTSS, IntRedirBitmap));
1937 AssertReturn( rc == VINF_SUCCESS
1938 /* Happens early in XP boot during page table switching. */
1939 || ( (rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT)
1940 && !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
1941 false);
1942 if ( !(cr4 & X86_CR4_VME)
1943 || ( RT_SUCCESS(rc)
1944 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1945 && Tss.offIoBitmap > cbTss)
1946 )
1947 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1948 else if (RT_SUCCESS(rc))
1949 {
1950 cbMonitoredTss = Tss.offIoBitmap;
1951 AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1952 ("%#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1953 false);
1954
1955 /* check the bitmap */
1956 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1957 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
1958 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1959 AssertRCReturn(rc, false);
1960 AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
1961 ("offIoBitmap=%#x cbTss=%#x\n"
1962 " Guest: %.32Rhxs\n"
1963 "Shadow: %.32Rhxs\n",
1964 Tss.offIoBitmap, cbTss,
1965 &Tss.IntRedirBitmap[0],
1966 &pVM->selm.s.Tss.IntRedirBitmap[0]),
1967 false);
1968 }
1969 else
1970 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, IntRedirBitmap);
1971
1972 /*
1973 * Check SS0 and ESP0.
1974 */
1975 if ( !pVM->selm.s.fSyncTSSRing0Stack
1976 && RT_SUCCESS(rc))
1977 {
1978 if ( Tss.esp0 != pVM->selm.s.Tss.esp1
1979 || Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
1980 {
1981 RTGCPHYS GCPhys;
1982 rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1983 AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
1984 (pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
1985 Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
1986 return false;
1987 }
1988 }
1989 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1990 }
1991 else
1992 {
1993 AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
1994 AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
1995 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1996 }
1997
1998
1999
2000 return true;
2001
2002# else /* !VBOX_STRICT */
2003 NOREF(pVM);
2004 return true;
2005# endif /* !VBOX_STRICT */
2006}
2007
2008
2009# ifdef VBOX_WITH_SAFE_STR
2010/**
2011 * Validates the RawR0 TR shadow GDT entry.
2012 *
2013 * @returns true if it matches.
2014 * @returns false and assertions on mismatch..
2015 * @param pVM The cross context VM structure.
2016 */
2017VMMR3DECL(bool) SELMR3CheckShadowTR(PVM pVM)
2018{
2019# ifdef VBOX_STRICT
2020 PX86DESC paGdt = pVM->selm.s.paGdtR3;
2021
2022 /*
2023 * TSS descriptor
2024 */
2025 PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
2026 RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
2027
2028 if ( pDesc->Gen.u16BaseLow != RT_LOWORD(RCPtrTSS)
2029 || pDesc->Gen.u8BaseHigh1 != RT_BYTE3(RCPtrTSS)
2030 || pDesc->Gen.u8BaseHigh2 != RT_BYTE4(RCPtrTSS)
2031 || pDesc->Gen.u16LimitLow != sizeof(VBOXTSS) - 1
2032 || pDesc->Gen.u4LimitHigh != 0
2033 || (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL && pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2034 || pDesc->Gen.u1DescType != 0 /* system */
2035 || pDesc->Gen.u2Dpl != 0 /* supervisor */
2036 || pDesc->Gen.u1Present != 1
2037 || pDesc->Gen.u1Available != 0
2038 || pDesc->Gen.u1Long != 0
2039 || pDesc->Gen.u1DefBig != 0
2040 || pDesc->Gen.u1Granularity != 0 /* byte limit */
2041 )
2042 {
2043 AssertFailed();
2044 return false;
2045 }
2046# else
2047 RT_NOREF_PV(pVM);
2048# endif
2049 return true;
2050}
2051# endif /* VBOX_WITH_SAFE_STR */
2052
2053#endif /* VBOX_WITH_RAW_MODE */
2054
2055/**
2056 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2057 *
2058 * See SELMR3GetSelectorInfo for details.
2059 *
2060 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
2061 *
2062 * @param pVCpu The cross context virtual CPU structure.
2063 * @param Sel The selector to get info about.
2064 * @param pSelInfo Where to store the information.
2065 */
2066static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2067{
2068 /*
2069 * Read it from the guest descriptor table.
2070 */
2071/** @todo this is bogus wrt the LDT/GDT limit on long selectors. */
2072 X86DESC64 Desc;
2073 RTGCPTR GCPtrDesc;
2074 if (!(Sel & X86_SEL_LDT))
2075 {
2076 /* GDT */
2077 VBOXGDTR Gdtr;
2078 CPUMGetGuestGDTR(pVCpu, &Gdtr);
2079 if ((Sel | X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2080 return VERR_INVALID_SELECTOR;
2081 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2082 }
2083 else
2084 {
2085 /* LDT */
2086 uint64_t GCPtrBase;
2087 uint32_t cbLimit;
2088 CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2089 if ((Sel | X86_SEL_RPL_LDT) > cbLimit)
2090 return VERR_INVALID_SELECTOR;
2091
2092 /* calc the descriptor location. */
2093 GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2094 }
2095
2096 /* read the descriptor. */
2097 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2098 if (RT_FAILURE(rc))
2099 {
2100 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2101 if (RT_FAILURE(rc))
2102 return rc;
2103 Desc.au64[1] = 0;
2104 }
2105
2106 /*
2107 * Extract the base and limit
2108 * (We ignore the present bit here, which is probably a bit silly...)
2109 */
2110 pSelInfo->Sel = Sel;
2111 pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2112 pSelInfo->u.Raw64 = Desc;
2113 if (Desc.Gen.u1DescType)
2114 {
2115 /*
2116 * 64-bit code selectors are wide open, it's not possible to detect
2117 * 64-bit data or stack selectors without also dragging in assumptions
2118 * about current CS (i.e. that's we're executing in 64-bit mode). So,
2119 * the selinfo user needs to deal with this in the context the info is
2120 * used unfortunately.
2121 */
2122 if ( Desc.Gen.u1Long
2123 && !Desc.Gen.u1DefBig
2124 && (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2125 {
2126 /* Note! We ignore the segment limit hacks that was added by AMD. */
2127 pSelInfo->GCPtrBase = 0;
2128 pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2129 }
2130 else
2131 {
2132 pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2133 pSelInfo->GCPtrBase = X86DESC_BASE(&Desc);
2134 }
2135 pSelInfo->SelGate = 0;
2136 }
2137 else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2138 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2139 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2140 {
2141 /* Note. LDT descriptors are weird in long mode, we ignore the footnote
2142 in the AMD manual here as a simplification. */
2143 pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc);
2144 pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2145 pSelInfo->SelGate = 0;
2146 }
2147 else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2148 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2149 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2150 {
2151 pSelInfo->cbLimit = X86DESC64_BASE(&Desc);
2152 pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2153 | ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2154 | ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2155 pSelInfo->SelGate = Desc.Gate.u16Sel;
2156 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_GATE;
2157 }
2158 else
2159 {
2160 pSelInfo->cbLimit = 0;
2161 pSelInfo->GCPtrBase = 0;
2162 pSelInfo->SelGate = 0;
2163 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_INVALID;
2164 }
2165 if (!Desc.Gen.u1Present)
2166 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_NOT_PRESENT;
2167
2168 return VINF_SUCCESS;
2169}
2170
2171
2172/**
2173 * Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2174 * interprets a legacy descriptor table entry and fills in the selector info
2175 * structure from it.
2176 *
2177 * @param pSelInfo Where to store the selector info. Only the fFlags and
2178 * Sel members have been initialized.
2179 * @param pDesc The legacy descriptor to parse.
2180 */
2181DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2182{
2183 pSelInfo->u.Raw64.au64[1] = 0;
2184 pSelInfo->u.Raw = *pDesc;
2185 if ( pDesc->Gen.u1DescType
2186 || !(pDesc->Gen.u4Type & 4))
2187 {
2188 pSelInfo->cbLimit = X86DESC_LIMIT_G(pDesc);
2189 pSelInfo->GCPtrBase = X86DESC_BASE(pDesc);
2190 pSelInfo->SelGate = 0;
2191 }
2192 else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2193 {
2194 pSelInfo->cbLimit = 0;
2195 if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2196 pSelInfo->GCPtrBase = 0;
2197 else
2198 pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2199 | (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2200 pSelInfo->SelGate = pDesc->Gate.u16Sel;
2201 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_GATE;
2202 }
2203 else
2204 {
2205 pSelInfo->cbLimit = 0;
2206 pSelInfo->GCPtrBase = 0;
2207 pSelInfo->SelGate = 0;
2208 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_INVALID;
2209 }
2210 if (!pDesc->Gen.u1Present)
2211 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_NOT_PRESENT;
2212}
2213
2214
2215/**
2216 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2217 *
2218 * See SELMR3GetSelectorInfo for details.
2219 *
2220 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
2221 *
2222 * @param pVM The cross context VM structure.
2223 * @param pVCpu The cross context virtual CPU structure.
2224 * @param Sel The selector to get info about.
2225 * @param pSelInfo Where to store the information.
2226 */
2227static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2228{
2229 /*
2230 * Read the descriptor entry
2231 */
2232 pSelInfo->fFlags = 0;
2233 X86DESC Desc;
2234 if ( !(Sel & X86_SEL_LDT)
2235 && ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_RPL_LDT)
2236 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_RPL_LDT)
2237 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_RPL_LDT)
2238 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_RPL_LDT)
2239 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_RPL_LDT))
2240 )
2241 {
2242 /*
2243 * Hypervisor descriptor.
2244 */
2245 pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2246 if (CPUMIsGuestInProtectedMode(pVCpu))
2247 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_PROT_MODE;
2248 else
2249 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_REAL_MODE;
2250
2251 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2252 }
2253 else if (CPUMIsGuestInProtectedMode(pVCpu))
2254 {
2255 /*
2256 * Read it from the guest descriptor table.
2257 */
2258 pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2259
2260 RTGCPTR GCPtrDesc;
2261 if (!(Sel & X86_SEL_LDT))
2262 {
2263 /* GDT */
2264 VBOXGDTR Gdtr;
2265 CPUMGetGuestGDTR(pVCpu, &Gdtr);
2266 if ((Sel | X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2267 return VERR_INVALID_SELECTOR;
2268 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2269 }
2270 else
2271 {
2272 /* LDT */
2273 uint64_t GCPtrBase;
2274 uint32_t cbLimit;
2275 CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2276 if ((Sel | X86_SEL_RPL_LDT) > cbLimit)
2277 return VERR_INVALID_SELECTOR;
2278
2279 /* calc the descriptor location. */
2280 GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2281 }
2282
2283 /* read the descriptor. */
2284 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2285 if (RT_FAILURE(rc))
2286 return rc;
2287 }
2288 else
2289 {
2290 /*
2291 * We're in real mode.
2292 */
2293 pSelInfo->Sel = Sel;
2294 pSelInfo->GCPtrBase = Sel << 4;
2295 pSelInfo->cbLimit = 0xffff;
2296 pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2297 pSelInfo->u.Raw64.au64[0] = 0;
2298 pSelInfo->u.Raw64.au64[1] = 0;
2299 pSelInfo->SelGate = 0;
2300 return VINF_SUCCESS;
2301 }
2302
2303 /*
2304 * Extract the base and limit or sel:offset for gates.
2305 */
2306 pSelInfo->Sel = Sel;
2307 selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2308
2309 return VINF_SUCCESS;
2310}
2311
2312
2313/**
2314 * Gets information about a selector.
2315 *
2316 * Intended for the debugger mostly and will prefer the guest descriptor tables
2317 * over the shadow ones.
2318 *
2319 * @retval VINF_SUCCESS on success.
2320 * @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2321 * descriptor table.
2322 * @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2323 * is not returned if the selector itself isn't present, you have to
2324 * check that for yourself (see DBGFSELINFO::fFlags).
2325 * @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2326 * pagetable or page backing the selector table wasn't present.
2327 * @returns Other VBox status code on other errors.
2328 *
2329 * @param pVM The cross context VM structure.
2330 * @param pVCpu The cross context virtual CPU structure.
2331 * @param Sel The selector to get info about.
2332 * @param pSelInfo Where to store the information.
2333 */
2334VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2335{
2336 AssertPtr(pSelInfo);
2337 if (CPUMIsGuestInLongMode(pVCpu))
2338 return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2339 return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2340}
2341
2342
2343/**
2344 * Gets information about a selector from the shadow tables.
2345 *
2346 * This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2347 * requires that the caller ensures that the shadow tables are up to date.
2348 *
2349 * @retval VINF_SUCCESS on success.
2350 * @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2351 * descriptor table.
2352 * @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2353 * is not returned if the selector itself isn't present, you have to
2354 * check that for yourself (see DBGFSELINFO::fFlags).
2355 * @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2356 * pagetable or page backing the selector table wasn't present.
2357 * @returns Other VBox status code on other errors.
2358 *
2359 * @param pVM The cross context VM structure.
2360 * @param Sel The selector to get info about.
2361 * @param pSelInfo Where to store the information.
2362 *
2363 * @remarks Don't use this when in hardware assisted virtualization mode.
2364 */
2365VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2366{
2367 Assert(pSelInfo);
2368
2369 /*
2370 * Read the descriptor entry
2371 */
2372 X86DESC Desc;
2373 if (!(Sel & X86_SEL_LDT))
2374 {
2375 /*
2376 * Global descriptor.
2377 */
2378 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2379 pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK_OFF_RPL)
2380 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK_OFF_RPL)
2381 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK_OFF_RPL)
2382 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK_OFF_RPL)
2383 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK_OFF_RPL)
2384 ? DBGFSELINFO_FLAGS_HYPER
2385 : 0;
2386 /** @todo check that the GDT offset is valid. */
2387 }
2388 else
2389 {
2390 /*
2391 * Local Descriptor.
2392 */
2393 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2394 Desc = paLDT[Sel >> X86_SEL_SHIFT];
2395 /** @todo check if the LDT page is actually available. */
2396 /** @todo check that the LDT offset is valid. */
2397 pSelInfo->fFlags = 0;
2398 }
2399 if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2400 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_PROT_MODE;
2401 else
2402 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_REAL_MODE;
2403
2404 /*
2405 * Extract the base and limit or sel:offset for gates.
2406 */
2407 pSelInfo->Sel = Sel;
2408 selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2409
2410 return VINF_SUCCESS;
2411}
2412
2413
2414/**
2415 * Formats a descriptor.
2416 *
2417 * @param Desc Descriptor to format.
2418 * @param Sel Selector number.
2419 * @param pszOutput Output buffer.
2420 * @param cchOutput Size of output buffer.
2421 */
2422static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2423{
2424 /*
2425 * Make variable description string.
2426 */
2427 static struct
2428 {
2429 unsigned cch;
2430 const char *psz;
2431 } const aTypes[32] =
2432 {
2433#define STRENTRY(str) { sizeof(str) - 1, str }
2434 /* system */
2435 STRENTRY("Reserved0 "), /* 0x00 */
2436 STRENTRY("TSS16Avail "), /* 0x01 */
2437 STRENTRY("LDT "), /* 0x02 */
2438 STRENTRY("TSS16Busy "), /* 0x03 */
2439 STRENTRY("Call16 "), /* 0x04 */
2440 STRENTRY("Task "), /* 0x05 */
2441 STRENTRY("Int16 "), /* 0x06 */
2442 STRENTRY("Trap16 "), /* 0x07 */
2443 STRENTRY("Reserved8 "), /* 0x08 */
2444 STRENTRY("TSS32Avail "), /* 0x09 */
2445 STRENTRY("ReservedA "), /* 0x0a */
2446 STRENTRY("TSS32Busy "), /* 0x0b */
2447 STRENTRY("Call32 "), /* 0x0c */
2448 STRENTRY("ReservedD "), /* 0x0d */
2449 STRENTRY("Int32 "), /* 0x0e */
2450 STRENTRY("Trap32 "), /* 0x0f */
2451 /* non system */
2452 STRENTRY("DataRO "), /* 0x10 */
2453 STRENTRY("DataRO Accessed "), /* 0x11 */
2454 STRENTRY("DataRW "), /* 0x12 */
2455 STRENTRY("DataRW Accessed "), /* 0x13 */
2456 STRENTRY("DataDownRO "), /* 0x14 */
2457 STRENTRY("DataDownRO Accessed "), /* 0x15 */
2458 STRENTRY("DataDownRW "), /* 0x16 */
2459 STRENTRY("DataDownRW Accessed "), /* 0x17 */
2460 STRENTRY("CodeEO "), /* 0x18 */
2461 STRENTRY("CodeEO Accessed "), /* 0x19 */
2462 STRENTRY("CodeER "), /* 0x1a */
2463 STRENTRY("CodeER Accessed "), /* 0x1b */
2464 STRENTRY("CodeConfEO "), /* 0x1c */
2465 STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2466 STRENTRY("CodeConfER "), /* 0x1e */
2467 STRENTRY("CodeConfER Accessed ") /* 0x1f */
2468#undef SYSENTRY
2469 };
2470#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2471 char szMsg[128];
2472 char *psz = &szMsg[0];
2473 unsigned i = Desc.Gen.u1DescType << 4 | Desc.Gen.u4Type;
2474 memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2475 psz += aTypes[i].cch;
2476
2477 if (Desc.Gen.u1Present)
2478 ADD_STR(psz, "Present ");
2479 else
2480 ADD_STR(psz, "Not-Present ");
2481 if (Desc.Gen.u1Granularity)
2482 ADD_STR(psz, "Page ");
2483 if (Desc.Gen.u1DefBig)
2484 ADD_STR(psz, "32-bit ");
2485 else
2486 ADD_STR(psz, "16-bit ");
2487#undef ADD_STR
2488 *psz = '\0';
2489
2490 /*
2491 * Limit and Base and format the output.
2492 */
2493 uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
2494 uint32_t u32Base = X86DESC_BASE(&Desc);
2495
2496 RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2497 Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2498}
2499
2500
2501/**
2502 * Dumps a descriptor.
2503 *
2504 * @param Desc Descriptor to dump.
2505 * @param Sel Selector number.
2506 * @param pszMsg Message to prepend the log entry with.
2507 */
2508VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2509{
2510#ifdef LOG_ENABLED
2511 if (LogIsEnabled())
2512 {
2513 char szOutput[128];
2514 selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2515 Log(("%s: %s\n", pszMsg, szOutput));
2516 }
2517#else
2518 RT_NOREF3(Desc, Sel, pszMsg);
2519#endif
2520}
2521
2522
2523/**
2524 * Display the shadow gdt.
2525 *
2526 * @param pVM The cross context VM structure.
2527 * @param pHlp The info helpers.
2528 * @param pszArgs Arguments, ignored.
2529 */
2530static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2531{
2532 NOREF(pszArgs);
2533 pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2534 for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2535 {
2536 if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2537 {
2538 char szOutput[128];
2539 selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2540 const char *psz = "";
2541 if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2542 psz = " HyperCS";
2543 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2544 psz = " HyperDS";
2545 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2546 psz = " HyperCS64";
2547 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2548 psz = " HyperTSS";
2549 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2550 psz = " HyperTSSTrap08";
2551 pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2552 }
2553 }
2554}
2555
2556
2557/**
2558 * Display the guest gdt.
2559 *
2560 * @param pVM The cross context VM structure.
2561 * @param pHlp The info helpers.
2562 * @param pszArgs Arguments, ignored.
2563 */
2564static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2565{
2566 /** @todo SMP support! */
2567 PVMCPU pVCpu = &pVM->aCpus[0];
2568
2569 VBOXGDTR GDTR;
2570 CPUMGetGuestGDTR(pVCpu, &GDTR);
2571 RTGCPTR GCPtrGDT = GDTR.pGdt;
2572 unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2573
2574 pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2575 for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2576 {
2577 X86DESC GDTE;
2578 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2579 if (RT_SUCCESS(rc))
2580 {
2581 if (GDTE.Gen.u1Present)
2582 {
2583 char szOutput[128];
2584 selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2585 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2586 }
2587 }
2588 else if (rc == VERR_PAGE_NOT_PRESENT)
2589 {
2590 if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2591 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2592 }
2593 else
2594 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2595 }
2596 NOREF(pszArgs);
2597}
2598
2599
2600/**
2601 * Display the shadow ldt.
2602 *
2603 * @param pVM The cross context VM structure.
2604 * @param pHlp The info helpers.
2605 * @param pszArgs Arguments, ignored.
2606 */
2607static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2608{
2609 unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2610 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2611 pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2612 for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2613 {
2614 if (paLDT[iLDT].Gen.u1Present)
2615 {
2616 char szOutput[128];
2617 selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2618 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2619 }
2620 }
2621 NOREF(pszArgs);
2622}
2623
2624
2625/**
2626 * Display the guest ldt.
2627 *
2628 * @param pVM The cross context VM structure.
2629 * @param pHlp The info helpers.
2630 * @param pszArgs Arguments, ignored.
2631 */
2632static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2633{
2634 /** @todo SMP support! */
2635 PVMCPU pVCpu = &pVM->aCpus[0];
2636
2637 uint64_t GCPtrLdt;
2638 uint32_t cbLdt;
2639 RTSEL SelLdt = CPUMGetGuestLdtrEx(pVCpu, &GCPtrLdt, &cbLdt);
2640 if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
2641 {
2642 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2643 return;
2644 }
2645
2646 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RX64 limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2647 unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2648 for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2649 {
2650 X86DESC LdtE;
2651 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2652 if (RT_SUCCESS(rc))
2653 {
2654 if (LdtE.Gen.u1Present)
2655 {
2656 char szOutput[128];
2657 selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2658 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2659 }
2660 }
2661 else if (rc == VERR_PAGE_NOT_PRESENT)
2662 {
2663 if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2664 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, GCPtrLdt);
2665 }
2666 else
2667 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, rc, GCPtrLdt);
2668 }
2669 NOREF(pszArgs);
2670}
2671
2672
2673/**
2674 * Dumps the hypervisor GDT
2675 *
2676 * @param pVM The cross context VM structure.
2677 */
2678VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2679{
2680 DBGFR3Info(pVM->pUVM, "gdt", NULL, NULL);
2681}
2682
2683
2684/**
2685 * Dumps the hypervisor LDT
2686 *
2687 * @param pVM The cross context VM structure.
2688 */
2689VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2690{
2691 DBGFR3Info(pVM->pUVM, "ldt", NULL, NULL);
2692}
2693
2694
2695/**
2696 * Dumps the guest GDT
2697 *
2698 * @param pVM The cross context VM structure.
2699 */
2700VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2701{
2702 DBGFR3Info(pVM->pUVM, "gdtguest", NULL, NULL);
2703}
2704
2705
2706/**
2707 * Dumps the guest LDT
2708 *
2709 * @param pVM The cross context VM structure.
2710 */
2711VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2712{
2713 DBGFR3Info(pVM->pUVM, "ldtguest", NULL, NULL);
2714}
2715
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