VirtualBox

About
Screenshots
Downloads
Documentation
End-user docs
Technical docs
Contribute
Community

Browse Source

Context Navigation

source: vbox/trunk/src/VBox/VMM/VMMR3/PGMSavedState.cpp@ 87765

Last change on this file since 87765 was 86473, checked in by vboxsync, 4 years ago
VMM/PGM: Working on eliminating page table bitfield use. bugref:9841 bugref:9746
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 127.5 KB

Line
1	/* $Id: PGMSavedState.cpp 86473 2020-10-07 17:30:25Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM
23	#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
24	#include <VBox/vmm/pgm.h>
25	#include <VBox/vmm/stam.h>
26	#include <VBox/vmm/ssm.h>
27	#include <VBox/vmm/pdmdrv.h>
28	#include <VBox/vmm/pdmdev.h>
29	#include "PGMInternal.h"
30	#include <VBox/vmm/vm.h>
31	#include "PGMInline.h"
32
33	#include <VBox/param.h>
34	#include <VBox/err.h>
35
36	#include <iprt/asm.h>
37	#include <iprt/assert.h>
38	#include <iprt/crc.h>
39	#include <iprt/mem.h>
40	#include <iprt/sha.h>
41	#include <iprt/string.h>
42	#include <iprt/thread.h>
43
44
45	/*********************************************************************************************************************************
46	* Defined Constants And Macros *
47	*********************************************************************************************************************************/
48	/** Saved state data unit version. */
49	#define PGM_SAVED_STATE_VERSION 14
50	/** Saved state data unit version before the PAE PDPE registers. */
51	#define PGM_SAVED_STATE_VERSION_PRE_PAE 13
52	/** Saved state data unit version after this includes ballooned page flags in
53	* the state (see @bugref{5515}). */
54	#define PGM_SAVED_STATE_VERSION_BALLOON_BROKEN 12
55	/** Saved state before the balloon change. */
56	#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
57	/** Saved state data unit version used during 3.1 development, misses the RAM
58	* config. */
59	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
60	/** Saved state data unit version for 3.0 (pre teleportation). */
61	#define PGM_SAVED_STATE_VERSION_3_0_0 9
62	/** Saved state data unit version for 2.2.2 and later. */
63	#define PGM_SAVED_STATE_VERSION_2_2_2 8
64	/** Saved state data unit version for 2.2.0. */
65	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
66	/** Saved state data unit version. */
67	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
68
69
70	/** @name Sparse state record types
71	* @{ */
72	/** Zero page. No data. */
73	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
74	/** Raw page. */
75	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
76	/** Raw MMIO2 page. */
77	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
78	/** Zero MMIO2 page. */
79	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
80	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
81	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
82	/** Raw shadowed ROM page. The protection (8-bit) precedes the raw bits. */
83	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
84	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
85	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
86	/** ROM protection (8-bit). */
87	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
88	/** Ballooned page. No data. */
89	#define PGM_STATE_REC_RAM_BALLOONED UINT8_C(0x08)
90	/** The last record type. */
91	#define PGM_STATE_REC_LAST PGM_STATE_REC_RAM_BALLOONED
92	/** End marker. */
93	#define PGM_STATE_REC_END UINT8_C(0xff)
94	/** Flag indicating that the data is preceded by the page address.
95	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
96	* range ID and a 32-bit page index.
97	*/
98	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
99	/** @} */
100
101	/** The CRC-32 for a zero page. */
102	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
103	/** The CRC-32 for a zero half page. */
104	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
105
106
107
108	/** @name Old Page types used in older saved states.
109	* @{ */
110	/** Old saved state: The usual invalid zero entry. */
111	#define PGMPAGETYPE_OLD_INVALID 0
112	/** Old saved state: RAM page. (RWX) */
113	#define PGMPAGETYPE_OLD_RAM 1
114	/** Old saved state: MMIO2 page. (RWX) */
115	#define PGMPAGETYPE_OLD_MMIO2 1
116	/** Old saved state: MMIO2 page aliased over an MMIO page. (RWX)
117	* See PGMHandlerPhysicalPageAlias(). */
118	#define PGMPAGETYPE_OLD_MMIO2_ALIAS_MMIO 2
119	/** Old saved state: Shadowed ROM. (RWX) */
120	#define PGMPAGETYPE_OLD_ROM_SHADOW 3
121	/** Old saved state: ROM page. (R-X) */
122	#define PGMPAGETYPE_OLD_ROM 4
123	/** Old saved state: MMIO page. (---) */
124	#define PGMPAGETYPE_OLD_MMIO 5
125	/** @} */
126
127
128	/*********************************************************************************************************************************
129	* Structures and Typedefs *
130	*********************************************************************************************************************************/
131	/** For loading old saved states. (pre-smp) */
132	typedef struct
133	{
134	/** If set no conflict checks are required. (boolean) */
135	bool fMappingsFixed;
136	/** Size of fixed mapping */
137	uint32_t cbMappingFixed;
138	/** Base address (GC) of fixed mapping */
139	RTGCPTR GCPtrMappingFixed;
140	/** A20 gate mask.
141	* Our current approach to A20 emulation is to let REM do it and don't bother
142	* anywhere else. The interesting guests will be operating with it enabled anyway.
143	* But should the need arise, we'll subject physical addresses to this mask. */
144	RTGCPHYS GCPhysA20Mask;
145	/** A20 gate state - boolean! */
146	bool fA20Enabled;
147	/** The guest paging mode. */
148	PGMMODE enmGuestMode;
149	} PGMOLD;
150
151
152	/*********************************************************************************************************************************
153	* Global Variables *
154	*********************************************************************************************************************************/
155	/** PGM fields to save/load. */
156
157	static const SSMFIELD s_aPGMFields[] =
158	{
159	SSMFIELD_ENTRY( PGM, fMappingsFixed),
160	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
161	SSMFIELD_ENTRY( PGM, cbMappingFixed),
162	SSMFIELD_ENTRY( PGM, cBalloonedPages),
163	SSMFIELD_ENTRY_TERM()
164	};
165
166	static const SSMFIELD s_aPGMFieldsPreBalloon[] =
167	{
168	SSMFIELD_ENTRY( PGM, fMappingsFixed),
169	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
170	SSMFIELD_ENTRY( PGM, cbMappingFixed),
171	SSMFIELD_ENTRY_TERM()
172	};
173
174	static const SSMFIELD s_aPGMCpuFields[] =
175	{
176	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
177	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
178	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
179	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[0]),
180	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[1]),
181	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[2]),
182	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[3]),
183	SSMFIELD_ENTRY_TERM()
184	};
185
186	static const SSMFIELD s_aPGMCpuFieldsPrePae[] =
187	{
188	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
189	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
190	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
191	SSMFIELD_ENTRY_TERM()
192	};
193
194	static const SSMFIELD s_aPGMFields_Old[] =
195	{
196	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
197	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
198	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
199	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
200	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
201	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
202	SSMFIELD_ENTRY_TERM()
203	};
204
205
206	/**
207	* Find the ROM tracking structure for the given page.
208	*
209	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
210	* that it's a ROM page.
211	* @param pVM The cross context VM structure.
212	* @param GCPhys The address of the ROM page.
213	*/
214	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
215	{
216	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
217	pRomRange;
218	pRomRange = pRomRange->CTX_SUFF(pNext))
219	{
220	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
221	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
222	return &pRomRange->aPages[off >> PAGE_SHIFT];
223	}
224	return NULL;
225	}
226
227
228	/**
229	* Prepares the ROM pages for a live save.
230	*
231	* @returns VBox status code.
232	* @param pVM The cross context VM structure.
233	*/
234	static int pgmR3PrepRomPages(PVM pVM)
235	{
236	/*
237	* Initialize the live save tracking in the ROM page descriptors.
238	*/
239	pgmLock(pVM);
240	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
241	{
242	PPGMRAMRANGE pRamHint = NULL;;
243	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
244
245	for (uint32_t iPage = 0; iPage < cPages; iPage++)
246	{
247	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
248	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
249	pRom->aPages[iPage].LiveSave.fDirty = true;
250	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
251	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
252	{
253	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
254	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
255	else
256	{
257	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
258	PPGMPAGE pPage;
259	int rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, &pRamHint);
260	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
261	if (RT_SUCCESS(rc))
262	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage) && !PGM_PAGE_IS_BALLOONED(pPage);
263	else
264	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
265	}
266	}
267	}
268
269	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
270	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
271	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
272	}
273	pgmUnlock(pVM);
274
275	return VINF_SUCCESS;
276	}
277
278
279	/**
280	* Assigns IDs to the ROM ranges and saves them.
281	*
282	* @returns VBox status code.
283	* @param pVM The cross context VM structure.
284	* @param pSSM Saved state handle.
285	*/
286	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
287	{
288	pgmLock(pVM);
289	uint8_t id = 1;
290	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
291	{
292	pRom->idSavedState = id;
293	SSMR3PutU8(pSSM, id);
294	SSMR3PutStrZ(pSSM, ""); /* device name */
295	SSMR3PutU32(pSSM, 0); /* device instance */
296	SSMR3PutU8(pSSM, 0); /* region */
297	SSMR3PutStrZ(pSSM, pRom->pszDesc);
298	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
299	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
300	if (RT_FAILURE(rc))
301	break;
302	}
303	pgmUnlock(pVM);
304	return SSMR3PutU8(pSSM, UINT8_MAX);
305	}
306
307
308	/**
309	* Loads the ROM range ID assignments.
310	*
311	* @returns VBox status code.
312	*
313	* @param pVM The cross context VM structure.
314	* @param pSSM The saved state handle.
315	*/
316	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
317	{
318	PGM_LOCK_ASSERT_OWNER(pVM);
319
320	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
321	pRom->idSavedState = UINT8_MAX;
322
323	for (;;)
324	{
325	/*
326	* Read the data.
327	*/
328	uint8_t id;
329	int rc = SSMR3GetU8(pSSM, &id);
330	if (RT_FAILURE(rc))
331	return rc;
332	if (id == UINT8_MAX)
333	{
334	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
335	if (pRom->idSavedState != UINT8_MAX)
336	{ /* likely */ }
337	else if (pRom->fFlags & PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE)
338	LogRel(("PGM: The '%s' ROM was not found in the saved state, but it is marked as maybe-missing, so that's probably okay.\n",
339	pRom->pszDesc));
340	else
341	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX,
342	("The '%s' ROM was not found in the saved state. Probably due to some misconfiguration\n",
343	pRom->pszDesc));
344	return VINF_SUCCESS; /* the end */
345	}
346	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
347
348	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
349	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
350	AssertLogRelRCReturn(rc, rc);
351
352	uint32_t uInstance;
353	SSMR3GetU32(pSSM, &uInstance);
354	uint8_t iRegion;
355	SSMR3GetU8(pSSM, &iRegion);
356
357	char szDesc[64];
358	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
359	AssertLogRelRCReturn(rc, rc);
360
361	RTGCPHYS GCPhys;
362	SSMR3GetGCPhys(pSSM, &GCPhys);
363	RTGCPHYS cb;
364	rc = SSMR3GetGCPhys(pSSM, &cb);
365	if (RT_FAILURE(rc))
366	return rc;
367	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
368	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
369
370	/*
371	* Locate a matching ROM range.
372	*/
373	AssertLogRelMsgReturn( uInstance == 0
374	&& iRegion == 0
375	&& szDevName[0] == '\0',
376	("GCPhys=%RGp %s\n", GCPhys, szDesc),
377	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
378	PPGMROMRANGE pRom;
379	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
380	{
381	if ( pRom->idSavedState == UINT8_MAX
382	&& !strcmp(pRom->pszDesc, szDesc))
383	{
384	pRom->idSavedState = id;
385	break;
386	}
387	}
388	if (!pRom)
389	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
390	} /* forever */
391	}
392
393
394	/**
395	* Scan ROM pages.
396	*
397	* @param pVM The cross context VM structure.
398	*/
399	static void pgmR3ScanRomPages(PVM pVM)
400	{
401	/*
402	* The shadow ROMs.
403	*/
404	pgmLock(pVM);
405	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
406	{
407	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
408	{
409	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
410	for (uint32_t iPage = 0; iPage < cPages; iPage++)
411	{
412	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
413	if (pRomPage->LiveSave.fWrittenTo)
414	{
415	pRomPage->LiveSave.fWrittenTo = false;
416	if (!pRomPage->LiveSave.fDirty)
417	{
418	pRomPage->LiveSave.fDirty = true;
419	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
420	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
421	}
422	pRomPage->LiveSave.fDirtiedRecently = true;
423	}
424	else
425	pRomPage->LiveSave.fDirtiedRecently = false;
426	}
427	}
428	}
429	pgmUnlock(pVM);
430	}
431
432
433	/**
434	* Takes care of the virgin ROM pages in the first pass.
435	*
436	* This is an attempt at simplifying the handling of ROM pages a little bit.
437	* This ASSUMES that no new ROM ranges will be added and that they won't be
438	* relinked in any way.
439	*
440	* @param pVM The cross context VM structure.
441	* @param pSSM The SSM handle.
442	* @param fLiveSave Whether we're in a live save or not.
443	*/
444	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
445	{
446	pgmLock(pVM);
447	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
448	{
449	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
450	for (uint32_t iPage = 0; iPage < cPages; iPage++)
451	{
452	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
453	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
454
455	/* Get the virgin page descriptor. */
456	PPGMPAGE pPage;
457	if (PGMROMPROT_IS_ROM(enmProt))
458	pPage = pgmPhysGetPage(pVM, GCPhys);
459	else
460	pPage = &pRom->aPages[iPage].Virgin;
461
462	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
463	int rc = VINF_SUCCESS;
464	char abPage[PAGE_SIZE];
465	if ( !PGM_PAGE_IS_ZERO(pPage)
466	&& !PGM_PAGE_IS_BALLOONED(pPage))
467	{
468	void const *pvPage;
469	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
470	if (RT_SUCCESS(rc))
471	memcpy(abPage, pvPage, PAGE_SIZE);
472	}
473	else
474	ASMMemZeroPage(abPage);
475	pgmUnlock(pVM);
476	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
477
478	/* Save it. */
479	if (iPage > 0)
480	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
481	else
482	{
483	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
484	SSMR3PutU8(pSSM, pRom->idSavedState);
485	SSMR3PutU32(pSSM, iPage);
486	}
487	SSMR3PutU8(pSSM, (uint8_t)enmProt);
488	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
489	if (RT_FAILURE(rc))
490	return rc;
491
492	/* Update state. */
493	pgmLock(pVM);
494	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
495	if (fLiveSave)
496	{
497	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
498	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
499	pVM->pgm.s.LiveSave.cSavedPages++;
500	}
501	}
502	}
503	pgmUnlock(pVM);
504	return VINF_SUCCESS;
505	}
506
507
508	/**
509	* Saves dirty pages in the shadowed ROM ranges.
510	*
511	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
512	*
513	* @returns VBox status code.
514	* @param pVM The cross context VM structure.
515	* @param pSSM The SSM handle.
516	* @param fLiveSave Whether it's a live save or not.
517	* @param fFinalPass Whether this is the final pass or not.
518	*/
519	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
520	{
521	/*
522	* The Shadowed ROMs.
523	*
524	* ASSUMES that the ROM ranges are fixed.
525	* ASSUMES that all the ROM ranges are mapped.
526	*/
527	pgmLock(pVM);
528	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
529	{
530	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
531	{
532	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
533	uint32_t iPrevPage = cPages;
534	for (uint32_t iPage = 0; iPage < cPages; iPage++)
535	{
536	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
537	if ( !fLiveSave
538	\|\| ( pRomPage->LiveSave.fDirty
539	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
540	&& !pRomPage->LiveSave.fWrittenTo)
541	\|\| fFinalPass
542	)
543	)
544	)
545	{
546	uint8_t abPage[PAGE_SIZE];
547	PGMROMPROT enmProt = pRomPage->enmProt;
548	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
549	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(pVM, GCPhys);
550	bool fZero = PGM_PAGE_IS_ZERO(pPage) \|\| PGM_PAGE_IS_BALLOONED(pPage); Assert(!PGM_PAGE_IS_BALLOONED(pPage)); /* Shouldn't be ballooned. */
551	int rc = VINF_SUCCESS;
552	if (!fZero)
553	{
554	void const *pvPage;
555	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
556	if (RT_SUCCESS(rc))
557	memcpy(abPage, pvPage, PAGE_SIZE);
558	}
559	if (fLiveSave && RT_SUCCESS(rc))
560	{
561	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
562	pRomPage->LiveSave.fDirty = false;
563	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
564	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
565	pVM->pgm.s.LiveSave.cSavedPages++;
566	}
567	pgmUnlock(pVM);
568	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
569
570	if (iPage - 1U == iPrevPage && iPage > 0)
571	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
572	else
573	{
574	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
575	SSMR3PutU8(pSSM, pRom->idSavedState);
576	SSMR3PutU32(pSSM, iPage);
577	}
578	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
579	if (!fZero)
580	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
581	if (RT_FAILURE(rc))
582	return rc;
583
584	pgmLock(pVM);
585	iPrevPage = iPage;
586	}
587	/*
588	* In the final pass, make sure the protection is in sync.
589	*/
590	else if ( fFinalPass
591	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
592	{
593	PGMROMPROT enmProt = pRomPage->enmProt;
594	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
595	pgmUnlock(pVM);
596
597	if (iPage - 1U == iPrevPage && iPage > 0)
598	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
599	else
600	{
601	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
602	SSMR3PutU8(pSSM, pRom->idSavedState);
603	SSMR3PutU32(pSSM, iPage);
604	}
605	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
606	if (RT_FAILURE(rc))
607	return rc;
608
609	pgmLock(pVM);
610	iPrevPage = iPage;
611	}
612	}
613	}
614	}
615	pgmUnlock(pVM);
616	return VINF_SUCCESS;
617	}
618
619
620	/**
621	* Cleans up ROM pages after a live save.
622	*
623	* @param pVM The cross context VM structure.
624	*/
625	static void pgmR3DoneRomPages(PVM pVM)
626	{
627	NOREF(pVM);
628	}
629
630
631	/**
632	* Prepares the MMIO2 pages for a live save.
633	*
634	* @returns VBox status code.
635	* @param pVM The cross context VM structure.
636	*/
637	static int pgmR3PrepMmio2Pages(PVM pVM)
638	{
639	/*
640	* Initialize the live save tracking in the MMIO2 ranges.
641	* ASSUME nothing changes here.
642	*/
643	pgmLock(pVM);
644	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
645	{
646	if (pRegMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2)
647	{
648	uint32_t const cPages = pRegMmio->RamRange.cb >> PAGE_SHIFT;
649	pgmUnlock(pVM);
650
651	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
652	if (!paLSPages)
653	return VERR_NO_MEMORY;
654	for (uint32_t iPage = 0; iPage < cPages; iPage++)
655	{
656	/* Initialize it as a dirty zero page. */
657	paLSPages[iPage].fDirty = true;
658	paLSPages[iPage].cUnchangedScans = 0;
659	paLSPages[iPage].fZero = true;
660	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
661	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
662	}
663
664	pgmLock(pVM);
665	pRegMmio->paLSPages = paLSPages;
666	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
667	}
668	}
669	pgmUnlock(pVM);
670	return VINF_SUCCESS;
671	}
672
673
674	/**
675	* Assigns IDs to the MMIO2 ranges and saves them.
676	*
677	* @returns VBox status code.
678	* @param pVM The cross context VM structure.
679	* @param pSSM Saved state handle.
680	*/
681	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
682	{
683	pgmLock(pVM);
684	uint8_t id = 1;
685	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
686	{
687	if (pRegMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2)
688	{
689	pRegMmio->idSavedState = id;
690	SSMR3PutU8(pSSM, id);
691	SSMR3PutStrZ(pSSM, pRegMmio->pDevInsR3->pReg->szName);
692	SSMR3PutU32(pSSM, pRegMmio->pDevInsR3->iInstance);
693	SSMR3PutU8(pSSM, pRegMmio->iRegion);
694	SSMR3PutStrZ(pSSM, pRegMmio->RamRange.pszDesc);
695	int rc = SSMR3PutGCPhys(pSSM, pRegMmio->RamRange.cb);
696	if (RT_FAILURE(rc))
697	break;
698	id++;
699	}
700	}
701	pgmUnlock(pVM);
702	return SSMR3PutU8(pSSM, UINT8_MAX);
703	}
704
705
706	/**
707	* Loads the MMIO2 range ID assignments.
708	*
709	* @returns VBox status code.
710	*
711	* @param pVM The cross context VM structure.
712	* @param pSSM The saved state handle.
713	*/
714	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
715	{
716	PGM_LOCK_ASSERT_OWNER(pVM);
717
718	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
719	if (pRegMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2)
720	pRegMmio->idSavedState = UINT8_MAX;
721
722	for (;;)
723	{
724	/*
725	* Read the data.
726	*/
727	uint8_t id;
728	int rc = SSMR3GetU8(pSSM, &id);
729	if (RT_FAILURE(rc))
730	return rc;
731	if (id == UINT8_MAX)
732	{
733	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
734	AssertLogRelMsg( pRegMmio->idSavedState != UINT8_MAX
735	\|\| !(pRegMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2),
736	("%s\n", pRegMmio->RamRange.pszDesc));
737	return VINF_SUCCESS; /* the end */
738	}
739	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
740
741	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
742	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
743	AssertLogRelRCReturn(rc, rc);
744
745	uint32_t uInstance;
746	SSMR3GetU32(pSSM, &uInstance);
747	uint8_t iRegion;
748	SSMR3GetU8(pSSM, &iRegion);
749
750	char szDesc[64];
751	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
752	AssertLogRelRCReturn(rc, rc);
753
754	RTGCPHYS cb;
755	rc = SSMR3GetGCPhys(pSSM, &cb);
756	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
757
758	/*
759	* Locate a matching MMIO2 range.
760	*/
761	PPGMREGMMIO2RANGE pRegMmio;
762	for (pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
763	{
764	if ( pRegMmio->idSavedState == UINT8_MAX
765	&& pRegMmio->iRegion == iRegion
766	&& pRegMmio->pDevInsR3->iInstance == uInstance
767	&& (pRegMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2)
768	&& !strcmp(pRegMmio->pDevInsR3->pReg->szName, szDevName))
769	{
770	pRegMmio->idSavedState = id;
771	break;
772	}
773	}
774	if (!pRegMmio)
775	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
776	szDesc, szDevName, uInstance, iRegion);
777
778	/*
779	* Validate the configuration, the size of the MMIO2 region should be
780	* the same.
781	*/
782	if (cb != pRegMmio->RamRange.cb)
783	{
784	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
785	pRegMmio->RamRange.pszDesc, cb, pRegMmio->RamRange.cb));
786	if (cb > pRegMmio->RamRange.cb) /* bad idea? */
787	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
788	pRegMmio->RamRange.pszDesc, cb, pRegMmio->RamRange.cb);
789	}
790	} /* forever */
791	}
792
793
794	/**
795	* Scans one MMIO2 page.
796	*
797	* @returns True if changed, false if unchanged.
798	*
799	* @param pVM The cross context VM structure.
800	* @param pbPage The page bits.
801	* @param pLSPage The live save tracking structure for the page.
802	*
803	*/
804	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
805	{
806	/*
807	* Special handling of zero pages.
808	*/
809	bool const fZero = pLSPage->fZero;
810	if (fZero)
811	{
812	if (ASMMemIsZeroPage(pbPage))
813	{
814	/* Not modified. */
815	if (pLSPage->fDirty)
816	pLSPage->cUnchangedScans++;
817	return false;
818	}
819
820	pLSPage->fZero = false;
821	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
822	}
823	else
824	{
825	/*
826	* CRC the first half, if it doesn't match the page is dirty and
827	* we won't check the 2nd half (we'll do that next time).
828	*/
829	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
830	if (u32CrcH1 == pLSPage->u32CrcH1)
831	{
832	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
833	if (u32CrcH2 == pLSPage->u32CrcH2)
834	{
835	/* Probably not modified. */
836	if (pLSPage->fDirty)
837	pLSPage->cUnchangedScans++;
838	return false;
839	}
840
841	pLSPage->u32CrcH2 = u32CrcH2;
842	}
843	else
844	{
845	pLSPage->u32CrcH1 = u32CrcH1;
846	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
847	&& ASMMemIsZeroPage(pbPage))
848	{
849	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
850	pLSPage->fZero = true;
851	}
852	}
853	}
854
855	/* dirty page path */
856	pLSPage->cUnchangedScans = 0;
857	if (!pLSPage->fDirty)
858	{
859	pLSPage->fDirty = true;
860	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
861	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
862	if (fZero)
863	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
864	}
865	return true;
866	}
867
868
869	/**
870	* Scan for MMIO2 page modifications.
871	*
872	* @param pVM The cross context VM structure.
873	* @param uPass The pass number.
874	*/
875	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
876	{
877	/*
878	* Since this is a bit expensive we lower the scan rate after a little while.
879	*/
880	if ( ( (uPass & 3) != 0
881	&& uPass > 10)
882	\|\| uPass == SSM_PASS_FINAL)
883	return;
884
885	pgmLock(pVM); /* paranoia */
886	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
887	if (pRegMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2)
888	{
889	PPGMLIVESAVEMMIO2PAGE paLSPages = pRegMmio->paLSPages;
890	uint32_t cPages = pRegMmio->RamRange.cb >> PAGE_SHIFT;
891	pgmUnlock(pVM);
892
893	for (uint32_t iPage = 0; iPage < cPages; iPage++)
894	{
895	uint8_t const pbPage = (uint8_t const )pRegMmio->pvR3 + iPage * PAGE_SIZE;
896	pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
897	}
898
899	pgmLock(pVM);
900	}
901	pgmUnlock(pVM);
902
903	}
904
905
906	/**
907	* Save quiescent MMIO2 pages.
908	*
909	* @returns VBox status code.
910	* @param pVM The cross context VM structure.
911	* @param pSSM The SSM handle.
912	* @param fLiveSave Whether it's a live save or not.
913	* @param uPass The pass number.
914	*/
915	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
916	{
917	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
918	* device that we wish to know about changes.) */
919
920	int rc = VINF_SUCCESS;
921	if (uPass == SSM_PASS_FINAL)
922	{
923	/*
924	* The mop up round.
925	*/
926	pgmLock(pVM);
927	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3;
928	pRegMmio && RT_SUCCESS(rc);
929	pRegMmio = pRegMmio->pNextR3)
930	if (pRegMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2)
931	{
932	PPGMLIVESAVEMMIO2PAGE paLSPages = pRegMmio->paLSPages;
933	uint8_t const pbPage = (uint8_t const )pRegMmio->RamRange.pvR3;
934	uint32_t cPages = pRegMmio->RamRange.cb >> PAGE_SHIFT;
935	uint32_t iPageLast = cPages;
936	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
937	{
938	uint8_t u8Type;
939	if (!fLiveSave)
940	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
941	else
942	{
943	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
944	if ( !paLSPages[iPage].fDirty
945	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
946	{
947	if (paLSPages[iPage].fZero)
948	continue;
949
950	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
951	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
952	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
953	continue;
954	}
955	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
956	pVM->pgm.s.LiveSave.cSavedPages++;
957	}
958
959	if (iPage != 0 && iPage == iPageLast + 1)
960	rc = SSMR3PutU8(pSSM, u8Type);
961	else
962	{
963	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
964	SSMR3PutU8(pSSM, pRegMmio->idSavedState);
965	rc = SSMR3PutU32(pSSM, iPage);
966	}
967	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
968	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
969	if (RT_FAILURE(rc))
970	break;
971	iPageLast = iPage;
972	}
973	}
974	pgmUnlock(pVM);
975	}
976	/*
977	* Reduce the rate after a little while since the current MMIO2 approach is
978	* a bit expensive.
979	* We position it two passes after the scan pass to avoid saving busy pages.
980	*/
981	else if ( uPass <= 10
982	\|\| (uPass & 3) == 2)
983	{
984	pgmLock(pVM);
985	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3;
986	pRegMmio && RT_SUCCESS(rc);
987	pRegMmio = pRegMmio->pNextR3)
988	if (pRegMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2)
989	{
990	PPGMLIVESAVEMMIO2PAGE paLSPages = pRegMmio->paLSPages;
991	uint8_t const pbPage = (uint8_t const )pRegMmio->RamRange.pvR3;
992	uint32_t cPages = pRegMmio->RamRange.cb >> PAGE_SHIFT;
993	uint32_t iPageLast = cPages;
994	pgmUnlock(pVM);
995
996	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
997	{
998	/* Skip clean pages and pages which hasn't quiesced. */
999	if (!paLSPages[iPage].fDirty)
1000	continue;
1001	if (paLSPages[iPage].cUnchangedScans < 3)
1002	continue;
1003	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
1004	continue;
1005
1006	/* Save it. */
1007	bool const fZero = paLSPages[iPage].fZero;
1008	uint8_t abPage[PAGE_SIZE];
1009	if (!fZero)
1010	{
1011	memcpy(abPage, pbPage, PAGE_SIZE);
1012	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
1013	}
1014
1015	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
1016	if (iPage != 0 && iPage == iPageLast + 1)
1017	rc = SSMR3PutU8(pSSM, u8Type);
1018	else
1019	{
1020	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
1021	SSMR3PutU8(pSSM, pRegMmio->idSavedState);
1022	rc = SSMR3PutU32(pSSM, iPage);
1023	}
1024	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
1025	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1026	if (RT_FAILURE(rc))
1027	break;
1028
1029	/* Housekeeping. */
1030	paLSPages[iPage].fDirty = false;
1031	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
1032	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
1033	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
1034	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
1035	pVM->pgm.s.LiveSave.cSavedPages++;
1036	iPageLast = iPage;
1037	}
1038
1039	pgmLock(pVM);
1040	}
1041	pgmUnlock(pVM);
1042	}
1043
1044	return rc;
1045	}
1046
1047
1048	/**
1049	* Cleans up MMIO2 pages after a live save.
1050	*
1051	* @param pVM The cross context VM structure.
1052	*/
1053	static void pgmR3DoneMmio2Pages(PVM pVM)
1054	{
1055	/*
1056	* Free the tracking structures for the MMIO2 pages.
1057	* We do the freeing outside the lock in case the VM is running.
1058	*/
1059	pgmLock(pVM);
1060	for (PPGMREGMMIO2RANGE pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
1061	if (pRegMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2)
1062	{
1063	void *pvMmio2ToFree = pRegMmio->paLSPages;
1064	if (pvMmio2ToFree)
1065	{
1066	pRegMmio->paLSPages = NULL;
1067	pgmUnlock(pVM);
1068	MMR3HeapFree(pvMmio2ToFree);
1069	pgmLock(pVM);
1070	}
1071	}
1072	pgmUnlock(pVM);
1073	}
1074
1075
1076	/**
1077	* Prepares the RAM pages for a live save.
1078	*
1079	* @returns VBox status code.
1080	* @param pVM The cross context VM structure.
1081	*/
1082	static int pgmR3PrepRamPages(PVM pVM)
1083	{
1084
1085	/*
1086	* Try allocating tracking structures for the ram ranges.
1087	*
1088	* To avoid lock contention, we leave the lock every time we're allocating
1089	* a new array. This means we'll have to ditch the allocation and start
1090	* all over again if the RAM range list changes in-between.
1091	*
1092	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1093	* for cleaning up.
1094	*/
1095	PPGMRAMRANGE pCur;
1096	pgmLock(pVM);
1097	do
1098	{
1099	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1100	{
1101	if ( !pCur->paLSPages
1102	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1103	{
1104	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1105	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1106	pgmUnlock(pVM);
1107	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1108	if (!paLSPages)
1109	return VERR_NO_MEMORY;
1110	pgmLock(pVM);
1111	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1112	{
1113	pgmUnlock(pVM);
1114	MMR3HeapFree(paLSPages);
1115	pgmLock(pVM);
1116	break; /* try again */
1117	}
1118	pCur->paLSPages = paLSPages;
1119
1120	/*
1121	* Initialize the array.
1122	*/
1123	uint32_t iPage = cPages;
1124	while (iPage-- > 0)
1125	{
1126	/** @todo yield critsect! (after moving this away from EMT0) */
1127	PCPGMPAGE pPage = &pCur->aPages[iPage];
1128	paLSPages[iPage].cDirtied = 0;
1129	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1130	paLSPages[iPage].fWriteMonitored = 0;
1131	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1132	paLSPages[iPage].u2Reserved = 0;
1133	switch (PGM_PAGE_GET_TYPE(pPage))
1134	{
1135	case PGMPAGETYPE_RAM:
1136	if ( PGM_PAGE_IS_ZERO(pPage)
1137	\|\| PGM_PAGE_IS_BALLOONED(pPage))
1138	{
1139	paLSPages[iPage].fZero = 1;
1140	paLSPages[iPage].fShared = 0;
1141	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1142	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1143	#endif
1144	}
1145	else if (PGM_PAGE_IS_SHARED(pPage))
1146	{
1147	paLSPages[iPage].fZero = 0;
1148	paLSPages[iPage].fShared = 1;
1149	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1150	paLSPages[iPage].u32Crc = UINT32_MAX;
1151	#endif
1152	}
1153	else
1154	{
1155	paLSPages[iPage].fZero = 0;
1156	paLSPages[iPage].fShared = 0;
1157	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1158	paLSPages[iPage].u32Crc = UINT32_MAX;
1159	#endif
1160	}
1161	paLSPages[iPage].fIgnore = 0;
1162	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1163	break;
1164
1165	case PGMPAGETYPE_ROM_SHADOW:
1166	case PGMPAGETYPE_ROM:
1167	{
1168	paLSPages[iPage].fZero = 0;
1169	paLSPages[iPage].fShared = 0;
1170	paLSPages[iPage].fDirty = 0;
1171	paLSPages[iPage].fIgnore = 1;
1172	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1173	paLSPages[iPage].u32Crc = UINT32_MAX;
1174	#endif
1175	pVM->pgm.s.LiveSave.cIgnoredPages++;
1176	break;
1177	}
1178
1179	default:
1180	AssertMsgFailed(("%R[pgmpage]", pPage));
1181	RT_FALL_THRU();
1182	case PGMPAGETYPE_MMIO2:
1183	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1184	paLSPages[iPage].fZero = 0;
1185	paLSPages[iPage].fShared = 0;
1186	paLSPages[iPage].fDirty = 0;
1187	paLSPages[iPage].fIgnore = 1;
1188	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1189	paLSPages[iPage].u32Crc = UINT32_MAX;
1190	#endif
1191	pVM->pgm.s.LiveSave.cIgnoredPages++;
1192	break;
1193
1194	case PGMPAGETYPE_MMIO:
1195	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
1196	paLSPages[iPage].fZero = 0;
1197	paLSPages[iPage].fShared = 0;
1198	paLSPages[iPage].fDirty = 0;
1199	paLSPages[iPage].fIgnore = 1;
1200	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1201	paLSPages[iPage].u32Crc = UINT32_MAX;
1202	#endif
1203	pVM->pgm.s.LiveSave.cIgnoredPages++;
1204	break;
1205	}
1206	}
1207	}
1208	}
1209	} while (pCur);
1210	pgmUnlock(pVM);
1211
1212	return VINF_SUCCESS;
1213	}
1214
1215
1216	/**
1217	* Saves the RAM configuration.
1218	*
1219	* @returns VBox status code.
1220	* @param pVM The cross context VM structure.
1221	* @param pSSM The saved state handle.
1222	*/
1223	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1224	{
1225	uint32_t cbRamHole = 0;
1226	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1227	AssertRCReturn(rc, rc);
1228
1229	uint64_t cbRam = 0;
1230	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1231	AssertRCReturn(rc, rc);
1232
1233	SSMR3PutU32(pSSM, cbRamHole);
1234	return SSMR3PutU64(pSSM, cbRam);
1235	}
1236
1237
1238	/**
1239	* Loads and verifies the RAM configuration.
1240	*
1241	* @returns VBox status code.
1242	* @param pVM The cross context VM structure.
1243	* @param pSSM The saved state handle.
1244	*/
1245	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1246	{
1247	uint32_t cbRamHoleCfg = 0;
1248	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1249	AssertRCReturn(rc, rc);
1250
1251	uint64_t cbRamCfg = 0;
1252	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1253	AssertRCReturn(rc, rc);
1254
1255	uint32_t cbRamHoleSaved;
1256	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1257
1258	uint64_t cbRamSaved;
1259	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1260	AssertRCReturn(rc, rc);
1261
1262	if ( cbRamHoleCfg != cbRamHoleSaved
1263	\|\| cbRamCfg != cbRamSaved)
1264	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1265	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1266	return VINF_SUCCESS;
1267	}
1268
1269	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1270
1271	/**
1272	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1273	* info with it.
1274	*
1275	* @param pVM The cross context VM structure.
1276	* @param pCur The current RAM range.
1277	* @param paLSPages The current array of live save page tracking
1278	* structures.
1279	* @param iPage The page index.
1280	*/
1281	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1282	{
1283	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1284	PGMPAGEMAPLOCK PgMpLck;
1285	void const *pvPage;
1286	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage, &PgMpLck);
1287	if (RT_SUCCESS(rc))
1288	{
1289	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1290	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1291	}
1292	else
1293	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1294	}
1295
1296
1297	/**
1298	* Verifies the CRC-32 for a page given it's raw bits.
1299	*
1300	* @param pvPage The page bits.
1301	* @param pCur The current RAM range.
1302	* @param paLSPages The current array of live save page tracking
1303	* structures.
1304	* @param iPage The page index.
1305	*/
1306	static void pgmR3StateVerifyCrc32ForPage(void const pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char pszWhere)
1307	{
1308	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1309	{
1310	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1311	Assert( ( !PGM_PAGE_IS_ZERO(&pCur->aPages[iPage])
1312	&& !PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]))
1313	\|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1314	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1315	("%08x != %08x for %RGp %R[pgmpage] %s\n", paLSPages[iPage].u32Crc, u32Crc,
1316	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage], pszWhere));
1317	}
1318	}
1319
1320
1321	/**
1322	* Verifies the CRC-32 for a RAM page.
1323	*
1324	* @param pVM The cross context VM structure.
1325	* @param pCur The current RAM range.
1326	* @param paLSPages The current array of live save page tracking
1327	* structures.
1328	* @param iPage The page index.
1329	*/
1330	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char *pszWhere)
1331	{
1332	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1333	{
1334	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1335	PGMPAGEMAPLOCK PgMpLck;
1336	void const *pvPage;
1337	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage, &PgMpLck);
1338	if (RT_SUCCESS(rc))
1339	{
1340	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage, pszWhere);
1341	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1342	}
1343	}
1344	}
1345
1346	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1347
1348	/**
1349	* Scan for RAM page modifications and reprotect them.
1350	*
1351	* @param pVM The cross context VM structure.
1352	* @param fFinalPass Whether this is the final pass or not.
1353	*/
1354	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1355	{
1356	/*
1357	* The RAM.
1358	*/
1359	RTGCPHYS GCPhysCur = 0;
1360	PPGMRAMRANGE pCur;
1361	pgmLock(pVM);
1362	do
1363	{
1364	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1365	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1366	{
1367	if ( pCur->GCPhysLast > GCPhysCur
1368	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1369	{
1370	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1371	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1372	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1373	GCPhysCur = 0;
1374	for (; iPage < cPages; iPage++)
1375	{
1376	/* Do yield first. */
1377	if ( !fFinalPass
1378	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1379	&& (iPage & 0x7ff) == 0x100
1380	#endif
1381	&& PDMR3CritSectYield(pVM, &pVM->pgm.s.CritSectX)
1382	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1383	{
1384	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1385	break; /* restart */
1386	}
1387
1388	/* Skip already ignored pages. */
1389	if (paLSPages[iPage].fIgnore)
1390	continue;
1391
1392	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1393	{
1394	/*
1395	* A RAM page.
1396	*/
1397	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1398	{
1399	case PGM_PAGE_STATE_ALLOCATED:
1400	/** @todo Optimize this: Don't always re-enable write
1401	* monitoring if the page is known to be very busy. */
1402	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1403	{
1404	AssertMsg(paLSPages[iPage].fWriteMonitored,
1405	("%RGp %R[pgmpage]\n", pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1406	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]);
1407	Assert(pVM->pgm.s.cWrittenToPages > 0);
1408	pVM->pgm.s.cWrittenToPages--;
1409	}
1410	else
1411	{
1412	AssertMsg(!paLSPages[iPage].fWriteMonitored,
1413	("%RGp %R[pgmpage]\n", pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1414	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1415	}
1416
1417	if (!paLSPages[iPage].fDirty)
1418	{
1419	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1420	if (paLSPages[iPage].fZero)
1421	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1422	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1423	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1424	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1425	}
1426
1427	pgmPhysPageWriteMonitor(pVM, &pCur->aPages[iPage],
1428	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1429	paLSPages[iPage].fWriteMonitored = 1;
1430	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1431	paLSPages[iPage].fDirty = 1;
1432	paLSPages[iPage].fZero = 0;
1433	paLSPages[iPage].fShared = 0;
1434	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1435	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1436	#endif
1437	break;
1438
1439	case PGM_PAGE_STATE_WRITE_MONITORED:
1440	Assert(paLSPages[iPage].fWriteMonitored);
1441	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1442	{
1443	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1444	if (paLSPages[iPage].fWriteMonitoredJustNow)
1445	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1446	else
1447	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "scan");
1448	#endif
1449	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1450	}
1451	else
1452	{
1453	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1454	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1455	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1456	#endif
1457	if (!paLSPages[iPage].fDirty)
1458	{
1459	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1460	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1461	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1462	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1463	}
1464	}
1465	break;
1466
1467	case PGM_PAGE_STATE_ZERO:
1468	case PGM_PAGE_STATE_BALLOONED:
1469	if (!paLSPages[iPage].fZero)
1470	{
1471	if (!paLSPages[iPage].fDirty)
1472	{
1473	paLSPages[iPage].fDirty = 1;
1474	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1475	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1476	}
1477	paLSPages[iPage].fZero = 1;
1478	paLSPages[iPage].fShared = 0;
1479	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1480	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1481	#endif
1482	}
1483	break;
1484
1485	case PGM_PAGE_STATE_SHARED:
1486	if (!paLSPages[iPage].fShared)
1487	{
1488	if (!paLSPages[iPage].fDirty)
1489	{
1490	paLSPages[iPage].fDirty = 1;
1491	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1492	if (paLSPages[iPage].fZero)
1493	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1494	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1495	}
1496	paLSPages[iPage].fZero = 0;
1497	paLSPages[iPage].fShared = 1;
1498	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1499	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1500	#endif
1501	}
1502	break;
1503	}
1504	}
1505	else
1506	{
1507	/*
1508	* All other types => Ignore the page.
1509	*/
1510	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1511	paLSPages[iPage].fIgnore = 1;
1512	if (paLSPages[iPage].fWriteMonitored)
1513	{
1514	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1515	* pages! */
1516	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1517	{
1518	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1519	PGM_PAGE_SET_STATE(pVM, &pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1520	Assert(pVM->pgm.s.cMonitoredPages > 0);
1521	pVM->pgm.s.cMonitoredPages--;
1522	}
1523	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1524	{
1525	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]);
1526	Assert(pVM->pgm.s.cWrittenToPages > 0);
1527	pVM->pgm.s.cWrittenToPages--;
1528	}
1529	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1530	}
1531
1532	/** @todo the counting doesn't quite work out here. fix later? */
1533	if (paLSPages[iPage].fDirty)
1534	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1535	else
1536	{
1537	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1538	if (paLSPages[iPage].fZero)
1539	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1540	}
1541	pVM->pgm.s.LiveSave.cIgnoredPages++;
1542	}
1543	} /* for each page in range */
1544
1545	if (GCPhysCur != 0)
1546	break; /* Yield + ramrange change */
1547	GCPhysCur = pCur->GCPhysLast;
1548	}
1549	} /* for each range */
1550	} while (pCur);
1551	pgmUnlock(pVM);
1552	}
1553
1554
1555	/**
1556	* Save quiescent RAM pages.
1557	*
1558	* @returns VBox status code.
1559	* @param pVM The cross context VM structure.
1560	* @param pSSM The SSM handle.
1561	* @param fLiveSave Whether it's a live save or not.
1562	* @param uPass The pass number.
1563	*/
1564	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1565	{
1566	NOREF(fLiveSave);
1567
1568	/*
1569	* The RAM.
1570	*/
1571	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1572	RTGCPHYS GCPhysCur = 0;
1573	PPGMRAMRANGE pCur;
1574
1575	pgmLock(pVM);
1576	do
1577	{
1578	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1579	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1580	{
1581	if ( pCur->GCPhysLast > GCPhysCur
1582	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1583	{
1584	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1585	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1586	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1587	GCPhysCur = 0;
1588	for (; iPage < cPages; iPage++)
1589	{
1590	/* Do yield first. */
1591	if ( uPass != SSM_PASS_FINAL
1592	&& (iPage & 0x7ff) == 0x100
1593	&& PDMR3CritSectYield(pVM, &pVM->pgm.s.CritSectX)
1594	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1595	{
1596	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1597	break; /* restart */
1598	}
1599
1600	PPGMPAGE pCurPage = &pCur->aPages[iPage];
1601
1602	/*
1603	* Only save pages that haven't changed since last scan and are dirty.
1604	*/
1605	if ( uPass != SSM_PASS_FINAL
1606	&& paLSPages)
1607	{
1608	if (!paLSPages[iPage].fDirty)
1609	continue;
1610	if (paLSPages[iPage].fWriteMonitoredJustNow)
1611	continue;
1612	if (paLSPages[iPage].fIgnore)
1613	continue;
1614	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM) /* in case of recent remappings */
1615	continue;
1616	if ( PGM_PAGE_GET_STATE(pCurPage)
1617	!= ( paLSPages[iPage].fZero
1618	? PGM_PAGE_STATE_ZERO
1619	: paLSPages[iPage].fShared
1620	? PGM_PAGE_STATE_SHARED
1621	: PGM_PAGE_STATE_WRITE_MONITORED))
1622	continue;
1623	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1624	continue;
1625	}
1626	else
1627	{
1628	if ( paLSPages
1629	&& !paLSPages[iPage].fDirty
1630	&& !paLSPages[iPage].fIgnore)
1631	{
1632	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1633	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1634	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#1");
1635	#endif
1636	continue;
1637	}
1638	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1639	continue;
1640	}
1641
1642	/*
1643	* Do the saving outside the PGM critsect since SSM may block on I/O.
1644	*/
1645	int rc;
1646	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1647	bool fZero = PGM_PAGE_IS_ZERO(pCurPage);
1648	bool fBallooned = PGM_PAGE_IS_BALLOONED(pCurPage);
1649	bool fSkipped = false;
1650
1651	if (!fZero && !fBallooned)
1652	{
1653	/*
1654	* Copy the page and then save it outside the lock (since any
1655	* SSM call may block).
1656	*/
1657	uint8_t abPage[PAGE_SIZE];
1658	PGMPAGEMAPLOCK PgMpLck;
1659	void const *pvPage;
1660	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pCurPage, GCPhys, &pvPage, &PgMpLck);
1661	if (RT_SUCCESS(rc))
1662	{
1663	memcpy(abPage, pvPage, PAGE_SIZE);
1664	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1665	if (paLSPages)
1666	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage, "save#3");
1667	#endif
1668	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1669	}
1670	pgmUnlock(pVM);
1671	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1672
1673	/* Try save some memory when restoring. */
1674	if (!ASMMemIsZeroPage(pvPage))
1675	{
1676	if (GCPhys == GCPhysLast + PAGE_SIZE)
1677	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1678	else
1679	{
1680	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1681	SSMR3PutGCPhys(pSSM, GCPhys);
1682	}
1683	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1684	}
1685	else
1686	{
1687	if (GCPhys == GCPhysLast + PAGE_SIZE)
1688	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1689	else
1690	{
1691	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1692	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1693	}
1694	}
1695	}
1696	else
1697	{
1698	/*
1699	* Dirty zero or ballooned page.
1700	*/
1701	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1702	if (paLSPages)
1703	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#2");
1704	#endif
1705	pgmUnlock(pVM);
1706
1707	uint8_t u8RecType = fBallooned ? PGM_STATE_REC_RAM_BALLOONED : PGM_STATE_REC_RAM_ZERO;
1708	if (GCPhys == GCPhysLast + PAGE_SIZE)
1709	rc = SSMR3PutU8(pSSM, u8RecType);
1710	else
1711	{
1712	SSMR3PutU8(pSSM, u8RecType \| PGM_STATE_REC_FLAG_ADDR);
1713	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1714	}
1715	}
1716	if (RT_FAILURE(rc))
1717	return rc;
1718
1719	pgmLock(pVM);
1720	if (!fSkipped)
1721	GCPhysLast = GCPhys;
1722	if (paLSPages)
1723	{
1724	paLSPages[iPage].fDirty = 0;
1725	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1726	if (fZero)
1727	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1728	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1729	pVM->pgm.s.LiveSave.cSavedPages++;
1730	}
1731	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1732	{
1733	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1734	break; /* restart */
1735	}
1736
1737	} /* for each page in range */
1738
1739	if (GCPhysCur != 0)
1740	break; /* Yield + ramrange change */
1741	GCPhysCur = pCur->GCPhysLast;
1742	}
1743	} /* for each range */
1744	} while (pCur);
1745
1746	pgmUnlock(pVM);
1747
1748	return VINF_SUCCESS;
1749	}
1750
1751
1752	/**
1753	* Cleans up RAM pages after a live save.
1754	*
1755	* @param pVM The cross context VM structure.
1756	*/
1757	static void pgmR3DoneRamPages(PVM pVM)
1758	{
1759	/*
1760	* Free the tracking arrays and disable write monitoring.
1761	*
1762	* Play nice with the PGM lock in case we're called while the VM is still
1763	* running. This means we have to delay the freeing since we wish to use
1764	* paLSPages as an indicator of which RAM ranges which we need to scan for
1765	* write monitored pages.
1766	*/
1767	void *pvToFree = NULL;
1768	PPGMRAMRANGE pCur;
1769	uint32_t cMonitoredPages = 0;
1770	pgmLock(pVM);
1771	do
1772	{
1773	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1774	{
1775	if (pCur->paLSPages)
1776	{
1777	if (pvToFree)
1778	{
1779	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1780	pgmUnlock(pVM);
1781	MMR3HeapFree(pvToFree);
1782	pvToFree = NULL;
1783	pgmLock(pVM);
1784	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1785	break; /* start over again. */
1786	}
1787
1788	pvToFree = pCur->paLSPages;
1789	pCur->paLSPages = NULL;
1790
1791	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1792	while (iPage--)
1793	{
1794	PPGMPAGE pPage = &pCur->aPages[iPage];
1795	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
1796	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1797	{
1798	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
1799	cMonitoredPages++;
1800	}
1801	}
1802	}
1803	}
1804	} while (pCur);
1805
1806	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1807	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1808	pVM->pgm.s.cMonitoredPages = 0;
1809	else
1810	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1811
1812	pgmUnlock(pVM);
1813
1814	MMR3HeapFree(pvToFree);
1815	pvToFree = NULL;
1816	}
1817
1818
1819	/**
1820	* @callback_method_impl{FNSSMINTLIVEEXEC}
1821	*/
1822	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1823	{
1824	int rc;
1825
1826	/*
1827	* Save the MMIO2 and ROM range IDs in pass 0.
1828	*/
1829	if (uPass == 0)
1830	{
1831	rc = pgmR3SaveRamConfig(pVM, pSSM);
1832	if (RT_FAILURE(rc))
1833	return rc;
1834	rc = pgmR3SaveRomRanges(pVM, pSSM);
1835	if (RT_FAILURE(rc))
1836	return rc;
1837	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1838	if (RT_FAILURE(rc))
1839	return rc;
1840	}
1841	/*
1842	* Reset the page-per-second estimate to avoid inflation by the initial
1843	* load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1844	*/
1845	else if (uPass == 7)
1846	{
1847	pVM->pgm.s.LiveSave.cSavedPages = 0;
1848	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1849	}
1850
1851	/*
1852	* Do the scanning.
1853	*/
1854	pgmR3ScanRomPages(pVM);
1855	pgmR3ScanMmio2Pages(pVM, uPass);
1856	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1857	pgmR3PoolClearAll(pVM, true /fFlushRemTlb/); /** @todo this could perhaps be optimized a bit. */
1858
1859	/*
1860	* Save the pages.
1861	*/
1862	if (uPass == 0)
1863	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1864	else
1865	rc = VINF_SUCCESS;
1866	if (RT_SUCCESS(rc))
1867	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1868	if (RT_SUCCESS(rc))
1869	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1870	if (RT_SUCCESS(rc))
1871	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1872	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes care of it.) */
1873
1874	return rc;
1875	}
1876
1877
1878	/**
1879	* @callback_method_impl{FNSSMINTLIVEVOTE}
1880	*/
1881	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1882	{
1883	/*
1884	* Update and calculate parameters used in the decision making.
1885	*/
1886	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1887
1888	/* update history. */
1889	pgmLock(pVM);
1890	uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1891	pgmUnlock(pVM);
1892	uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1893	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1894	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1895	+ cWrittenToPages;
1896	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1897	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1898	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1899
1900	/* calc shortterm average (4 passes). */
1901	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1902	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1903	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1904	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1905	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1906	uint32_t const cDirtyPagesShort = cTotal / 4;
1907	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1908
1909	/* calc longterm average. */
1910	cTotal = 0;
1911	if (uPass < cHistoryEntries)
1912	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1913	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1914	else
1915	for (i = 0; i < cHistoryEntries; i++)
1916	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1917	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1918	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1919
1920	/* estimate the speed */
1921	uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1922	uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1923	/ ((long double)cNsElapsed / 1000000000.0) );
1924	pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1925
1926	/*
1927	* Try make a decision.
1928	*/
1929	if ( cDirtyPagesShort <= cDirtyPagesLong
1930	&& ( cDirtyNow <= cDirtyPagesShort
1931	\|\| cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1932	)
1933	)
1934	{
1935	if (uPass > 10)
1936	{
1937	uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1938	uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1939	uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1940	if (cMsMaxDowntime < 32)
1941	cMsMaxDowntime = 32;
1942	if ( ( cMsLeftLong <= cMsMaxDowntime
1943	&& cMsLeftShort < cMsMaxDowntime)
1944	\|\| cMsLeftShort < cMsMaxDowntime / 2
1945	)
1946	{
1947	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u\|%ums cDirtyPagesLong=%u\|%ums cMsMaxDowntime=%u\n",
1948	uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1949	return VINF_SUCCESS;
1950	}
1951	}
1952	else
1953	{
1954	if ( ( cDirtyPagesShort <= 128
1955	&& cDirtyPagesLong <= 1024)
1956	\|\| cDirtyPagesLong <= 256
1957	)
1958	{
1959	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1960	return VINF_SUCCESS;
1961	}
1962	}
1963	}
1964
1965	/*
1966	* Come up with a completion percentage. Currently this is a simple
1967	* dirty page (long term) vs. total pages ratio + some pass trickery.
1968	*/
1969	unsigned uPctDirty = (unsigned)( (long double)cDirtyPagesLong
1970	/ (pVM->pgm.s.cAllPages - pVM->pgm.s.LiveSave.cIgnoredPages - pVM->pgm.s.cZeroPages) );
1971	if (uPctDirty <= 100)
1972	SSMR3HandleReportLivePercent(pSSM, RT_MIN(100 - uPctDirty, uPass * 2));
1973	else
1974	AssertMsgFailed(("uPctDirty=%u cDirtyPagesLong=%#x cAllPages=%#x cIgnoredPages=%#x cZeroPages=%#x\n",
1975	uPctDirty, cDirtyPagesLong, pVM->pgm.s.cAllPages, pVM->pgm.s.LiveSave.cIgnoredPages, pVM->pgm.s.cZeroPages));
1976
1977	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1978	}
1979
1980
1981	/**
1982	* @callback_method_impl{FNSSMINTLIVEPREP}
1983	*
1984	* This will attempt to allocate and initialize the tracking structures. It
1985	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1986	* pgmR3SaveDone will do the cleanups.
1987	*/
1988	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1989	{
1990	/*
1991	* Indicate that we will be using the write monitoring.
1992	*/
1993	pgmLock(pVM);
1994	/** @todo find a way of mediating this when more users are added. */
1995	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1996	{
1997	pgmUnlock(pVM);
1998	AssertLogRelFailedReturn(VERR_PGM_WRITE_MONITOR_ENGAGED);
1999	}
2000	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
2001	pgmUnlock(pVM);
2002
2003	/*
2004	* Initialize the statistics.
2005	*/
2006	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
2007	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
2008	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
2009	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
2010	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
2011	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
2012	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
2013	pVM->pgm.s.LiveSave.fActive = true;
2014	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
2015	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
2016	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
2017	pVM->pgm.s.LiveSave.cSavedPages = 0;
2018	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
2019	pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
2020
2021	/*
2022	* Per page type.
2023	*/
2024	int rc = pgmR3PrepRomPages(pVM);
2025	if (RT_SUCCESS(rc))
2026	rc = pgmR3PrepMmio2Pages(pVM);
2027	if (RT_SUCCESS(rc))
2028	rc = pgmR3PrepRamPages(pVM);
2029
2030	NOREF(pSSM);
2031	return rc;
2032	}
2033
2034
2035	/**
2036	* @callback_method_impl{FNSSMINTSAVEEXEC}
2037	*/
2038	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2039	{
2040	int rc = VINF_SUCCESS;
2041	PPGM pPGM = &pVM->pgm.s;
2042
2043	/*
2044	* Lock PGM and set the no-more-writes indicator.
2045	*/
2046	pgmLock(pVM);
2047	pVM->pgm.s.fNoMorePhysWrites = true;
2048
2049	/*
2050	* Save basic data (required / unaffected by relocation).
2051	*/
2052	bool const fMappingsFixed = pVM->pgm.s.fMappingsFixed;
2053	pVM->pgm.s.fMappingsFixed \|= pVM->pgm.s.fMappingsFixedRestored;
2054	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2055	pVM->pgm.s.fMappingsFixed = fMappingsFixed;
2056
2057	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2058	rc = SSMR3PutStruct(pSSM, &pVM->apCpusR3[idCpu]->pgm.s, &s_aPGMCpuFields[0]);
2059
2060	/*
2061	* Save the (remainder of the) memory.
2062	*/
2063	if (RT_SUCCESS(rc))
2064	{
2065	if (pVM->pgm.s.LiveSave.fActive)
2066	{
2067	pgmR3ScanRomPages(pVM);
2068	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
2069	pgmR3ScanRamPages(pVM, true /fFinalPass/);
2070
2071	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
2072	if (RT_SUCCESS(rc))
2073	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2074	if (RT_SUCCESS(rc))
2075	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2076	}
2077	else
2078	{
2079	rc = pgmR3SaveRamConfig(pVM, pSSM);
2080	if (RT_SUCCESS(rc))
2081	rc = pgmR3SaveRomRanges(pVM, pSSM);
2082	if (RT_SUCCESS(rc))
2083	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2084	if (RT_SUCCESS(rc))
2085	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
2086	if (RT_SUCCESS(rc))
2087	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
2088	if (RT_SUCCESS(rc))
2089	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2090	if (RT_SUCCESS(rc))
2091	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2092	}
2093	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2094	}
2095
2096	pgmUnlock(pVM);
2097	return rc;
2098	}
2099
2100
2101	/**
2102	* @callback_method_impl{FNSSMINTSAVEDONE}
2103	*/
2104	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2105	{
2106	/*
2107	* Do per page type cleanups first.
2108	*/
2109	if (pVM->pgm.s.LiveSave.fActive)
2110	{
2111	pgmR3DoneRomPages(pVM);
2112	pgmR3DoneMmio2Pages(pVM);
2113	pgmR3DoneRamPages(pVM);
2114	}
2115
2116	/*
2117	* Clear the live save indicator and disengage write monitoring.
2118	*/
2119	pgmLock(pVM);
2120	pVM->pgm.s.LiveSave.fActive = false;
2121	/** @todo this is blindly assuming that we're the only user of write
2122	* monitoring. Fix this when more users are added. */
2123	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2124	pgmUnlock(pVM);
2125
2126	NOREF(pSSM);
2127	return VINF_SUCCESS;
2128	}
2129
2130
2131	/**
2132	* @callback_method_impl{FNSSMINTLOADPREP}
2133	*/
2134	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2135	{
2136	/*
2137	* Call the reset function to make sure all the memory is cleared.
2138	*/
2139	PGMR3Reset(pVM);
2140	pVM->pgm.s.LiveSave.fActive = false;
2141	NOREF(pSSM);
2142	return VINF_SUCCESS;
2143	}
2144
2145
2146	/**
2147	* Load an ignored page.
2148	*
2149	* @returns VBox status code.
2150	* @param pSSM The saved state handle.
2151	*/
2152	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2153	{
2154	uint8_t abPage[PAGE_SIZE];
2155	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2156	}
2157
2158
2159	/**
2160	* Compares a page with an old save type value.
2161	*
2162	* @returns true if equal, false if not.
2163	* @param pPage The page to compare.
2164	* @param uOldType The old type value from the saved state.
2165	*/
2166	DECLINLINE(bool) pgmR3CompareNewAndOldPageTypes(PPGMPAGE pPage, uint8_t uOldType)
2167	{
2168	uint8_t uOldPageType;
2169	switch (PGM_PAGE_GET_TYPE(pPage))
2170	{
2171	case PGMPAGETYPE_INVALID: uOldPageType = PGMPAGETYPE_OLD_INVALID; break;
2172	case PGMPAGETYPE_RAM: uOldPageType = PGMPAGETYPE_OLD_RAM; break;
2173	case PGMPAGETYPE_MMIO2: uOldPageType = PGMPAGETYPE_OLD_MMIO2; break;
2174	case PGMPAGETYPE_MMIO2_ALIAS_MMIO: uOldPageType = PGMPAGETYPE_OLD_MMIO2_ALIAS_MMIO; break;
2175	case PGMPAGETYPE_ROM_SHADOW: uOldPageType = PGMPAGETYPE_OLD_ROM_SHADOW; break;
2176	case PGMPAGETYPE_ROM: uOldPageType = PGMPAGETYPE_OLD_ROM; break;
2177	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: RT_FALL_THRU();
2178	case PGMPAGETYPE_MMIO: uOldPageType = PGMPAGETYPE_OLD_MMIO; break;
2179	default:
2180	AssertFailed();
2181	uOldPageType = PGMPAGETYPE_OLD_INVALID;
2182	break;
2183	}
2184	return uOldPageType == uOldType;
2185	}
2186
2187
2188	/**
2189	* Loads a page without any bits in the saved state, i.e. making sure it's
2190	* really zero.
2191	*
2192	* @returns VBox status code.
2193	* @param pVM The cross context VM structure.
2194	* @param uOldType The page type or PGMPAGETYPE_OLD_INVALID (old saved
2195	* state).
2196	* @param pPage The guest page tracking structure.
2197	* @param GCPhys The page address.
2198	* @param pRam The ram range (logging).
2199	*/
2200	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uOldType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2201	{
2202	if ( uOldType != PGMPAGETYPE_OLD_INVALID
2203	&& !pgmR3CompareNewAndOldPageTypes(pPage, uOldType))
2204	return VERR_SSM_UNEXPECTED_DATA;
2205
2206	/* I think this should be sufficient. */
2207	if ( !PGM_PAGE_IS_ZERO(pPage)
2208	&& !PGM_PAGE_IS_BALLOONED(pPage))
2209	return VERR_SSM_UNEXPECTED_DATA;
2210
2211	NOREF(pVM);
2212	NOREF(GCPhys);
2213	NOREF(pRam);
2214	return VINF_SUCCESS;
2215	}
2216
2217
2218	/**
2219	* Loads a page from the saved state.
2220	*
2221	* @returns VBox status code.
2222	* @param pVM The cross context VM structure.
2223	* @param pSSM The SSM handle.
2224	* @param uOldType The page type or PGMPAGETYPE_OLD_INVALID (old saved
2225	* state).
2226	* @param pPage The guest page tracking structure.
2227	* @param GCPhys The page address.
2228	* @param pRam The ram range (logging).
2229	*/
2230	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uOldType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2231	{
2232	/*
2233	* Match up the type, dealing with MMIO2 aliases (dropped).
2234	*/
2235	AssertLogRelMsgReturn( uOldType == PGMPAGETYPE_INVALID
2236	\|\| pgmR3CompareNewAndOldPageTypes(pPage, uOldType)
2237	/* kudge for the expanded PXE bios (r67885) - @bugref{5687}: */
2238	\|\| ( uOldType == PGMPAGETYPE_OLD_RAM
2239	&& GCPhys >= 0xed000
2240	&& GCPhys <= 0xeffff
2241	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM)
2242	,
2243	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2244	VERR_SSM_UNEXPECTED_DATA);
2245
2246	/*
2247	* Load the page.
2248	*/
2249	PGMPAGEMAPLOCK PgMpLck;
2250	void *pvPage;
2251	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage, &PgMpLck);
2252	if (RT_SUCCESS(rc))
2253	{
2254	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2255	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2256	}
2257
2258	return rc;
2259	}
2260
2261
2262	/**
2263	* Loads a page (counter part to pgmR3SavePage).
2264	*
2265	* @returns VBox status code, fully bitched errors.
2266	* @param pVM The cross context VM structure.
2267	* @param pSSM The SSM handle.
2268	* @param uOldType The page type.
2269	* @param pPage The page.
2270	* @param GCPhys The page address.
2271	* @param pRam The RAM range (for error messages).
2272	*/
2273	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uOldType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2274	{
2275	uint8_t uState;
2276	int rc = SSMR3GetU8(pSSM, &uState);
2277	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2278	if (uState == 0 /* zero */)
2279	rc = pgmR3LoadPageZeroOld(pVM, uOldType, pPage, GCPhys, pRam);
2280	else if (uState == 1)
2281	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uOldType, pPage, GCPhys, pRam);
2282	else
2283	rc = VERR_PGM_INVALID_SAVED_PAGE_STATE;
2284	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uOldType=%d GCPhys=%RGp %s rc=%Rrc\n",
2285	pPage, uState, uOldType, GCPhys, pRam->pszDesc, rc),
2286	rc);
2287	return VINF_SUCCESS;
2288	}
2289
2290
2291	/**
2292	* Loads a shadowed ROM page.
2293	*
2294	* @returns VBox status code, errors are fully bitched.
2295	* @param pVM The cross context VM structure.
2296	* @param pSSM The saved state handle.
2297	* @param pPage The page.
2298	* @param GCPhys The page address.
2299	* @param pRam The RAM range (for error messages).
2300	*/
2301	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2302	{
2303	/*
2304	* Load and set the protection first, then load the two pages, the first
2305	* one is the active the other is the passive.
2306	*/
2307	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2308	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_PGM_SAVED_ROM_PAGE_NOT_FOUND);
2309
2310	uint8_t uProt;
2311	int rc = SSMR3GetU8(pSSM, &uProt);
2312	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2313	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2314	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2315	&& enmProt < PGMROMPROT_END,
2316	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2317	VERR_SSM_UNEXPECTED_DATA);
2318
2319	if (pRomPage->enmProt != enmProt)
2320	{
2321	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2322	AssertLogRelRCReturn(rc, rc);
2323	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_PGM_SAVED_ROM_PAGE_PROT);
2324	}
2325
2326	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2327	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2328	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2329	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2330
2331	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2332	* used down the line (will the 2nd page will be written to the first
2333	* one because of a false TLB hit since the TLB is using GCPhys and
2334	* doesn't check the HCPhys of the desired page). */
2335	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2336	if (RT_SUCCESS(rc))
2337	{
2338	pPageActive = pPage;
2339	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2340	}
2341	return rc;
2342	}
2343
2344	/**
2345	* Ram range flags and bits for older versions of the saved state.
2346	*
2347	* @returns VBox status code.
2348	*
2349	* @param pVM The cross context VM structure.
2350	* @param pSSM The SSM handle.
2351	* @param uVersion The saved state version.
2352	*/
2353	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2354	{
2355	PPGM pPGM = &pVM->pgm.s;
2356
2357	/*
2358	* Ram range flags and bits.
2359	*/
2360	uint32_t i = 0;
2361	for (PPGMRAMRANGE pRam = pPGM->pRamRangesXR3; ; pRam = pRam->pNextR3, i++)
2362	{
2363	/* Check the sequence number / separator. */
2364	uint32_t u32Sep;
2365	int rc = SSMR3GetU32(pSSM, &u32Sep);
2366	if (RT_FAILURE(rc))
2367	return rc;
2368	if (u32Sep == ~0U)
2369	break;
2370	if (u32Sep != i)
2371	{
2372	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2373	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2374	}
2375	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2376
2377	/* Get the range details. */
2378	RTGCPHYS GCPhys;
2379	SSMR3GetGCPhys(pSSM, &GCPhys);
2380	RTGCPHYS GCPhysLast;
2381	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2382	RTGCPHYS cb;
2383	SSMR3GetGCPhys(pSSM, &cb);
2384	uint8_t fHaveBits;
2385	rc = SSMR3GetU8(pSSM, &fHaveBits);
2386	if (RT_FAILURE(rc))
2387	return rc;
2388	if (fHaveBits & ~1)
2389	{
2390	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2391	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2392	}
2393	size_t cchDesc = 0;
2394	char szDesc[256];
2395	szDesc[0] = '\0';
2396	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2397	{
2398	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2399	if (RT_FAILURE(rc))
2400	return rc;
2401	/* Since we've modified the description strings in r45878, only compare
2402	them if the saved state is more recent. */
2403	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2404	cchDesc = strlen(szDesc);
2405	}
2406
2407	/*
2408	* Match it up with the current range.
2409	*
2410	* Note there is a hack for dealing with the high BIOS mapping
2411	* in the old saved state format, this means we might not have
2412	* a 1:1 match on success.
2413	*/
2414	if ( ( GCPhys != pRam->GCPhys
2415	\|\| GCPhysLast != pRam->GCPhysLast
2416	\|\| cb != pRam->cb
2417	\|\| ( cchDesc
2418	&& strcmp(szDesc, pRam->pszDesc)) )
2419	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2420	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2421	\|\| GCPhys != UINT32_C(0xfff80000)
2422	\|\| GCPhysLast != UINT32_C(0xffffffff)
2423	\|\| pRam->GCPhysLast != GCPhysLast
2424	\|\| pRam->GCPhys < GCPhys
2425	\|\| !fHaveBits)
2426	)
2427	{
2428	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2429	"State : %RGp-%RGp %RGp bytes %s %s\n",
2430	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2431	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2432	/*
2433	* If we're loading a state for debugging purpose, don't make a fuss if
2434	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2435	*/
2436	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2437	\|\| GCPhys < 8 * _1M)
2438	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2439	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2440	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2441	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2442
2443	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2444	continue;
2445	}
2446
2447	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2448	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2449	{
2450	/*
2451	* Load the pages one by one.
2452	*/
2453	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2454	{
2455	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2456	PPGMPAGE pPage = &pRam->aPages[iPage];
2457	uint8_t uOldType;
2458	rc = SSMR3GetU8(pSSM, &uOldType);
2459	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2460	if (uOldType == PGMPAGETYPE_OLD_ROM_SHADOW)
2461	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2462	else
2463	rc = pgmR3LoadPageOld(pVM, pSSM, uOldType, pPage, GCPhysPage, pRam);
2464	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2465	}
2466	}
2467	else
2468	{
2469	/*
2470	* Old format.
2471	*/
2472
2473	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2474	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2475	uint32_t fFlags = 0;
2476	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2477	{
2478	uint16_t u16Flags;
2479	rc = SSMR3GetU16(pSSM, &u16Flags);
2480	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2481	fFlags \|= u16Flags;
2482	}
2483
2484	/* Load the bits */
2485	if ( !fHaveBits
2486	&& GCPhysLast < UINT32_C(0xe0000000))
2487	{
2488	/*
2489	* Dynamic chunks.
2490	*/
2491	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2492	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2493	("cPages=%#x cPagesInChunk=%#x GCPhys=%RGp %s\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2494	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2495
2496	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2497	{
2498	uint8_t fPresent;
2499	rc = SSMR3GetU8(pSSM, &fPresent);
2500	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2501	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2502	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2503	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2504
2505	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2506	{
2507	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2508	PPGMPAGE pPage = &pRam->aPages[iPage];
2509	if (fPresent)
2510	{
2511	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO
2512	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO)
2513	rc = pgmR3LoadPageToDevNullOld(pSSM);
2514	else
2515	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2516	}
2517	else
2518	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2519	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2520	}
2521	}
2522	}
2523	else if (pRam->pvR3)
2524	{
2525	/*
2526	* MMIO2.
2527	*/
2528	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2529	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2530	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2531	AssertLogRelMsgReturn(pRam->pvR3,
2532	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2533	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2534
2535	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2536	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2537	}
2538	else if (GCPhysLast < UINT32_C(0xfff80000))
2539	{
2540	/*
2541	* PCI MMIO, no pages saved.
2542	*/
2543	}
2544	else
2545	{
2546	/*
2547	* Load the 0xfff80000..0xffffffff BIOS range.
2548	* It starts with X reserved pages that we have to skip over since
2549	* the RAMRANGE create by the new code won't include those.
2550	*/
2551	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2552	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2553	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2554	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2555	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2556	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2557	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2558
2559	/* Skip wasted reserved pages before the ROM. */
2560	while (GCPhys < pRam->GCPhys)
2561	{
2562	rc = pgmR3LoadPageToDevNullOld(pSSM);
2563	GCPhys += PAGE_SIZE;
2564	}
2565
2566	/* Load the bios pages. */
2567	cPages = pRam->cb >> PAGE_SHIFT;
2568	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2569	{
2570	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2571	PPGMPAGE pPage = &pRam->aPages[iPage];
2572
2573	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2574	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2575	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2576	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2577	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2578	}
2579	}
2580	}
2581	}
2582
2583	return VINF_SUCCESS;
2584	}
2585
2586
2587	/**
2588	* Worker for pgmR3Load and pgmR3LoadLocked.
2589	*
2590	* @returns VBox status code.
2591	*
2592	* @param pVM The cross context VM structure.
2593	* @param pSSM The SSM handle.
2594	* @param uVersion The PGM saved state unit version.
2595	* @param uPass The pass number.
2596	*
2597	* @todo This needs splitting up if more record types or code twists are
2598	* added...
2599	*/
2600	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2601	{
2602	NOREF(uPass);
2603
2604	/*
2605	* Process page records until we hit the terminator.
2606	*/
2607	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2608	PPGMRAMRANGE pRamHint = NULL;
2609	uint8_t id = UINT8_MAX;
2610	uint32_t iPage = UINT32_MAX - 10;
2611	PPGMROMRANGE pRom = NULL;
2612	PPGMREGMMIO2RANGE pRegMmio = NULL;
2613
2614	/*
2615	* We batch up pages that should be freed instead of calling GMM for
2616	* each and every one of them. Note that we'll lose the pages in most
2617	* failure paths - this should probably be addressed one day.
2618	*/
2619	uint32_t cPendingPages = 0;
2620	PGMMFREEPAGESREQ pReq;
2621	int rc = GMMR3FreePagesPrepare(pVM, &pReq, 128 /* batch size */, GMMACCOUNT_BASE);
2622	AssertLogRelRCReturn(rc, rc);
2623
2624	for (;;)
2625	{
2626	/*
2627	* Get the record type and flags.
2628	*/
2629	uint8_t u8;
2630	rc = SSMR3GetU8(pSSM, &u8);
2631	if (RT_FAILURE(rc))
2632	return rc;
2633	if (u8 == PGM_STATE_REC_END)
2634	{
2635	/*
2636	* Finish off any pages pending freeing.
2637	*/
2638	if (cPendingPages)
2639	{
2640	Log(("pgmR3LoadMemory: GMMR3FreePagesPerform pVM=%p cPendingPages=%u\n", pVM, cPendingPages));
2641	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2642	AssertLogRelRCReturn(rc, rc);
2643	}
2644	GMMR3FreePagesCleanup(pReq);
2645	return VINF_SUCCESS;
2646	}
2647	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2648	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2649	{
2650	/*
2651	* RAM page.
2652	*/
2653	case PGM_STATE_REC_RAM_ZERO:
2654	case PGM_STATE_REC_RAM_RAW:
2655	case PGM_STATE_REC_RAM_BALLOONED:
2656	{
2657	/*
2658	* Get the address and resolve it into a page descriptor.
2659	*/
2660	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2661	GCPhys += PAGE_SIZE;
2662	else
2663	{
2664	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2665	if (RT_FAILURE(rc))
2666	return rc;
2667	}
2668	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2669
2670	PPGMPAGE pPage;
2671	rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, &pRamHint);
2672	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2673
2674	/*
2675	* Take action according to the record type.
2676	*/
2677	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2678	{
2679	case PGM_STATE_REC_RAM_ZERO:
2680	{
2681	if (PGM_PAGE_IS_ZERO(pPage))
2682	break;
2683
2684	/* Ballooned pages must be unmarked (live snapshot and
2685	teleportation scenarios). */
2686	if (PGM_PAGE_IS_BALLOONED(pPage))
2687	{
2688	Assert(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
2689	if (uVersion == PGM_SAVED_STATE_VERSION_BALLOON_BROKEN)
2690	break;
2691	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2692	break;
2693	}
2694
2695	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_PGM_UNEXPECTED_PAGE_STATE);
2696
2697	/* If this is a ROM page, we must clear it and not try to
2698	* free it. Ditto if the VM is using RamPreAlloc (see
2699	* @bugref{6318}). */
2700	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM
2701	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM_SHADOW
2702	\|\| pVM->pgm.s.fRamPreAlloc)
2703	{
2704	PGMPAGEMAPLOCK PgMpLck;
2705	void *pvDstPage;
2706	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage, &PgMpLck);
2707	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2708
2709	ASMMemZeroPage(pvDstPage);
2710	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2711	}
2712	/* Free it only if it's not part of a previously
2713	allocated large page (no need to clear the page). */
2714	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
2715	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2716	{
2717	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys, (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
2718	AssertRCReturn(rc, rc);
2719	}
2720	/** @todo handle large pages (see @bugref{5545}) */
2721	break;
2722	}
2723
2724	case PGM_STATE_REC_RAM_BALLOONED:
2725	{
2726	Assert(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
2727	if (PGM_PAGE_IS_BALLOONED(pPage))
2728	break;
2729
2730	/* We don't map ballooned pages in our shadow page tables, let's
2731	just free it if allocated and mark as ballooned. See @bugref{5515}. */
2732	if (PGM_PAGE_IS_ALLOCATED(pPage))
2733	{
2734	/** @todo handle large pages + ballooning when it works. (see @bugref{5515},
2735	* @bugref{5545}). */
2736	AssertLogRelMsgReturn( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
2737	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED,
2738	("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_PGM_LOAD_UNEXPECTED_PAGE_TYPE);
2739
2740	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys, (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
2741	AssertRCReturn(rc, rc);
2742	}
2743	Assert(PGM_PAGE_IS_ZERO(pPage));
2744	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
2745	break;
2746	}
2747
2748	case PGM_STATE_REC_RAM_RAW:
2749	{
2750	PGMPAGEMAPLOCK PgMpLck;
2751	void *pvDstPage;
2752	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage, &PgMpLck);
2753	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2754	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2755	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2756	if (RT_FAILURE(rc))
2757	return rc;
2758	break;
2759	}
2760
2761	default:
2762	AssertMsgFailedReturn(("%#x\n", u8), VERR_PGM_SAVED_REC_TYPE);
2763	}
2764	id = UINT8_MAX;
2765	break;
2766	}
2767
2768	/*
2769	* MMIO2 page.
2770	*/
2771	case PGM_STATE_REC_MMIO2_RAW:
2772	case PGM_STATE_REC_MMIO2_ZERO:
2773	{
2774	/*
2775	* Get the ID + page number and resolved that into a MMIO2 page.
2776	*/
2777	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2778	iPage++;
2779	else
2780	{
2781	SSMR3GetU8(pSSM, &id);
2782	rc = SSMR3GetU32(pSSM, &iPage);
2783	if (RT_FAILURE(rc))
2784	return rc;
2785	}
2786	if ( !pRegMmio
2787	\|\| pRegMmio->idSavedState != id)
2788	{
2789	for (pRegMmio = pVM->pgm.s.pRegMmioRangesR3; pRegMmio; pRegMmio = pRegMmio->pNextR3)
2790	if ( pRegMmio->idSavedState == id
2791	&& (pRegMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2))
2792	break;
2793	AssertLogRelMsgReturn(pRegMmio, ("id=%#u iPage=%#x\n", id, iPage), VERR_PGM_SAVED_MMIO2_RANGE_NOT_FOUND);
2794	}
2795	AssertLogRelMsgReturn(iPage < (pRegMmio->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRegMmio->RamRange.cb, pRegMmio->RamRange.pszDesc), VERR_PGM_SAVED_MMIO2_PAGE_NOT_FOUND);
2796	void pvDstPage = (uint8_t )pRegMmio->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2797
2798	/*
2799	* Load the page bits.
2800	*/
2801	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2802	ASMMemZeroPage(pvDstPage);
2803	else
2804	{
2805	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2806	if (RT_FAILURE(rc))
2807	return rc;
2808	}
2809	GCPhys = NIL_RTGCPHYS;
2810	break;
2811	}
2812
2813	/*
2814	* ROM pages.
2815	*/
2816	case PGM_STATE_REC_ROM_VIRGIN:
2817	case PGM_STATE_REC_ROM_SHW_RAW:
2818	case PGM_STATE_REC_ROM_SHW_ZERO:
2819	case PGM_STATE_REC_ROM_PROT:
2820	{
2821	/*
2822	* Get the ID + page number and resolved that into a ROM page descriptor.
2823	*/
2824	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2825	iPage++;
2826	else
2827	{
2828	SSMR3GetU8(pSSM, &id);
2829	rc = SSMR3GetU32(pSSM, &iPage);
2830	if (RT_FAILURE(rc))
2831	return rc;
2832	}
2833	if ( !pRom
2834	\|\| pRom->idSavedState != id)
2835	{
2836	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2837	if (pRom->idSavedState == id)
2838	break;
2839	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_PGM_SAVED_ROM_RANGE_NOT_FOUND);
2840	}
2841	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_PGM_SAVED_ROM_PAGE_NOT_FOUND);
2842	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2843	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2844
2845	/*
2846	* Get and set the protection.
2847	*/
2848	uint8_t u8Prot;
2849	rc = SSMR3GetU8(pSSM, &u8Prot);
2850	if (RT_FAILURE(rc))
2851	return rc;
2852	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2853	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_PGM_SAVED_ROM_PAGE_PROT);
2854
2855	if (enmProt != pRomPage->enmProt)
2856	{
2857	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2858	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2859	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2860	GCPhys, enmProt, pRom->pszDesc);
2861	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2862	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2863	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_PGM_SAVED_ROM_PAGE_PROT);
2864	}
2865	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2866	break; /* done */
2867
2868	/*
2869	* Get the right page descriptor.
2870	*/
2871	PPGMPAGE pRealPage;
2872	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2873	{
2874	case PGM_STATE_REC_ROM_VIRGIN:
2875	if (!PGMROMPROT_IS_ROM(enmProt))
2876	pRealPage = &pRomPage->Virgin;
2877	else
2878	pRealPage = NULL;
2879	break;
2880
2881	case PGM_STATE_REC_ROM_SHW_RAW:
2882	case PGM_STATE_REC_ROM_SHW_ZERO:
2883	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2884	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2885	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2886	GCPhys, enmProt, pRom->pszDesc);
2887	if (PGMROMPROT_IS_ROM(enmProt))
2888	pRealPage = &pRomPage->Shadow;
2889	else
2890	pRealPage = NULL;
2891	break;
2892
2893	default: AssertLogRelFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE); /* shut up gcc */
2894	}
2895	if (!pRealPage)
2896	{
2897	rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pRealPage, &pRamHint);
2898	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2899	}
2900
2901	/*
2902	* Make it writable and map it (if necessary).
2903	*/
2904	void *pvDstPage = NULL;
2905	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2906	{
2907	case PGM_STATE_REC_ROM_SHW_ZERO:
2908	if ( PGM_PAGE_IS_ZERO(pRealPage)
2909	\|\| PGM_PAGE_IS_BALLOONED(pRealPage))
2910	break;
2911	/** @todo implement zero page replacing. */
2912	RT_FALL_THRU();
2913	case PGM_STATE_REC_ROM_VIRGIN:
2914	case PGM_STATE_REC_ROM_SHW_RAW:
2915	{
2916	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2917	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2918	break;
2919	}
2920	}
2921
2922	/*
2923	* Load the bits.
2924	*/
2925	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2926	{
2927	case PGM_STATE_REC_ROM_SHW_ZERO:
2928	if (pvDstPage)
2929	ASMMemZeroPage(pvDstPage);
2930	break;
2931
2932	case PGM_STATE_REC_ROM_VIRGIN:
2933	case PGM_STATE_REC_ROM_SHW_RAW:
2934	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2935	if (RT_FAILURE(rc))
2936	return rc;
2937	break;
2938	}
2939	GCPhys = NIL_RTGCPHYS;
2940	break;
2941	}
2942
2943	/*
2944	* Unknown type.
2945	*/
2946	default:
2947	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_PGM_SAVED_REC_TYPE);
2948	}
2949	} /* forever */
2950	}
2951
2952
2953	/**
2954	* Worker for pgmR3Load.
2955	*
2956	* @returns VBox status code.
2957	*
2958	* @param pVM The cross context VM structure.
2959	* @param pSSM The SSM handle.
2960	* @param uVersion The saved state version.
2961	*/
2962	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2963	{
2964	PPGM pPGM = &pVM->pgm.s;
2965	int rc;
2966	uint32_t u32Sep;
2967
2968	/*
2969	* Load basic data (required / unaffected by relocation).
2970	*/
2971	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2972	{
2973	if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2974	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2975	else
2976	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFieldsPreBalloon[0]);
2977
2978	AssertLogRelRCReturn(rc, rc);
2979
2980	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2981	{
2982	if (uVersion <= PGM_SAVED_STATE_VERSION_PRE_PAE)
2983	rc = SSMR3GetStruct(pSSM, &pVM->apCpusR3[i]->pgm.s, &s_aPGMCpuFieldsPrePae[0]);
2984	else
2985	rc = SSMR3GetStruct(pSSM, &pVM->apCpusR3[i]->pgm.s, &s_aPGMCpuFields[0]);
2986	AssertLogRelRCReturn(rc, rc);
2987	}
2988	}
2989	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2990	{
2991	AssertRelease(pVM->cCpus == 1);
2992
2993	PGMOLD pgmOld;
2994	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2995	AssertLogRelRCReturn(rc, rc);
2996
2997	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2998	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2999	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
3000
3001	PVMCPU pVCpu0 = pVM->apCpusR3[0];
3002	pVCpu0->pgm.s.fA20Enabled = pgmOld.fA20Enabled;
3003	pVCpu0->pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
3004	pVCpu0->pgm.s.enmGuestMode = pgmOld.enmGuestMode;
3005	}
3006	else
3007	{
3008	AssertRelease(pVM->cCpus == 1);
3009
3010	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
3011	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
3012	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
3013
3014	uint32_t cbRamSizeIgnored;
3015	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
3016	if (RT_FAILURE(rc))
3017	return rc;
3018	PVMCPU pVCpu0 = pVM->apCpusR3[0];
3019	SSMR3GetGCPhys(pSSM, &pVCpu0->pgm.s.GCPhysA20Mask);
3020
3021	uint32_t u32 = 0;
3022	SSMR3GetUInt(pSSM, &u32);
3023	pVCpu0->pgm.s.fA20Enabled = !!u32;
3024	SSMR3GetUInt(pSSM, &pVCpu0->pgm.s.fSyncFlags);
3025	RTUINT uGuestMode;
3026	SSMR3GetUInt(pSSM, &uGuestMode);
3027	pVCpu0->pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
3028
3029	/* check separator. */
3030	SSMR3GetU32(pSSM, &u32Sep);
3031	if (RT_FAILURE(rc))
3032	return rc;
3033	if (u32Sep != (uint32_t)~0)
3034	{
3035	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
3036	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3037	}
3038	}
3039
3040	/*
3041	* Fix the A20 mask.
3042	*/
3043	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3044	{
3045	PVMCPU pVCpu = pVM->apCpusR3[i];
3046	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
3047	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
3048	}
3049
3050	/*
3051	* The guest mappings - skipped now, see re-fixation in the caller.
3052	*/
3053	if (uVersion <= PGM_SAVED_STATE_VERSION_PRE_PAE)
3054	{
3055	for (uint32_t i = 0; ; i++)
3056	{
3057	rc = SSMR3GetU32(pSSM, &u32Sep); /* sequence number */
3058	if (RT_FAILURE(rc))
3059	return rc;
3060	if (u32Sep == ~0U)
3061	break;
3062	AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3063
3064	char szDesc[256];
3065	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
3066	if (RT_FAILURE(rc))
3067	return rc;
3068	RTGCPTR GCPtrIgnore;
3069	SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
3070	rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
3071	if (RT_FAILURE(rc))
3072	return rc;
3073	}
3074	}
3075
3076	/*
3077	* Load the RAM contents.
3078	*/
3079	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
3080	{
3081	if (!pVM->pgm.s.LiveSave.fActive)
3082	{
3083	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3084	{
3085	rc = pgmR3LoadRamConfig(pVM, pSSM);
3086	if (RT_FAILURE(rc))
3087	return rc;
3088	}
3089	rc = pgmR3LoadRomRanges(pVM, pSSM);
3090	if (RT_FAILURE(rc))
3091	return rc;
3092	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3093	if (RT_FAILURE(rc))
3094	return rc;
3095	}
3096
3097	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, SSM_PASS_FINAL);
3098	}
3099	else
3100	rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
3101
3102	/* Refresh balloon accounting. */
3103	if (pVM->pgm.s.cBalloonedPages)
3104	{
3105	Log(("pgmR3LoadFinalLocked: pVM=%p cBalloonedPages=%#x\n", pVM, pVM->pgm.s.cBalloonedPages));
3106	rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
3107	AssertRCReturn(rc, rc);
3108	}
3109	return rc;
3110	}
3111
3112
3113	/**
3114	* @callback_method_impl{FNSSMINTLOADEXEC}
3115	*/
3116	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3117	{
3118	int rc;
3119
3120	/*
3121	* Validate version.
3122	*/
3123	if ( ( uPass != SSM_PASS_FINAL
3124	&& uVersion != PGM_SAVED_STATE_VERSION
3125	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_PAE
3126	&& uVersion != PGM_SAVED_STATE_VERSION_BALLOON_BROKEN
3127	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3128	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3129	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
3130	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_PAE
3131	&& uVersion != PGM_SAVED_STATE_VERSION_BALLOON_BROKEN
3132	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3133	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
3134	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
3135	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
3136	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
3137	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3138	)
3139	{
3140	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
3141	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3142	}
3143
3144	/*
3145	* Do the loading while owning the lock because a bunch of the functions
3146	* we're using requires this.
3147	*/
3148	if (uPass != SSM_PASS_FINAL)
3149	{
3150	pgmLock(pVM);
3151	if (uPass != 0)
3152	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, uPass);
3153	else
3154	{
3155	pVM->pgm.s.LiveSave.fActive = true;
3156	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3157	rc = pgmR3LoadRamConfig(pVM, pSSM);
3158	else
3159	rc = VINF_SUCCESS;
3160	if (RT_SUCCESS(rc))
3161	rc = pgmR3LoadRomRanges(pVM, pSSM);
3162	if (RT_SUCCESS(rc))
3163	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3164	if (RT_SUCCESS(rc))
3165	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, uPass);
3166	}
3167	pgmUnlock(pVM);
3168	}
3169	else
3170	{
3171	pgmLock(pVM);
3172	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
3173	pVM->pgm.s.LiveSave.fActive = false;
3174	pgmUnlock(pVM);
3175	if (RT_SUCCESS(rc))
3176	{
3177	/*
3178	* We require a full resync now.
3179	*/
3180	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3181	{
3182	PVMCPU pVCpu = pVM->apCpusR3[i];
3183	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3184	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3185	/** @todo For guest PAE, we might get the wrong
3186	* aGCPhysGstPaePDs values now. We should used the
3187	* saved ones... Postponing this since it nothing new
3188	* and PAE/PDPTR needs some general readjusting, see
3189	* @bugref{5880}. */
3190	}
3191
3192	pgmR3HandlerPhysicalUpdateAll(pVM);
3193
3194	/*
3195	* Change the paging mode (indirectly restores PGMCPU::GCPhysCR3).
3196	* (Requires the CPUM state to be restored already!)
3197	*/
3198	if (CPUMR3IsStateRestorePending(pVM))
3199	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3200	N_("PGM was unexpectedly restored before CPUM"));
3201
3202	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3203	{
3204	PVMCPU pVCpu = pVM->apCpusR3[i];
3205
3206	rc = PGMHCChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3207	AssertLogRelRCReturn(rc, rc);
3208
3209	/* Update the PSE, NX flags and validity masks. */
3210	pVCpu->pgm.s.fGst32BitPageSizeExtension = CPUMIsGuestPageSizeExtEnabled(pVCpu);
3211	PGMNotifyNxeChanged(pVCpu, CPUMIsGuestNXEnabled(pVCpu));
3212	}
3213
3214	/*
3215	* Try re-fixate the guest mappings.
3216	*/
3217	pVM->pgm.s.fMappingsFixedRestored = false;
3218	if ( pVM->pgm.s.fMappingsFixed
3219	&& pgmMapAreMappingsEnabled(pVM))
3220	{
3221	#ifndef PGM_WITHOUT_MAPPINGS
3222	RTGCPTR GCPtrFixed = pVM->pgm.s.GCPtrMappingFixed;
3223	uint32_t cbFixed = pVM->pgm.s.cbMappingFixed;
3224	pVM->pgm.s.fMappingsFixed = false;
3225
3226	uint32_t cbRequired;
3227	int rc2 = PGMR3MappingsSize(pVM, &cbRequired); AssertRC(rc2);
3228	if ( RT_SUCCESS(rc2)
3229	&& cbRequired > cbFixed)
3230	rc2 = VERR_OUT_OF_RANGE;
3231	if (RT_SUCCESS(rc2))
3232	rc2 = pgmR3MappingsFixInternal(pVM, GCPtrFixed, cbFixed);
3233	if (RT_FAILURE(rc2))
3234	{
3235	LogRel(("PGM: Unable to re-fixate the guest mappings at %RGv-%RGv: rc=%Rrc (cbRequired=%#x)\n",
3236	GCPtrFixed, GCPtrFixed + cbFixed, rc2, cbRequired));
3237	pVM->pgm.s.fMappingsFixed = false;
3238	pVM->pgm.s.fMappingsFixedRestored = true;
3239	pVM->pgm.s.GCPtrMappingFixed = GCPtrFixed;
3240	pVM->pgm.s.cbMappingFixed = cbFixed;
3241	}
3242	#else
3243	AssertFailed();
3244	#endif
3245	}
3246	else
3247	{
3248	/* We used to set fixed + disabled while we only use disabled now,
3249	so wipe the state to avoid any confusion. */
3250	pVM->pgm.s.fMappingsFixed = false;
3251	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
3252	pVM->pgm.s.cbMappingFixed = 0;
3253	}
3254
3255	/*
3256	* If we have floating mappings, do a CR3 sync now to make sure the HMA
3257	* doesn't conflict with guest code / data and thereby cause trouble
3258	* when restoring other components like PATM.
3259	*/
3260	if (pgmMapAreMappingsFloating(pVM))
3261	{
3262	PVMCPU pVCpu = pVM->apCpusR3[0];
3263	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
3264	if (RT_FAILURE(rc))
3265	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3266	N_("PGMSyncCR3 failed unexpectedly with rc=%Rrc"), rc);
3267
3268	/* Make sure to re-sync before executing code. */
3269	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3270	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3271	}
3272	}
3273	}
3274
3275	return rc;
3276	}
3277
3278
3279	/**
3280	* @callback_method_impl{FNSSMINTLOADDONE}
3281	*/
3282	static DECLCALLBACK(int) pgmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3283	{
3284	pVM->pgm.s.fRestoreRomPagesOnReset = true;
3285	NOREF(pSSM);
3286	return VINF_SUCCESS;
3287	}
3288
3289
3290	/**
3291	* Registers the saved state callbacks with SSM.
3292	*
3293	* @returns VBox status code.
3294	* @param pVM The cross context VM structure.
3295	* @param cbRam The RAM size.
3296	*/
3297	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3298	{
3299	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3300	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3301	NULL, pgmR3SaveExec, pgmR3SaveDone,
3302	pgmR3LoadPrep, pgmR3Load, pgmR3LoadDone);
3303	}
3304

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

© 2023 Oracle
Contact – Privacy policy – Terms of Use