VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PGMMap.cpp@ 84044

Last change on this file since 84044 was 82968, checked in by vboxsync, 4 years ago

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1/* $Id: PGMMap.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2/** @file
3 * PGM - Page Manager, Guest Context Mappings.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM
23#include <VBox/vmm/dbgf.h>
24#include <VBox/vmm/pgm.h>
25#include "PGMInternal.h"
26#include <VBox/vmm/vm.h>
27#include "PGMInline.h"
28
29#include <VBox/log.h>
30#include <VBox/err.h>
31#include <iprt/asm.h>
32#include <iprt/assert.h>
33#include <iprt/string.h>
34
35
36/*********************************************************************************************************************************
37* Internal Functions *
38*********************************************************************************************************************************/
39#ifndef PGM_WITHOUT_MAPPINGS
40static void pgmR3MapClearPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iOldPDE);
41static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
42static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
43static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
44#endif
45
46
47#ifndef PGM_WITHOUT_MAPPINGS
48
49/**
50 * Creates a page table based mapping in GC.
51 *
52 * @returns VBox status code.
53 * @param pVM The cross context VM structure.
54 * @param GCPtr Virtual Address. (Page table aligned!)
55 * @param cb Size of the range. Must be a 4MB aligned!
56 * @param fFlags PGMR3MAPPT_FLAGS_UNMAPPABLE or 0.
57 * @param pfnRelocate Relocation callback function.
58 * @param pvUser User argument to the callback.
59 * @param pszDesc Pointer to description string. This must not be freed.
60 */
61VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void *pvUser, const char *pszDesc)
62{
63 LogFlow(("PGMR3MapPT: GCPtr=%#x cb=%d fFlags=%#x pfnRelocate=%p pvUser=%p pszDesc=%s\n", GCPtr, cb, fFlags, pfnRelocate, pvUser, pszDesc));
64 AssertMsg(pVM->pgm.s.pInterPD, ("Paging isn't initialized, init order problems!\n"));
65
66 /*
67 * Validate input.
68 * Note! The lower limit (1 MB) matches how pgmR3PhysMMIOExCreate works.
69 */
70 Assert(!fFlags || fFlags == PGMR3MAPPT_FLAGS_UNMAPPABLE);
71 AssertMsgReturn(cb >= _1M && cb <= _64M, ("Seriously? cb=%d (%#x)\n", cb, cb), VERR_OUT_OF_RANGE);
72
73 cb = RT_ALIGN_32(cb, _4M);
74 RTGCPTR GCPtrLast = GCPtr + cb - 1;
75
76 AssertMsgReturn(GCPtrLast >= GCPtr, ("Range wraps! GCPtr=%x GCPtrLast=%x\n", GCPtr, GCPtrLast),
77 VERR_INVALID_PARAMETER);
78 AssertMsgReturn(!pVM->pgm.s.fMappingsFixed, ("Mappings are fixed! It's not possible to add new mappings at this time!\n"),
79 VERR_PGM_MAPPINGS_FIXED);
80 AssertPtrReturn(pfnRelocate, VERR_INVALID_PARAMETER);
81
82 /*
83 * Find list location.
84 */
85 PPGMMAPPING pPrev = NULL;
86 PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
87 while (pCur)
88 {
89 if (pCur->GCPtrLast >= GCPtr && pCur->GCPtr <= GCPtrLast)
90 {
91 AssertMsgFailed(("Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
92 pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
93 LogRel(("VERR_PGM_MAPPING_CONFLICT: Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
94 pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
95 return VERR_PGM_MAPPING_CONFLICT;
96 }
97 if (pCur->GCPtr > GCPtr)
98 break;
99 pPrev = pCur;
100 pCur = pCur->pNextR3;
101 }
102
103 /*
104 * Check for conflicts with intermediate mappings.
105 */
106 const unsigned iPageDir = GCPtr >> X86_PD_SHIFT;
107 const unsigned cPTs = cb >> X86_PD_SHIFT;
108 if (pVM->pgm.s.fFinalizedMappings)
109 {
110 for (unsigned i = 0; i < cPTs; i++)
111 if (pVM->pgm.s.pInterPD->a[iPageDir + i].n.u1Present)
112 {
113 AssertMsgFailed(("Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
114 LogRel(("VERR_PGM_MAPPING_CONFLICT: Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
115 return VERR_PGM_MAPPING_CONFLICT;
116 }
117 /** @todo AMD64: add check in PAE structures too, so we can remove all the 32-Bit paging stuff there. */
118 }
119
120 /*
121 * Allocate and initialize the new list node.
122 */
123 PPGMMAPPING pNew;
124 int rc;
125 if (fFlags & PGMR3MAPPT_FLAGS_UNMAPPABLE)
126 rc = MMHyperAlloc( pVM, RT_UOFFSETOF_DYN(PGMMAPPING, aPTs[cPTs]), 0, MM_TAG_PGM_MAPPINGS, (void **)&pNew);
127 else
128 rc = MMR3HyperAllocOnceNoRel(pVM, RT_UOFFSETOF_DYN(PGMMAPPING, aPTs[cPTs]), 0, MM_TAG_PGM_MAPPINGS, (void **)&pNew);
129 if (RT_FAILURE(rc))
130 return rc;
131 pNew->GCPtr = GCPtr;
132 pNew->GCPtrLast = GCPtrLast;
133 pNew->cb = cb;
134 pNew->pfnRelocate = pfnRelocate;
135 pNew->pvUser = pvUser;
136 pNew->pszDesc = pszDesc;
137 pNew->cPTs = cPTs;
138
139 /*
140 * Allocate page tables and insert them into the page directories.
141 * (One 32-bit PT and two PAE PTs.)
142 */
143 uint8_t *pbPTs;
144 if (fFlags & PGMR3MAPPT_FLAGS_UNMAPPABLE)
145 rc = MMHyperAlloc( pVM, PAGE_SIZE * 3 * cPTs, PAGE_SIZE, MM_TAG_PGM_MAPPINGS, (void **)&pbPTs);
146 else
147 rc = MMR3HyperAllocOnceNoRel(pVM, PAGE_SIZE * 3 * cPTs, PAGE_SIZE, MM_TAG_PGM_MAPPINGS, (void **)&pbPTs);
148 if (RT_FAILURE(rc))
149 {
150 MMHyperFree(pVM, pNew);
151 return VERR_NO_MEMORY;
152 }
153
154 /*
155 * Init the page tables and insert them into the page directories.
156 */
157 Log4(("PGMR3MapPT: GCPtr=%RGv cPTs=%u pbPTs=%p\n", GCPtr, cPTs, pbPTs));
158 for (unsigned i = 0; i < cPTs; i++)
159 {
160 /*
161 * 32-bit.
162 */
163 pNew->aPTs[i].pPTR3 = (PX86PT)pbPTs;
164 pNew->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pNew->aPTs[i].pPTR3);
165 pNew->aPTs[i].pPTR0 = MMHyperR3ToR0(pVM, pNew->aPTs[i].pPTR3);
166 pNew->aPTs[i].HCPhysPT = MMR3HyperHCVirt2HCPhys(pVM, pNew->aPTs[i].pPTR3);
167 pbPTs += PAGE_SIZE;
168 Log4(("PGMR3MapPT: i=%d: pPTR3=%RHv pPTRC=%RRv pPRTR0=%RHv HCPhysPT=%RHp\n",
169 i, pNew->aPTs[i].pPTR3, pNew->aPTs[i].pPTRC, pNew->aPTs[i].pPTR0, pNew->aPTs[i].HCPhysPT));
170
171 /*
172 * PAE.
173 */
174 pNew->aPTs[i].HCPhysPaePT0 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs);
175 pNew->aPTs[i].HCPhysPaePT1 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs + PAGE_SIZE);
176 pNew->aPTs[i].paPaePTsR3 = (PPGMSHWPTPAE)pbPTs;
177 pNew->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pbPTs);
178 pNew->aPTs[i].paPaePTsR0 = MMHyperR3ToR0(pVM, pbPTs);
179 pbPTs += PAGE_SIZE * 2;
180 Log4(("PGMR3MapPT: i=%d: paPaePTsR#=%RHv paPaePTsRC=%RRv paPaePTsR#=%RHv HCPhysPaePT0=%RHp HCPhysPaePT1=%RHp\n",
181 i, pNew->aPTs[i].paPaePTsR3, pNew->aPTs[i].paPaePTsRC, pNew->aPTs[i].paPaePTsR0, pNew->aPTs[i].HCPhysPaePT0, pNew->aPTs[i].HCPhysPaePT1));
182 }
183 if (pVM->pgm.s.fFinalizedMappings)
184 pgmR3MapSetPDEs(pVM, pNew, iPageDir);
185 /* else PGMR3FinalizeMappings() */
186
187 /*
188 * Insert the new mapping.
189 */
190 pNew->pNextR3 = pCur;
191 pNew->pNextRC = pCur ? MMHyperR3ToRC(pVM, pCur) : NIL_RTRCPTR;
192 pNew->pNextR0 = pCur ? MMHyperR3ToR0(pVM, pCur) : NIL_RTR0PTR;
193 if (pPrev)
194 {
195 pPrev->pNextR3 = pNew;
196 pPrev->pNextRC = MMHyperR3ToRC(pVM, pNew);
197 pPrev->pNextR0 = MMHyperR3ToR0(pVM, pNew);
198 }
199 else
200 {
201 pVM->pgm.s.pMappingsR3 = pNew;
202 pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pNew);
203 pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pNew);
204 }
205
206 for (VMCPUID i = 0; i < pVM->cCpus; i++)
207 {
208 PVMCPU pVCpu = pVM->apCpusR3[i];
209 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
210 }
211 return VINF_SUCCESS;
212}
213
214#ifdef VBOX_WITH_UNUSED_CODE
215
216/**
217 * Removes a page table based mapping.
218 *
219 * @returns VBox status code.
220 * @param pVM The cross context VM structure.
221 * @param GCPtr Virtual Address. (Page table aligned!)
222 *
223 * @remarks Don't call this without passing PGMR3MAPPT_FLAGS_UNMAPPABLE to
224 * PGMR3MapPT or you'll burn in the heap.
225 */
226VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr)
227{
228 LogFlow(("PGMR3UnmapPT: GCPtr=%#x\n", GCPtr));
229 AssertReturn(pVM->pgm.s.fFinalizedMappings, VERR_WRONG_ORDER);
230
231 /*
232 * Find it.
233 */
234 PPGMMAPPING pPrev = NULL;
235 PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
236 while (pCur)
237 {
238 if (pCur->GCPtr == GCPtr)
239 {
240 /*
241 * Unlink it.
242 */
243 if (pPrev)
244 {
245 pPrev->pNextR3 = pCur->pNextR3;
246 pPrev->pNextRC = pCur->pNextRC;
247 pPrev->pNextR0 = pCur->pNextR0;
248 }
249 else
250 {
251 pVM->pgm.s.pMappingsR3 = pCur->pNextR3;
252 pVM->pgm.s.pMappingsRC = pCur->pNextRC;
253 pVM->pgm.s.pMappingsR0 = pCur->pNextR0;
254 }
255
256 /*
257 * Free the page table memory, clear page directory entries
258 * and free the page tables and node memory.
259 */
260 MMHyperFree(pVM, pCur->aPTs[0].pPTR3);
261 if (pCur->GCPtr != NIL_RTGCPTR)
262 pgmR3MapClearPDEs(pVM, pCur, pCur->GCPtr >> X86_PD_SHIFT);
263 MMHyperFree(pVM, pCur);
264
265 for (VMCPUID i = 0; i < pVM->cCpus; i++)
266 {
267 PVMCPU pVCpu = pVM->apCpusR3[i];
268 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
269 }
270 return VINF_SUCCESS;
271 }
272
273 /* done? */
274 if (pCur->GCPtr > GCPtr)
275 break;
276
277 /* next */
278 pPrev = pCur;
279 pCur = pCur->pNextR3;
280 }
281
282 AssertMsgFailed(("No mapping for %#x found!\n", GCPtr));
283 return VERR_INVALID_PARAMETER;
284}
285
286#endif /* unused */
287
288
289/**
290 * Checks whether a range of PDEs in the intermediate
291 * memory context are unused.
292 *
293 * We're talking 32-bit PDEs here.
294 *
295 * @returns true/false.
296 * @param pVM The cross context VM structure.
297 * @param iPD The first PDE in the range.
298 * @param cPTs The number of PDEs in the range.
299 */
300DECLINLINE(bool) pgmR3AreIntermediatePDEsUnused(PVM pVM, unsigned iPD, unsigned cPTs)
301{
302 if (pVM->pgm.s.pInterPD->a[iPD].n.u1Present)
303 return false;
304 while (cPTs > 1)
305 {
306 iPD++;
307 if (pVM->pgm.s.pInterPD->a[iPD].n.u1Present)
308 return false;
309 cPTs--;
310 }
311 return true;
312}
313
314
315/**
316 * Unlinks the mapping.
317 *
318 * The mapping *must* be in the list.
319 *
320 * @param pVM The cross context VM structure.
321 * @param pMapping The mapping to unlink.
322 */
323static void pgmR3MapUnlink(PVM pVM, PPGMMAPPING pMapping)
324{
325 PPGMMAPPING pAfterThis = pVM->pgm.s.pMappingsR3;
326 if (pAfterThis == pMapping)
327 {
328 /* head */
329 pVM->pgm.s.pMappingsR3 = pMapping->pNextR3;
330 pVM->pgm.s.pMappingsRC = pMapping->pNextRC;
331 pVM->pgm.s.pMappingsR0 = pMapping->pNextR0;
332 }
333 else
334 {
335 /* in the list */
336 while (pAfterThis->pNextR3 != pMapping)
337 {
338 pAfterThis = pAfterThis->pNextR3;
339 AssertReleaseReturnVoid(pAfterThis);
340 }
341
342 pAfterThis->pNextR3 = pMapping->pNextR3;
343 pAfterThis->pNextRC = pMapping->pNextRC;
344 pAfterThis->pNextR0 = pMapping->pNextR0;
345 }
346}
347
348
349/**
350 * Links the mapping.
351 *
352 * @param pVM The cross context VM structure.
353 * @param pMapping The mapping to linked.
354 */
355static void pgmR3MapLink(PVM pVM, PPGMMAPPING pMapping)
356{
357 /*
358 * Find the list location (it's sorted by GCPhys) and link it in.
359 */
360 if ( !pVM->pgm.s.pMappingsR3
361 || pVM->pgm.s.pMappingsR3->GCPtr > pMapping->GCPtr)
362 {
363 /* head */
364 pMapping->pNextR3 = pVM->pgm.s.pMappingsR3;
365 pMapping->pNextRC = pVM->pgm.s.pMappingsRC;
366 pMapping->pNextR0 = pVM->pgm.s.pMappingsR0;
367 pVM->pgm.s.pMappingsR3 = pMapping;
368 pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pMapping);
369 pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pMapping);
370 }
371 else
372 {
373 /* in the list */
374 PPGMMAPPING pAfterThis = pVM->pgm.s.pMappingsR3;
375 PPGMMAPPING pBeforeThis = pAfterThis->pNextR3;
376 while (pBeforeThis && pBeforeThis->GCPtr <= pMapping->GCPtr)
377 {
378 pAfterThis = pBeforeThis;
379 pBeforeThis = pBeforeThis->pNextR3;
380 }
381
382 pMapping->pNextR3 = pAfterThis->pNextR3;
383 pMapping->pNextRC = pAfterThis->pNextRC;
384 pMapping->pNextR0 = pAfterThis->pNextR0;
385 pAfterThis->pNextR3 = pMapping;
386 pAfterThis->pNextRC = MMHyperR3ToRC(pVM, pMapping);
387 pAfterThis->pNextR0 = MMHyperR3ToR0(pVM, pMapping);
388 }
389}
390
391
392/**
393 * Finalizes the intermediate context.
394 *
395 * This is called at the end of the ring-3 init and will construct the
396 * intermediate paging structures, relocating all the mappings in the process.
397 *
398 * @returns VBox status code.
399 * @param pVM The cross context VM structure.
400 * @thread EMT(0)
401 */
402VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM)
403{
404 AssertReturn(!pVM->pgm.s.fFinalizedMappings, VERR_WRONG_ORDER);
405 pVM->pgm.s.fFinalizedMappings = true;
406
407 /*
408 * Loop until all mappings have been finalized.
409 */
410#if 0
411 unsigned iPDNext = UINT32_C(0xc0000000) >> X86_PD_SHIFT; /* makes CSAM/PATM freak out booting linux. :-/ */
412#elif 0
413 unsigned iPDNext = MM_HYPER_AREA_ADDRESS >> X86_PD_SHIFT;
414#else
415 unsigned iPDNext = 1 << X86_PD_SHIFT; /* no hint, map them from the top. */
416#endif
417
418 PPGMMAPPING pCur;
419 do
420 {
421 pCur = pVM->pgm.s.pMappingsR3;
422 while (pCur)
423 {
424 if (!pCur->fFinalized)
425 {
426 /*
427 * Find a suitable location.
428 */
429 RTGCPTR const GCPtrOld = pCur->GCPtr;
430 const unsigned cPTs = pCur->cPTs;
431 unsigned iPDNew = iPDNext;
432 if ( iPDNew + cPTs >= X86_PG_ENTRIES /* exclude the last PD */
433 || !pgmR3AreIntermediatePDEsUnused(pVM, iPDNew, cPTs)
434 || !pCur->pfnRelocate(pVM, GCPtrOld, (RTGCPTR)iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
435 {
436 /* No luck, just scan down from 4GB-4MB, giving up at 4MB. */
437 iPDNew = X86_PG_ENTRIES - cPTs - 1;
438 while ( iPDNew > 0
439 && ( !pgmR3AreIntermediatePDEsUnused(pVM, iPDNew, cPTs)
440 || !pCur->pfnRelocate(pVM, GCPtrOld, (RTGCPTR)iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
441 )
442 iPDNew--;
443 AssertLogRelReturn(iPDNew != 0, VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
444 }
445
446 /*
447 * Relocate it (something akin to pgmR3MapRelocate).
448 */
449 pgmR3MapSetPDEs(pVM, pCur, iPDNew);
450
451 /* unlink the mapping, update the entry and relink it. */
452 pgmR3MapUnlink(pVM, pCur);
453
454 RTGCPTR const GCPtrNew = (RTGCPTR)iPDNew << X86_PD_SHIFT;
455 pCur->GCPtr = GCPtrNew;
456 pCur->GCPtrLast = GCPtrNew + pCur->cb - 1;
457 pCur->fFinalized = true;
458
459 pgmR3MapLink(pVM, pCur);
460
461 /* Finally work the callback. */
462 pCur->pfnRelocate(pVM, GCPtrOld, GCPtrNew, PGMRELOCATECALL_RELOCATE, pCur->pvUser);
463
464 /*
465 * The list order might have changed, start from the beginning again.
466 */
467 iPDNext = iPDNew + cPTs;
468 break;
469 }
470
471 /* next */
472 pCur = pCur->pNextR3;
473 }
474 } while (pCur);
475
476 return VINF_SUCCESS;
477}
478
479#endif /* !PGM_WITHOUT_MAPPINGS */
480
481
482/**
483 * Gets the size of the current guest mappings if they were to be
484 * put next to one another.
485 *
486 * @returns VBox status code.
487 * @param pVM The cross context VM structure.
488 * @param pcb Where to store the size.
489 */
490VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb)
491{
492 RTGCPTR cb = 0;
493#ifndef PGM_WITHOUT_MAPPINGS
494 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
495 cb += pCur->cb;
496#else
497 RT_NOREF(pVM);
498#endif
499
500 *pcb = cb;
501 AssertReturn(*pcb == cb, VERR_NUMBER_TOO_BIG);
502 Log(("PGMR3MappingsSize: return %d (%#x) bytes\n", cb, cb));
503 return VINF_SUCCESS;
504}
505
506
507/**
508 * Fixates the guest context mappings in a range reserved from the Guest OS.
509 *
510 * @returns VBox status code.
511 * @param pVM The cross context VM structure.
512 * @param GCPtrBase The address of the reserved range of guest memory.
513 * @param cb The size of the range starting at GCPtrBase.
514 */
515VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb)
516{
517 Log(("PGMR3MappingsFix: GCPtrBase=%RGv cb=%#x (fMappingsFixed=%RTbool MappingEnabled=%RTbool)\n",
518 GCPtrBase, cb, pVM->pgm.s.fMappingsFixed, pgmMapAreMappingsEnabled(pVM)));
519
520#ifndef PGM_WITHOUT_MAPPINGS
521 if (pgmMapAreMappingsEnabled(pVM))
522 {
523 /*
524 * Only applies to VCPU 0 as we don't support SMP guests with raw mode.
525 */
526 Assert(pVM->cCpus == 1);
527 PVMCPU pVCpu = pVM->apCpusR3[0];
528
529 /*
530 * Before we do anything we'll do a forced PD sync to try make sure any
531 * pending relocations because of these mappings have been resolved.
532 */
533 PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
534
535 return pgmR3MappingsFixInternal(pVM, GCPtrBase, cb);
536 }
537
538#else /* PGM_WITHOUT_MAPPINGS */
539 RT_NOREF(pVM, GCPtrBase, cb);
540#endif /* PGM_WITHOUT_MAPPINGS */
541
542 Assert(!VM_IS_RAW_MODE_ENABLED(pVM));
543 return VINF_SUCCESS;
544}
545
546
547#ifndef PGM_WITHOUT_MAPPINGS
548/**
549 * Internal worker for PGMR3MappingsFix and pgmR3Load.
550 *
551 * (This does not perform a SyncCR3 before the fixation like PGMR3MappingsFix.)
552 *
553 * @returns VBox status code.
554 * @param pVM The cross context VM structure.
555 * @param GCPtrBase The address of the reserved range of guest memory.
556 * @param cb The size of the range starting at GCPtrBase.
557 */
558int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb)
559{
560 /*
561 * Check input arguments and pre-conditions.
562 */
563 AssertMsgReturn(!(GCPtrBase & X86_PAGE_4M_OFFSET_MASK), ("GCPtrBase (%#x) has to be aligned on a 4MB address!\n", GCPtrBase),
564 VERR_INVALID_PARAMETER);
565 AssertMsgReturn(cb && !(cb & X86_PAGE_4M_OFFSET_MASK), ("cb (%#x) is 0 or not aligned on a 4MB address!\n", cb),
566 VERR_INVALID_PARAMETER);
567 AssertReturn(pgmMapAreMappingsEnabled(pVM), VERR_PGM_MAPPINGS_DISABLED);
568 AssertReturn(pVM->cCpus == 1, VERR_PGM_MAPPINGS_SMP);
569
570 /*
571 * Check that it's not conflicting with a core code mapping in the intermediate page table.
572 */
573 unsigned iPDNew = GCPtrBase >> X86_PD_SHIFT;
574 unsigned i = cb >> X86_PD_SHIFT;
575 while (i-- > 0)
576 {
577 if (pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present)
578 {
579 /* Check that it's not one or our mappings. */
580 PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
581 while (pCur)
582 {
583 if (iPDNew + i - (pCur->GCPtr >> X86_PD_SHIFT) < (pCur->cb >> X86_PD_SHIFT))
584 break;
585 pCur = pCur->pNextR3;
586 }
587 if (!pCur)
588 {
589 LogRel(("PGMR3MappingsFix: Conflicts with intermediate PDE %#x (GCPtrBase=%RGv cb=%#zx). The guest should retry.\n",
590 iPDNew + i, GCPtrBase, cb));
591 return VERR_PGM_MAPPINGS_FIX_CONFLICT;
592 }
593 }
594 }
595
596 /*
597 * In PAE / PAE mode, make sure we don't cross page directories.
598 */
599 PVMCPU pVCpu = pVM->apCpusR3[0];
600 if ( ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
601 || pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX)
602 && ( pVCpu->pgm.s.enmShadowMode == PGMMODE_PAE
603 || pVCpu->pgm.s.enmShadowMode == PGMMODE_PAE_NX))
604 {
605 unsigned iPdptBase = GCPtrBase >> X86_PDPT_SHIFT;
606 unsigned iPdptLast = (GCPtrBase + cb - 1) >> X86_PDPT_SHIFT;
607 if (iPdptBase != iPdptLast)
608 {
609 LogRel(("PGMR3MappingsFix: Crosses PD boundary; iPdptBase=%#x iPdptLast=%#x (GCPtrBase=%RGv cb=%#zx). The guest should retry.\n",
610 iPdptBase, iPdptLast, GCPtrBase, cb));
611 return VERR_PGM_MAPPINGS_FIX_CONFLICT;
612 }
613 }
614
615 /*
616 * Loop the mappings and check that they all agree on their new locations.
617 */
618 RTGCPTR GCPtrCur = GCPtrBase;
619 PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
620 while (pCur)
621 {
622 if (!pCur->pfnRelocate(pVM, pCur->GCPtr, GCPtrCur, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
623 {
624 AssertMsgFailed(("The suggested fixed address %#x was rejected by '%s'!\n", GCPtrCur, pCur->pszDesc));
625 return VERR_PGM_MAPPINGS_FIX_REJECTED;
626 }
627 /* next */
628 GCPtrCur += pCur->cb;
629 pCur = pCur->pNextR3;
630 }
631 if (GCPtrCur > GCPtrBase + cb)
632 {
633 AssertMsgFailed(("cb (%#x) is less than the required range %#x!\n", cb, GCPtrCur - GCPtrBase));
634 return VERR_PGM_MAPPINGS_FIX_TOO_SMALL;
635 }
636
637 /*
638 * Loop the table assigning the mappings to the passed in memory
639 * and call their relocator callback.
640 */
641 GCPtrCur = GCPtrBase;
642 pCur = pVM->pgm.s.pMappingsR3;
643 while (pCur)
644 {
645 RTGCPTR const GCPtrOld = pCur->GCPtr;
646
647 /*
648 * Relocate the page table(s).
649 */
650 if (pCur->GCPtr != NIL_RTGCPTR)
651 pgmR3MapClearPDEs(pVM, pCur, GCPtrOld >> X86_PD_SHIFT);
652 pgmR3MapSetPDEs(pVM, pCur, GCPtrCur >> X86_PD_SHIFT);
653
654 /*
655 * Update the entry.
656 */
657 pCur->GCPtr = GCPtrCur;
658 pCur->GCPtrLast = GCPtrCur + pCur->cb - 1;
659
660 /*
661 * Callback to execute the relocation.
662 */
663 pCur->pfnRelocate(pVM, GCPtrOld, GCPtrCur, PGMRELOCATECALL_RELOCATE, pCur->pvUser);
664
665 /*
666 * Advance.
667 */
668 GCPtrCur += pCur->cb;
669 pCur = pCur->pNextR3;
670 }
671
672 /*
673 * Mark the mappings as fixed at this new location and return.
674 */
675 pVM->pgm.s.fMappingsFixed = true;
676 pVM->pgm.s.fMappingsFixedRestored = false;
677 pVM->pgm.s.GCPtrMappingFixed = GCPtrBase;
678 pVM->pgm.s.cbMappingFixed = cb;
679
680 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
681 {
682 pVM->aCpus[idCpu].pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
683 VMCPU_FF_SET(pVM->apCpusR3[idCpu], VMCPU_FF_PGM_SYNC_CR3);
684 }
685 return VINF_SUCCESS;
686}
687#endif /* !PGM_WITHOUT_MAPPINGS */
688
689
690/**
691 * Unfixes the mappings.
692 *
693 * Unless PGMR3MappingsDisable is in effect, mapping conflict detection will be
694 * enabled after this call. If the mappings are fixed, a full CR3 resync will
695 * take place afterwards.
696 *
697 * @returns VBox status code.
698 * @param pVM The cross context VM structure.
699 */
700VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM)
701{
702 Log(("PGMR3MappingsUnfix: fMappingsFixed=%RTbool MappingsEnabled=%RTbool\n", pVM->pgm.s.fMappingsFixed, pgmMapAreMappingsEnabled(pVM)));
703 if ( pgmMapAreMappingsEnabled(pVM)
704 && ( pVM->pgm.s.fMappingsFixed
705 || pVM->pgm.s.fMappingsFixedRestored)
706 )
707 {
708 bool const fResyncCR3 = pVM->pgm.s.fMappingsFixed;
709
710 pVM->pgm.s.fMappingsFixed = false;
711 pVM->pgm.s.fMappingsFixedRestored = false;
712 pVM->pgm.s.GCPtrMappingFixed = 0;
713 pVM->pgm.s.cbMappingFixed = 0;
714
715 if (fResyncCR3)
716 for (VMCPUID i = 0; i < pVM->cCpus; i++)
717 VMCPU_FF_SET(pVM->apCpusR3[i], VMCPU_FF_PGM_SYNC_CR3);
718 }
719 return VINF_SUCCESS;
720}
721
722#ifndef PGM_WITHOUT_MAPPINGS
723
724/**
725 * Checks if the mappings needs re-fixing after a restore.
726 *
727 * @returns true if they need, false if not.
728 * @param pVM The cross context VM structure.
729 */
730VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM)
731{
732 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
733 return pVM->pgm.s.fMappingsFixedRestored;
734}
735
736
737/**
738 * Map pages into the intermediate context (switcher code).
739 *
740 * These pages are mapped at both the give virtual address and at the physical
741 * address (for identity mapping).
742 *
743 * @returns VBox status code.
744 * @param pVM The cross context VM structure.
745 * @param Addr Intermediate context address of the mapping.
746 * @param HCPhys Start of the range of physical pages. This must be entriely below 4GB!
747 * @param cbPages Number of bytes to map.
748 *
749 * @remark This API shall not be used to anything but mapping the switcher code.
750 */
751VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages)
752{
753 LogFlow(("PGMR3MapIntermediate: Addr=%RTptr HCPhys=%RHp cbPages=%#x\n", Addr, HCPhys, cbPages));
754
755 /*
756 * Adjust input.
757 */
758 cbPages += (uint32_t)HCPhys & PAGE_OFFSET_MASK;
759 cbPages = RT_ALIGN(cbPages, PAGE_SIZE);
760 HCPhys &= X86_PTE_PAE_PG_MASK;
761 Addr &= PAGE_BASE_MASK;
762 /* We only care about the first 4GB, because on AMD64 we'll be repeating them all over the address space. */
763 uint32_t uAddress = (uint32_t)Addr;
764
765 /*
766 * Assert input and state.
767 */
768 AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
769 AssertMsg(pVM->pgm.s.pInterPD, ("Bad init order, paging.\n"));
770 AssertMsg(cbPages <= (512 << PAGE_SHIFT), ("The mapping is too big %d bytes\n", cbPages));
771 AssertMsg(HCPhys < _4G && HCPhys + cbPages < _4G, ("Addr=%RTptr HCPhys=%RHp cbPages=%d\n", Addr, HCPhys, cbPages));
772 AssertReturn(!pVM->pgm.s.fFinalizedMappings, VERR_WRONG_ORDER);
773
774 /*
775 * Check for internal conflicts between the virtual address and the physical address.
776 * A 1:1 mapping is fine, but partial overlapping is a no-no.
777 */
778 if ( uAddress != HCPhys
779 && ( uAddress < HCPhys
780 ? HCPhys - uAddress < cbPages
781 : uAddress - HCPhys < cbPages
782 )
783 )
784 AssertLogRelMsgFailedReturn(("Addr=%RTptr HCPhys=%RHp cbPages=%d\n", Addr, HCPhys, cbPages),
785 VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
786
787 const unsigned cPages = cbPages >> PAGE_SHIFT;
788 int rc = pgmR3MapIntermediateCheckOne(pVM, uAddress, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
789 if (RT_FAILURE(rc))
790 return rc;
791 rc = pgmR3MapIntermediateCheckOne(pVM, (uintptr_t)HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
792 if (RT_FAILURE(rc))
793 return rc;
794
795 /*
796 * Everythings fine, do the mapping.
797 */
798 pgmR3MapIntermediateDoOne(pVM, uAddress, HCPhys, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
799 pgmR3MapIntermediateDoOne(pVM, (uintptr_t)HCPhys, HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
800
801 return VINF_SUCCESS;
802}
803
804
805/**
806 * Validates that there are no conflicts for this mapping into the intermediate context.
807 *
808 * @returns VBox status code.
809 * @param pVM The cross context VM structure.
810 * @param uAddress Address of the mapping.
811 * @param cPages Number of pages.
812 * @param pPTDefault Pointer to the default page table for this mapping.
813 * @param pPTPaeDefault Pointer to the default page table for this mapping.
814 */
815static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
816{
817 AssertMsg((uAddress >> X86_PD_SHIFT) + cPages <= 1024, ("64-bit fixme uAddress=%RGv cPages=%u\n", uAddress, cPages));
818
819 /*
820 * Check that the ranges are available.
821 * (This code doesn't have to be fast.)
822 */
823 while (cPages > 0)
824 {
825 /*
826 * 32-Bit.
827 */
828 unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
829 unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
830 PX86PT pPT = pPTDefault;
831 if (pVM->pgm.s.pInterPD->a[iPDE].u)
832 {
833 RTHCPHYS HCPhysPT = pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK;
834 if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]))
835 pPT = pVM->pgm.s.apInterPTs[0];
836 else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]))
837 pPT = pVM->pgm.s.apInterPTs[1];
838 else
839 {
840 /** @todo this must be handled with a relocation of the conflicting mapping!
841 * Which of course cannot be done because we're in the middle of the initialization. bad design! */
842 AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%RHv\n", uAddress),
843 VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
844 }
845 }
846 if (pPT->a[iPTE].u)
847 AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%RHv pPT->a[iPTE].u=%RX32\n", iPTE, iPDE, uAddress, pPT->a[iPTE].u),
848 VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
849
850 /*
851 * PAE.
852 */
853 const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
854 iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
855 iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
856 Assert(iPDPE < 4);
857 Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
858 PX86PTPAE pPTPae = pPTPaeDefault;
859 if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
860 {
861 RTHCPHYS HCPhysPT = pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK;
862 if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
863 pPTPae = pVM->pgm.s.apInterPaePTs[0];
864 else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
865 pPTPae = pVM->pgm.s.apInterPaePTs[1];
866 else
867 {
868 /** @todo this must be handled with a relocation of the conflicting mapping!
869 * Which of course cannot be done because we're in the middle of the initialization. bad design! */
870 AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%RHv\n", uAddress),
871 VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
872 }
873 }
874 if (pPTPae->a[iPTE].u)
875 AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%RHv pPTPae->a[iPTE].u=%#RX64\n", iPTE, iPDE, uAddress, pPTPae->a[iPTE].u),
876 VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
877
878 /* next */
879 uAddress += PAGE_SIZE;
880 cPages--;
881 }
882
883 return VINF_SUCCESS;
884}
885
886
887
888/**
889 * Sets up the intermediate page tables for a verified mapping.
890 *
891 * @param pVM The cross context VM structure.
892 * @param uAddress Address of the mapping.
893 * @param HCPhys The physical address of the page range.
894 * @param cPages Number of pages.
895 * @param pPTDefault Pointer to the default page table for this mapping.
896 * @param pPTPaeDefault Pointer to the default page table for this mapping.
897 */
898static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
899{
900 while (cPages > 0)
901 {
902 /*
903 * 32-Bit.
904 */
905 unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
906 unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
907 PX86PT pPT;
908 if (pVM->pgm.s.pInterPD->a[iPDE].u)
909 pPT = (PX86PT)MMPagePhys2Page(pVM, pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK);
910 else
911 {
912 pVM->pgm.s.pInterPD->a[iPDE].u = X86_PDE_P | X86_PDE_A | X86_PDE_RW
913 | (uint32_t)MMPage2Phys(pVM, pPTDefault);
914 pPT = pPTDefault;
915 }
916 pPT->a[iPTE].u = X86_PTE_P | X86_PTE_RW | X86_PTE_A | X86_PTE_D | (uint32_t)HCPhys;
917
918 /*
919 * PAE
920 */
921 const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
922 iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
923 iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
924 Assert(iPDPE < 4);
925 Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
926 PX86PTPAE pPTPae;
927 if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
928 pPTPae = (PX86PTPAE)MMPagePhys2Page(pVM, pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK);
929 else
930 {
931 pPTPae = pPTPaeDefault;
932 pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u = X86_PDE_P | X86_PDE_A | X86_PDE_RW
933 | MMPage2Phys(pVM, pPTPaeDefault);
934 }
935 pPTPae->a[iPTE].u = X86_PTE_P | X86_PTE_RW | X86_PTE_A | X86_PTE_D | HCPhys;
936
937 /* next */
938 cPages--;
939 HCPhys += PAGE_SIZE;
940 uAddress += PAGE_SIZE;
941 }
942}
943
944
945/**
946 * Clears all PDEs involved with the mapping in the shadow and intermediate page tables.
947 *
948 * @param pVM The cross context VM structure.
949 * @param pMap Pointer to the mapping in question.
950 * @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
951 */
952static void pgmR3MapClearPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iOldPDE)
953{
954 unsigned i = pMap->cPTs;
955 PVMCPU pVCpu = VMMGetCpu(pVM);
956 pgmLock(pVM); /* to avoid assertions */
957
958 pgmMapClearShadowPDEs(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pMap, iOldPDE, false /*fDeactivateCR3*/);
959
960 iOldPDE += i;
961 while (i-- > 0)
962 {
963 iOldPDE--;
964
965 /*
966 * 32-bit.
967 */
968 pVM->pgm.s.pInterPD->a[iOldPDE].u = 0;
969
970 /*
971 * PAE.
972 */
973 const unsigned iPD = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
974 unsigned iPDE = iOldPDE * 2 % 512;
975 pVM->pgm.s.apInterPaePDs[iPD]->a[iPDE].u = 0;
976 iPDE++;
977 AssertFatal(iPDE < 512);
978 pVM->pgm.s.apInterPaePDs[iPD]->a[iPDE].u = 0;
979 }
980
981 pgmUnlock(pVM);
982}
983
984
985/**
986 * Sets all PDEs involved with the mapping in the shadow and intermediate page tables.
987 *
988 * @param pVM The cross context VM structure.
989 * @param pMap Pointer to the mapping in question.
990 * @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
991 */
992static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
993{
994 PPGM pPGM = &pVM->pgm.s;
995# ifdef VBOX_STRICT
996 PVMCPU pVCpu = VMMGetCpu(pVM);
997# endif
998 pgmLock(pVM); /* to avoid assertions */
999
1000 Assert(!pgmMapAreMappingsEnabled(pVM) || PGMGetGuestMode(pVCpu) <= PGMMODE_PAE_NX);
1001
1002 pgmMapSetShadowPDEs(pVM, pMap, iNewPDE);
1003
1004 /*
1005 * Init the page tables and insert them into the page directories.
1006 */
1007 unsigned i = pMap->cPTs;
1008 iNewPDE += i;
1009 while (i-- > 0)
1010 {
1011 iNewPDE--;
1012
1013 /*
1014 * 32-bit.
1015 */
1016 X86PDE Pde;
1017 /* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
1018 Pde.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT;
1019 pPGM->pInterPD->a[iNewPDE] = Pde;
1020
1021 /*
1022 * PAE.
1023 */
1024 const unsigned iPD = iNewPDE / 256;
1025 unsigned iPDE = iNewPDE * 2 % 512;
1026 X86PDEPAE PdePae0;
1027 PdePae0.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0;
1028 pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae0;
1029 iPDE++;
1030 AssertFatal(iPDE < 512);
1031 X86PDEPAE PdePae1;
1032 PdePae1.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1;
1033 pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae1;
1034 }
1035
1036 pgmUnlock(pVM);
1037}
1038
1039
1040/**
1041 * Relocates a mapping to a new address.
1042 *
1043 * @param pVM The cross context VM structure.
1044 * @param pMapping The mapping to relocate.
1045 * @param GCPtrOldMapping The address of the start of the old mapping.
1046 * NIL_RTGCPTR if not currently mapped.
1047 * @param GCPtrNewMapping The address of the start of the new mapping.
1048 */
1049static void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping)
1050{
1051 Log(("PGM: Relocating %s from %RGv to %RGv\n", pMapping->pszDesc, GCPtrOldMapping, GCPtrNewMapping));
1052 AssertMsg(GCPtrOldMapping == pMapping->GCPtr, ("%RGv vs %RGv\n", GCPtrOldMapping, pMapping->GCPtr));
1053 AssertMsg((GCPtrOldMapping >> X86_PD_SHIFT) < X86_PG_ENTRIES, ("%RGv\n", GCPtrOldMapping));
1054 AssertMsg((GCPtrNewMapping >> X86_PD_SHIFT) < X86_PG_ENTRIES, ("%RGv\n", GCPtrOldMapping));
1055
1056 /*
1057 * Relocate the page table(s).
1058 */
1059 if (GCPtrOldMapping != NIL_RTGCPTR)
1060 pgmR3MapClearPDEs(pVM, pMapping, GCPtrOldMapping >> X86_PD_SHIFT);
1061 pgmR3MapSetPDEs(pVM, pMapping, GCPtrNewMapping >> X86_PD_SHIFT);
1062
1063 /*
1064 * Update and resort the mapping list.
1065 */
1066
1067 /* Find previous mapping for pMapping, put result into pPrevMap. */
1068 PPGMMAPPING pPrevMap = NULL;
1069 PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
1070 while (pCur && pCur != pMapping)
1071 {
1072 /* next */
1073 pPrevMap = pCur;
1074 pCur = pCur->pNextR3;
1075 }
1076 Assert(pCur);
1077
1078 /* Find mapping which >= than pMapping. */
1079 RTGCPTR GCPtrNew = GCPtrNewMapping;
1080 PPGMMAPPING pPrev = NULL;
1081 pCur = pVM->pgm.s.pMappingsR3;
1082 while (pCur && pCur->GCPtr < GCPtrNew)
1083 {
1084 /* next */
1085 pPrev = pCur;
1086 pCur = pCur->pNextR3;
1087 }
1088
1089 if (pCur != pMapping && pPrev != pMapping)
1090 {
1091 /*
1092 * Unlink.
1093 */
1094 if (pPrevMap)
1095 {
1096 pPrevMap->pNextR3 = pMapping->pNextR3;
1097 pPrevMap->pNextRC = pMapping->pNextRC;
1098 pPrevMap->pNextR0 = pMapping->pNextR0;
1099 }
1100 else
1101 {
1102 pVM->pgm.s.pMappingsR3 = pMapping->pNextR3;
1103 pVM->pgm.s.pMappingsRC = pMapping->pNextRC;
1104 pVM->pgm.s.pMappingsR0 = pMapping->pNextR0;
1105 }
1106
1107 /*
1108 * Link
1109 */
1110 pMapping->pNextR3 = pCur;
1111 if (pPrev)
1112 {
1113 pMapping->pNextRC = pPrev->pNextRC;
1114 pMapping->pNextR0 = pPrev->pNextR0;
1115 pPrev->pNextR3 = pMapping;
1116 pPrev->pNextRC = MMHyperR3ToRC(pVM, pMapping);
1117 pPrev->pNextR0 = MMHyperR3ToR0(pVM, pMapping);
1118 }
1119 else
1120 {
1121 pMapping->pNextRC = pVM->pgm.s.pMappingsRC;
1122 pMapping->pNextR0 = pVM->pgm.s.pMappingsR0;
1123 pVM->pgm.s.pMappingsR3 = pMapping;
1124 pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pMapping);
1125 pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pMapping);
1126 }
1127 }
1128
1129 /*
1130 * Update the entry.
1131 */
1132 pMapping->GCPtr = GCPtrNew;
1133 pMapping->GCPtrLast = GCPtrNew + pMapping->cb - 1;
1134
1135 /*
1136 * Callback to execute the relocation.
1137 */
1138 pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_RELOCATE, pMapping->pvUser);
1139}
1140
1141
1142/**
1143 * Checks if a new mapping address wasn't previously used and caused a clash with guest mappings.
1144 *
1145 * @returns VBox status code.
1146 * @param pMapping The mapping which conflicts.
1147 * @param GCPtr New mapping address to try
1148 */
1149bool pgmR3MapIsKnownConflictAddress(PPGMMAPPING pMapping, RTGCPTR GCPtr)
1150{
1151 for (unsigned i = 0; i < RT_ELEMENTS(pMapping->aGCPtrConflicts); i++)
1152 {
1153 if (GCPtr == pMapping->aGCPtrConflicts[i])
1154 return true;
1155 }
1156 return false;
1157}
1158
1159
1160/**
1161 * Resolves a conflict between a page table based GC mapping and
1162 * the Guest OS page tables. (32 bits version)
1163 *
1164 * @returns VBox status code.
1165 * @param pVM The cross context VM structure.
1166 * @param pMapping The mapping which conflicts.
1167 * @param pPDSrc The page directory of the guest OS.
1168 * @param GCPtrOldMapping The address of the start of the current mapping.
1169 */
1170int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping)
1171{
1172 STAM_REL_COUNTER_INC(&pVM->pgm.s.cRelocations);
1173 STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3ResolveConflict, a);
1174
1175 /* Raw mode only which implies one VCPU. */
1176 Assert(pVM->cCpus == 1);
1177
1178 pMapping->aGCPtrConflicts[pMapping->cConflicts & (PGMMAPPING_CONFLICT_MAX-1)] = GCPtrOldMapping;
1179 pMapping->cConflicts++;
1180
1181 /*
1182 * Scan for free page directory entries.
1183 *
1184 * Note that we do not support mappings at the very end of the
1185 * address space since that will break our GCPtrEnd assumptions.
1186 */
1187 const unsigned cPTs = pMapping->cPTs;
1188 unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
1189 while (iPDNew-- > 0)
1190 {
1191 if (pPDSrc->a[iPDNew].n.u1Present)
1192 continue;
1193
1194 if (pgmR3MapIsKnownConflictAddress(pMapping, iPDNew << X86_PD_SHIFT))
1195 continue;
1196
1197 if (cPTs > 1)
1198 {
1199 bool fOk = true;
1200 for (unsigned i = 1; fOk && i < cPTs; i++)
1201 if (pPDSrc->a[iPDNew + i].n.u1Present)
1202 fOk = false;
1203 if (!fOk)
1204 continue;
1205 }
1206
1207 /*
1208 * Check that it's not conflicting with an intermediate page table mapping.
1209 */
1210 bool fOk = true;
1211 unsigned i = cPTs;
1212 while (fOk && i-- > 0)
1213 fOk = !pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present;
1214 if (!fOk)
1215 continue;
1216 /** @todo AMD64 should check the PAE directories and skip the 32bit stuff. */
1217
1218 /*
1219 * Ask for the mapping.
1220 */
1221 RTGCPTR GCPtrNewMapping = (RTGCPTR32)iPDNew << X86_PD_SHIFT;
1222
1223 if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
1224 {
1225 pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
1226 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3ResolveConflict, a);
1227 return VINF_SUCCESS;
1228 }
1229 }
1230
1231 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3ResolveConflict, a);
1232# ifdef DEBUG_bird
1233 /*
1234 * Ended up here frequently recently with an NT4.0 VM (using SMP kernel).
1235 *
1236 * The problem is when enabling large pages (i.e. updating CR4) using the
1237 * _Ki386EnableCurrentLargePage@8 assembly routine (address 0x801c97ad-9).
1238 * The routine loads a sparsely popuplated page tables with identiy mappings
1239 * of its own code, most entries are whatever ExAllocatePool returned, which
1240 * is documented as undefined but all 0xffffffff in this case. Once loaded,
1241 * it jumps to the physical code address, disables paging, set CR4.PSE=1,
1242 * re-enables paging, restore the original page table and returns successfully.
1243 *
1244 * Theory: if CSAM/PATM patches the pushf;cli;mov eax,cr3; sequence, at the
1245 * start of that function we're apparently in trouble, if CSAM/PATM doesn't
1246 * we're switching back to REM and doing disabling of paging there instead.
1247 *
1248 * Normal PD: CR3=00030000; Problematic identity mapped PD: CR3=0x5fa000.
1249 */
1250 DBGFSTOP(pVM);
1251# endif
1252 AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, cPTs));
1253 return VERR_PGM_NO_HYPERVISOR_ADDRESS;
1254}
1255
1256
1257/**
1258 * Resolves a conflict between a page table based GC mapping and
1259 * the Guest OS page tables. (PAE bits version)
1260 *
1261 * @returns VBox status code.
1262 * @param pVM The cross context VM structure.
1263 * @param pMapping The mapping which conflicts.
1264 * @param GCPtrOldMapping The address of the start of the current mapping.
1265 */
1266int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping)
1267{
1268 STAM_REL_COUNTER_INC(&pVM->pgm.s.cRelocations);
1269 STAM_PROFILE_START(&pVM->pgm.s.StatR3ResolveConflict, a);
1270
1271 /* Raw mode only which implies one VCPU. */
1272 Assert(pVM->cCpus == 1);
1273 PVMCPU pVCpu = VMMGetCpu(pVM);
1274
1275 pMapping->aGCPtrConflicts[pMapping->cConflicts & (PGMMAPPING_CONFLICT_MAX-1)] = GCPtrOldMapping;
1276 pMapping->cConflicts++;
1277
1278 for (int iPDPTE = X86_PG_PAE_PDPE_ENTRIES - 1; iPDPTE >= 0; iPDPTE--)
1279 {
1280 unsigned iPDSrc;
1281 PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, (RTGCPTR32)iPDPTE << X86_PDPT_SHIFT, &iPDSrc, NULL);
1282
1283 /*
1284 * Scan for free page directory entries.
1285 *
1286 * Note that we do not support mappings at the very end of the
1287 * address space since that will break our GCPtrEnd assumptions.
1288 * Nor do we support mappings crossing page directories.
1289 */
1290 const unsigned cPTs = pMapping->cb >> X86_PD_PAE_SHIFT;
1291 unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
1292
1293 while (iPDNew-- > 0)
1294 {
1295 /* Ugly assumption that mappings start on a 4 MB boundary. */
1296 if (iPDNew & 1)
1297 continue;
1298
1299 if (pgmR3MapIsKnownConflictAddress(pMapping, ((RTGCPTR32)iPDPTE << X86_PDPT_SHIFT) + (iPDNew << X86_PD_PAE_SHIFT)))
1300 continue;
1301
1302 if (pPDSrc)
1303 {
1304 if (pPDSrc->a[iPDNew].n.u1Present)
1305 continue;
1306 if (cPTs > 1)
1307 {
1308 bool fOk = true;
1309 for (unsigned i = 1; fOk && i < cPTs; i++)
1310 if (pPDSrc->a[iPDNew + i].n.u1Present)
1311 fOk = false;
1312 if (!fOk)
1313 continue;
1314 }
1315 }
1316 /*
1317 * Check that it's not conflicting with an intermediate page table mapping.
1318 */
1319 bool fOk = true;
1320 unsigned i = cPTs;
1321 while (fOk && i-- > 0)
1322 fOk = !pVM->pgm.s.apInterPaePDs[iPDPTE]->a[iPDNew + i].n.u1Present;
1323 if (!fOk)
1324 continue;
1325
1326 /*
1327 * Ask for the mapping.
1328 */
1329 RTGCPTR GCPtrNewMapping = ((RTGCPTR32)iPDPTE << X86_PDPT_SHIFT) + ((RTGCPTR32)iPDNew << X86_PD_PAE_SHIFT);
1330
1331 if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
1332 {
1333 pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
1334 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3ResolveConflict, a);
1335 return VINF_SUCCESS;
1336 }
1337 }
1338 }
1339 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3ResolveConflict, a);
1340 AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, pMapping->cb >> X86_PD_PAE_SHIFT));
1341 return VERR_PGM_NO_HYPERVISOR_ADDRESS;
1342}
1343
1344
1345/**
1346 * Read memory from the guest mappings.
1347 *
1348 * This will use the page tables associated with the mappings to
1349 * read the memory. This means that not all kind of memory is readable
1350 * since we don't necessarily know how to convert that physical address
1351 * to a HC virtual one.
1352 *
1353 * @returns VBox status code.
1354 * @param pVM The cross context VM structure.
1355 * @param pvDst The destination address (HC of course).
1356 * @param GCPtrSrc The source address (GC virtual address).
1357 * @param cb Number of bytes to read.
1358 *
1359 * @remarks The is indirectly for DBGF only.
1360 * @todo Consider renaming it to indicate it's special usage, or just
1361 * reimplement it in MMR3HyperReadGCVirt.
1362 */
1363VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
1364{
1365 /*
1366 * Simplicity over speed... Chop the request up into chunks
1367 * which don't cross pages.
1368 */
1369 if (cb + (GCPtrSrc & PAGE_OFFSET_MASK) > PAGE_SIZE)
1370 {
1371 for (;;)
1372 {
1373 size_t cbRead = RT_MIN(cb, PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK));
1374 int rc = PGMR3MapRead(pVM, pvDst, GCPtrSrc, cbRead);
1375 if (RT_FAILURE(rc))
1376 return rc;
1377 cb -= cbRead;
1378 if (!cb)
1379 break;
1380 pvDst = (char *)pvDst + cbRead;
1381 GCPtrSrc += cbRead;
1382 }
1383 return VINF_SUCCESS;
1384 }
1385
1386 /*
1387 * Find the mapping.
1388 */
1389 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
1390 while (pCur)
1391 {
1392 RTGCPTR off = GCPtrSrc - pCur->GCPtr;
1393 if (off < pCur->cb)
1394 {
1395 if (off + cb > pCur->cb)
1396 {
1397 AssertMsgFailed(("Invalid page range %RGv LB%#x. mapping '%s' %RGv to %RGv\n",
1398 GCPtrSrc, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast));
1399 return VERR_INVALID_PARAMETER;
1400 }
1401
1402 unsigned iPT = off >> X86_PD_SHIFT;
1403 unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
1404 while (cb > 0 && iPTE < RT_ELEMENTS(CTXALLSUFF(pCur->aPTs[iPT].pPT)->a))
1405 {
1406 PCPGMSHWPTEPAE pPte = &pCur->aPTs[iPT].CTXALLSUFF(paPaePTs)[iPTE / 512].a[iPTE % 512];
1407 if (!PGMSHWPTEPAE_IS_P(*pPte))
1408 return VERR_PAGE_NOT_PRESENT;
1409 RTHCPHYS HCPhys = PGMSHWPTEPAE_GET_HCPHYS(*pPte);
1410
1411 /*
1412 * Get the virtual page from the physical one.
1413 */
1414 void *pvPage;
1415 int rc = MMR3HCPhys2HCVirt(pVM, HCPhys, &pvPage);
1416 if (RT_FAILURE(rc))
1417 return rc;
1418
1419 memcpy(pvDst, (char *)pvPage + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
1420 return VINF_SUCCESS;
1421 }
1422 }
1423
1424 /* next */
1425 pCur = CTXALLSUFF(pCur->pNext);
1426 }
1427
1428 return VERR_INVALID_POINTER;
1429}
1430
1431
1432/**
1433 * Info callback for 'pgmhandlers'.
1434 *
1435 * @param pVM The cross context VM structure.
1436 * @param pHlp The output helpers.
1437 * @param pszArgs The arguments. phys or virt.
1438 */
1439DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1440{
1441 NOREF(pszArgs);
1442 if (!pgmMapAreMappingsEnabled(pVM))
1443 pHlp->pfnPrintf(pHlp, "\nThe mappings are DISABLED.\n");
1444 else if (pVM->pgm.s.fMappingsFixed)
1445 pHlp->pfnPrintf(pHlp, "\nThe mappings are FIXED: %RGv-%RGv\n",
1446 pVM->pgm.s.GCPtrMappingFixed, pVM->pgm.s.GCPtrMappingFixed + pVM->pgm.s.cbMappingFixed - 1);
1447 else if (pVM->pgm.s.fMappingsFixedRestored)
1448 pHlp->pfnPrintf(pHlp, "\nThe mappings are FLOATING-RESTORED-FIXED: %RGv-%RGv\n",
1449 pVM->pgm.s.GCPtrMappingFixed, pVM->pgm.s.GCPtrMappingFixed + pVM->pgm.s.cbMappingFixed - 1);
1450 else
1451 pHlp->pfnPrintf(pHlp, "\nThe mappings are FLOATING.\n");
1452
1453 PPGMMAPPING pCur;
1454 for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1455 {
1456 pHlp->pfnPrintf(pHlp, "%RGv - %RGv %s\n", pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
1457 if (pCur->cConflicts > 0)
1458 {
1459 pHlp->pfnPrintf(pHlp, " %u conflict%s: ", pCur->cConflicts, pCur->cConflicts == 1 ? "" : "s");
1460 uint32_t cLeft = RT_MIN(pCur->cConflicts, RT_ELEMENTS(pCur->aGCPtrConflicts));
1461 uint32_t i = pCur->cConflicts;
1462 while (cLeft-- > 0)
1463 {
1464 i = (i - 1) & (PGMMAPPING_CONFLICT_MAX - 1);
1465 pHlp->pfnPrintf(pHlp, cLeft ? "%RGv, " : "%RGv\n", pCur->aGCPtrConflicts[i]);
1466 }
1467 }
1468 }
1469}
1470
1471#endif /* !PGM_WITHOUT_MAPPINGS */
1472
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