VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 80191

Last change on this file since 80191 was 80191, checked in by vboxsync, 5 years ago

VMM/r3: Refactored VMCPU enumeration in preparation that aCpus will be replaced with a pointer array. Removed two raw-mode offset members from the CPUM and CPUMCPU sub-structures. bugref:9217 bugref:9517

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1/* $Id: PGM.cpp 80191 2019-08-08 00:36:57Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/** @page pg_pgm PGM - The Page Manager and Monitor
20 *
21 * @sa @ref grp_pgm
22 * @subpage pg_pgm_pool
23 * @subpage pg_pgm_phys
24 *
25 *
26 * @section sec_pgm_modes Paging Modes
27 *
28 * There are three memory contexts: Host Context (HC), Guest Context (GC)
29 * and intermediate context. When talking about paging HC can also be referred
30 * to as "host paging", and GC referred to as "shadow paging".
31 *
32 * We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33 * is defined by the host operating system. The mode used in the shadow paging mode
34 * depends on the host paging mode and what the mode the guest is currently in. The
35 * following relation between the two is defined:
36 *
37 * @verbatim
38 Host > 32-bit | PAE | AMD64 |
39 Guest | | | |
40 ==v================================
41 32-bit 32-bit PAE PAE
42 -------|--------|--------|--------|
43 PAE PAE PAE PAE
44 -------|--------|--------|--------|
45 AMD64 AMD64 AMD64 AMD64
46 -------|--------|--------|--------| @endverbatim
47 *
48 * All configuration except those in the diagonal (upper left) are expected to
49 * require special effort from the switcher (i.e. a bit slower).
50 *
51 *
52 *
53 *
54 * @section sec_pgm_shw The Shadow Memory Context
55 *
56 *
57 * [..]
58 *
59 * Because of guest context mappings requires PDPT and PML4 entries to allow
60 * writing on AMD64, the two upper levels will have fixed flags whatever the
61 * guest is thinking of using there. So, when shadowing the PD level we will
62 * calculate the effective flags of PD and all the higher levels. In legacy
63 * PAE mode this only applies to the PWT and PCD bits (the rest are
64 * ignored/reserved/MBZ). We will ignore those bits for the present.
65 *
66 *
67 *
68 * @section sec_pgm_int The Intermediate Memory Context
69 *
70 * The world switch goes thru an intermediate memory context which purpose it is
71 * to provide different mappings of the switcher code. All guest mappings are also
72 * present in this context.
73 *
74 * The switcher code is mapped at the same location as on the host, at an
75 * identity mapped location (physical equals virtual address), and at the
76 * hypervisor location. The identity mapped location is for when the world
77 * switches that involves disabling paging.
78 *
79 * PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80 * simplifies switching guest CPU mode and consistency at the cost of more
81 * code to do the work. All memory use for those page tables is located below
82 * 4GB (this includes page tables for guest context mappings).
83 *
84 * Note! The intermediate memory context is also used for 64-bit guest
85 * execution on 32-bit hosts. Because we need to load 64-bit registers
86 * prior to switching to guest context, we need to be in 64-bit mode
87 * first. So, HM has some 64-bit worker routines in VMMRC.rc that get
88 * invoked via the special world switcher code in LegacyToAMD64.asm.
89 *
90 *
91 * @subsection subsec_pgm_int_gc Guest Context Mappings
92 *
93 * During assignment and relocation of a guest context mapping the intermediate
94 * memory context is used to verify the new location.
95 *
96 * Guest context mappings are currently restricted to below 4GB, for reasons
97 * of simplicity. This may change when we implement AMD64 support.
98 *
99 *
100 *
101 *
102 * @section sec_pgm_misc Misc
103 *
104 *
105 * @subsection sec_pgm_misc_A20 The A20 Gate
106 *
107 * PGM implements the A20 gate masking when translating a virtual guest address
108 * into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
109 * the code reading the guest page table entries during shadowing. The masking
110 * is done consistenly for all CPU modes, paged ones included. Large pages are
111 * also masked correctly. (On current CPUs, experiments indicates that AMD does
112 * not apply A20M in paged modes and intel only does it for the 2nd MB of
113 * memory.)
114 *
115 * The A20 gate implementation is per CPU core. It can be configured on a per
116 * core basis via the keyboard device and PC architecture device. This is
117 * probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
118 * guest OSes try pushing things anyway, so who cares. (On current real systems
119 * the A20M signal is probably only sent to the boot CPU and it affects all
120 * thread and probably all cores in that package.)
121 *
122 * The keyboard device and the PC architecture device doesn't OR their A20
123 * config bits together, rather they are currently implemented such that they
124 * mirror the CPU state. So, flipping the bit in either of them will change the
125 * A20 state. (On real hardware the bits of the two devices should probably be
126 * ORed together to indicate enabled, i.e. both needs to be cleared to disable
127 * A20 masking.)
128 *
129 * The A20 state will change immediately, transmeta fashion. There is no delays
130 * due to buses, wiring or other physical stuff. (On real hardware there are
131 * normally delays, the delays differs between the two devices and probably also
132 * between chipsets and CPU generations. Note that it's said that transmeta CPUs
133 * does the change immediately like us, they apparently intercept/handles the
134 * port accesses in microcode. Neat.)
135 *
136 * @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
137 *
138 *
139 * @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
140 *
141 * The differences between legacy PAE and long mode PAE are:
142 * -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
143 * all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
144 * usual meanings while 6 is ignored (AMD). This means that upon switching to
145 * legacy PAE mode we'll have to clear these bits and when going to long mode
146 * they must be set. This applies to both intermediate and shadow contexts,
147 * however we don't need to do it for the intermediate one since we're
148 * executing with CR0.WP at that time.
149 * -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
150 * a page aligned one is required.
151 *
152 *
153 * @section sec_pgm_handlers Access Handlers
154 *
155 * Placeholder.
156 *
157 *
158 * @subsection sec_pgm_handlers_phys Physical Access Handlers
159 *
160 * Placeholder.
161 *
162 *
163 * @subsection sec_pgm_handlers_virt Virtual Access Handlers (obsolete)
164 *
165 * We currently implement three types of virtual access handlers: ALL, WRITE
166 * and HYPERVISOR (WRITE). See PGMVIRTHANDLERKIND for some more details.
167 *
168 * The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
169 * to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
170 * a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
171 * rest of this section is going to be about these handlers.
172 *
173 * We'll go thru the life cycle of a handler and try make sense of it all, don't know
174 * how successful this is gonna be...
175 *
176 * 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
177 * PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
178 * and create a new node that is inserted into the AVL tree (range key). Then
179 * a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
180 *
181 * 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
182 *
183 * 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
184 * via the current guest CR3 and update the physical page -> virtual handler
185 * translation. Needless to say, this doesn't exactly scale very well. If any changes
186 * are detected, it will flag a virtual bit update just like we did on registration.
187 * PGMPHYS pages with changes will have their virtual handler state reset to NONE.
188 *
189 * 2b. The virtual bit update process will iterate all the pages covered by all the
190 * virtual handlers and update the PGMPAGE virtual handler state to the max of all
191 * virtual handlers on that page.
192 *
193 * 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
194 * we don't miss any alias mappings of the monitored pages.
195 *
196 * 2d. SyncCR3 will then proceed with syncing the CR3 table.
197 *
198 * 3. \#PF(np,read) on a page in the range. This will cause it to be synced
199 * read-only and resumed if it's a WRITE handler. If it's an ALL handler we
200 * will call the handlers like in the next step. If the physical mapping has
201 * changed we will - some time in the future - perform a handler callback
202 * (optional) and update the physical -> virtual handler cache.
203 *
204 * 4. \#PF(,write) on a page in the range. This will cause the handler to
205 * be invoked.
206 *
207 * 5. The guest invalidates the page and changes the physical backing or
208 * unmaps it. This should cause the invalidation callback to be invoked
209 * (it might not yet be 100% perfect). Exactly what happens next... is
210 * this where we mess up and end up out of sync for a while?
211 *
212 * 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
213 * We will then set all PGMPAGEs in the physical -> virtual handler cache for
214 * this handler to NONE and trigger a full PGM resync (basically the same
215 * as int step 1). Which means 2 is executed again.
216 *
217 *
218 * @subsubsection sub_sec_pgm_handler_virt_todo TODOs
219 *
220 * There is a bunch of things that needs to be done to make the virtual handlers
221 * work 100% correctly and work more efficiently.
222 *
223 * The first bit hasn't been implemented yet because it's going to slow the
224 * whole mess down even more, and besides it seems to be working reliably for
225 * our current uses. OTOH, some of the optimizations might end up more or less
226 * implementing the missing bits, so we'll see.
227 *
228 * On the optimization side, the first thing to do is to try avoid unnecessary
229 * cache flushing. Then try team up with the shadowing code to track changes
230 * in mappings by means of access to them (shadow in), updates to shadows pages,
231 * invlpg, and shadow PT discarding (perhaps).
232 *
233 * Some idea that have popped up for optimization for current and new features:
234 * - bitmap indicating where there are virtual handlers installed.
235 * (4KB => 2**20 pages, page 2**12 => covers 32-bit address space 1:1!)
236 * - Further optimize this by min/max (needs min/max avl getters).
237 * - Shadow page table entry bit (if any left)?
238 *
239 */
240
241
242/** @page pg_pgm_phys PGM Physical Guest Memory Management
243 *
244 *
245 * Objectives:
246 * - Guest RAM over-commitment using memory ballooning,
247 * zero pages and general page sharing.
248 * - Moving or mirroring a VM onto a different physical machine.
249 *
250 *
251 * @section sec_pgmPhys_Definitions Definitions
252 *
253 * Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
254 * machinery associated with it.
255 *
256 *
257 *
258 *
259 * @section sec_pgmPhys_AllocPage Allocating a page.
260 *
261 * Initially we map *all* guest memory to the (per VM) zero page, which
262 * means that none of the read functions will cause pages to be allocated.
263 *
264 * Exception, access bit in page tables that have been shared. This must
265 * be handled, but we must also make sure PGMGst*Modify doesn't make
266 * unnecessary modifications.
267 *
268 * Allocation points:
269 * - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
270 * - Replacing a zero page mapping at \#PF.
271 * - Replacing a shared page mapping at \#PF.
272 * - ROM registration (currently MMR3RomRegister).
273 * - VM restore (pgmR3Load).
274 *
275 * For the first three it would make sense to keep a few pages handy
276 * until we've reached the max memory commitment for the VM.
277 *
278 * For the ROM registration, we know exactly how many pages we need
279 * and will request these from ring-0. For restore, we will save
280 * the number of non-zero pages in the saved state and allocate
281 * them up front. This would allow the ring-0 component to refuse
282 * the request if the isn't sufficient memory available for VM use.
283 *
284 * Btw. for both ROM and restore allocations we won't be requiring
285 * zeroed pages as they are going to be filled instantly.
286 *
287 *
288 * @section sec_pgmPhys_FreePage Freeing a page
289 *
290 * There are a few points where a page can be freed:
291 * - After being replaced by the zero page.
292 * - After being replaced by a shared page.
293 * - After being ballooned by the guest additions.
294 * - At reset.
295 * - At restore.
296 *
297 * When freeing one or more pages they will be returned to the ring-0
298 * component and replaced by the zero page.
299 *
300 * The reasoning for clearing out all the pages on reset is that it will
301 * return us to the exact same state as on power on, and may thereby help
302 * us reduce the memory load on the system. Further it might have a
303 * (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
304 *
305 * On restore, as mention under the allocation topic, pages should be
306 * freed / allocated depending on how many is actually required by the
307 * new VM state. The simplest approach is to do like on reset, and free
308 * all non-ROM pages and then allocate what we need.
309 *
310 * A measure to prevent some fragmentation, would be to let each allocation
311 * chunk have some affinity towards the VM having allocated the most pages
312 * from it. Also, try make sure to allocate from allocation chunks that
313 * are almost full. Admittedly, both these measures might work counter to
314 * our intentions and its probably not worth putting a lot of effort,
315 * cpu time or memory into this.
316 *
317 *
318 * @section sec_pgmPhys_SharePage Sharing a page
319 *
320 * The basic idea is that there there will be a idle priority kernel
321 * thread walking the non-shared VM pages hashing them and looking for
322 * pages with the same checksum. If such pages are found, it will compare
323 * them byte-by-byte to see if they actually are identical. If found to be
324 * identical it will allocate a shared page, copy the content, check that
325 * the page didn't change while doing this, and finally request both the
326 * VMs to use the shared page instead. If the page is all zeros (special
327 * checksum and byte-by-byte check) it will request the VM that owns it
328 * to replace it with the zero page.
329 *
330 * To make this efficient, we will have to make sure not to try share a page
331 * that will change its contents soon. This part requires the most work.
332 * A simple idea would be to request the VM to write monitor the page for
333 * a while to make sure it isn't modified any time soon. Also, it may
334 * make sense to skip pages that are being write monitored since this
335 * information is readily available to the thread if it works on the
336 * per-VM guest memory structures (presently called PGMRAMRANGE).
337 *
338 *
339 * @section sec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
340 *
341 * The pages are organized in allocation chunks in ring-0, this is a necessity
342 * if we wish to have an OS agnostic approach to this whole thing. (On Linux we
343 * could easily work on a page-by-page basis if we liked. Whether this is possible
344 * or efficient on NT I don't quite know.) Fragmentation within these chunks may
345 * become a problem as part of the idea here is that we wish to return memory to
346 * the host system.
347 *
348 * For instance, starting two VMs at the same time, they will both allocate the
349 * guest memory on-demand and if permitted their page allocations will be
350 * intermixed. Shut down one of the two VMs and it will be difficult to return
351 * any memory to the host system because the page allocation for the two VMs are
352 * mixed up in the same allocation chunks.
353 *
354 * To further complicate matters, when pages are freed because they have been
355 * ballooned or become shared/zero the whole idea is that the page is supposed
356 * to be reused by another VM or returned to the host system. This will cause
357 * allocation chunks to contain pages belonging to different VMs and prevent
358 * returning memory to the host when one of those VM shuts down.
359 *
360 * The only way to really deal with this problem is to move pages. This can
361 * either be done at VM shutdown and or by the idle priority worker thread
362 * that will be responsible for finding sharable/zero pages. The mechanisms
363 * involved for coercing a VM to move a page (or to do it for it) will be
364 * the same as when telling it to share/zero a page.
365 *
366 *
367 * @section sec_pgmPhys_Tracking Tracking Structures And Their Cost
368 *
369 * There's a difficult balance between keeping the per-page tracking structures
370 * (global and guest page) easy to use and keeping them from eating too much
371 * memory. We have limited virtual memory resources available when operating in
372 * 32-bit kernel space (on 64-bit there'll it's quite a different story). The
373 * tracking structures will be attempted designed such that we can deal with up
374 * to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
375 *
376 *
377 * @subsection subsec_pgmPhys_Tracking_Kernel Kernel Space
378 *
379 * @see pg_GMM
380 *
381 * @subsection subsec_pgmPhys_Tracking_PerVM Per-VM
382 *
383 * Fixed info is the physical address of the page (HCPhys) and the page id
384 * (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
385 * Today we've restricting ourselves to 40(-12) bits because this is the current
386 * restrictions of all AMD64 implementations (I think Barcelona will up this
387 * to 48(-12) bits, not that it really matters) and I needed the bits for
388 * tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
389 * decent range for the page id: 2^(28+12) = 1024TB.
390 *
391 * In additions to these, we'll have to keep maintaining the page flags as we
392 * currently do. Although it wouldn't harm to optimize these quite a bit, like
393 * for instance the ROM shouldn't depend on having a write handler installed
394 * in order for it to become read-only. A RO/RW bit should be considered so
395 * that the page syncing code doesn't have to mess about checking multiple
396 * flag combinations (ROM || RW handler || write monitored) in order to
397 * figure out how to setup a shadow PTE. But this of course, is second
398 * priority at present. Current this requires 12 bits, but could probably
399 * be optimized to ~8.
400 *
401 * Then there's the 24 bits used to track which shadow page tables are
402 * currently mapping a page for the purpose of speeding up physical
403 * access handlers, and thereby the page pool cache. More bit for this
404 * purpose wouldn't hurt IIRC.
405 *
406 * Then there is a new bit in which we need to record what kind of page
407 * this is, shared, zero, normal or write-monitored-normal. This'll
408 * require 2 bits. One bit might be needed for indicating whether a
409 * write monitored page has been written to. And yet another one or
410 * two for tracking migration status. 3-4 bits total then.
411 *
412 * Whatever is left will can be used to record the sharabilitiy of a
413 * page. The page checksum will not be stored in the per-VM table as
414 * the idle thread will not be permitted to do modifications to it.
415 * It will instead have to keep its own working set of potentially
416 * shareable pages and their check sums and stuff.
417 *
418 * For the present we'll keep the current packing of the
419 * PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
420 * we'll have to change it to a struct with a total of 128-bits at
421 * our disposal.
422 *
423 * The initial layout will be like this:
424 * @verbatim
425 RTHCPHYS HCPhys; The current stuff.
426 63:40 Current shadow PT tracking stuff.
427 39:12 The physical page frame number.
428 11:0 The current flags.
429 uint32_t u28PageId : 28; The page id.
430 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
431 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
432 uint32_t u1Reserved : 1; Reserved for later.
433 uint32_t u32Reserved; Reserved for later, mostly sharing stats.
434 @endverbatim
435 *
436 * The final layout will be something like this:
437 * @verbatim
438 RTHCPHYS HCPhys; The current stuff.
439 63:48 High page id (12+).
440 47:12 The physical page frame number.
441 11:0 Low page id.
442 uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
443 uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
444 uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
445 uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
446 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
447 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
448 uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
449 uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
450 @endverbatim
451 *
452 * Cost wise, this means we'll double the cost for guest memory. There isn't anyway
453 * around that I'm afraid. It means that the cost of dealing out 32GB of memory
454 * to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
455 * example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
456 *
457 * A couple of cost examples for the total cost per-VM + kernel.
458 * 32-bit Windows and 32-bit linux:
459 * 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
460 * 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
461 * 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
462 * 64-bit Windows and 64-bit linux:
463 * 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
464 * 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
465 * 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
466 *
467 * UPDATE - 2007-09-27:
468 * Will need a ballooned flag/state too because we cannot
469 * trust the guest 100% and reporting the same page as ballooned more
470 * than once will put the GMM off balance.
471 *
472 *
473 * @section sec_pgmPhys_Serializing Serializing Access
474 *
475 * Initially, we'll try a simple scheme:
476 *
477 * - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
478 * by the EMT thread of that VM while in the pgm critsect.
479 * - Other threads in the VM process that needs to make reliable use of
480 * the per-VM RAM tracking structures will enter the critsect.
481 * - No process external thread or kernel thread will ever try enter
482 * the pgm critical section, as that just won't work.
483 * - The idle thread (and similar threads) doesn't not need 100% reliable
484 * data when performing it tasks as the EMT thread will be the one to
485 * do the actual changes later anyway. So, as long as it only accesses
486 * the main ram range, it can do so by somehow preventing the VM from
487 * being destroyed while it works on it...
488 *
489 * - The over-commitment management, including the allocating/freeing
490 * chunks, is serialized by a ring-0 mutex lock (a fast one since the
491 * more mundane mutex implementation is broken on Linux).
492 * - A separate mutex is protecting the set of allocation chunks so
493 * that pages can be shared or/and freed up while some other VM is
494 * allocating more chunks. This mutex can be take from under the other
495 * one, but not the other way around.
496 *
497 *
498 * @section sec_pgmPhys_Request VM Request interface
499 *
500 * When in ring-0 it will become necessary to send requests to a VM so it can
501 * for instance move a page while defragmenting during VM destroy. The idle
502 * thread will make use of this interface to request VMs to setup shared
503 * pages and to perform write monitoring of pages.
504 *
505 * I would propose an interface similar to the current VMReq interface, similar
506 * in that it doesn't require locking and that the one sending the request may
507 * wait for completion if it wishes to. This shouldn't be very difficult to
508 * realize.
509 *
510 * The requests themselves are also pretty simple. They are basically:
511 * -# Check that some precondition is still true.
512 * -# Do the update.
513 * -# Update all shadow page tables involved with the page.
514 *
515 * The 3rd step is identical to what we're already doing when updating a
516 * physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
517 *
518 *
519 *
520 * @section sec_pgmPhys_MappingCaches Mapping Caches
521 *
522 * In order to be able to map in and out memory and to be able to support
523 * guest with more RAM than we've got virtual address space, we'll employing
524 * a mapping cache. Normally ring-0 and ring-3 can share the same cache,
525 * however on 32-bit darwin the ring-0 code is running in a different memory
526 * context and therefore needs a separate cache. In raw-mode context we also
527 * need a separate cache. The 32-bit darwin mapping cache and the one for
528 * raw-mode context share a lot of code, see PGMRZDYNMAP.
529 *
530 *
531 * @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
532 *
533 * We've considered implementing the ring-3 mapping cache page based but found
534 * that this was bother some when one had to take into account TLBs+SMP and
535 * portability (missing the necessary APIs on several platforms). There were
536 * also some performance concerns with this approach which hadn't quite been
537 * worked out.
538 *
539 * Instead, we'll be mapping allocation chunks into the VM process. This simplifies
540 * matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
541 * only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
542 * compared to the previous idea is that mapping or unmapping a 1MB chunk is more
543 * costly than a single page, although how much more costly is uncertain. We'll
544 * try address this by using a very big cache, preferably bigger than the actual
545 * VM RAM size if possible. The current VM RAM sizes should give some idea for
546 * 32-bit boxes, while on 64-bit we can probably get away with employing an
547 * unlimited cache.
548 *
549 * The cache have to parts, as already indicated, the ring-3 side and the
550 * ring-0 side.
551 *
552 * The ring-0 will be tied to the page allocator since it will operate on the
553 * memory objects it contains. It will therefore require the first ring-0 mutex
554 * discussed in @ref sec_pgmPhys_Serializing. We some double house keeping wrt
555 * to who has mapped what I think, since both VMMR0.r0 and RTR0MemObj will keep
556 * track of mapping relations
557 *
558 * The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
559 * require anyone that desires to do changes to the mapping cache to do that
560 * from within this critsect. Alternatively, we could employ a separate critsect
561 * for serializing changes to the mapping cache as this would reduce potential
562 * contention with other threads accessing mappings unrelated to the changes
563 * that are in process. We can see about this later, contention will show
564 * up in the statistics anyway, so it'll be simple to tell.
565 *
566 * The organization of the ring-3 part will be very much like how the allocation
567 * chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
568 * having to walk the tree all the time, we'll have a couple of lookaside entries
569 * like in we do for I/O ports and MMIO in IOM.
570 *
571 * The simplified flow of a PGMPhysRead/Write function:
572 * -# Enter the PGM critsect.
573 * -# Lookup GCPhys in the ram ranges and get the Page ID.
574 * -# Calc the Allocation Chunk ID from the Page ID.
575 * -# Check the lookaside entries and then the AVL tree for the Chunk ID.
576 * If not found in cache:
577 * -# Call ring-0 and request it to be mapped and supply
578 * a chunk to be unmapped if the cache is maxed out already.
579 * -# Insert the new mapping into the AVL tree (id + R3 address).
580 * -# Update the relevant lookaside entry and return the mapping address.
581 * -# Do the read/write according to monitoring flags and everything.
582 * -# Leave the critsect.
583 *
584 *
585 * @section sec_pgmPhys_Fallback Fallback
586 *
587 * Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
588 * API and thus require a fallback.
589 *
590 * So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
591 * will return to the ring-3 caller (and later ring-0) and asking it to seed
592 * the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
593 * then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
594 * "SeededAllocPages" call to ring-0.
595 *
596 * The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
597 * all page sharing (zero page detection will continue). It will also force
598 * all allocations to come from the VM which seeded the page. Both these
599 * measures are taken to make sure that there will never be any need for
600 * mapping anything into ring-3 - everything will be mapped already.
601 *
602 * Whether we'll continue to use the current MM locked memory management
603 * for this I don't quite know (I'd prefer not to and just ditch that all
604 * together), we'll see what's simplest to do.
605 *
606 *
607 *
608 * @section sec_pgmPhys_Changes Changes
609 *
610 * Breakdown of the changes involved?
611 */
612
613
614/*********************************************************************************************************************************
615* Header Files *
616*********************************************************************************************************************************/
617#define VBOX_BUGREF_9217_PART_I
618#define LOG_GROUP LOG_GROUP_PGM
619#include <VBox/vmm/dbgf.h>
620#include <VBox/vmm/pgm.h>
621#include <VBox/vmm/cpum.h>
622#include <VBox/vmm/iom.h>
623#include <VBox/sup.h>
624#include <VBox/vmm/mm.h>
625#include <VBox/vmm/em.h>
626#include <VBox/vmm/stam.h>
627#ifdef VBOX_WITH_REM
628# include <VBox/vmm/rem.h>
629#endif
630#include <VBox/vmm/selm.h>
631#include <VBox/vmm/ssm.h>
632#include <VBox/vmm/hm.h>
633#include "PGMInternal.h"
634#include <VBox/vmm/vm.h>
635#include <VBox/vmm/uvm.h>
636#include "PGMInline.h"
637
638#include <VBox/dbg.h>
639#include <VBox/param.h>
640#include <VBox/err.h>
641
642#include <iprt/asm.h>
643#include <iprt/asm-amd64-x86.h>
644#include <iprt/assert.h>
645#include <iprt/env.h>
646#include <iprt/mem.h>
647#include <iprt/file.h>
648#include <iprt/string.h>
649#include <iprt/thread.h>
650
651
652/*********************************************************************************************************************************
653* Structures and Typedefs *
654*********************************************************************************************************************************/
655/**
656 * Argument package for pgmR3RElocatePhysHnadler, pgmR3RelocateVirtHandler and
657 * pgmR3RelocateHyperVirtHandler.
658 */
659typedef struct PGMRELOCHANDLERARGS
660{
661 RTGCINTPTR offDelta;
662 PVM pVM;
663} PGMRELOCHANDLERARGS;
664/** Pointer to a page access handlere relocation argument package. */
665typedef PGMRELOCHANDLERARGS const *PCPGMRELOCHANDLERARGS;
666
667
668/*********************************************************************************************************************************
669* Internal Functions *
670*********************************************************************************************************************************/
671static int pgmR3InitPaging(PVM pVM);
672static int pgmR3InitStats(PVM pVM);
673static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
674static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
675static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
676#ifdef VBOX_STRICT
677static FNVMATSTATE pgmR3ResetNoMorePhysWritesFlag;
678#endif
679
680#ifdef VBOX_WITH_DEBUGGER
681static FNDBGCCMD pgmR3CmdError;
682static FNDBGCCMD pgmR3CmdSync;
683static FNDBGCCMD pgmR3CmdSyncAlways;
684# ifdef VBOX_STRICT
685static FNDBGCCMD pgmR3CmdAssertCR3;
686# endif
687static FNDBGCCMD pgmR3CmdPhysToFile;
688#endif
689
690
691/*********************************************************************************************************************************
692* Global Variables *
693*********************************************************************************************************************************/
694#ifdef VBOX_WITH_DEBUGGER
695/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
696static const DBGCVARDESC g_aPgmErrorArgs[] =
697{
698 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
699 { 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
700};
701
702static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
703{
704 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
705 { 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
706 { 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
707};
708
709# ifdef DEBUG_sandervl
710static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
711{
712 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
713 { 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
714 { 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
715};
716# endif
717
718/** Command descriptors. */
719static const DBGCCMD g_aCmds[] =
720{
721 /* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
722 { "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
723 { "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
724 { "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
725# ifdef VBOX_STRICT
726 { "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
727# ifdef VBOX_WITH_PAGE_SHARING
728 { "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
729 { "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
730# endif
731# endif
732 { "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
733 { "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
734};
735#endif
736
737
738
739
740/**
741 * Initiates the paging of VM.
742 *
743 * @returns VBox status code.
744 * @param pVM The cross context VM structure.
745 */
746VMMR3DECL(int) PGMR3Init(PVM pVM)
747{
748 LogFlow(("PGMR3Init:\n"));
749 PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
750 int rc;
751
752 /*
753 * Assert alignment and sizes.
754 */
755 AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
756 AssertCompile(sizeof(pVM->apCpusR3[0]->pgm.s) <= sizeof(pVM->apCpusR3[0]->pgm.padding));
757 AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
758
759 /*
760 * Init the structure.
761 */
762 pVM->pgm.s.offVM = RT_UOFFSETOF(VM, pgm.s);
763 pVM->pgm.s.offVCpuPGM = RT_UOFFSETOF(VMCPU, pgm.s);
764 /*pVM->pgm.s.fRestoreRomPagesAtReset = false;*/
765
766 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
767 {
768 pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_RTHCPHYS;
769 pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
770 pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
771 }
772
773 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
774 {
775 pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_RTHCPHYS;
776 pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
777 pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
778 }
779
780 /* Init the per-CPU part. */
781 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
782 {
783 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
784 PPGMCPU pPGM = &pVCpu->pgm.s;
785
786 pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
787 pPGM->offVCpu = RT_UOFFSETOF(VMCPU, pgm.s);
788 pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
789
790 pPGM->enmShadowMode = PGMMODE_INVALID;
791 pPGM->enmGuestMode = PGMMODE_INVALID;
792 pPGM->idxGuestModeData = UINT8_MAX;
793 pPGM->idxShadowModeData = UINT8_MAX;
794 pPGM->idxBothModeData = UINT8_MAX;
795
796 pPGM->GCPhysCR3 = NIL_RTGCPHYS;
797
798 pPGM->pGst32BitPdR3 = NULL;
799 pPGM->pGstPaePdptR3 = NULL;
800 pPGM->pGstAmd64Pml4R3 = NULL;
801#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
802 pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
803 pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
804 pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
805#endif
806 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
807 {
808 pPGM->apGstPaePDsR3[i] = NULL;
809#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
810 pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
811#endif
812 pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
813 pPGM->aGstPaePdpeRegs[i].u = UINT64_MAX;
814 pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
815 }
816
817 pPGM->fA20Enabled = true;
818 pPGM->GCPhysA20Mask = ~((RTGCPHYS)!pPGM->fA20Enabled << 20);
819 }
820
821 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
822 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
823 pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
824
825 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
826#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
827 true
828#else
829 false
830#endif
831 );
832 AssertLogRelRCReturn(rc, rc);
833
834#if HC_ARCH_BITS == 32
835# ifdef RT_OS_DARWIN
836 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
837# else
838 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
839# endif
840#else
841 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
842#endif
843 AssertLogRelRCReturn(rc, rc);
844 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
845 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
846
847 /*
848 * Get the configured RAM size - to estimate saved state size.
849 */
850 uint64_t cbRam;
851 rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
852 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
853 cbRam = 0;
854 else if (RT_SUCCESS(rc))
855 {
856 if (cbRam < PAGE_SIZE)
857 cbRam = 0;
858 cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
859 }
860 else
861 {
862 AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
863 return rc;
864 }
865
866 /*
867 * Check for PCI pass-through and other configurables.
868 */
869 rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
870 AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
871 AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough || pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
872
873 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "PageFusionAllowed", &pVM->pgm.s.fPageFusionAllowed, false);
874 AssertLogRelRCReturn(rc, rc);
875
876 /** @cfgm{/PGM/ZeroRamPagesOnReset, boolean, true}
877 * Whether to clear RAM pages on (hard) reset. */
878 rc = CFGMR3QueryBoolDef(pCfgPGM, "ZeroRamPagesOnReset", &pVM->pgm.s.fZeroRamPagesOnReset, true);
879 AssertLogRelRCReturn(rc, rc);
880
881#ifdef VBOX_WITH_STATISTICS
882 /*
883 * Allocate memory for the statistics before someone tries to use them.
884 */
885 size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
886 void *pv;
887 rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
888 AssertRCReturn(rc, rc);
889
890 pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
891 pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
892 pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
893
894 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
895 {
896 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
897 pVCpu->pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
898 pVCpu->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
899
900 pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
901 }
902#endif /* VBOX_WITH_STATISTICS */
903
904 /*
905 * Register callbacks, string formatters and the saved state data unit.
906 */
907#ifdef VBOX_STRICT
908 VMR3AtStateRegister(pVM->pUVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
909#endif
910 PGMRegisterStringFormatTypes();
911
912 rc = pgmR3InitSavedState(pVM, cbRam);
913 if (RT_FAILURE(rc))
914 return rc;
915
916 /*
917 * Initialize the PGM critical section and flush the phys TLBs
918 */
919 rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
920 AssertRCReturn(rc, rc);
921
922 PGMR3PhysChunkInvalidateTLB(pVM);
923 pgmPhysInvalidatePageMapTLB(pVM);
924
925 /*
926 * For the time being we sport a full set of handy pages in addition to the base
927 * memory to simplify things.
928 */
929 rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
930 AssertRCReturn(rc, rc);
931
932 /*
933 * Trees
934 */
935 rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
936 if (RT_SUCCESS(rc))
937 pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
938
939 /*
940 * Allocate the zero page.
941 */
942 if (RT_SUCCESS(rc))
943 {
944 rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
945 if (RT_SUCCESS(rc))
946 {
947 pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
948 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
949 pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
950 AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
951 }
952 }
953
954 /*
955 * Allocate the invalid MMIO page.
956 * (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
957 */
958 if (RT_SUCCESS(rc))
959 {
960 rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
961 if (RT_SUCCESS(rc))
962 {
963 ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
964 pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
965 AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
966 pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
967 }
968 }
969
970 /*
971 * Register the physical access handler protecting ROMs.
972 */
973 if (RT_SUCCESS(rc))
974 rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_WRITE,
975 pgmPhysRomWriteHandler,
976 NULL, NULL, "pgmPhysRomWritePfHandler",
977 NULL, NULL, "pgmPhysRomWritePfHandler",
978 "ROM write protection",
979 &pVM->pgm.s.hRomPhysHandlerType);
980
981 /*
982 * Init the paging.
983 */
984 if (RT_SUCCESS(rc))
985 rc = pgmR3InitPaging(pVM);
986
987 /*
988 * Init the page pool.
989 */
990 if (RT_SUCCESS(rc))
991 rc = pgmR3PoolInit(pVM);
992
993 if (RT_SUCCESS(rc))
994 {
995 for (VMCPUID i = 0; i < pVM->cCpus; i++)
996 {
997 PVMCPU pVCpu = pVM->apCpusR3[i];
998 rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
999 if (RT_FAILURE(rc))
1000 break;
1001 }
1002 }
1003
1004 if (RT_SUCCESS(rc))
1005 {
1006 /*
1007 * Info & statistics
1008 */
1009 DBGFR3InfoRegisterInternalEx(pVM, "mode",
1010 "Shows the current paging mode. "
1011 "Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1012 pgmR3InfoMode,
1013 DBGFINFO_FLAGS_ALL_EMTS);
1014 DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1015 "Dumps all the entries in the top level paging table. No arguments.",
1016 pgmR3InfoCr3);
1017 DBGFR3InfoRegisterInternal(pVM, "phys",
1018 "Dumps all the physical address ranges. Pass 'verbose' to get more details.",
1019 pgmR3PhysInfo);
1020 DBGFR3InfoRegisterInternal(pVM, "handlers",
1021 "Dumps physical, virtual and hyper virtual handlers. "
1022 "Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1023 "Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1024 pgmR3InfoHandlers);
1025#ifndef PGM_WITHOUT_MAPPINGS
1026 DBGFR3InfoRegisterInternal(pVM, "mappings",
1027 "Dumps guest mappings.",
1028 pgmR3MapInfo);
1029#endif
1030
1031 pgmR3InitStats(pVM);
1032
1033#ifdef VBOX_WITH_DEBUGGER
1034 /*
1035 * Debugger commands.
1036 */
1037 static bool s_fRegisteredCmds = false;
1038 if (!s_fRegisteredCmds)
1039 {
1040 int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1041 if (RT_SUCCESS(rc2))
1042 s_fRegisteredCmds = true;
1043 }
1044#endif
1045 return VINF_SUCCESS;
1046 }
1047
1048 /* Almost no cleanup necessary, MM frees all memory. */
1049 PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
1050
1051 return rc;
1052}
1053
1054
1055/**
1056 * Init paging.
1057 *
1058 * Since we need to check what mode the host is operating in before we can choose
1059 * the right paging functions for the host we have to delay this until R0 has
1060 * been initialized.
1061 *
1062 * @returns VBox status code.
1063 * @param pVM The cross context VM structure.
1064 */
1065static int pgmR3InitPaging(PVM pVM)
1066{
1067 /*
1068 * Force a recalculation of modes and switcher so everyone gets notified.
1069 */
1070 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1071 {
1072 PVMCPU pVCpu = pVM->apCpusR3[i];
1073
1074 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1075 pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1076 pVCpu->pgm.s.idxGuestModeData = UINT8_MAX;
1077 pVCpu->pgm.s.idxShadowModeData = UINT8_MAX;
1078 pVCpu->pgm.s.idxBothModeData = UINT8_MAX;
1079 }
1080
1081 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1082
1083#ifndef PGM_WITHOUT_MAPPINGS
1084 /*
1085 * Allocate static mapping space for whatever the cr3 register
1086 * points to and in the case of PAE mode to the 4 PDs.
1087 */
1088 int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1089 if (RT_FAILURE(rc))
1090 {
1091 AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1092 return rc;
1093 }
1094 MMR3HyperReserveFence(pVM);
1095#endif
1096
1097#if 0
1098 /*
1099 * Allocate pages for the three possible intermediate contexts
1100 * (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1101 * for the sake of simplicity. The AMD64 uses the PAE for the
1102 * lower levels, making the total number of pages 11 (3 + 7 + 1).
1103 *
1104 * We assume that two page tables will be enought for the core code
1105 * mappings (HC virtual and identity).
1106 */
1107 pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1108 pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1109 pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1110 pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1111 pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1112 pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1113 pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1114 pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1115 pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1116 pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1117 pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1118 pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1119
1120 pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1121 AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1122 pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1123 AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1124 pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1125 AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1126
1127 /*
1128 * Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1129 */
1130 ASMMemZeroPage(pVM->pgm.s.pInterPD);
1131 ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1132 ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1133
1134 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1135 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1136
1137 ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1138 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1139 {
1140 ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1141 pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P | PGM_PLXFLAGS_PERMANENT
1142 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1143 }
1144
1145 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1146 {
1147 const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1148 pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A | PGM_PLXFLAGS_PERMANENT
1149 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1150 }
1151
1152 RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1153 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1154 pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A | PGM_PLXFLAGS_PERMANENT
1155 | HCPhysInterPaePDPT64;
1156#endif
1157
1158 /*
1159 * Initialize paging workers and mode from current host mode
1160 * and the guest running in real mode.
1161 */
1162 pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1163 switch (pVM->pgm.s.enmHostMode)
1164 {
1165 case SUPPAGINGMODE_32_BIT:
1166 case SUPPAGINGMODE_32_BIT_GLOBAL:
1167 case SUPPAGINGMODE_PAE:
1168 case SUPPAGINGMODE_PAE_GLOBAL:
1169 case SUPPAGINGMODE_PAE_NX:
1170 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1171 break;
1172
1173 case SUPPAGINGMODE_AMD64:
1174 case SUPPAGINGMODE_AMD64_GLOBAL:
1175 case SUPPAGINGMODE_AMD64_NX:
1176 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1177 if (ARCH_BITS != 64)
1178 {
1179 AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1180 LogRel(("PGM: Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1181 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1182 }
1183 break;
1184 default:
1185 AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1186 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1187 }
1188
1189 LogFlow(("pgmR3InitPaging: returns successfully\n"));
1190#if HC_ARCH_BITS == 64 && 0
1191 LogRel(("PGM: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1192 pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1193 LogRel(("PGM: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1194 MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1195 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1196 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1197 MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1198#endif
1199
1200 /*
1201 * Log the host paging mode. It may come in handy.
1202 */
1203 const char *pszHostMode;
1204 switch (pVM->pgm.s.enmHostMode)
1205 {
1206 case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1207 case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1208 case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1209 case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1210 case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1211 case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1212 case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1213 case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1214 case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1215 case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1216 default: pszHostMode = "???"; break;
1217 }
1218 LogRel(("PGM: Host paging mode: %s\n", pszHostMode));
1219
1220 return VINF_SUCCESS;
1221}
1222
1223
1224/**
1225 * Init statistics
1226 * @returns VBox status code.
1227 */
1228static int pgmR3InitStats(PVM pVM)
1229{
1230 PPGM pPGM = &pVM->pgm.s;
1231 int rc;
1232
1233 /*
1234 * Release statistics.
1235 */
1236 /* Common - misc variables */
1237 STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1238 STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1239 STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1240 STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1241 STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1242 STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1243 STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1244 STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1245 STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1246 STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1247 STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1248 STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1249 STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1250 STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1251 STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1252 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1253 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1254 STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1255 STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1256
1257 STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1258 STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1259 STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1260
1261 STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1262
1263 /* Live save */
1264 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1265 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1266 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1267 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1268 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1269 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1270 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1271 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1272 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1273 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1274 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1275 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1276 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1277 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1278 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1279 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1280 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1281 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1282
1283#ifdef VBOX_WITH_STATISTICS
1284
1285# define PGM_REG_COUNTER(a, b, c) \
1286 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1287 AssertRC(rc);
1288
1289# define PGM_REG_COUNTER_BYTES(a, b, c) \
1290 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1291 AssertRC(rc);
1292
1293# define PGM_REG_PROFILE(a, b, c) \
1294 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1295 AssertRC(rc);
1296
1297 PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1298
1299 PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1300 PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1301 PGM_REG_COUNTER(&pStats->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
1302 PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1303 PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1304
1305 PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1306 PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1307 PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1308 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1309 PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1310 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1311 PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1312 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1313 PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1314 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1315
1316 PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1317 PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1318 PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1319 PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1320 PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1321 PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1322
1323 PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1324 PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1325 PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1326 PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1327 PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1328 PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1329 PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1330 PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1331
1332 PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
1333 PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
1334 PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
1335 PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
1336
1337 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1338 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1339 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1340 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1341 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1342 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1343
1344 PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1345 PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1346/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1347 PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1348 PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1349/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1350
1351 PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1352 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1353 PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1354 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1355 PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1356 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1357 PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1358 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1359
1360 /* GC only: */
1361 PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1362 PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1363
1364 PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1365 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1366 PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1367 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1368 PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1369 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1370 PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1371 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1372
1373 PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1374 PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1375 PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1376 PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1377 PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1378 PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1379 PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1380
1381# undef PGM_REG_COUNTER
1382# undef PGM_REG_PROFILE
1383#endif
1384
1385 /*
1386 * Note! The layout below matches the member layout exactly!
1387 */
1388
1389 /*
1390 * Common - stats
1391 */
1392 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1393 {
1394 PPGMCPU pPgmCpu = &pVM->apCpusR3[idCpu]->pgm.s;
1395
1396#define PGM_REG_COUNTER(a, b, c) \
1397 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1398 AssertRC(rc);
1399#define PGM_REG_PROFILE(a, b, c) \
1400 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1401 AssertRC(rc);
1402
1403 PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1404 PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
1405
1406#ifdef VBOX_WITH_STATISTICS
1407 PGMCPUSTATS *pCpuStats = pVM->apCpusR3[idCpu]->pgm.s.pStatsR3;
1408
1409# if 0 /* rarely useful; leave for debugging. */
1410 for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1411 STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1412 "The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1413 for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1414 STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1415 "The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1416# endif
1417 /* R0 only: */
1418 PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1419 PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1420
1421 /* RZ only: */
1422 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1423 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1424 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1425 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1426 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1427 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1428 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1429 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1430 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1431 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is related to the guest mappings.");
1432 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1433 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1434 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1435 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1436 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1437 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1438 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsHack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USHack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled.");
1439 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsUnhack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USUnhack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled.");
1440 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1441 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1442 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1443 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1444 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1445 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1446 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1447 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1448 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1449 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1450 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1451 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1452 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1453 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1454 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1455 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1456 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1457 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1458 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1459 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1460 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1461 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1462 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1463#if 0 /* rarely useful; leave for debugging. */
1464 for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1465 STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1466 "The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1467#endif
1468 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1469 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1470 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1471 PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1472 PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1473
1474 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1475 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1476 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1477 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1478 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1479 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1480 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1481 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1482 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1483 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1484 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1485 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
1486 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1487 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1488 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1489 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1490 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1491 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1492 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1493 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1494 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1495 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1496 //PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1497 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1498 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1499 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1500 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1501 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1502 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1503 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1504 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1505 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1506 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1507 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1508 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1509 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1510
1511 /* HC only: */
1512
1513 /* RZ & R3: */
1514 PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1515 PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1516 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1517 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1518 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1519 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1520 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1521 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1522 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1523 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1524 PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1525 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1526 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1527 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1528 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1529 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1530 PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1531 PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1532 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1533 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1534 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1535 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1536 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1537 PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1538 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1539 PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1540 PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1541 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1542 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1543 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1544 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1545 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1546 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1547 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1548 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSizeChanges, "/PGM/CPU%u/RZ/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
1549 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1550 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1551 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1552 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1553 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1554 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1555 PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1556 PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1557 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1558 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1559 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1560 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1561 PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1562
1563 PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1564 PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1565 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1566 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1567 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1568 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1569 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1570 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1571 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1572 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1573 PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1574 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1575 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1576 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1577 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1578 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1579 PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1580 PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1581 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1582 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1583 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1584 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1585 PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1586 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1587 PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1588 PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1589 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1590 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1591 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1592 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1593 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1594 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1595 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1596 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSizeChanges, "/PGM/CPU%u/R3/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
1597 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1598 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1599 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1600 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1601 PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1602 PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1603 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1604 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1605 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1606 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1607 PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1608#endif /* VBOX_WITH_STATISTICS */
1609
1610#undef PGM_REG_PROFILE
1611#undef PGM_REG_COUNTER
1612
1613 }
1614
1615 return VINF_SUCCESS;
1616}
1617
1618
1619/**
1620 * Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1621 *
1622 * The dynamic mapping area will also be allocated and initialized at this
1623 * time. We could allocate it during PGMR3Init of course, but the mapping
1624 * wouldn't be allocated at that time preventing us from setting up the
1625 * page table entries with the dummy page.
1626 *
1627 * @returns VBox status code.
1628 * @param pVM The cross context VM structure.
1629 */
1630VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1631{
1632#ifndef PGM_WITHOUT_MAPPINGS
1633 RTGCPTR GCPtr;
1634 int rc;
1635
1636 /*
1637 * Reserve space for the dynamic mappings.
1638 */
1639 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1640 if (RT_SUCCESS(rc))
1641 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1642
1643 if ( RT_SUCCESS(rc)
1644 && (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1645 {
1646 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1647 if (RT_SUCCESS(rc))
1648 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1649 }
1650 if (RT_SUCCESS(rc))
1651 {
1652 AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1653 MMR3HyperReserveFence(pVM);
1654 }
1655 return rc;
1656#else
1657 RT_NOREF(pVM);
1658 return VINF_SUCCESS;
1659#endif
1660}
1661
1662
1663/**
1664 * Ring-3 init finalizing.
1665 *
1666 * @returns VBox status code.
1667 * @param pVM The cross context VM structure.
1668 */
1669VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1670{
1671#ifndef PGM_WITHOUT_MAPPINGS
1672 int rc = VERR_IPE_UNINITIALIZED_STATUS; /* (MSC incorrectly thinks it can be used uninitialized) */
1673
1674 /*
1675 * Reserve space for the dynamic mappings.
1676 * Initialize the dynamic mapping pages with dummy pages to simply the cache.
1677 */
1678 /* get the pointer to the page table entries. */
1679 PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1680 AssertRelease(pMapping);
1681 const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1682 const unsigned iPT = off >> X86_PD_SHIFT;
1683 const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1684 pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1685 pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1686
1687 /* init cache area */
1688 RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1689 for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
1690 {
1691 rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
1692 AssertRCReturn(rc, rc);
1693 }
1694#endif
1695
1696 /*
1697 * Determine the max physical address width (MAXPHYADDR) and apply it to
1698 * all the mask members and stuff.
1699 */
1700 uint32_t cMaxPhysAddrWidth;
1701 uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
1702 if ( uMaxExtLeaf >= 0x80000008
1703 && uMaxExtLeaf <= 0x80000fff)
1704 {
1705 cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
1706 LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
1707 cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
1708 pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
1709 for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
1710 pVM->pgm.s.HCPhysInvMmioPg |= RT_BIT_64(iBit);
1711 }
1712 else
1713 {
1714 LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
1715 cMaxPhysAddrWidth = 48;
1716 pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
1717 pVM->pgm.s.HCPhysInvMmioPg |= UINT64_C(0x000f0000000000);
1718 }
1719
1720 /** @todo query from CPUM. */
1721 pVM->pgm.s.GCPhysInvAddrMask = 0;
1722 for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
1723 pVM->pgm.s.GCPhysInvAddrMask |= RT_BIT_64(iBit);
1724
1725 /*
1726 * Initialize the invalid paging entry masks, assuming NX is disabled.
1727 */
1728 uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
1729 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1730 {
1731 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1732
1733 /** @todo The manuals are not entirely clear whether the physical
1734 * address width is relevant. See table 5-9 in the intel
1735 * manual vs the PDE4M descriptions. Write testcase (NP). */
1736 pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
1737 | X86_PDE4M_MBZ_MASK;
1738
1739 pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask | X86_PTE_PAE_MBZ_MASK_NO_NX;
1740 pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask | X86_PDE_PAE_MBZ_MASK_NO_NX;
1741 pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask | X86_PDE2M_PAE_MBZ_MASK_NO_NX;
1742 pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask | X86_PDPE_PAE_MBZ_MASK;
1743
1744 pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask | X86_PTE_LM_MBZ_MASK_NO_NX;
1745 pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask | X86_PDE_LM_MBZ_MASK_NX;
1746 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask | X86_PDE2M_LM_MBZ_MASK_NX;
1747 pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask | X86_PDPE_LM_MBZ_MASK_NO_NX;
1748 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask | X86_PDPE1G_LM_MBZ_MASK_NO_NX;
1749 pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask | X86_PML4E_MBZ_MASK_NO_NX;
1750
1751 pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_G | X86_PTE_A | X86_PTE_D;
1752 pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_A;
1753 pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A;
1754 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
1755 X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_G | X86_PDE4M_A | X86_PDE4M_D;
1756 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A;
1757 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A;
1758 }
1759
1760 /*
1761 * Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1762 * Intel only goes up to 36 bits, so we stick to 36 as well.
1763 * Update: More recent intel manuals specifies 40 bits just like AMD.
1764 */
1765 uint32_t u32Dummy, u32Features;
1766 CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, 0, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1767 if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1768 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
1769 else
1770 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1771
1772 /*
1773 * Allocate memory if we're supposed to do that.
1774 */
1775#ifdef PGM_WITHOUT_MAPPINGS
1776 int rc = VINF_SUCCESS;
1777#endif
1778 if (pVM->pgm.s.fRamPreAlloc)
1779 rc = pgmR3PhysRamPreAllocate(pVM);
1780
1781 //pgmLogState(pVM);
1782 LogRel(("PGM: PGMR3InitFinalize: 4 MB PSE mask %RGp -> %Rrc\n", pVM->pgm.s.GCPhys4MBPSEMask, rc));
1783 return rc;
1784}
1785
1786
1787/**
1788 * Init phase completed callback.
1789 *
1790 * @returns VBox status code.
1791 * @param pVM The cross context VM structure.
1792 * @param enmWhat What has been completed.
1793 * @thread EMT(0)
1794 */
1795VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1796{
1797 switch (enmWhat)
1798 {
1799 case VMINITCOMPLETED_HM:
1800#ifdef VBOX_WITH_PCI_PASSTHROUGH
1801 if (pVM->pgm.s.fPciPassthrough)
1802 {
1803 AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
1804 AssertLogRelReturn(HMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HM);
1805 AssertLogRelReturn(HMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
1806
1807 /*
1808 * Report assignments to the IOMMU (hope that's good enough for now).
1809 */
1810 if (pVM->pgm.s.fPciPassthrough)
1811 {
1812 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
1813 AssertRCReturn(rc, rc);
1814 }
1815 }
1816#else
1817 AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
1818#endif
1819 break;
1820
1821 default:
1822 /* shut up gcc */
1823 break;
1824 }
1825
1826 return VINF_SUCCESS;
1827}
1828
1829
1830/**
1831 * Applies relocations to data and code managed by this component.
1832 *
1833 * This function will be called at init and whenever the VMM need to relocate it
1834 * self inside the GC.
1835 *
1836 * @param pVM The cross context VM structure.
1837 * @param offDelta Relocation delta relative to old location.
1838 */
1839VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1840{
1841 LogFlow(("PGMR3Relocate: offDelta=%RGv\n", offDelta));
1842
1843 /*
1844 * Paging stuff.
1845 */
1846
1847 /* Shadow, guest and both mode switch & relocation for each VCPU. */
1848 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1849 {
1850 PVMCPU pVCpu = pVM->apCpusR3[i];
1851
1852 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1853 if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
1854 && g_aPgmShadowModeData[idxShw].pfnRelocate)
1855 g_aPgmShadowModeData[idxShw].pfnRelocate(pVCpu, offDelta);
1856 else
1857 AssertFailed();
1858
1859 uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
1860 if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
1861 && g_aPgmGuestModeData[idxGst].pfnRelocate)
1862 g_aPgmGuestModeData[idxGst].pfnRelocate(pVCpu, offDelta);
1863 else
1864 AssertFailed();
1865 }
1866
1867 /*
1868 * Ram ranges.
1869 */
1870 if (pVM->pgm.s.pRamRangesXR3)
1871 pgmR3PhysRelinkRamRanges(pVM);
1872
1873#ifndef PGM_WITHOUT_MAPPINGS
1874
1875 /*
1876 * Update the two page directories with all page table mappings.
1877 * (One or more of them have changed, that's why we're here.)
1878 */
1879 pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1880 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1881 pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1882
1883 /* Relocate GC addresses of Page Tables. */
1884 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1885 {
1886 for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1887 {
1888 pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1889 pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1890 }
1891 }
1892
1893 /*
1894 * Dynamic page mapping area.
1895 */
1896 pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1897 pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1898 pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1899
1900 if (pVM->pgm.s.pRCDynMap)
1901 {
1902 pVM->pgm.s.pRCDynMap += offDelta;
1903 PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
1904
1905 pDynMap->paPages += offDelta;
1906 PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
1907
1908 for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
1909 {
1910 paPages[iPage].pvPage += offDelta;
1911 paPages[iPage].uPte.pLegacy += offDelta;
1912 paPages[iPage].uPte.pPae += offDelta;
1913 }
1914 }
1915
1916#endif /* PGM_WITHOUT_MAPPINGS */
1917
1918 /*
1919 * The Zero page.
1920 */
1921 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1922 AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
1923
1924 /*
1925 * The page pool.
1926 */
1927 pgmR3PoolRelocate(pVM);
1928}
1929
1930
1931/**
1932 * Resets a virtual CPU when unplugged.
1933 *
1934 * @param pVM The cross context VM structure.
1935 * @param pVCpu The cross context virtual CPU structure.
1936 */
1937VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1938{
1939 uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
1940 if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
1941 && g_aPgmGuestModeData[idxGst].pfnExit)
1942 {
1943 int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
1944 AssertReleaseRC(rc);
1945 }
1946 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1947
1948 int rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1949 AssertReleaseRC(rc);
1950
1951 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
1952
1953 pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
1954
1955 /*
1956 * Re-init other members.
1957 */
1958 pVCpu->pgm.s.fA20Enabled = true;
1959 pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
1960
1961 /*
1962 * Clear the FFs PGM owns.
1963 */
1964 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1965 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1966}
1967
1968
1969/**
1970 * The VM is being reset.
1971 *
1972 * For the PGM component this means that any PD write monitors
1973 * needs to be removed.
1974 *
1975 * @param pVM The cross context VM structure.
1976 */
1977VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM)
1978{
1979 LogFlow(("PGMR3Reset:\n"));
1980 VM_ASSERT_EMT(pVM);
1981
1982 pgmLock(pVM);
1983
1984 /*
1985 * Unfix any fixed mappings and disable CR3 monitoring.
1986 */
1987 pVM->pgm.s.fMappingsFixed = false;
1988 pVM->pgm.s.fMappingsFixedRestored = false;
1989 pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
1990 pVM->pgm.s.cbMappingFixed = 0;
1991
1992 /*
1993 * Exit the guest paging mode before the pgm pool gets reset.
1994 * Important to clean up the amd64 case.
1995 */
1996 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1997 {
1998 PVMCPU pVCpu = pVM->apCpusR3[i];
1999 uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
2000 if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
2001 && g_aPgmGuestModeData[idxGst].pfnExit)
2002 {
2003 int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
2004 AssertReleaseRC(rc);
2005 }
2006 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2007 }
2008
2009#ifdef DEBUG
2010 DBGFR3_INFO_LOG_SAFE(pVM, "mappings", NULL);
2011 DBGFR3_INFO_LOG_SAFE(pVM, "handlers", "all nostat");
2012#endif
2013
2014 /*
2015 * Switch mode back to real mode. (Before resetting the pgm pool!)
2016 */
2017 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2018 {
2019 PVMCPU pVCpu = pVM->apCpusR3[i];
2020
2021 int rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
2022 AssertReleaseRC(rc);
2023
2024 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2025 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
2026 }
2027
2028 /*
2029 * Reset the shadow page pool.
2030 */
2031 pgmR3PoolReset(pVM);
2032
2033 /*
2034 * Re-init various other members and clear the FFs that PGM owns.
2035 */
2036 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2037 {
2038 PVMCPU pVCpu = pVM->apCpusR3[i];
2039
2040 pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2041 PGMNotifyNxeChanged(pVCpu, false);
2042
2043 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2044 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2045
2046 if (!pVCpu->pgm.s.fA20Enabled)
2047 {
2048 pVCpu->pgm.s.fA20Enabled = true;
2049 pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2050#ifdef PGM_WITH_A20
2051 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2052 pgmR3RefreshShadowModeAfterA20Change(pVCpu);
2053 HMFlushTlb(pVCpu);
2054#endif
2055 }
2056 }
2057
2058 //pgmLogState(pVM);
2059 pgmUnlock(pVM);
2060}
2061
2062
2063/**
2064 * Memory setup after VM construction or reset.
2065 *
2066 * @param pVM The cross context VM structure.
2067 * @param fAtReset Indicates the context, after reset if @c true or after
2068 * construction if @c false.
2069 */
2070VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fAtReset)
2071{
2072 if (fAtReset)
2073 {
2074 pgmLock(pVM);
2075
2076 int rc = pgmR3PhysRamZeroAll(pVM);
2077 AssertReleaseRC(rc);
2078
2079 rc = pgmR3PhysRomReset(pVM);
2080 AssertReleaseRC(rc);
2081
2082 pgmUnlock(pVM);
2083 }
2084}
2085
2086
2087#ifdef VBOX_STRICT
2088/**
2089 * VM state change callback for clearing fNoMorePhysWrites after
2090 * a snapshot has been created.
2091 */
2092static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PUVM pUVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2093{
2094 if ( enmState == VMSTATE_RUNNING
2095 || enmState == VMSTATE_RESUMING)
2096 pUVM->pVM->pgm.s.fNoMorePhysWrites = false;
2097 NOREF(enmOldState); NOREF(pvUser);
2098}
2099#endif
2100
2101/**
2102 * Private API to reset fNoMorePhysWrites.
2103 */
2104VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2105{
2106 pVM->pgm.s.fNoMorePhysWrites = false;
2107}
2108
2109/**
2110 * Terminates the PGM.
2111 *
2112 * @returns VBox status code.
2113 * @param pVM The cross context VM structure.
2114 */
2115VMMR3DECL(int) PGMR3Term(PVM pVM)
2116{
2117 /* Must free shared pages here. */
2118 pgmLock(pVM);
2119 pgmR3PhysRamTerm(pVM);
2120 pgmR3PhysRomTerm(pVM);
2121 pgmUnlock(pVM);
2122
2123 PGMDeregisterStringFormatTypes();
2124 return PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
2125}
2126
2127
2128/**
2129 * Show paging mode.
2130 *
2131 * @param pVM The cross context VM structure.
2132 * @param pHlp The info helpers.
2133 * @param pszArgs "all" (default), "guest", "shadow" or "host".
2134 */
2135static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2136{
2137 /* digest argument. */
2138 bool fGuest, fShadow, fHost;
2139 if (pszArgs)
2140 pszArgs = RTStrStripL(pszArgs);
2141 if (!pszArgs || !*pszArgs || strstr(pszArgs, "all"))
2142 fShadow = fHost = fGuest = true;
2143 else
2144 {
2145 fShadow = fHost = fGuest = false;
2146 if (strstr(pszArgs, "guest"))
2147 fGuest = true;
2148 if (strstr(pszArgs, "shadow"))
2149 fShadow = true;
2150 if (strstr(pszArgs, "host"))
2151 fHost = true;
2152 }
2153
2154 PVMCPU pVCpu = VMMGetCpu(pVM);
2155 if (!pVCpu)
2156 pVCpu = pVM->apCpusR3[0];
2157
2158
2159 /* print info. */
2160 if (fGuest)
2161 pHlp->pfnPrintf(pHlp, "Guest paging mode (VCPU #%u): %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
2162 pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmGuestMode), pVCpu->pgm.s.cGuestModeChanges.c,
2163 pVCpu->pgm.s.fA20Enabled ? "enabled" : "disabled", pVCpu->pgm.s.cA20Changes.c);
2164 if (fShadow)
2165 pHlp->pfnPrintf(pHlp, "Shadow paging mode (VCPU #%u): %s\n", pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmShadowMode));
2166 if (fHost)
2167 {
2168 const char *psz;
2169 switch (pVM->pgm.s.enmHostMode)
2170 {
2171 case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2172 case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2173 case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2174 case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2175 case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2176 case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2177 case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2178 case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2179 case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2180 case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2181 case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2182 default: psz = "unknown"; break;
2183 }
2184 pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2185 }
2186}
2187
2188
2189/**
2190 * Dump registered MMIO ranges to the log.
2191 *
2192 * @param pVM The cross context VM structure.
2193 * @param pHlp The info helpers.
2194 * @param pszArgs Arguments, ignored.
2195 */
2196static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2197{
2198 bool const fVerbose = pszArgs && strstr(pszArgs, "verbose") != NULL;
2199
2200 pHlp->pfnPrintf(pHlp,
2201 "RAM ranges (pVM=%p)\n"
2202 "%.*s %.*s\n",
2203 pVM,
2204 sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2205 sizeof(RTHCPTR) * 2, "pvHC ");
2206
2207 for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2208 {
2209 pHlp->pfnPrintf(pHlp,
2210 "%RGp-%RGp %RHv %s\n",
2211 pCur->GCPhys,
2212 pCur->GCPhysLast,
2213 pCur->pvR3,
2214 pCur->pszDesc);
2215 if (fVerbose)
2216 {
2217 RTGCPHYS const cPages = pCur->cb >> X86_PAGE_SHIFT;
2218 RTGCPHYS iPage = 0;
2219 while (iPage < cPages)
2220 {
2221 RTGCPHYS const iFirstPage = iPage;
2222 PGMPAGETYPE const enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]);
2223 do
2224 iPage++;
2225 while (iPage < cPages && (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == enmType);
2226 const char *pszType;
2227 const char *pszMore = NULL;
2228 switch (enmType)
2229 {
2230 case PGMPAGETYPE_RAM:
2231 pszType = "RAM";
2232 break;
2233
2234 case PGMPAGETYPE_MMIO2:
2235 pszType = "MMIO2";
2236 break;
2237
2238 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2239 pszType = "MMIO2-alias-MMIO";
2240 break;
2241
2242 case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2243 pszType = "special-alias-MMIO";
2244 break;
2245
2246 case PGMPAGETYPE_ROM_SHADOW:
2247 case PGMPAGETYPE_ROM:
2248 {
2249 pszType = enmType == PGMPAGETYPE_ROM_SHADOW ? "ROM-shadowed" : "ROM";
2250
2251 RTGCPHYS const GCPhysFirstPg = iFirstPage * X86_PAGE_SIZE;
2252 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2253 while (pRom && GCPhysFirstPg > pRom->GCPhysLast)
2254 pRom = pRom->pNextR3;
2255 if (pRom && GCPhysFirstPg - pRom->GCPhys < pRom->cb)
2256 pszMore = pRom->pszDesc;
2257 break;
2258 }
2259
2260 case PGMPAGETYPE_MMIO:
2261 {
2262 pszType = "MMIO";
2263 pgmLock(pVM);
2264 PPGMPHYSHANDLER pHandler = pgmHandlerPhysicalLookup(pVM, iFirstPage * X86_PAGE_SIZE);
2265 if (pHandler)
2266 pszMore = pHandler->pszDesc;
2267 pgmUnlock(pVM);
2268 break;
2269 }
2270
2271 case PGMPAGETYPE_INVALID:
2272 pszType = "invalid";
2273 break;
2274
2275 default:
2276 pszType = "bad";
2277 break;
2278 }
2279 if (pszMore)
2280 pHlp->pfnPrintf(pHlp, " %RGp-%RGp %-20s %s\n",
2281 pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
2282 pCur->GCPhys + iPage * X86_PAGE_SIZE,
2283 pszType, pszMore);
2284 else
2285 pHlp->pfnPrintf(pHlp, " %RGp-%RGp %s\n",
2286 pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
2287 pCur->GCPhys + iPage * X86_PAGE_SIZE,
2288 pszType);
2289
2290 }
2291 }
2292 }
2293}
2294
2295
2296/**
2297 * Dump the page directory to the log.
2298 *
2299 * @param pVM The cross context VM structure.
2300 * @param pHlp The info helpers.
2301 * @param pszArgs Arguments, ignored.
2302 */
2303static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2304{
2305 /** @todo SMP support!! */
2306 PVMCPU pVCpu = pVM->apCpusR3[0];
2307
2308/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2309 /* Big pages supported? */
2310 const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2311
2312 /* Global pages supported? */
2313 const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2314
2315 NOREF(pszArgs);
2316
2317 /*
2318 * Get page directory addresses.
2319 */
2320 pgmLock(pVM);
2321 PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2322 Assert(pPDSrc);
2323
2324 /*
2325 * Iterate the page directory.
2326 */
2327 for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2328 {
2329 X86PDE PdeSrc = pPDSrc->a[iPD];
2330 if (PdeSrc.n.u1Present)
2331 {
2332 if (PdeSrc.b.u1Size && fPSE)
2333 pHlp->pfnPrintf(pHlp,
2334 "%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2335 iPD,
2336 pgmGstGet4MBPhysPage(pVM, PdeSrc),
2337 PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2338 else
2339 pHlp->pfnPrintf(pHlp,
2340 "%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2341 iPD,
2342 (RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2343 PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2344 }
2345 }
2346 pgmUnlock(pVM);
2347}
2348
2349
2350/**
2351 * Service a VMMCALLRING3_PGM_LOCK call.
2352 *
2353 * @returns VBox status code.
2354 * @param pVM The cross context VM structure.
2355 */
2356VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2357{
2358 int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSectX, true /* fHostCall */);
2359 AssertRC(rc);
2360 return rc;
2361}
2362
2363
2364/**
2365 * Called by pgmPoolFlushAllInt prior to flushing the pool.
2366 *
2367 * @returns VBox status code, fully asserted.
2368 * @param pVCpu The cross context virtual CPU structure.
2369 */
2370int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
2371{
2372 /* Unmap the old CR3 value before flushing everything. */
2373 int rc = VINF_SUCCESS;
2374 uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
2375 if ( idxBth < RT_ELEMENTS(g_aPgmBothModeData)
2376 && g_aPgmBothModeData[idxBth].pfnMapCR3)
2377 {
2378 rc = g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
2379 AssertRC(rc);
2380 }
2381
2382 /* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
2383 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
2384 if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
2385 && g_aPgmShadowModeData[idxShw].pfnExit)
2386 {
2387 rc = g_aPgmShadowModeData[idxShw].pfnExit(pVCpu);
2388 AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
2389 }
2390
2391 Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
2392 return rc;
2393}
2394
2395
2396/**
2397 * Called by pgmPoolFlushAllInt after flushing the pool.
2398 *
2399 * @returns VBox status code, fully asserted.
2400 * @param pVM The cross context VM structure.
2401 * @param pVCpu The cross context virtual CPU structure.
2402 */
2403int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
2404{
2405 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
2406 int rc = PGMHCChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
2407 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2408 AssertRCReturn(rc, rc);
2409 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2410
2411 Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL || pVCpu->pgm.s.enmShadowMode == PGMMODE_NONE);
2412 AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED_32BIT
2413 || CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
2414 ("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
2415 return rc;
2416}
2417
2418
2419/**
2420 * Called by PGMR3PhysSetA20 after changing the A20 state.
2421 *
2422 * @param pVCpu The cross context virtual CPU structure.
2423 */
2424void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
2425{
2426 /** @todo Probably doing a bit too much here. */
2427 int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
2428 AssertReleaseRC(rc);
2429 rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
2430 AssertReleaseRC(rc);
2431}
2432
2433
2434#ifdef VBOX_WITH_DEBUGGER
2435
2436/**
2437 * @callback_method_impl{FNDBGCCMD, The '.pgmerror' and '.pgmerroroff' commands.}
2438 */
2439static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2440{
2441 /*
2442 * Validate input.
2443 */
2444 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2445 PVM pVM = pUVM->pVM;
2446 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 0 || (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING));
2447
2448 if (!cArgs)
2449 {
2450 /*
2451 * Print the list of error injection locations with status.
2452 */
2453 DBGCCmdHlpPrintf(pCmdHlp, "PGM error inject locations:\n");
2454 DBGCCmdHlpPrintf(pCmdHlp, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
2455 }
2456 else
2457 {
2458 /*
2459 * String switch on where to inject the error.
2460 */
2461 bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
2462 const char *pszWhere = paArgs[0].u.pszString;
2463 if (!strcmp(pszWhere, "handy"))
2464 ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
2465 else
2466 return DBGCCmdHlpPrintf(pCmdHlp, "error: Invalid 'where' value: %s.\n", pszWhere);
2467 DBGCCmdHlpPrintf(pCmdHlp, "done\n");
2468 }
2469 return VINF_SUCCESS;
2470}
2471
2472
2473/**
2474 * @callback_method_impl{FNDBGCCMD, The '.pgmsync' command.}
2475 */
2476static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2477{
2478 /*
2479 * Validate input.
2480 */
2481 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2482 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2483 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
2484 if (!pVCpu)
2485 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
2486
2487 /*
2488 * Force page directory sync.
2489 */
2490 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2491
2492 int rc = DBGCCmdHlpPrintf(pCmdHlp, "Forcing page directory sync.\n");
2493 if (RT_FAILURE(rc))
2494 return rc;
2495
2496 return VINF_SUCCESS;
2497}
2498
2499#ifdef VBOX_STRICT
2500
2501/**
2502 * EMT callback for pgmR3CmdAssertCR3.
2503 *
2504 * @returns VBox status code.
2505 * @param pUVM The user mode VM handle.
2506 * @param pcErrors Where to return the error count.
2507 */
2508static DECLCALLBACK(int) pgmR3CmdAssertCR3EmtWorker(PUVM pUVM, unsigned *pcErrors)
2509{
2510 PVM pVM = pUVM->pVM;
2511 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
2512 PVMCPU pVCpu = VMMGetCpu(pVM);
2513
2514 *pcErrors = PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
2515
2516 return VINF_SUCCESS;
2517}
2518
2519
2520/**
2521 * @callback_method_impl{FNDBGCCMD, The '.pgmassertcr3' command.}
2522 */
2523static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2524{
2525 /*
2526 * Validate input.
2527 */
2528 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2529 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2530
2531 int rc = DBGCCmdHlpPrintf(pCmdHlp, "Checking shadow CR3 page tables for consistency.\n");
2532 if (RT_FAILURE(rc))
2533 return rc;
2534
2535 unsigned cErrors = 0;
2536 rc = VMR3ReqCallWaitU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp), (PFNRT)pgmR3CmdAssertCR3EmtWorker, 2, pUVM, &cErrors);
2537 if (RT_FAILURE(rc))
2538 return DBGCCmdHlpFail(pCmdHlp, pCmd, "VMR3ReqCallWaitU failed: %Rrc", rc);
2539 if (cErrors > 0)
2540 return DBGCCmdHlpFail(pCmdHlp, pCmd, "PGMAssertCR3: %u error(s)", cErrors);
2541 return DBGCCmdHlpPrintf(pCmdHlp, "PGMAssertCR3: OK\n");
2542}
2543
2544#endif /* VBOX_STRICT */
2545
2546/**
2547 * @callback_method_impl{FNDBGCCMD, The '.pgmsyncalways' command.}
2548 */
2549static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2550{
2551 /*
2552 * Validate input.
2553 */
2554 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2555 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2556 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
2557 if (!pVCpu)
2558 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
2559
2560 /*
2561 * Force page directory sync.
2562 */
2563 int rc;
2564 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
2565 {
2566 ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
2567 rc = DBGCCmdHlpPrintf(pCmdHlp, "Disabled permanent forced page directory syncing.\n");
2568 }
2569 else
2570 {
2571 ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
2572 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2573 rc = DBGCCmdHlpPrintf(pCmdHlp, "Enabled permanent forced page directory syncing.\n");
2574 }
2575 return rc;
2576}
2577
2578
2579/**
2580 * @callback_method_impl{FNDBGCCMD, The '.pgmphystofile' command.}
2581 */
2582static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2583{
2584 /*
2585 * Validate input.
2586 */
2587 NOREF(pCmd);
2588 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2589 PVM pVM = pUVM->pVM;
2590 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 1 || cArgs == 2);
2591 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, paArgs[0].enmType == DBGCVAR_TYPE_STRING);
2592 if (cArgs == 2)
2593 {
2594 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 1, paArgs[1].enmType == DBGCVAR_TYPE_STRING);
2595 if (strcmp(paArgs[1].u.pszString, "nozero"))
2596 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
2597 }
2598 bool fIncZeroPgs = cArgs < 2;
2599
2600 /*
2601 * Open the output file and get the ram parameters.
2602 */
2603 RTFILE hFile;
2604 int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE | RTFILE_O_CREATE_REPLACE | RTFILE_O_DENY_WRITE);
2605 if (RT_FAILURE(rc))
2606 return DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
2607
2608 uint32_t cbRamHole = 0;
2609 CFGMR3QueryU32Def(CFGMR3GetRootU(pUVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
2610 uint64_t cbRam = 0;
2611 CFGMR3QueryU64Def(CFGMR3GetRootU(pUVM), "RamSize", &cbRam, 0);
2612 RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
2613
2614 /*
2615 * Dump the physical memory, page by page.
2616 */
2617 RTGCPHYS GCPhys = 0;
2618 char abZeroPg[PAGE_SIZE];
2619 RT_ZERO(abZeroPg);
2620
2621 pgmLock(pVM);
2622 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2623 pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
2624 pRam = pRam->pNextR3)
2625 {
2626 /* fill the gap */
2627 if (pRam->GCPhys > GCPhys && fIncZeroPgs)
2628 {
2629 while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
2630 {
2631 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
2632 GCPhys += PAGE_SIZE;
2633 }
2634 }
2635
2636 PCPGMPAGE pPage = &pRam->aPages[0];
2637 while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
2638 {
2639 if ( PGM_PAGE_IS_ZERO(pPage)
2640 || PGM_PAGE_IS_BALLOONED(pPage))
2641 {
2642 if (fIncZeroPgs)
2643 {
2644 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
2645 if (RT_FAILURE(rc))
2646 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2647 }
2648 }
2649 else
2650 {
2651 switch (PGM_PAGE_GET_TYPE(pPage))
2652 {
2653 case PGMPAGETYPE_RAM:
2654 case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
2655 case PGMPAGETYPE_ROM:
2656 case PGMPAGETYPE_MMIO2:
2657 {
2658 void const *pvPage;
2659 PGMPAGEMAPLOCK Lock;
2660 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
2661 if (RT_SUCCESS(rc))
2662 {
2663 rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
2664 PGMPhysReleasePageMappingLock(pVM, &Lock);
2665 if (RT_FAILURE(rc))
2666 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2667 }
2668 else
2669 DBGCCmdHlpPrintf(pCmdHlp, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2670 break;
2671 }
2672
2673 default:
2674 AssertFailed();
2675 RT_FALL_THRU();
2676 case PGMPAGETYPE_MMIO:
2677 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2678 case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2679 if (fIncZeroPgs)
2680 {
2681 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
2682 if (RT_FAILURE(rc))
2683 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2684 }
2685 break;
2686 }
2687 }
2688
2689
2690 /* advance */
2691 GCPhys += PAGE_SIZE;
2692 pPage++;
2693 }
2694 }
2695 pgmUnlock(pVM);
2696
2697 RTFileClose(hFile);
2698 if (RT_SUCCESS(rc))
2699 return DBGCCmdHlpPrintf(pCmdHlp, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
2700 return VINF_SUCCESS;
2701}
2702
2703#endif /* VBOX_WITH_DEBUGGER */
2704
2705/**
2706 * pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
2707 */
2708typedef struct PGMCHECKINTARGS
2709{
2710 bool fLeftToRight; /**< true: left-to-right; false: right-to-left. */
2711 PPGMPHYSHANDLER pPrevPhys;
2712 PVM pVM;
2713} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
2714
2715/**
2716 * Validate a node in the physical handler tree.
2717 *
2718 * @returns 0 on if ok, other wise 1.
2719 * @param pNode The handler node.
2720 * @param pvUser pVM.
2721 */
2722static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2723{
2724 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
2725 PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
2726 AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
2727 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,
2728 ("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
2729 AssertReleaseMsg( !pArgs->pPrevPhys
2730 || ( pArgs->fLeftToRight
2731 ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key
2732 : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
2733 ("pPrevPhys=%p %RGp-%RGp %s\n"
2734 " pCur=%p %RGp-%RGp %s\n",
2735 pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
2736 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
2737 pArgs->pPrevPhys = pCur;
2738 return 0;
2739}
2740
2741
2742/**
2743 * Perform an integrity check on the PGM component.
2744 *
2745 * @returns VINF_SUCCESS if everything is fine.
2746 * @returns VBox error status after asserting on integrity breach.
2747 * @param pVM The cross context VM structure.
2748 */
2749VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
2750{
2751 AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
2752
2753 /*
2754 * Check the trees.
2755 */
2756 int cErrors = 0;
2757 const PGMCHECKINTARGS LeftToRight = { true, NULL, pVM };
2758 const PGMCHECKINTARGS RightToLeft = { false, NULL, pVM };
2759 PGMCHECKINTARGS Args = LeftToRight;
2760 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
2761 Args = RightToLeft;
2762 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
2763
2764 return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
2765}
2766
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