VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp

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1/* $Id: PGM.cpp 106061 2024-09-16 14:03:52Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4 */
5
6/*
7 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/** @page pg_pgm PGM - The Page Manager and Monitor
30 *
31 * @sa @ref grp_pgm
32 * @subpage pg_pgm_pool
33 * @subpage pg_pgm_phys
34 *
35 *
36 * @section sec_pgm_modes Paging Modes
37 *
38 * There are three memory contexts: Host Context (HC), Guest Context (GC)
39 * and intermediate context. When talking about paging HC can also be referred
40 * to as "host paging", and GC referred to as "shadow paging".
41 *
42 * We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
43 * is defined by the host operating system. The mode used in the shadow paging mode
44 * depends on the host paging mode and what the mode the guest is currently in. The
45 * following relation between the two is defined:
46 *
47 * @verbatim
48 Host > 32-bit | PAE | AMD64 |
49 Guest | | | |
50 ==v================================
51 32-bit 32-bit PAE PAE
52 -------|--------|--------|--------|
53 PAE PAE PAE PAE
54 -------|--------|--------|--------|
55 AMD64 AMD64 AMD64 AMD64
56 -------|--------|--------|--------| @endverbatim
57 *
58 * All configuration except those in the diagonal (upper left) are expected to
59 * require special effort from the switcher (i.e. a bit slower).
60 *
61 *
62 *
63 *
64 * @section sec_pgm_shw The Shadow Memory Context
65 *
66 *
67 * [..]
68 *
69 * Because of guest context mappings requires PDPT and PML4 entries to allow
70 * writing on AMD64, the two upper levels will have fixed flags whatever the
71 * guest is thinking of using there. So, when shadowing the PD level we will
72 * calculate the effective flags of PD and all the higher levels. In legacy
73 * PAE mode this only applies to the PWT and PCD bits (the rest are
74 * ignored/reserved/MBZ). We will ignore those bits for the present.
75 *
76 *
77 *
78 * @section sec_pgm_int The Intermediate Memory Context
79 *
80 * The world switch goes thru an intermediate memory context which purpose it is
81 * to provide different mappings of the switcher code. All guest mappings are also
82 * present in this context.
83 *
84 * The switcher code is mapped at the same location as on the host, at an
85 * identity mapped location (physical equals virtual address), and at the
86 * hypervisor location. The identity mapped location is for when the world
87 * switches that involves disabling paging.
88 *
89 * PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
90 * simplifies switching guest CPU mode and consistency at the cost of more
91 * code to do the work. All memory use for those page tables is located below
92 * 4GB (this includes page tables for guest context mappings).
93 *
94 * Note! The intermediate memory context is also used for 64-bit guest
95 * execution on 32-bit hosts. Because we need to load 64-bit registers
96 * prior to switching to guest context, we need to be in 64-bit mode
97 * first. So, HM has some 64-bit worker routines in VMMRC.rc that get
98 * invoked via the special world switcher code in LegacyToAMD64.asm.
99 *
100 *
101 * @subsection subsec_pgm_int_gc Guest Context Mappings
102 *
103 * During assignment and relocation of a guest context mapping the intermediate
104 * memory context is used to verify the new location.
105 *
106 * Guest context mappings are currently restricted to below 4GB, for reasons
107 * of simplicity. This may change when we implement AMD64 support.
108 *
109 *
110 *
111 *
112 * @section sec_pgm_misc Misc
113 *
114 *
115 * @subsection sec_pgm_misc_A20 The A20 Gate
116 *
117 * PGM implements the A20 gate masking when translating a virtual guest address
118 * into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
119 * the code reading the guest page table entries during shadowing. The masking
120 * is done consistenly for all CPU modes, paged ones included. Large pages are
121 * also masked correctly. (On current CPUs, experiments indicates that AMD does
122 * not apply A20M in paged modes and intel only does it for the 2nd MB of
123 * memory.)
124 *
125 * The A20 gate implementation is per CPU core. It can be configured on a per
126 * core basis via the keyboard device and PC architecture device. This is
127 * probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
128 * guest OSes try pushing things anyway, so who cares. (On current real systems
129 * the A20M signal is probably only sent to the boot CPU and it affects all
130 * thread and probably all cores in that package.)
131 *
132 * The keyboard device and the PC architecture device doesn't OR their A20
133 * config bits together, rather they are currently implemented such that they
134 * mirror the CPU state. So, flipping the bit in either of them will change the
135 * A20 state. (On real hardware the bits of the two devices should probably be
136 * ORed together to indicate enabled, i.e. both needs to be cleared to disable
137 * A20 masking.)
138 *
139 * The A20 state will change immediately, transmeta fashion. There is no delays
140 * due to buses, wiring or other physical stuff. (On real hardware there are
141 * normally delays, the delays differs between the two devices and probably also
142 * between chipsets and CPU generations. Note that it's said that transmeta CPUs
143 * does the change immediately like us, they apparently intercept/handles the
144 * port accesses in microcode. Neat.)
145 *
146 * @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
147 *
148 *
149 * @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
150 *
151 * The differences between legacy PAE and long mode PAE are:
152 * -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
153 * all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
154 * usual meanings while 6 is ignored (AMD). This means that upon switching to
155 * legacy PAE mode we'll have to clear these bits and when going to long mode
156 * they must be set. This applies to both intermediate and shadow contexts,
157 * however we don't need to do it for the intermediate one since we're
158 * executing with CR0.WP at that time.
159 * -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
160 * a page aligned one is required.
161 *
162 *
163 * @section sec_pgm_handlers Access Handlers
164 *
165 * Placeholder.
166 *
167 *
168 * @subsection sec_pgm_handlers_phys Physical Access Handlers
169 *
170 * Placeholder.
171 *
172 *
173 * @subsection sec_pgm_handlers_virt Virtual Access Handlers (obsolete)
174 *
175 * We currently implement three types of virtual access handlers: ALL, WRITE
176 * and HYPERVISOR (WRITE). See PGMVIRTHANDLERKIND for some more details.
177 *
178 * The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
179 * to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
180 * a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
181 * rest of this section is going to be about these handlers.
182 *
183 * We'll go thru the life cycle of a handler and try make sense of it all, don't know
184 * how successful this is gonna be...
185 *
186 * 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
187 * PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
188 * and create a new node that is inserted into the AVL tree (range key). Then
189 * a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
190 *
191 * 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
192 *
193 * 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
194 * via the current guest CR3 and update the physical page -> virtual handler
195 * translation. Needless to say, this doesn't exactly scale very well. If any changes
196 * are detected, it will flag a virtual bit update just like we did on registration.
197 * PGMPHYS pages with changes will have their virtual handler state reset to NONE.
198 *
199 * 2b. The virtual bit update process will iterate all the pages covered by all the
200 * virtual handlers and update the PGMPAGE virtual handler state to the max of all
201 * virtual handlers on that page.
202 *
203 * 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
204 * we don't miss any alias mappings of the monitored pages.
205 *
206 * 2d. SyncCR3 will then proceed with syncing the CR3 table.
207 *
208 * 3. \#PF(np,read) on a page in the range. This will cause it to be synced
209 * read-only and resumed if it's a WRITE handler. If it's an ALL handler we
210 * will call the handlers like in the next step. If the physical mapping has
211 * changed we will - some time in the future - perform a handler callback
212 * (optional) and update the physical -> virtual handler cache.
213 *
214 * 4. \#PF(,write) on a page in the range. This will cause the handler to
215 * be invoked.
216 *
217 * 5. The guest invalidates the page and changes the physical backing or
218 * unmaps it. This should cause the invalidation callback to be invoked
219 * (it might not yet be 100% perfect). Exactly what happens next... is
220 * this where we mess up and end up out of sync for a while?
221 *
222 * 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
223 * We will then set all PGMPAGEs in the physical -> virtual handler cache for
224 * this handler to NONE and trigger a full PGM resync (basically the same
225 * as int step 1). Which means 2 is executed again.
226 *
227 *
228 * @subsubsection sub_sec_pgm_handler_virt_todo TODOs
229 *
230 * There is a bunch of things that needs to be done to make the virtual handlers
231 * work 100% correctly and work more efficiently.
232 *
233 * The first bit hasn't been implemented yet because it's going to slow the
234 * whole mess down even more, and besides it seems to be working reliably for
235 * our current uses. OTOH, some of the optimizations might end up more or less
236 * implementing the missing bits, so we'll see.
237 *
238 * On the optimization side, the first thing to do is to try avoid unnecessary
239 * cache flushing. Then try team up with the shadowing code to track changes
240 * in mappings by means of access to them (shadow in), updates to shadows pages,
241 * invlpg, and shadow PT discarding (perhaps).
242 *
243 * Some idea that have popped up for optimization for current and new features:
244 * - bitmap indicating where there are virtual handlers installed.
245 * (4KB => 2**20 pages, page 2**12 => covers 32-bit address space 1:1!)
246 * - Further optimize this by min/max (needs min/max avl getters).
247 * - Shadow page table entry bit (if any left)?
248 *
249 */
250
251
252/** @page pg_pgm_phys PGM Physical Guest Memory Management
253 *
254 *
255 * Objectives:
256 * - Guest RAM over-commitment using memory ballooning,
257 * zero pages and general page sharing.
258 * - Moving or mirroring a VM onto a different physical machine.
259 *
260 *
261 * @section sec_pgmPhys_Definitions Definitions
262 *
263 * Allocation chunk - A RTR0MemObjAllocPhysNC or RTR0MemObjAllocPhys allocate
264 * memory object and the tracking machinery associated with it.
265 *
266 *
267 *
268 *
269 * @section sec_pgmPhys_AllocPage Allocating a page.
270 *
271 * Initially we map *all* guest memory to the (per VM) zero page, which
272 * means that none of the read functions will cause pages to be allocated.
273 *
274 * Exception, access bit in page tables that have been shared. This must
275 * be handled, but we must also make sure PGMGst*Modify doesn't make
276 * unnecessary modifications.
277 *
278 * Allocation points:
279 * - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
280 * - Replacing a zero page mapping at \#PF.
281 * - Replacing a shared page mapping at \#PF.
282 * - ROM registration (currently MMR3RomRegister).
283 * - VM restore (pgmR3Load).
284 *
285 * For the first three it would make sense to keep a few pages handy
286 * until we've reached the max memory commitment for the VM.
287 *
288 * For the ROM registration, we know exactly how many pages we need
289 * and will request these from ring-0. For restore, we will save
290 * the number of non-zero pages in the saved state and allocate
291 * them up front. This would allow the ring-0 component to refuse
292 * the request if the isn't sufficient memory available for VM use.
293 *
294 * Btw. for both ROM and restore allocations we won't be requiring
295 * zeroed pages as they are going to be filled instantly.
296 *
297 *
298 * @section sec_pgmPhys_FreePage Freeing a page
299 *
300 * There are a few points where a page can be freed:
301 * - After being replaced by the zero page.
302 * - After being replaced by a shared page.
303 * - After being ballooned by the guest additions.
304 * - At reset.
305 * - At restore.
306 *
307 * When freeing one or more pages they will be returned to the ring-0
308 * component and replaced by the zero page.
309 *
310 * The reasoning for clearing out all the pages on reset is that it will
311 * return us to the exact same state as on power on, and may thereby help
312 * us reduce the memory load on the system. Further it might have a
313 * (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
314 *
315 * On restore, as mention under the allocation topic, pages should be
316 * freed / allocated depending on how many is actually required by the
317 * new VM state. The simplest approach is to do like on reset, and free
318 * all non-ROM pages and then allocate what we need.
319 *
320 * A measure to prevent some fragmentation, would be to let each allocation
321 * chunk have some affinity towards the VM having allocated the most pages
322 * from it. Also, try make sure to allocate from allocation chunks that
323 * are almost full. Admittedly, both these measures might work counter to
324 * our intentions and its probably not worth putting a lot of effort,
325 * cpu time or memory into this.
326 *
327 *
328 * @section sec_pgmPhys_SharePage Sharing a page
329 *
330 * The basic idea is that there there will be a idle priority kernel
331 * thread walking the non-shared VM pages hashing them and looking for
332 * pages with the same checksum. If such pages are found, it will compare
333 * them byte-by-byte to see if they actually are identical. If found to be
334 * identical it will allocate a shared page, copy the content, check that
335 * the page didn't change while doing this, and finally request both the
336 * VMs to use the shared page instead. If the page is all zeros (special
337 * checksum and byte-by-byte check) it will request the VM that owns it
338 * to replace it with the zero page.
339 *
340 * To make this efficient, we will have to make sure not to try share a page
341 * that will change its contents soon. This part requires the most work.
342 * A simple idea would be to request the VM to write monitor the page for
343 * a while to make sure it isn't modified any time soon. Also, it may
344 * make sense to skip pages that are being write monitored since this
345 * information is readily available to the thread if it works on the
346 * per-VM guest memory structures (presently called PGMRAMRANGE).
347 *
348 *
349 * @section sec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
350 *
351 * The pages are organized in allocation chunks in ring-0, this is a necessity
352 * if we wish to have an OS agnostic approach to this whole thing. (On Linux we
353 * could easily work on a page-by-page basis if we liked. Whether this is possible
354 * or efficient on NT I don't quite know.) Fragmentation within these chunks may
355 * become a problem as part of the idea here is that we wish to return memory to
356 * the host system.
357 *
358 * For instance, starting two VMs at the same time, they will both allocate the
359 * guest memory on-demand and if permitted their page allocations will be
360 * intermixed. Shut down one of the two VMs and it will be difficult to return
361 * any memory to the host system because the page allocation for the two VMs are
362 * mixed up in the same allocation chunks.
363 *
364 * To further complicate matters, when pages are freed because they have been
365 * ballooned or become shared/zero the whole idea is that the page is supposed
366 * to be reused by another VM or returned to the host system. This will cause
367 * allocation chunks to contain pages belonging to different VMs and prevent
368 * returning memory to the host when one of those VM shuts down.
369 *
370 * The only way to really deal with this problem is to move pages. This can
371 * either be done at VM shutdown and or by the idle priority worker thread
372 * that will be responsible for finding sharable/zero pages. The mechanisms
373 * involved for coercing a VM to move a page (or to do it for it) will be
374 * the same as when telling it to share/zero a page.
375 *
376 *
377 * @section sec_pgmPhys_Tracking Tracking Structures And Their Cost
378 *
379 * There's a difficult balance between keeping the per-page tracking structures
380 * (global and guest page) easy to use and keeping them from eating too much
381 * memory. We have limited virtual memory resources available when operating in
382 * 32-bit kernel space (on 64-bit there'll it's quite a different story). The
383 * tracking structures will be attempted designed such that we can deal with up
384 * to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
385 *
386 *
387 * @subsection subsec_pgmPhys_Tracking_Kernel Kernel Space
388 *
389 * @see pg_GMM
390 *
391 * @subsection subsec_pgmPhys_Tracking_PerVM Per-VM
392 *
393 * Fixed info is the physical address of the page (HCPhys) and the page id
394 * (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
395 * Today we've restricting ourselves to 40(-12) bits because this is the current
396 * restrictions of all AMD64 implementations (I think Barcelona will up this
397 * to 48(-12) bits, not that it really matters) and I needed the bits for
398 * tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
399 * decent range for the page id: 2^(28+12) = 1024TB.
400 *
401 * In additions to these, we'll have to keep maintaining the page flags as we
402 * currently do. Although it wouldn't harm to optimize these quite a bit, like
403 * for instance the ROM shouldn't depend on having a write handler installed
404 * in order for it to become read-only. A RO/RW bit should be considered so
405 * that the page syncing code doesn't have to mess about checking multiple
406 * flag combinations (ROM || RW handler || write monitored) in order to
407 * figure out how to setup a shadow PTE. But this of course, is second
408 * priority at present. Current this requires 12 bits, but could probably
409 * be optimized to ~8.
410 *
411 * Then there's the 24 bits used to track which shadow page tables are
412 * currently mapping a page for the purpose of speeding up physical
413 * access handlers, and thereby the page pool cache. More bit for this
414 * purpose wouldn't hurt IIRC.
415 *
416 * Then there is a new bit in which we need to record what kind of page
417 * this is, shared, zero, normal or write-monitored-normal. This'll
418 * require 2 bits. One bit might be needed for indicating whether a
419 * write monitored page has been written to. And yet another one or
420 * two for tracking migration status. 3-4 bits total then.
421 *
422 * Whatever is left will can be used to record the sharabilitiy of a
423 * page. The page checksum will not be stored in the per-VM table as
424 * the idle thread will not be permitted to do modifications to it.
425 * It will instead have to keep its own working set of potentially
426 * shareable pages and their check sums and stuff.
427 *
428 * For the present we'll keep the current packing of the
429 * PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
430 * we'll have to change it to a struct with a total of 128-bits at
431 * our disposal.
432 *
433 * The initial layout will be like this:
434 * @verbatim
435 RTHCPHYS HCPhys; The current stuff.
436 63:40 Current shadow PT tracking stuff.
437 39:12 The physical page frame number.
438 11:0 The current flags.
439 uint32_t u28PageId : 28; The page id.
440 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
441 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
442 uint32_t u1Reserved : 1; Reserved for later.
443 uint32_t u32Reserved; Reserved for later, mostly sharing stats.
444 @endverbatim
445 *
446 * The final layout will be something like this:
447 * @verbatim
448 RTHCPHYS HCPhys; The current stuff.
449 63:48 High page id (12+).
450 47:12 The physical page frame number.
451 11:0 Low page id.
452 uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
453 uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
454 uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
455 uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
456 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
457 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
458 uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
459 uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
460 @endverbatim
461 *
462 * Cost wise, this means we'll double the cost for guest memory. There isn't anyway
463 * around that I'm afraid. It means that the cost of dealing out 32GB of memory
464 * to one or more VMs is: (32GB >> GUEST_PAGE_SHIFT) * 16 bytes, or 128MBs. Or
465 * another example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
466 *
467 * A couple of cost examples for the total cost per-VM + kernel.
468 * 32-bit Windows and 32-bit linux:
469 * 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
470 * 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
471 * 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
472 * 64-bit Windows and 64-bit linux:
473 * 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
474 * 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
475 * 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
476 *
477 * UPDATE - 2007-09-27:
478 * Will need a ballooned flag/state too because we cannot
479 * trust the guest 100% and reporting the same page as ballooned more
480 * than once will put the GMM off balance.
481 *
482 *
483 * @section sec_pgmPhys_Serializing Serializing Access
484 *
485 * Initially, we'll try a simple scheme:
486 *
487 * - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
488 * by the EMT thread of that VM while in the pgm critsect.
489 * - Other threads in the VM process that needs to make reliable use of
490 * the per-VM RAM tracking structures will enter the critsect.
491 * - No process external thread or kernel thread will ever try enter
492 * the pgm critical section, as that just won't work.
493 * - The idle thread (and similar threads) doesn't not need 100% reliable
494 * data when performing it tasks as the EMT thread will be the one to
495 * do the actual changes later anyway. So, as long as it only accesses
496 * the main ram range, it can do so by somehow preventing the VM from
497 * being destroyed while it works on it...
498 *
499 * - The over-commitment management, including the allocating/freeing
500 * chunks, is serialized by a ring-0 mutex lock (a fast one since the
501 * more mundane mutex implementation is broken on Linux).
502 * - A separate mutex is protecting the set of allocation chunks so
503 * that pages can be shared or/and freed up while some other VM is
504 * allocating more chunks. This mutex can be take from under the other
505 * one, but not the other way around.
506 *
507 *
508 * @section sec_pgmPhys_Request VM Request interface
509 *
510 * When in ring-0 it will become necessary to send requests to a VM so it can
511 * for instance move a page while defragmenting during VM destroy. The idle
512 * thread will make use of this interface to request VMs to setup shared
513 * pages and to perform write monitoring of pages.
514 *
515 * I would propose an interface similar to the current VMReq interface, similar
516 * in that it doesn't require locking and that the one sending the request may
517 * wait for completion if it wishes to. This shouldn't be very difficult to
518 * realize.
519 *
520 * The requests themselves are also pretty simple. They are basically:
521 * -# Check that some precondition is still true.
522 * -# Do the update.
523 * -# Update all shadow page tables involved with the page.
524 *
525 * The 3rd step is identical to what we're already doing when updating a
526 * physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
527 *
528 *
529 *
530 * @section sec_pgmPhys_MappingCaches Mapping Caches
531 *
532 * In order to be able to map in and out memory and to be able to support
533 * guest with more RAM than we've got virtual address space, we'll employing
534 * a mapping cache. Normally ring-0 and ring-3 can share the same cache,
535 * however on 32-bit darwin the ring-0 code is running in a different memory
536 * context and therefore needs a separate cache. In raw-mode context we also
537 * need a separate cache. The 32-bit darwin mapping cache and the one for
538 * raw-mode context share a lot of code, see PGMRZDYNMAP.
539 *
540 *
541 * @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
542 *
543 * We've considered implementing the ring-3 mapping cache page based but found
544 * that this was bother some when one had to take into account TLBs+SMP and
545 * portability (missing the necessary APIs on several platforms). There were
546 * also some performance concerns with this approach which hadn't quite been
547 * worked out.
548 *
549 * Instead, we'll be mapping allocation chunks into the VM process. This simplifies
550 * matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
551 * only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
552 * compared to the previous idea is that mapping or unmapping a 1MB chunk is more
553 * costly than a single page, although how much more costly is uncertain. We'll
554 * try address this by using a very big cache, preferably bigger than the actual
555 * VM RAM size if possible. The current VM RAM sizes should give some idea for
556 * 32-bit boxes, while on 64-bit we can probably get away with employing an
557 * unlimited cache.
558 *
559 * The cache have to parts, as already indicated, the ring-3 side and the
560 * ring-0 side.
561 *
562 * The ring-0 will be tied to the page allocator since it will operate on the
563 * memory objects it contains. It will therefore require the first ring-0 mutex
564 * discussed in @ref sec_pgmPhys_Serializing. We some double house keeping wrt
565 * to who has mapped what I think, since both VMMR0.r0 and RTR0MemObj will keep
566 * track of mapping relations
567 *
568 * The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
569 * require anyone that desires to do changes to the mapping cache to do that
570 * from within this critsect. Alternatively, we could employ a separate critsect
571 * for serializing changes to the mapping cache as this would reduce potential
572 * contention with other threads accessing mappings unrelated to the changes
573 * that are in process. We can see about this later, contention will show
574 * up in the statistics anyway, so it'll be simple to tell.
575 *
576 * The organization of the ring-3 part will be very much like how the allocation
577 * chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
578 * having to walk the tree all the time, we'll have a couple of lookaside entries
579 * like in we do for I/O ports and MMIO in IOM.
580 *
581 * The simplified flow of a PGMPhysRead/Write function:
582 * -# Enter the PGM critsect.
583 * -# Lookup GCPhys in the ram ranges and get the Page ID.
584 * -# Calc the Allocation Chunk ID from the Page ID.
585 * -# Check the lookaside entries and then the AVL tree for the Chunk ID.
586 * If not found in cache:
587 * -# Call ring-0 and request it to be mapped and supply
588 * a chunk to be unmapped if the cache is maxed out already.
589 * -# Insert the new mapping into the AVL tree (id + R3 address).
590 * -# Update the relevant lookaside entry and return the mapping address.
591 * -# Do the read/write according to monitoring flags and everything.
592 * -# Leave the critsect.
593 *
594 *
595 * @section sec_pgmPhys_Changes Changes
596 *
597 * Breakdown of the changes involved?
598 */
599
600
601/*********************************************************************************************************************************
602* Header Files *
603*********************************************************************************************************************************/
604#define LOG_GROUP LOG_GROUP_PGM
605#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
606#include <VBox/vmm/dbgf.h>
607#include <VBox/vmm/pgm.h>
608#include <VBox/vmm/cpum.h>
609#include <VBox/vmm/iom.h>
610#include <VBox/sup.h>
611#include <VBox/vmm/mm.h>
612#include <VBox/vmm/em.h>
613#include <VBox/vmm/stam.h>
614#include <VBox/vmm/selm.h>
615#include <VBox/vmm/ssm.h>
616#include <VBox/vmm/hm.h>
617#include "PGMInternal.h"
618#include <VBox/vmm/vmcc.h>
619#include <VBox/vmm/uvm.h>
620#include "PGMInline.h"
621
622#include <VBox/dbg.h>
623#include <VBox/param.h>
624#include <VBox/err.h>
625
626#include <iprt/asm.h>
627#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
628# include <iprt/asm-amd64-x86.h>
629#endif
630#include <iprt/assert.h>
631#include <iprt/env.h>
632#include <iprt/file.h>
633#include <iprt/mem.h>
634#include <iprt/rand.h>
635#include <iprt/string.h>
636#include <iprt/thread.h>
637#ifdef RT_OS_LINUX
638# include <iprt/linux/sysfs.h>
639#endif
640
641
642/*********************************************************************************************************************************
643* Structures and Typedefs *
644*********************************************************************************************************************************/
645/**
646 * Argument package for pgmR3RElocatePhysHnadler, pgmR3RelocateVirtHandler and
647 * pgmR3RelocateHyperVirtHandler.
648 */
649typedef struct PGMRELOCHANDLERARGS
650{
651 RTGCINTPTR offDelta;
652 PVM pVM;
653} PGMRELOCHANDLERARGS;
654/** Pointer to a page access handlere relocation argument package. */
655typedef PGMRELOCHANDLERARGS const *PCPGMRELOCHANDLERARGS;
656
657
658/*********************************************************************************************************************************
659* Internal Functions *
660*********************************************************************************************************************************/
661static int pgmR3InitPaging(PVM pVM);
662static int pgmR3InitStats(PVM pVM);
663static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
664static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
665static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
666#ifdef VBOX_STRICT
667static FNVMATSTATE pgmR3ResetNoMorePhysWritesFlag;
668#endif
669
670#ifdef VBOX_WITH_DEBUGGER
671static FNDBGCCMD pgmR3CmdError;
672static FNDBGCCMD pgmR3CmdSync;
673static FNDBGCCMD pgmR3CmdSyncAlways;
674# ifdef VBOX_STRICT
675static FNDBGCCMD pgmR3CmdAssertCR3;
676# endif
677static FNDBGCCMD pgmR3CmdPhysToFile;
678#endif
679
680
681/*********************************************************************************************************************************
682* Global Variables *
683*********************************************************************************************************************************/
684#ifdef VBOX_WITH_DEBUGGER
685/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
686static const DBGCVARDESC g_aPgmErrorArgs[] =
687{
688 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
689 { 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
690};
691
692static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
693{
694 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
695 { 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
696 { 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
697};
698
699# ifdef DEBUG_sandervl
700static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
701{
702 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
703 { 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
704 { 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
705};
706# endif
707
708/** Command descriptors. */
709static const DBGCCMD g_aCmds[] =
710{
711 /* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
712 { "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
713 { "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
714 { "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
715# ifdef VBOX_STRICT
716 { "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
717# ifdef VBOX_WITH_PAGE_SHARING
718 { "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
719 { "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
720# endif
721# endif
722 { "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
723 { "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
724};
725#endif
726
727#ifdef VBOX_WITH_PGM_NEM_MODE
728
729/**
730 * Interface that NEM uses to switch PGM into simplified memory managment mode.
731 *
732 * This call occurs before PGMR3Init.
733 *
734 * @param pVM The cross context VM structure.
735 */
736VMMR3_INT_DECL(void) PGMR3EnableNemMode(PVM pVM)
737{
738 AssertFatal(!PDMCritSectIsInitialized(&pVM->pgm.s.CritSectX));
739 if (!pVM->pgm.s.fNemMode)
740 {
741 LogRel(("PGM: Enabling NEM mode\n"));
742 pVM->pgm.s.fNemMode = true;
743 }
744}
745
746
747/**
748 * Checks whether the simplificed memory management mode for NEM is enabled.
749 *
750 * @returns true if enabled, false if not.
751 * @param pVM The cross context VM structure.
752 */
753VMMR3_INT_DECL(bool) PGMR3IsNemModeEnabled(PVM pVM)
754{
755 return pVM->pgm.s.fNemMode;
756}
757
758#endif /* VBOX_WITH_PGM_NEM_MODE */
759
760/**
761 * Initiates the paging of VM.
762 *
763 * @returns VBox status code.
764 * @param pVM The cross context VM structure.
765 */
766VMMR3DECL(int) PGMR3Init(PVM pVM)
767{
768 LogFlow(("PGMR3Init:\n"));
769 PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
770 int rc;
771
772 /*
773 * Assert alignment and sizes.
774 */
775 AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
776 AssertCompile(sizeof(pVM->apCpusR3[0]->pgm.s) <= sizeof(pVM->apCpusR3[0]->pgm.padding));
777 AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
778
779 /*
780 * If we're in driveless mode we have to use the simplified memory mode.
781 */
782 bool const fDriverless = SUPR3IsDriverless();
783 if (fDriverless)
784 {
785#ifdef VBOX_WITH_PGM_NEM_MODE
786 if (!pVM->pgm.s.fNemMode)
787 {
788 LogRel(("PGM: Enabling NEM mode (driverless)\n"));
789 pVM->pgm.s.fNemMode = true;
790 }
791#else
792 return VMR3SetError(pVM->pUVM, VERR_SUP_DRIVERLESS, RT_SRC_POS,
793 "Driverless requires that VBox is built with VBOX_WITH_PGM_NEM_MODE defined");
794#endif
795 }
796
797 /*
798 * Init the structure.
799 */
800 /*pVM->pgm.s.fRestoreRomPagesAtReset = false;*/
801
802 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
803 {
804 pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_GMMPAGEDESC_PHYS;
805 pVM->pgm.s.aHandyPages[i].fZeroed = false;
806 pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
807 pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
808 }
809
810 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
811 {
812 pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_GMMPAGEDESC_PHYS;
813 pVM->pgm.s.aLargeHandyPage[i].fZeroed = false;
814 pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
815 pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
816 }
817
818 AssertReleaseReturn(pVM->pgm.s.cPhysHandlerTypes == 0, VERR_WRONG_ORDER);
819 for (size_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aPhysHandlerTypes); i++)
820 {
821 if (fDriverless)
822 pVM->pgm.s.aPhysHandlerTypes[i].hType = i | (RTRandU64() & ~(uint64_t)PGMPHYSHANDLERTYPE_IDX_MASK);
823 pVM->pgm.s.aPhysHandlerTypes[i].enmKind = PGMPHYSHANDLERKIND_INVALID;
824 pVM->pgm.s.aPhysHandlerTypes[i].pfnHandler = pgmR3HandlerPhysicalHandlerInvalid;
825 }
826
827 /* Init the per-CPU part. */
828 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
829 {
830 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
831 PPGMCPU pPGM = &pVCpu->pgm.s;
832
833 pPGM->enmShadowMode = PGMMODE_INVALID;
834 pPGM->enmGuestMode = PGMMODE_INVALID;
835 pPGM->enmGuestSlatMode = PGMSLAT_INVALID;
836 pPGM->idxGuestModeData = UINT8_MAX;
837 pPGM->idxShadowModeData = UINT8_MAX;
838 pPGM->idxBothModeData = UINT8_MAX;
839
840 pPGM->GCPhysCR3 = NIL_RTGCPHYS;
841 pPGM->GCPhysNstGstCR3 = NIL_RTGCPHYS;
842 pPGM->GCPhysPaeCR3 = NIL_RTGCPHYS;
843
844 pPGM->pGst32BitPdR3 = NULL;
845 pPGM->pGstPaePdptR3 = NULL;
846 pPGM->pGstAmd64Pml4R3 = NULL;
847 pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
848 pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
849 pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
850#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
851 pPGM->pGstEptPml4R3 = NULL;
852 pPGM->pGstEptPml4R0 = NIL_RTR0PTR;
853 pPGM->uEptPtr = 0;
854#endif
855 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
856 {
857 pPGM->apGstPaePDsR3[i] = NULL;
858 pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
859 pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
860 }
861
862 pPGM->fA20Enabled = true;
863 pPGM->GCPhysA20Mask = ~((RTGCPHYS)!pPGM->fA20Enabled << 20);
864 }
865
866 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
867 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
868
869 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
870#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
871 true
872#else
873 false
874#endif
875 );
876 AssertLogRelRCReturn(rc, rc);
877
878#if HC_ARCH_BITS == 32
879# ifdef RT_OS_DARWIN
880 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
881# else
882 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
883# endif
884#else
885 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
886#endif
887 AssertLogRelRCReturn(rc, rc);
888 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
889 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
890
891 /*
892 * Get the configured RAM size - to estimate saved state size.
893 */
894 uint64_t cbRam;
895 rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
896 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
897 cbRam = 0;
898 else if (RT_SUCCESS(rc))
899 {
900 if (cbRam < GUEST_PAGE_SIZE)
901 cbRam = 0;
902 cbRam = RT_ALIGN_64(cbRam, GUEST_PAGE_SIZE);
903 }
904 else
905 {
906 AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
907 return rc;
908 }
909
910 /*
911 * Check for PCI pass-through and other configurables.
912 */
913 rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
914 AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
915 AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough || pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
916
917 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "PageFusionAllowed", &pVM->pgm.s.fPageFusionAllowed, false);
918 AssertLogRelRCReturn(rc, rc);
919
920 /** @cfgm{/PGM/ZeroRamPagesOnReset, boolean, true}
921 * Whether to clear RAM pages on (hard) reset. */
922 rc = CFGMR3QueryBoolDef(pCfgPGM, "ZeroRamPagesOnReset", &pVM->pgm.s.fZeroRamPagesOnReset, true);
923 AssertLogRelRCReturn(rc, rc);
924
925 /*
926 * Register callbacks, string formatters and the saved state data unit.
927 */
928#ifdef VBOX_STRICT
929 VMR3AtStateRegister(pVM->pUVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
930#endif
931 PGMRegisterStringFormatTypes();
932
933 rc = pgmR3InitSavedState(pVM, cbRam);
934 if (RT_FAILURE(rc))
935 return rc;
936
937 /*
938 * Initialize the PGM critical section and flush the phys TLBs
939 */
940 rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
941 AssertRCReturn(rc, rc);
942
943 pgmR3PhysChunkInvalidateTLB(pVM, false /*fInRendezvous*/); /* includes pgmPhysInvalidatePageMapTLB call */
944
945 /*
946 * For the time being we sport a full set of handy pages in addition to the base
947 * memory to simplify things.
948 */
949 rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
950 AssertRCReturn(rc, rc);
951
952 /*
953 * Setup the zero page (HCPHysZeroPg is set by ring-0).
954 */
955 RT_ZERO(pVM->pgm.s.abZeroPg); /* paranoia */
956 if (fDriverless)
957 pVM->pgm.s.HCPhysZeroPg = _4G - GUEST_PAGE_SIZE * 2 /* fake to avoid PGM_PAGE_INIT_ZERO assertion */;
958 AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
959 AssertRelease(pVM->pgm.s.HCPhysZeroPg != 0);
960 Log(("HCPhysZeroPg=%RHp abZeroPg=%p\n", pVM->pgm.s.HCPhysZeroPg, pVM->pgm.s.abZeroPg));
961
962 /*
963 * Setup the invalid MMIO page (HCPhysMmioPg is set by ring-0).
964 * (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
965 */
966 ASMMemFill32(pVM->pgm.s.abMmioPg, sizeof(pVM->pgm.s.abMmioPg), 0xfeedface);
967 if (fDriverless)
968 pVM->pgm.s.HCPhysMmioPg = _4G - GUEST_PAGE_SIZE * 3 /* fake to avoid PGM_PAGE_INIT_ZERO assertion */;
969 AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
970 AssertRelease(pVM->pgm.s.HCPhysMmioPg != 0);
971 pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
972 Log(("HCPhysInvMmioPg=%RHp abMmioPg=%p\n", pVM->pgm.s.HCPhysMmioPg, pVM->pgm.s.abMmioPg));
973
974 /*
975 * Initialize physical access handlers.
976 */
977 /** @cfgm{/PGM/MaxPhysicalAccessHandlers, uint32_t, 32, 65536, 6144}
978 * Number of physical access handlers allowed (subject to rounding). This is
979 * managed as one time allocation during initializations. The default is
980 * lower for a driverless setup. */
981 /** @todo can lower it for nested paging too, at least when there is no
982 * nested guest involved. */
983 uint32_t cAccessHandlers = 0;
984 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxPhysicalAccessHandlers", &cAccessHandlers, !fDriverless ? 6144 : 640);
985 AssertLogRelRCReturn(rc, rc);
986 AssertLogRelMsgStmt(cAccessHandlers >= 32, ("cAccessHandlers=%#x, min 32\n", cAccessHandlers), cAccessHandlers = 32);
987 AssertLogRelMsgStmt(cAccessHandlers <= _64K, ("cAccessHandlers=%#x, max 65536\n", cAccessHandlers), cAccessHandlers = _64K);
988 if (!fDriverless)
989 {
990 rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_HANDLER_INIT, cAccessHandlers, NULL);
991 AssertRCReturn(rc, rc);
992 AssertPtr(pVM->pgm.s.pPhysHandlerTree);
993 AssertPtr(pVM->pgm.s.PhysHandlerAllocator.m_paNodes);
994 AssertPtr(pVM->pgm.s.PhysHandlerAllocator.m_pbmAlloc);
995 }
996 else
997 {
998 uint32_t cbTreeAndBitmap = 0;
999 uint32_t const cbTotalAligned = pgmHandlerPhysicalCalcTableSizes(&cAccessHandlers, &cbTreeAndBitmap);
1000 uint8_t *pb = NULL;
1001 rc = SUPR3PageAlloc(cbTotalAligned >> HOST_PAGE_SHIFT, 0, (void **)&pb);
1002 AssertLogRelRCReturn(rc, rc);
1003
1004 pVM->pgm.s.PhysHandlerAllocator.initSlabAllocator(cAccessHandlers, (PPGMPHYSHANDLER)&pb[cbTreeAndBitmap],
1005 (uint64_t *)&pb[sizeof(PGMPHYSHANDLERTREE)]);
1006 pVM->pgm.s.pPhysHandlerTree = (PPGMPHYSHANDLERTREE)pb;
1007 pVM->pgm.s.pPhysHandlerTree->initWithAllocator(&pVM->pgm.s.PhysHandlerAllocator);
1008 }
1009
1010 /*
1011 * Register the physical access handler protecting ROMs.
1012 */
1013 if (RT_SUCCESS(rc))
1014 /** @todo why isn't pgmPhysRomWriteHandler registered for ring-0? */
1015 rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_WRITE, 0 /*fFlags*/, pgmPhysRomWriteHandler,
1016 "ROM write protection", &pVM->pgm.s.hRomPhysHandlerType);
1017
1018 /*
1019 * Register the physical access handler doing dirty MMIO2 tracing.
1020 */
1021 if (RT_SUCCESS(rc))
1022 rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_WRITE, PGMPHYSHANDLER_F_KEEP_PGM_LOCK,
1023 pgmPhysMmio2WriteHandler, "MMIO2 dirty page tracing",
1024 &pVM->pgm.s.hMmio2DirtyPhysHandlerType);
1025
1026 /*
1027 * Init the paging.
1028 */
1029 if (RT_SUCCESS(rc))
1030 rc = pgmR3InitPaging(pVM);
1031
1032 /*
1033 * Init the page pool.
1034 */
1035 if (RT_SUCCESS(rc))
1036 rc = pgmR3PoolInit(pVM);
1037
1038 if (RT_SUCCESS(rc))
1039 {
1040 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1041 {
1042 PVMCPU pVCpu = pVM->apCpusR3[i];
1043 rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL, false /* fForce */);
1044 if (RT_FAILURE(rc))
1045 break;
1046 }
1047 }
1048
1049 if (RT_SUCCESS(rc))
1050 {
1051 /*
1052 * Info & statistics
1053 */
1054 DBGFR3InfoRegisterInternalEx(pVM, "mode",
1055 "Shows the current paging mode. "
1056 "Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1057 pgmR3InfoMode,
1058 DBGFINFO_FLAGS_ALL_EMTS);
1059 DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1060 "Dumps all the entries in the top level paging table. No arguments.",
1061 pgmR3InfoCr3);
1062 DBGFR3InfoRegisterInternal(pVM, "phys",
1063 "Dumps all the physical address ranges. Pass 'verbose' to get more details.",
1064 pgmR3PhysInfo);
1065 DBGFR3InfoRegisterInternal(pVM, "handlers",
1066 "Dumps physical, virtual and hyper virtual handlers. "
1067 "Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1068 "Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1069 pgmR3InfoHandlers);
1070
1071 pgmR3InitStats(pVM);
1072
1073#ifdef VBOX_WITH_DEBUGGER
1074 /*
1075 * Debugger commands.
1076 */
1077 static bool s_fRegisteredCmds = false;
1078 if (!s_fRegisteredCmds)
1079 {
1080 int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1081 if (RT_SUCCESS(rc2))
1082 s_fRegisteredCmds = true;
1083 }
1084#endif
1085
1086#ifdef RT_OS_LINUX
1087 /*
1088 * Log the /proc/sys/vm/max_map_count value on linux as that is
1089 * frequently giving us grief when too low.
1090 */
1091 int64_t const cGuessNeeded = MMR3PhysGetRamSize(pVM) / _2M + 16384 /*guesstimate*/;
1092 int64_t cMaxMapCount = 0;
1093 int rc2 = RTLinuxSysFsReadIntFile(10, &cMaxMapCount, "/proc/sys/vm/max_map_count");
1094 LogRel(("PGM: /proc/sys/vm/max_map_count = %RI64 (rc2=%Rrc); cGuessNeeded=%RI64\n", cMaxMapCount, rc2, cGuessNeeded));
1095 if (RT_SUCCESS(rc2) && cMaxMapCount < cGuessNeeded)
1096 LogRel(("PGM: WARNING!!\n"
1097 "PGM: WARNING!! Please increase /proc/sys/vm/max_map_count to at least %RI64 (or reduce the amount of RAM assigned to the VM)!\n"
1098 "PGM: WARNING!!\n", cMaxMapCount));
1099
1100#endif
1101
1102 return VINF_SUCCESS;
1103 }
1104
1105 /* Almost no cleanup necessary, MM frees all memory. */
1106 PDMR3CritSectDelete(pVM, &pVM->pgm.s.CritSectX);
1107
1108 return rc;
1109}
1110
1111
1112/**
1113 * Init paging.
1114 *
1115 * Since we need to check what mode the host is operating in before we can choose
1116 * the right paging functions for the host we have to delay this until R0 has
1117 * been initialized.
1118 *
1119 * @returns VBox status code.
1120 * @param pVM The cross context VM structure.
1121 */
1122static int pgmR3InitPaging(PVM pVM)
1123{
1124 /*
1125 * Force a recalculation of modes and switcher so everyone gets notified.
1126 */
1127 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1128 {
1129 PVMCPU pVCpu = pVM->apCpusR3[i];
1130
1131 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1132 pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1133 pVCpu->pgm.s.enmGuestSlatMode = PGMSLAT_INVALID;
1134 pVCpu->pgm.s.idxGuestModeData = UINT8_MAX;
1135 pVCpu->pgm.s.idxShadowModeData = UINT8_MAX;
1136 pVCpu->pgm.s.idxBothModeData = UINT8_MAX;
1137 }
1138
1139 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1140
1141 /*
1142 * Initialize paging workers and mode from current host mode
1143 * and the guest running in real mode.
1144 */
1145 pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1146 switch (pVM->pgm.s.enmHostMode)
1147 {
1148 case SUPPAGINGMODE_32_BIT:
1149 case SUPPAGINGMODE_32_BIT_GLOBAL:
1150 case SUPPAGINGMODE_PAE:
1151 case SUPPAGINGMODE_PAE_GLOBAL:
1152 case SUPPAGINGMODE_PAE_NX:
1153 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1154
1155 case SUPPAGINGMODE_AMD64:
1156 case SUPPAGINGMODE_AMD64_GLOBAL:
1157 case SUPPAGINGMODE_AMD64_NX:
1158 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1159 if (ARCH_BITS != 64)
1160 {
1161 AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1162 LogRel(("PGM: Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1163 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1164 }
1165 break;
1166#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
1167 case SUPPAGINGMODE_INVALID:
1168 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_AMD64_GLOBAL_NX;
1169 break;
1170#endif
1171 default:
1172 AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1173 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1174 }
1175
1176 LogFlow(("pgmR3InitPaging: returns successfully\n"));
1177#if HC_ARCH_BITS == 64 && 0
1178 LogRel(("PGM: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1179 pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1180 LogRel(("PGM: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1181 MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1182 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1183 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1184 MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1185#endif
1186
1187 /*
1188 * Log the host paging mode. It may come in handy.
1189 */
1190 const char *pszHostMode;
1191 switch (pVM->pgm.s.enmHostMode)
1192 {
1193 case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1194 case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1195 case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1196 case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1197 case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1198 case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1199 case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1200 case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1201 case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1202 case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1203 default: pszHostMode = "???"; break;
1204 }
1205 LogRel(("PGM: Host paging mode: %s\n", pszHostMode));
1206
1207 return VINF_SUCCESS;
1208}
1209
1210
1211/**
1212 * Init statistics
1213 * @returns VBox status code.
1214 */
1215static int pgmR3InitStats(PVM pVM)
1216{
1217 PPGM pPGM = &pVM->pgm.s;
1218 int rc;
1219
1220 /*
1221 * Release statistics.
1222 */
1223 /* Common - misc variables */
1224 STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1225 STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1226 STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1227 STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1228 STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1229 STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1230 STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1231 STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1232 STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1233 STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1234 STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1235 STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1236 STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1237 STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1238 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1239 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1240 STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1241 STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1242
1243 STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1244 STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1245 STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1246
1247 STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1248 STAM_REL_REG(pVM, &pPGM->StatMmio2QueryAndResetDirtyBitmap, STAMTYPE_PROFILE, "/PGM/Mmio2QueryAndResetDirtyBitmap", STAMUNIT_TICKS_PER_CALL, "Profiles calls to PGMR3PhysMmio2QueryAndResetDirtyBitmap (sans locking).");
1249
1250 /* Live save */
1251 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1252 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1253 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1254 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1255 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1256 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1257 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1258 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1259 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1260 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1261 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1262 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1263 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1264 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1265 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1266 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1267 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1268 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1269
1270#define PGM_REG_COUNTER(a, b, c) \
1271 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1272 AssertRC(rc);
1273
1274#define PGM_REG_U64(a, b, c) \
1275 rc = STAMR3RegisterF(pVM, a, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1276 AssertRC(rc);
1277
1278#define PGM_REG_U64_RESET(a, b, c) \
1279 rc = STAMR3RegisterF(pVM, a, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1280 AssertRC(rc);
1281
1282#define PGM_REG_U32(a, b, c) \
1283 rc = STAMR3RegisterF(pVM, a, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1284 AssertRC(rc);
1285
1286#define PGM_REG_COUNTER_BYTES(a, b, c) \
1287 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1288 AssertRC(rc);
1289
1290#define PGM_REG_PROFILE(a, b, c) \
1291 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1292 AssertRC(rc);
1293#define PGM_REG_PROFILE_NS(a, b, c) \
1294 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_NS_PER_CALL, c, b); \
1295 AssertRC(rc);
1296
1297#ifdef VBOX_WITH_STATISTICS
1298 PGMSTATS *pStats = &pPGM->Stats;
1299#endif
1300
1301 PGM_REG_PROFILE_NS(&pPGM->StatLargePageAlloc, "/PGM/LargePage/Alloc", "Time spent by the host OS for large page allocation.");
1302 PGM_REG_COUNTER(&pPGM->StatLargePageAllocFailed, "/PGM/LargePage/AllocFailed", "Number of allocation failures.");
1303 PGM_REG_COUNTER(&pPGM->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
1304 PGM_REG_COUNTER(&pPGM->StatLargePageTlbFlush, "/PGM/LargePage/TlbFlush", "The number of times a full VCPU TLB flush was required after a large allocation.");
1305 PGM_REG_COUNTER(&pPGM->StatLargePageZeroEvict, "/PGM/LargePage/ZeroEvict", "The number of zero page mappings we had to evict when allocating a large page.");
1306#ifdef VBOX_WITH_STATISTICS
1307 PGM_REG_PROFILE(&pStats->StatLargePageAlloc2, "/PGM/LargePage/Alloc2", "Time spent allocating large pages.");
1308 PGM_REG_PROFILE(&pStats->StatLargePageSetup, "/PGM/LargePage/Setup", "Time spent setting up the newly allocated large pages.");
1309 PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/IsValidR3", "pgmPhysIsValidLargePage profiling - R3.");
1310 PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/IsValidRZ", "pgmPhysIsValidLargePage profiling - RZ.");
1311
1312 PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1313 PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1314 PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1315 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1316 PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1317 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1318 PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1319 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1320 PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1321 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1322
1323 PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1324 PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1325 PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1326 PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1327 PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1328 PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1329
1330 PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1331 PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1332 PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1333 PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1334 PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1335 PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1336 PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1337 PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1338
1339 PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
1340 PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
1341 PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
1342 PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
1343
1344 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1345 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1346 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1347 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1348 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1349 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1350#endif /* VBOX_WITH_STATISTICS */
1351 PPGMPHYSHANDLERTREE pPhysHndlTree = pVM->pgm.s.pPhysHandlerTree;
1352 PGM_REG_U32(&pPhysHndlTree->m_cErrors, "/PGM/PhysHandlerTree/ErrorsTree", "Physical access handler tree errors.");
1353 PGM_REG_U32(&pVM->pgm.s.PhysHandlerAllocator.m_cErrors, "/PGM/PhysHandlerTree/ErrorsAllocatorR3", "Physical access handler tree allocator errors (ring-3 only).");
1354 PGM_REG_U64_RESET(&pPhysHndlTree->m_cInserts, "/PGM/PhysHandlerTree/Inserts", "Physical access handler tree inserts.");
1355 PGM_REG_U32(&pVM->pgm.s.PhysHandlerAllocator.m_cNodes, "/PGM/PhysHandlerTree/MaxHandlers", "Max physical access handlers.");
1356 PGM_REG_U64_RESET(&pPhysHndlTree->m_cRemovals, "/PGM/PhysHandlerTree/Removals", "Physical access handler tree removals.");
1357 PGM_REG_U64_RESET(&pPhysHndlTree->m_cRebalancingOperations, "/PGM/PhysHandlerTree/RebalancingOperations", "Physical access handler tree rebalancing transformations.");
1358
1359#ifdef VBOX_WITH_STATISTICS
1360 PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1361 PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1362/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1363 PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1364 PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1365/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1366
1367 PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1368 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1369 PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1370 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1371 PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1372 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1373 PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1374 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1375
1376 /* GC only: */
1377 PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1378 PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1379
1380 PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1381 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1382 PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1383 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1384 PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1385 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1386 PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1387 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1388
1389 PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1390 PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1391 PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1392 PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1393 PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1394 PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1395 PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1396#endif
1397
1398#undef PGM_REG_COUNTER
1399#undef PGM_REG_U64
1400#undef PGM_REG_U64_RESET
1401#undef PGM_REG_U32
1402#undef PGM_REG_PROFILE
1403#undef PGM_REG_PROFILE_NS
1404
1405 /*
1406 * Note! The layout below matches the member layout exactly!
1407 */
1408
1409 /*
1410 * Common - stats
1411 */
1412 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1413 {
1414 PPGMCPU pPgmCpu = &pVM->apCpusR3[idCpu]->pgm.s;
1415
1416#define PGM_REG_COUNTER(a, b, c) \
1417 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1418 AssertRC(rc);
1419#define PGM_REG_PROFILE(a, b, c) \
1420 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1421 AssertRC(rc);
1422
1423 PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1424 PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
1425
1426 PGM_REG_COUNTER(&pPgmCpu->StatRZRamRangeTlbMisses, "/PGM/CPU%u/RZ/RamRange/TlbMisses", "TLB misses (lockless).");
1427 PGM_REG_COUNTER(&pPgmCpu->StatRZRamRangeTlbLocking, "/PGM/CPU%u/RZ/RamRange/TlbLocking", "Lockless TLB failed, falling back on locked lookup.");
1428 PGM_REG_COUNTER(&pPgmCpu->StatRZPageMapTlbMisses, "/PGM/CPU%u/RZ/Page/MapTlbMisses", "Lockless page map TLB failed, falling back on locked lookup.");
1429
1430 PGM_REG_COUNTER(&pPgmCpu->StatR3RamRangeTlbMisses, "/PGM/CPU%u/R3/RamRange/TlbMisses", "TLB misses (lockless).");
1431 PGM_REG_COUNTER(&pPgmCpu->StatR3RamRangeTlbLocking, "/PGM/CPU%u/R3/RamRange/TlbLocking", "Lockless TLB failed, falling back on locked lookup.");
1432 PGM_REG_COUNTER(&pPgmCpu->StatR3PageMapTlbMisses, "/PGM/CPU%u/R3/Page/MapTlbMisses", "Lockless page map TLB failed, falling back on locked lookup.");
1433
1434#ifdef VBOX_WITH_STATISTICS
1435 PGMCPUSTATS *pCpuStats = &pVM->apCpusR3[idCpu]->pgm.s.Stats;
1436
1437# if 0 /* rarely useful; leave for debugging. */
1438 for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1439 STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1440 "The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1441 for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1442 STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1443 "The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1444# endif
1445 /* R0 only: */
1446 PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1447 PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1448
1449 /* RZ only: */
1450 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1451 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1452 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1453 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1454 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1455 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1456 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1457 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1458 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1459 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1460 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1461 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1462 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2PageZeroing, "/PGM/CPU%u/RZ/Trap0e/Time2/PageZeroing", "Profiling of the Trap0eHandler body when the cause is that a zero page is being zeroed.");
1463 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1464 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1465 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsHack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USHack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled.");
1466 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsUnhack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USUnhack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled.");
1467 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1468 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1469 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1470 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1471 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1472 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1473 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1474 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1475 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1476 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1477 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1478 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1479 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1480 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1481 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1482 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1483 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1484 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1485 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1486 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1487 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1488#if 0 /* rarely useful; leave for debugging. */
1489 for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1490 STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1491 "The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1492#endif
1493 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1494 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1495 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1496 PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1497 PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1498
1499 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1500 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1501 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1502 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1503 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1504 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1505 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1506 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1507 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1508 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1509 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1510 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
1511 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1512 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1513 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1514 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1515 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1516 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1517 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1518 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1519 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1520 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1521 //PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1522 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1523 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1524 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1525 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1526 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1527 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1528 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1529 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1530 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1531 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1532 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1533 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1534 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1535
1536 /* HC only: */
1537
1538 /* RZ & R3: */
1539 PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1540 PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1541 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1542 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1543 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1544 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1545 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1546 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1547 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1548 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1549 PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1550 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1551 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1552 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1553 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1554 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1555 PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1556 PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1557 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1558 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1559 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1560 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1561 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1562 PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1563 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1564 PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1565 PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1566 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1567 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1568 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1569 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1570 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1571 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1572 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSizeChanges, "/PGM/CPU%u/RZ/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
1573 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1574 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1575 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1576 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1577 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1578 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1579 PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1580 PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1581 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1582 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1583 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1584 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1585 PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1586 PGM_REG_COUNTER(&pCpuStats->StatRZRamRangeTlbHits, "/PGM/CPU%u/RZ/RamRange/TlbHits", "TLB hits (lockless).");
1587 PGM_REG_COUNTER(&pCpuStats->StatRZPageMapTlbHits, "/PGM/CPU%u/RZ/Page/MapTlbHits", "TLB hits (lockless).");
1588
1589 PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1590 PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1591 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1592 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1593 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1594 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1595 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1596 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1597 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1598 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1599 PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1600 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1601 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1602 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1603 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1604 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1605 PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1606 PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1607 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1608 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1609 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1610 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1611 PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1612 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1613 PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1614 PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1615 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1616 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1617 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1618 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1619 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1620 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1621 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSizeChanges, "/PGM/CPU%u/R3/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
1622 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1623 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1624 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1625 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1626 PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1627 PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1628 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1629 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1630 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1631 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1632 PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1633 PGM_REG_COUNTER(&pCpuStats->StatR3RamRangeTlbHits, "/PGM/CPU%u/R3/RamRange/TlbHits", "TLB hits (lockless).");
1634 PGM_REG_COUNTER(&pCpuStats->StatR3PageMapTlbHits, "/PGM/CPU%u/R3/Page/MapTlbHits", "TLB hits (lockless).");
1635#endif /* VBOX_WITH_STATISTICS */
1636
1637#undef PGM_REG_PROFILE
1638#undef PGM_REG_COUNTER
1639 }
1640
1641 return VINF_SUCCESS;
1642}
1643
1644
1645/**
1646 * Ring-3 init finalizing.
1647 *
1648 * @returns VBox status code.
1649 * @param pVM The cross context VM structure.
1650 */
1651VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1652{
1653 /*
1654 * Determine the max physical address width (MAXPHYADDR) and apply it to
1655 * all the mask members and stuff.
1656 */
1657#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
1658 uint32_t cMaxPhysAddrWidth;
1659 uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
1660 if ( uMaxExtLeaf >= 0x80000008
1661 && uMaxExtLeaf <= 0x80000fff)
1662 {
1663 cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
1664 LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
1665 cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
1666 pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
1667 for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
1668 pVM->pgm.s.HCPhysInvMmioPg |= RT_BIT_64(iBit);
1669 }
1670 else
1671 {
1672 LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
1673 cMaxPhysAddrWidth = 48;
1674 pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
1675 pVM->pgm.s.HCPhysInvMmioPg |= UINT64_C(0x000f0000000000);
1676 }
1677 /* Disabled the below assertion -- triggers 24 vs 39 on my Intel Skylake box for a 32-bit (Guest-type Other/Unknown) VM. */
1678 //AssertMsg(pVM->cpum.ro.GuestFeatures.cMaxPhysAddrWidth == cMaxPhysAddrWidth,
1679 // ("CPUM %u - PGM %u\n", pVM->cpum.ro.GuestFeatures.cMaxPhysAddrWidth, cMaxPhysAddrWidth));
1680#else
1681 uint32_t const cMaxPhysAddrWidth = pVM->cpum.ro.GuestFeatures.cMaxPhysAddrWidth;
1682 LogRel(("PGM: The (guest) CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
1683#endif
1684
1685 /** @todo query from CPUM. */
1686 pVM->pgm.s.GCPhysInvAddrMask = 0;
1687 for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
1688 pVM->pgm.s.GCPhysInvAddrMask |= RT_BIT_64(iBit);
1689
1690 /*
1691 * Initialize the invalid paging entry masks, assuming NX is disabled.
1692 */
1693 uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
1694#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1695 uint64_t const fEptVpidCap = CPUMGetGuestIa32VmxEptVpidCap(pVM->apCpusR3[0]); /* should be identical for all VCPUs */
1696 uint64_t const fGstEptMbzBigPdeMask = EPT_PDE2M_MBZ_MASK
1697 | (RT_BF_GET(fEptVpidCap, VMX_BF_EPT_VPID_CAP_PDE_2M) ^ 1) << EPT_E_BIT_LEAF;
1698 uint64_t const fGstEptMbzBigPdpteMask = EPT_PDPTE1G_MBZ_MASK
1699 | (RT_BF_GET(fEptVpidCap, VMX_BF_EPT_VPID_CAP_PDPTE_1G) ^ 1) << EPT_E_BIT_LEAF;
1700 //uint64_t const GCPhysRsvdAddrMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000fffffffffffff); /* bits 63:52 ignored */
1701#endif
1702 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1703 {
1704 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1705
1706 /** @todo The manuals are not entirely clear whether the physical
1707 * address width is relevant. See table 5-9 in the intel
1708 * manual vs the PDE4M descriptions. Write testcase (NP). */
1709 pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
1710 | X86_PDE4M_MBZ_MASK;
1711
1712 pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask | X86_PTE_PAE_MBZ_MASK_NO_NX;
1713 pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask | X86_PDE_PAE_MBZ_MASK_NO_NX;
1714 pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask | X86_PDE2M_PAE_MBZ_MASK_NO_NX;
1715 pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask | X86_PDPE_PAE_MBZ_MASK;
1716
1717 pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask | X86_PTE_LM_MBZ_MASK_NO_NX;
1718 pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask | X86_PDE_LM_MBZ_MASK_NX;
1719 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask | X86_PDE2M_LM_MBZ_MASK_NX;
1720 pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask | X86_PDPE_LM_MBZ_MASK_NO_NX;
1721 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask | X86_PDPE1G_LM_MBZ_MASK_NO_NX;
1722 pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask | X86_PML4E_MBZ_MASK_NO_NX;
1723
1724 pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_G | X86_PTE_A | X86_PTE_D;
1725 pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_A;
1726 pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A;
1727 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask
1728 = X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_G | X86_PDE4M_A | X86_PDE4M_D;
1729 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A;
1730 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A;
1731
1732#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1733 pVCpu->pgm.s.uEptVpidCapMsr = fEptVpidCap;
1734 pVCpu->pgm.s.fGstEptMbzPteMask = fMbzPageFrameMask | EPT_PTE_MBZ_MASK;
1735 pVCpu->pgm.s.fGstEptMbzPdeMask = fMbzPageFrameMask | EPT_PDE_MBZ_MASK;
1736 pVCpu->pgm.s.fGstEptMbzBigPdeMask = fMbzPageFrameMask | fGstEptMbzBigPdeMask;
1737 pVCpu->pgm.s.fGstEptMbzPdpteMask = fMbzPageFrameMask | EPT_PDPTE_MBZ_MASK;
1738 pVCpu->pgm.s.fGstEptMbzBigPdpteMask = fMbzPageFrameMask | fGstEptMbzBigPdpteMask;
1739 pVCpu->pgm.s.fGstEptMbzPml4eMask = fMbzPageFrameMask | EPT_PML4E_MBZ_MASK;
1740
1741 /* If any of the features in the assert below are enabled, additional bits would need to be shadowed. */
1742 Assert( !pVM->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt
1743 && !pVM->cpum.ro.GuestFeatures.fVmxSppEpt
1744 && !pVM->cpum.ro.GuestFeatures.fVmxEptXcptVe
1745 && !(fEptVpidCap & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY));
1746 /* We currently do -not- shadow reserved bits in guest page tables but instead trap them using non-present permissions,
1747 see todo in (NestedSyncPT). */
1748 pVCpu->pgm.s.fGstEptShadowedPteMask = EPT_PRESENT_MASK;
1749 pVCpu->pgm.s.fGstEptShadowedPdeMask = EPT_PRESENT_MASK;
1750 pVCpu->pgm.s.fGstEptShadowedBigPdeMask = EPT_PRESENT_MASK | EPT_E_LEAF;
1751 pVCpu->pgm.s.fGstEptShadowedPdpteMask = EPT_PRESENT_MASK;
1752 pVCpu->pgm.s.fGstEptShadowedPml4eMask = EPT_PRESENT_MASK | EPT_PML4E_MBZ_MASK;
1753 /* If mode-based execute control for EPT is enabled, we would need to include bit 10 in the present mask. */
1754 pVCpu->pgm.s.fGstEptPresentMask = EPT_PRESENT_MASK;
1755#endif
1756 }
1757
1758 /*
1759 * Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1760 * Intel only goes up to 36 bits, so we stick to 36 as well.
1761 * Update: More recent intel manuals specifies 40 bits just like AMD.
1762 */
1763 uint32_t u32Dummy, u32Features;
1764 CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, 0, -1 /*f64BitMode*/, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1765 if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1766 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
1767 else
1768 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1769
1770 /*
1771 * Allocate memory if we're supposed to do that.
1772 */
1773 int rc = VINF_SUCCESS;
1774 if (pVM->pgm.s.fRamPreAlloc)
1775 rc = pgmR3PhysRamPreAllocate(pVM);
1776
1777 //pgmLogState(pVM);
1778 LogRel(("PGM: PGMR3InitFinalize: 4 MB PSE mask %RGp -> %Rrc\n", pVM->pgm.s.GCPhys4MBPSEMask, rc));
1779 return rc;
1780}
1781
1782
1783/**
1784 * Init phase completed callback.
1785 *
1786 * @returns VBox status code.
1787 * @param pVM The cross context VM structure.
1788 * @param enmWhat What has been completed.
1789 * @thread EMT(0)
1790 */
1791VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1792{
1793 switch (enmWhat)
1794 {
1795 case VMINITCOMPLETED_HM:
1796#ifdef VBOX_WITH_PCI_PASSTHROUGH
1797 if (pVM->pgm.s.fPciPassthrough)
1798 {
1799 AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
1800 AssertLogRelReturn(HMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HM);
1801 AssertLogRelReturn(HMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
1802
1803 /*
1804 * Report assignments to the IOMMU (hope that's good enough for now).
1805 */
1806 if (pVM->pgm.s.fPciPassthrough)
1807 {
1808 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
1809 AssertRCReturn(rc, rc);
1810 }
1811 }
1812#else
1813 AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
1814#endif
1815 break;
1816
1817 default:
1818 /* shut up gcc */
1819 break;
1820 }
1821
1822 return VINF_SUCCESS;
1823}
1824
1825
1826/**
1827 * Applies relocations to data and code managed by this component.
1828 *
1829 * This function will be called at init and whenever the VMM need to relocate it
1830 * self inside the GC.
1831 *
1832 * @param pVM The cross context VM structure.
1833 * @param offDelta Relocation delta relative to old location.
1834 */
1835VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1836{
1837 LogFlow(("PGMR3Relocate: offDelta=%RGv\n", offDelta));
1838
1839 /*
1840 * Paging stuff.
1841 */
1842
1843 /* Shadow, guest and both mode switch & relocation for each VCPU. */
1844 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1845 {
1846 PVMCPU pVCpu = pVM->apCpusR3[i];
1847
1848 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1849 if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
1850 && g_aPgmShadowModeData[idxShw].pfnRelocate)
1851 g_aPgmShadowModeData[idxShw].pfnRelocate(pVCpu, offDelta);
1852 else
1853 AssertFailed();
1854
1855 uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
1856 if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
1857 && g_aPgmGuestModeData[idxGst].pfnRelocate)
1858 g_aPgmGuestModeData[idxGst].pfnRelocate(pVCpu, offDelta);
1859 else
1860 AssertFailed();
1861 }
1862
1863 /*
1864 * The page pool.
1865 */
1866 pgmR3PoolRelocate(pVM);
1867}
1868
1869
1870/**
1871 * Resets a virtual CPU when unplugged.
1872 *
1873 * @param pVM The cross context VM structure.
1874 * @param pVCpu The cross context virtual CPU structure.
1875 */
1876VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1877{
1878 uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
1879 if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
1880 && g_aPgmGuestModeData[idxGst].pfnExit)
1881 {
1882 int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
1883 AssertReleaseRC(rc);
1884 }
1885 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1886 pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
1887 pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
1888
1889 int rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL, false /* fForce */);
1890 AssertReleaseRC(rc);
1891
1892 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
1893
1894 pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
1895
1896 /*
1897 * Re-init other members.
1898 */
1899 pVCpu->pgm.s.fA20Enabled = true;
1900 pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
1901
1902 /*
1903 * Clear the FFs PGM owns.
1904 */
1905 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1906 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1907}
1908
1909
1910/**
1911 * The VM is being reset.
1912 *
1913 * For the PGM component this means that any PD write monitors
1914 * needs to be removed.
1915 *
1916 * @param pVM The cross context VM structure.
1917 */
1918VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM)
1919{
1920 LogFlow(("PGMR3Reset:\n"));
1921 VM_ASSERT_EMT(pVM);
1922
1923 PGM_LOCK_VOID(pVM);
1924
1925 /*
1926 * Exit the guest paging mode before the pgm pool gets reset.
1927 * Important to clean up the amd64 case.
1928 */
1929 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1930 {
1931 PVMCPU pVCpu = pVM->apCpusR3[i];
1932 uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
1933 if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
1934 && g_aPgmGuestModeData[idxGst].pfnExit)
1935 {
1936 int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
1937 AssertReleaseRC(rc);
1938 }
1939 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1940 pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
1941 }
1942
1943#ifdef DEBUG
1944 DBGFR3_INFO_LOG_SAFE(pVM, "mappings", NULL);
1945 DBGFR3_INFO_LOG_SAFE(pVM, "handlers", "all nostat");
1946#endif
1947
1948 /*
1949 * Switch mode back to real mode. (Before resetting the pgm pool!)
1950 */
1951 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1952 {
1953 PVMCPU pVCpu = pVM->apCpusR3[i];
1954
1955 int rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL, false /* fForce */);
1956 AssertReleaseRC(rc);
1957
1958 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
1959 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
1960 }
1961
1962 /*
1963 * Reset the shadow page pool.
1964 */
1965 pgmR3PoolReset(pVM);
1966
1967 /*
1968 * Re-init various other members and clear the FFs that PGM owns.
1969 */
1970 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1971 {
1972 PVMCPU pVCpu = pVM->apCpusR3[i];
1973
1974 pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
1975 PGMNotifyNxeChanged(pVCpu, false);
1976
1977 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1978 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1979
1980#if !defined(VBOX_VMM_TARGET_ARMV8)
1981 if (!pVCpu->pgm.s.fA20Enabled)
1982 {
1983 pVCpu->pgm.s.fA20Enabled = true;
1984 pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
1985# ifdef PGM_WITH_A20
1986 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1987 pgmR3RefreshShadowModeAfterA20Change(pVCpu);
1988 HMFlushTlb(pVCpu);
1989# endif
1990 }
1991#endif
1992 }
1993
1994 //pgmLogState(pVM);
1995 PGM_UNLOCK(pVM);
1996}
1997
1998
1999/**
2000 * Memory setup after VM construction or reset.
2001 *
2002 * @param pVM The cross context VM structure.
2003 * @param fAtReset Indicates the context, after reset if @c true or after
2004 * construction if @c false.
2005 */
2006VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fAtReset)
2007{
2008 if (fAtReset)
2009 {
2010 PGM_LOCK_VOID(pVM);
2011
2012 int rc = pgmR3PhysRamZeroAll(pVM);
2013 AssertReleaseRC(rc);
2014
2015 rc = pgmR3PhysRomReset(pVM);
2016 AssertReleaseRC(rc);
2017
2018 PGM_UNLOCK(pVM);
2019 }
2020}
2021
2022
2023#ifdef VBOX_STRICT
2024/**
2025 * VM state change callback for clearing fNoMorePhysWrites after
2026 * a snapshot has been created.
2027 */
2028static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PUVM pUVM, PCVMMR3VTABLE pVMM, VMSTATE enmState,
2029 VMSTATE enmOldState, void *pvUser)
2030{
2031 if ( enmState == VMSTATE_RUNNING
2032 || enmState == VMSTATE_RESUMING)
2033 pUVM->pVM->pgm.s.fNoMorePhysWrites = false;
2034 RT_NOREF(pVMM, enmOldState, pvUser);
2035}
2036#endif
2037
2038/**
2039 * Private API to reset fNoMorePhysWrites.
2040 */
2041VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2042{
2043 pVM->pgm.s.fNoMorePhysWrites = false;
2044}
2045
2046/**
2047 * Terminates the PGM.
2048 *
2049 * @returns VBox status code.
2050 * @param pVM The cross context VM structure.
2051 */
2052VMMR3DECL(int) PGMR3Term(PVM pVM)
2053{
2054 /* Must free shared pages here. */
2055 PGM_LOCK_VOID(pVM);
2056 pgmR3PhysRamTerm(pVM);
2057 pgmR3PhysRomTerm(pVM);
2058 PGM_UNLOCK(pVM);
2059
2060 PGMDeregisterStringFormatTypes();
2061 return PDMR3CritSectDelete(pVM, &pVM->pgm.s.CritSectX);
2062}
2063
2064
2065/**
2066 * Show paging mode.
2067 *
2068 * @param pVM The cross context VM structure.
2069 * @param pHlp The info helpers.
2070 * @param pszArgs "all" (default), "guest", "shadow" or "host".
2071 */
2072static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2073{
2074 /* digest argument. */
2075 bool fGuest, fShadow, fHost;
2076 if (pszArgs)
2077 pszArgs = RTStrStripL(pszArgs);
2078 if (!pszArgs || !*pszArgs || strstr(pszArgs, "all"))
2079 fShadow = fHost = fGuest = true;
2080 else
2081 {
2082 fShadow = fHost = fGuest = false;
2083 if (strstr(pszArgs, "guest"))
2084 fGuest = true;
2085 if (strstr(pszArgs, "shadow"))
2086 fShadow = true;
2087 if (strstr(pszArgs, "host"))
2088 fHost = true;
2089 }
2090
2091 PVMCPU pVCpu = VMMGetCpu(pVM);
2092 if (!pVCpu)
2093 pVCpu = pVM->apCpusR3[0];
2094
2095
2096 /* print info. */
2097 if (fGuest)
2098 {
2099 pHlp->pfnPrintf(pHlp, "Guest paging mode (VCPU #%u): %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
2100 pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmGuestMode), pVCpu->pgm.s.cGuestModeChanges.c,
2101 pVCpu->pgm.s.fA20Enabled ? "enabled" : "disabled", pVCpu->pgm.s.cA20Changes.c);
2102#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2103 if (pVCpu->pgm.s.enmGuestSlatMode != PGMSLAT_INVALID)
2104 pHlp->pfnPrintf(pHlp, "Guest SLAT mode (VCPU #%u): %s\n", pVCpu->idCpu,
2105 PGMGetSlatModeName(pVCpu->pgm.s.enmGuestSlatMode));
2106#endif
2107 }
2108 if (fShadow)
2109 pHlp->pfnPrintf(pHlp, "Shadow paging mode (VCPU #%u): %s\n", pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmShadowMode));
2110 if (fHost)
2111 {
2112 const char *psz;
2113 switch (pVM->pgm.s.enmHostMode)
2114 {
2115 case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2116 case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2117 case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2118 case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2119 case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2120 case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2121 case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2122 case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2123 case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2124 case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2125 case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2126 default: psz = "unknown"; break;
2127 }
2128 pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2129 }
2130}
2131
2132
2133/**
2134 * Display the RAM range info.
2135 *
2136 * @param pVM The cross context VM structure.
2137 * @param pHlp The info helpers.
2138 * @param pszArgs Arguments, ignored.
2139 */
2140static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2141{
2142 bool const fVerbose = pszArgs && strstr(pszArgs, "verbose") != NULL;
2143
2144 pHlp->pfnPrintf(pHlp,
2145 "RAM ranges (pVM=%p)\n"
2146 "%.*s %.*s\n",
2147 pVM,
2148 sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2149 sizeof(RTHCPTR) * 2, "pbR3 ");
2150
2151 /*
2152 * Traverse the lookup table so we only display mapped MMIO and get it in sorted order.
2153 */
2154 uint32_t const cRamRangeLookupEntries = RT_MIN(pVM->pgm.s.RamRangeUnion.cLookupEntries,
2155 RT_ELEMENTS(pVM->pgm.s.aRamRangeLookup));
2156 for (uint32_t idxLookup = 0; idxLookup < cRamRangeLookupEntries; idxLookup++)
2157 {
2158 uint32_t const idRamRange = PGMRAMRANGELOOKUPENTRY_GET_ID(pVM->pgm.s.aRamRangeLookup[idxLookup]);
2159 AssertContinue(idRamRange < RT_ELEMENTS(pVM->pgm.s.apRamRanges));
2160 PPGMRAMRANGE const pCur = pVM->pgm.s.apRamRanges[idRamRange];
2161 if (pCur != NULL) { /*likely*/ }
2162 else continue;
2163
2164 pHlp->pfnPrintf(pHlp,
2165 "%RGp-%RGp %RHv %s\n",
2166 pCur->GCPhys,
2167 pCur->GCPhysLast,
2168 pCur->pbR3,
2169 pCur->pszDesc);
2170 if (fVerbose)
2171 {
2172 RTGCPHYS const cPages = pCur->cb >> X86_PAGE_SHIFT;
2173 RTGCPHYS iPage = 0;
2174 while (iPage < cPages)
2175 {
2176 RTGCPHYS const iFirstPage = iPage;
2177 PGMPAGETYPE const enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]);
2178 do
2179 iPage++;
2180 while (iPage < cPages && (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == enmType);
2181 const char *pszType;
2182 const char *pszMore = NULL;
2183 switch (enmType)
2184 {
2185 case PGMPAGETYPE_RAM:
2186 pszType = "RAM";
2187 break;
2188
2189 case PGMPAGETYPE_MMIO2:
2190 pszType = "MMIO2";
2191 break;
2192
2193 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2194 pszType = "MMIO2-alias-MMIO";
2195 break;
2196
2197 case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2198 pszType = "special-alias-MMIO";
2199 break;
2200
2201 case PGMPAGETYPE_ROM_SHADOW:
2202 case PGMPAGETYPE_ROM:
2203 {
2204 pszType = enmType == PGMPAGETYPE_ROM_SHADOW ? "ROM-shadowed" : "ROM";
2205
2206 RTGCPHYS const GCPhysFirstPg = iFirstPage << GUEST_PAGE_SHIFT;
2207 uint32_t const cRomRanges = RT_MIN(pVM->pgm.s.cRomRanges, RT_ELEMENTS(pVM->pgm.s.apRomRanges));
2208 for (uint32_t idxRom = 0; idxRom < cRomRanges; idxRom++)
2209 {
2210 PPGMROMRANGE const pRomRange = pVM->pgm.s.apRomRanges[idxRom];
2211 if ( pRomRange
2212 && GCPhysFirstPg < pRomRange->GCPhysLast
2213 && GCPhysFirstPg >= pRomRange->GCPhys)
2214 {
2215 pszMore = pRomRange->pszDesc;
2216 break;
2217 }
2218 }
2219 break;
2220 }
2221
2222 case PGMPAGETYPE_MMIO:
2223 {
2224 pszType = "MMIO";
2225 PGM_LOCK_VOID(pVM);
2226 PPGMPHYSHANDLER pHandler;
2227 int rc = pgmHandlerPhysicalLookup(pVM, iFirstPage * X86_PAGE_SIZE, &pHandler);
2228 if (RT_SUCCESS(rc))
2229 pszMore = pHandler->pszDesc;
2230 PGM_UNLOCK(pVM);
2231 break;
2232 }
2233
2234 case PGMPAGETYPE_INVALID:
2235 pszType = "invalid";
2236 break;
2237
2238 default:
2239 pszType = "bad";
2240 break;
2241 }
2242 if (pszMore)
2243 pHlp->pfnPrintf(pHlp, " %RGp-%RGp %-20s %s\n",
2244 pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
2245 pCur->GCPhys + iPage * X86_PAGE_SIZE - 1,
2246 pszType, pszMore);
2247 else
2248 pHlp->pfnPrintf(pHlp, " %RGp-%RGp %s\n",
2249 pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
2250 pCur->GCPhys + iPage * X86_PAGE_SIZE - 1,
2251 pszType);
2252
2253 }
2254 }
2255 }
2256}
2257
2258
2259/**
2260 * Dump the page directory to the log.
2261 *
2262 * @param pVM The cross context VM structure.
2263 * @param pHlp The info helpers.
2264 * @param pszArgs Arguments, ignored.
2265 */
2266static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2267{
2268 /** @todo SMP support!! */
2269 PVMCPU pVCpu = pVM->apCpusR3[0];
2270
2271/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2272 /* Big pages supported? */
2273 const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2274
2275 /* Global pages supported? */
2276 const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2277
2278 NOREF(pszArgs);
2279
2280 /*
2281 * Get page directory addresses.
2282 */
2283 PGM_LOCK_VOID(pVM);
2284 PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2285 Assert(pPDSrc);
2286
2287 /*
2288 * Iterate the page directory.
2289 */
2290 for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2291 {
2292 X86PDE PdeSrc = pPDSrc->a[iPD];
2293 if (PdeSrc.u & X86_PDE_P)
2294 {
2295 if ((PdeSrc.u & X86_PDE_PS) && fPSE)
2296 pHlp->pfnPrintf(pHlp,
2297 "%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2298 iPD,
2299 pgmGstGet4MBPhysPage(pVM, PdeSrc), PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_US),
2300 !!(PdeSrc.u & X86_PDE_RW), (PdeSrc.u & X86_PDE4M_G) && fPGE);
2301 else
2302 pHlp->pfnPrintf(pHlp,
2303 "%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2304 iPD,
2305 (RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK), PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_US),
2306 !!(PdeSrc.u & X86_PDE_RW), (PdeSrc.u & X86_PDE4M_G) && fPGE);
2307 }
2308 }
2309 PGM_UNLOCK(pVM);
2310}
2311
2312
2313/**
2314 * Called by pgmPoolFlushAllInt prior to flushing the pool.
2315 *
2316 * @returns VBox status code, fully asserted.
2317 * @param pVCpu The cross context virtual CPU structure.
2318 */
2319int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
2320{
2321 /* Unmap the old CR3 value before flushing everything. */
2322 int rc = VINF_SUCCESS;
2323 uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
2324 if ( idxBth < RT_ELEMENTS(g_aPgmBothModeData)
2325 && g_aPgmBothModeData[idxBth].pfnUnmapCR3)
2326 {
2327 rc = g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
2328 AssertRC(rc);
2329 }
2330
2331 /* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
2332 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
2333 if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
2334 && g_aPgmShadowModeData[idxShw].pfnExit)
2335 {
2336 rc = g_aPgmShadowModeData[idxShw].pfnExit(pVCpu);
2337 AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
2338 }
2339
2340 Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
2341 return rc;
2342}
2343
2344
2345/**
2346 * Called by pgmPoolFlushAllInt after flushing the pool.
2347 *
2348 * @returns VBox status code, fully asserted.
2349 * @param pVM The cross context VM structure.
2350 * @param pVCpu The cross context virtual CPU structure.
2351 */
2352int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
2353{
2354 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
2355 int rc = PGMHCChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu), false /* fForce */);
2356 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2357 AssertRCReturn(rc, rc);
2358 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2359
2360 Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL || pVCpu->pgm.s.enmShadowMode == PGMMODE_NONE);
2361 AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED_32BIT
2362 || CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
2363 ("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
2364 return rc;
2365}
2366
2367
2368/**
2369 * Called by PGMR3PhysSetA20 after changing the A20 state.
2370 *
2371 * @param pVCpu The cross context virtual CPU structure.
2372 */
2373void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
2374{
2375 /** @todo Probably doing a bit too much here. */
2376 int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
2377 AssertReleaseRC(rc);
2378 rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
2379 AssertReleaseRC(rc);
2380}
2381
2382
2383#ifdef VBOX_WITH_DEBUGGER
2384
2385/**
2386 * @callback_method_impl{FNDBGCCMD, The '.pgmerror' and '.pgmerroroff' commands.}
2387 */
2388static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2389{
2390 /*
2391 * Validate input.
2392 */
2393 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2394 PVM pVM = pUVM->pVM;
2395 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 0 || (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING));
2396
2397 if (!cArgs)
2398 {
2399 /*
2400 * Print the list of error injection locations with status.
2401 */
2402 DBGCCmdHlpPrintf(pCmdHlp, "PGM error inject locations:\n");
2403 DBGCCmdHlpPrintf(pCmdHlp, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
2404 }
2405 else
2406 {
2407 /*
2408 * String switch on where to inject the error.
2409 */
2410 bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
2411 const char *pszWhere = paArgs[0].u.pszString;
2412 if (!strcmp(pszWhere, "handy"))
2413 ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
2414 else
2415 return DBGCCmdHlpPrintf(pCmdHlp, "error: Invalid 'where' value: %s.\n", pszWhere);
2416 DBGCCmdHlpPrintf(pCmdHlp, "done\n");
2417 }
2418 return VINF_SUCCESS;
2419}
2420
2421
2422/**
2423 * @callback_method_impl{FNDBGCCMD, The '.pgmsync' command.}
2424 */
2425static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2426{
2427 /*
2428 * Validate input.
2429 */
2430 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2431 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2432 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
2433 if (!pVCpu)
2434 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
2435
2436 /*
2437 * Force page directory sync.
2438 */
2439 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2440
2441 int rc = DBGCCmdHlpPrintf(pCmdHlp, "Forcing page directory sync.\n");
2442 if (RT_FAILURE(rc))
2443 return rc;
2444
2445 return VINF_SUCCESS;
2446}
2447
2448#ifdef VBOX_STRICT
2449
2450/**
2451 * EMT callback for pgmR3CmdAssertCR3.
2452 *
2453 * @returns VBox status code.
2454 * @param pUVM The user mode VM handle.
2455 * @param pcErrors Where to return the error count.
2456 */
2457static DECLCALLBACK(int) pgmR3CmdAssertCR3EmtWorker(PUVM pUVM, unsigned *pcErrors)
2458{
2459 PVM pVM = pUVM->pVM;
2460 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
2461 PVMCPU pVCpu = VMMGetCpu(pVM);
2462
2463 *pcErrors = PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
2464
2465 return VINF_SUCCESS;
2466}
2467
2468
2469/**
2470 * @callback_method_impl{FNDBGCCMD, The '.pgmassertcr3' command.}
2471 */
2472static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2473{
2474 /*
2475 * Validate input.
2476 */
2477 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2478 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2479
2480 int rc = DBGCCmdHlpPrintf(pCmdHlp, "Checking shadow CR3 page tables for consistency.\n");
2481 if (RT_FAILURE(rc))
2482 return rc;
2483
2484 unsigned cErrors = 0;
2485 rc = VMR3ReqCallWaitU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp), (PFNRT)pgmR3CmdAssertCR3EmtWorker, 2, pUVM, &cErrors);
2486 if (RT_FAILURE(rc))
2487 return DBGCCmdHlpFail(pCmdHlp, pCmd, "VMR3ReqCallWaitU failed: %Rrc", rc);
2488 if (cErrors > 0)
2489 return DBGCCmdHlpFail(pCmdHlp, pCmd, "PGMAssertCR3: %u error(s)", cErrors);
2490 return DBGCCmdHlpPrintf(pCmdHlp, "PGMAssertCR3: OK\n");
2491}
2492
2493#endif /* VBOX_STRICT */
2494
2495/**
2496 * @callback_method_impl{FNDBGCCMD, The '.pgmsyncalways' command.}
2497 */
2498static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2499{
2500 /*
2501 * Validate input.
2502 */
2503 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2504 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2505 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
2506 if (!pVCpu)
2507 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
2508
2509 /*
2510 * Force page directory sync.
2511 */
2512 int rc;
2513 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
2514 {
2515 ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
2516 rc = DBGCCmdHlpPrintf(pCmdHlp, "Disabled permanent forced page directory syncing.\n");
2517 }
2518 else
2519 {
2520 ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
2521 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2522 rc = DBGCCmdHlpPrintf(pCmdHlp, "Enabled permanent forced page directory syncing.\n");
2523 }
2524 return rc;
2525}
2526
2527
2528/**
2529 * @callback_method_impl{FNDBGCCMD, The '.pgmphystofile' command.}
2530 */
2531static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2532{
2533 /*
2534 * Validate input.
2535 */
2536 NOREF(pCmd);
2537 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2538 PVM pVM = pUVM->pVM;
2539 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 1 || cArgs == 2);
2540 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, paArgs[0].enmType == DBGCVAR_TYPE_STRING);
2541 if (cArgs == 2)
2542 {
2543 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 1, paArgs[1].enmType == DBGCVAR_TYPE_STRING);
2544 if (strcmp(paArgs[1].u.pszString, "nozero"))
2545 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
2546 }
2547 bool fIncZeroPgs = cArgs < 2;
2548
2549 /*
2550 * Open the output file and get the ram parameters.
2551 */
2552 RTFILE hFile;
2553 int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE | RTFILE_O_CREATE_REPLACE | RTFILE_O_DENY_WRITE);
2554 if (RT_FAILURE(rc))
2555 return DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
2556
2557 uint32_t cbRamHole = 0;
2558 CFGMR3QueryU32Def(CFGMR3GetRootU(pUVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
2559 uint64_t cbRam = 0;
2560 CFGMR3QueryU64Def(CFGMR3GetRootU(pUVM), "RamSize", &cbRam, 0);
2561 RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
2562
2563 /*
2564 * Dump the physical memory, page by page.
2565 */
2566 RTGCPHYS GCPhys = 0;
2567 char abZeroPg[GUEST_PAGE_SIZE];
2568 RT_ZERO(abZeroPg);
2569
2570 PGM_LOCK_VOID(pVM);
2571
2572 uint32_t const cRamRangeLookupEntries = RT_MIN(pVM->pgm.s.RamRangeUnion.cLookupEntries,
2573 RT_ELEMENTS(pVM->pgm.s.aRamRangeLookup));
2574 for (uint32_t idxLookup = 0; idxLookup < cRamRangeLookupEntries && RT_SUCCESS(rc); idxLookup++)
2575 {
2576 if (PGMRAMRANGELOOKUPENTRY_GET_FIRST(pVM->pgm.s.aRamRangeLookup[idxLookup]) >= GCPhysEnd)
2577 break;
2578 uint32_t const idRamRange = PGMRAMRANGELOOKUPENTRY_GET_ID(pVM->pgm.s.aRamRangeLookup[idxLookup]);
2579 AssertContinue(idRamRange < RT_ELEMENTS(pVM->pgm.s.apRamRanges));
2580 PPGMRAMRANGE const pRam = pVM->pgm.s.apRamRanges[idRamRange];
2581 AssertContinue(pRam);
2582 Assert(pRam->GCPhys == PGMRAMRANGELOOKUPENTRY_GET_FIRST(pVM->pgm.s.aRamRangeLookup[idxLookup]));
2583
2584 /* fill the gap */
2585 if (pRam->GCPhys > GCPhys && fIncZeroPgs)
2586 {
2587 while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
2588 {
2589 rc = RTFileWrite(hFile, abZeroPg, GUEST_PAGE_SIZE, NULL);
2590 GCPhys += GUEST_PAGE_SIZE;
2591 }
2592 }
2593
2594 PCPGMPAGE pPage = &pRam->aPages[0];
2595 while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
2596 {
2597 if ( PGM_PAGE_IS_ZERO(pPage)
2598 || PGM_PAGE_IS_BALLOONED(pPage))
2599 {
2600 if (fIncZeroPgs)
2601 {
2602 rc = RTFileWrite(hFile, abZeroPg, GUEST_PAGE_SIZE, NULL);
2603 if (RT_FAILURE(rc))
2604 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2605 }
2606 }
2607 else
2608 {
2609 switch (PGM_PAGE_GET_TYPE(pPage))
2610 {
2611 case PGMPAGETYPE_RAM:
2612 case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
2613 case PGMPAGETYPE_ROM:
2614 case PGMPAGETYPE_MMIO2:
2615 {
2616 void const *pvPage;
2617 PGMPAGEMAPLOCK Lock;
2618 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
2619 if (RT_SUCCESS(rc))
2620 {
2621 rc = RTFileWrite(hFile, pvPage, GUEST_PAGE_SIZE, NULL);
2622 PGMPhysReleasePageMappingLock(pVM, &Lock);
2623 if (RT_FAILURE(rc))
2624 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2625 }
2626 else
2627 DBGCCmdHlpPrintf(pCmdHlp, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2628 break;
2629 }
2630
2631 default:
2632 AssertFailed();
2633 RT_FALL_THRU();
2634 case PGMPAGETYPE_MMIO:
2635 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2636 case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2637 if (fIncZeroPgs)
2638 {
2639 rc = RTFileWrite(hFile, abZeroPg, GUEST_PAGE_SIZE, NULL);
2640 if (RT_FAILURE(rc))
2641 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2642 }
2643 break;
2644 }
2645 }
2646
2647
2648 /* advance */
2649 GCPhys += GUEST_PAGE_SIZE;
2650 pPage++;
2651 }
2652 }
2653 PGM_UNLOCK(pVM);
2654
2655 RTFileClose(hFile);
2656 if (RT_SUCCESS(rc))
2657 return DBGCCmdHlpPrintf(pCmdHlp, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
2658 return VINF_SUCCESS;
2659}
2660
2661#endif /* VBOX_WITH_DEBUGGER */
2662
2663/**
2664 * pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
2665 */
2666typedef struct PGMCHECKINTARGS
2667{
2668 bool fLeftToRight; /**< true: left-to-right; false: right-to-left. */
2669 uint32_t cErrors;
2670 PPGMPHYSHANDLER pPrevPhys;
2671 PVM pVM;
2672} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
2673
2674/**
2675 * Validate a node in the physical handler tree.
2676 *
2677 * @returns 0 on if ok, other wise 1.
2678 * @param pNode The handler node.
2679 * @param pvUser pVM.
2680 */
2681static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PPGMPHYSHANDLER pNode, void *pvUser)
2682{
2683 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
2684
2685 AssertLogRelMsgReturnStmt(!((uintptr_t)pNode & 7), ("pNode=%p\n", pNode), pArgs->cErrors++, VERR_INVALID_POINTER);
2686
2687 AssertLogRelMsgStmt(pNode->Key <= pNode->KeyLast,
2688 ("pNode=%p %RGp-%RGp %s\n", pNode, pNode->Key, pNode->KeyLast, pNode->pszDesc),
2689 pArgs->cErrors++);
2690
2691 AssertLogRelMsgStmt( !pArgs->pPrevPhys
2692 || ( pArgs->fLeftToRight
2693 ? pArgs->pPrevPhys->KeyLast < pNode->Key
2694 : pArgs->pPrevPhys->KeyLast > pNode->Key),
2695 ("pPrevPhys=%p %RGp-%RGp %s\n"
2696 " pNode=%p %RGp-%RGp %s\n",
2697 pArgs->pPrevPhys, pArgs->pPrevPhys->Key, pArgs->pPrevPhys->KeyLast, pArgs->pPrevPhys->pszDesc,
2698 pNode, pNode->Key, pNode->KeyLast, pNode->pszDesc),
2699 pArgs->cErrors++);
2700
2701 pArgs->pPrevPhys = pNode;
2702 return 0;
2703}
2704
2705
2706/**
2707 * Perform an integrity check on the PGM component.
2708 *
2709 * @returns VINF_SUCCESS if everything is fine.
2710 * @returns VBox error status after asserting on integrity breach.
2711 * @param pVM The cross context VM structure.
2712 */
2713VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
2714{
2715 /*
2716 * Check the trees.
2717 */
2718 PGMCHECKINTARGS Args = { true, 0, NULL, pVM };
2719 int rc = pVM->pgm.s.pPhysHandlerTree->doWithAllFromLeft(&pVM->pgm.s.PhysHandlerAllocator,
2720 pgmR3CheckIntegrityPhysHandlerNode, &Args);
2721 AssertLogRelRCReturn(rc, rc);
2722
2723 Args.fLeftToRight = false;
2724 Args.pPrevPhys = NULL;
2725 rc = pVM->pgm.s.pPhysHandlerTree->doWithAllFromRight(&pVM->pgm.s.PhysHandlerAllocator,
2726 pgmR3CheckIntegrityPhysHandlerNode, &Args);
2727 AssertLogRelMsgReturn(pVM->pgm.s.pPhysHandlerTree->m_cErrors == 0,
2728 ("m_cErrors=%#x\n", pVM->pgm.s.pPhysHandlerTree->m_cErrors == 0),
2729 VERR_INTERNAL_ERROR);
2730
2731 return Args.cErrors == 0 ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
2732}
2733
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