VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp@ 99756

Last change on this file since 99756 was 99051, checked in by vboxsync, 15 months ago

VMM: More ARMv8 x86/amd64 separation work, VBoxVMMArm compiles and links now, bugref:10385
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1/* $Id: PDMDevMiscHlp.cpp 99051 2023-03-19 16:40:06Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, Misc. Device Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_PDM_DEVICE
33#include "PDMInternal.h"
34#include <VBox/vmm/pdm.h>
35#include <VBox/vmm/pgm.h>
36#include <VBox/vmm/hm.h>
37#include <VBox/vmm/apic.h>
38#include <VBox/vmm/vm.h>
39#include <VBox/vmm/vmm.h>
40
41#include <VBox/log.h>
42#include <VBox/err.h>
43#include <VBox/msi.h>
44#include <iprt/asm.h>
45#include <iprt/assert.h>
46#include <iprt/thread.h>
47
48
49#include "PDMInline.h"
50#include "dtrace/VBoxVMM.h"
51
52
53
54/** @name Ring-3 PIC Helpers
55 * @{
56 */
57
58/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
59static DECLCALLBACK(void) pdmR3PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
60{
61 PDMDEV_ASSERT_DEVINS(pDevIns);
62 PVM pVM = pDevIns->Internal.s.pVMR3;
63 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
64
65 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
66 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
67
68#if defined(VBOX_VMM_TARGET_ARMV8)
69 AssertReleaseFailed();
70#else
71 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
72#endif
73}
74
75
76/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
77static DECLCALLBACK(void) pdmR3PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
78{
79 PDMDEV_ASSERT_DEVINS(pDevIns);
80 PVM pVM = pDevIns->Internal.s.pVMR3;
81 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
82
83 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
84 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
85
86#if defined(VBOX_VMM_TARGET_ARMV8)
87 AssertReleaseFailed();
88#else
89 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
90#endif
91}
92
93
94/** @interface_method_impl{PDMPICHLP,pfnLock} */
95static DECLCALLBACK(int) pdmR3PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
96{
97 PDMDEV_ASSERT_DEVINS(pDevIns);
98 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
99}
100
101
102/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
103static DECLCALLBACK(void) pdmR3PicHlp_Unlock(PPDMDEVINS pDevIns)
104{
105 PDMDEV_ASSERT_DEVINS(pDevIns);
106 pdmUnlock(pDevIns->Internal.s.pVMR3);
107}
108
109
110/**
111 * PIC Device Helpers.
112 */
113const PDMPICHLP g_pdmR3DevPicHlp =
114{
115 PDM_PICHLP_VERSION,
116 pdmR3PicHlp_SetInterruptFF,
117 pdmR3PicHlp_ClearInterruptFF,
118 pdmR3PicHlp_Lock,
119 pdmR3PicHlp_Unlock,
120 PDM_PICHLP_VERSION /* the end */
121};
122
123/** @} */
124
125
126/** @name Ring-3 I/O APIC Helpers
127 * @{
128 */
129
130/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
131static DECLCALLBACK(int) pdmR3IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
132 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
133 uint8_t u8TriggerMode, uint32_t uTagSrc)
134{
135 PDMDEV_ASSERT_DEVINS(pDevIns);
136 PVM pVM = pDevIns->Internal.s.pVMR3;
137 LogFlow(("pdmR3IoApicHlp_ApicBusDeliver: caller='%s'/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
138 pDevIns->pReg->szName, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
139#if defined(VBOX_VMM_TARGET_ARMV8)
140 AssertReleaseFailed();
141 return VERR_NOT_IMPLEMENTED;
142#else
143 return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
144#endif
145}
146
147
148/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
149static DECLCALLBACK(int) pdmR3IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
150{
151 PDMDEV_ASSERT_DEVINS(pDevIns);
152 LogFlow(("pdmR3IoApicHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
153 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
154}
155
156
157/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
158static DECLCALLBACK(void) pdmR3IoApicHlp_Unlock(PPDMDEVINS pDevIns)
159{
160 PDMDEV_ASSERT_DEVINS(pDevIns);
161 LogFlow(("pdmR3IoApicHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
162 pdmUnlock(pDevIns->Internal.s.pVMR3);
163}
164
165
166/** @interface_method_impl{PDMIOAPICHLP,pfnLockIsOwner} */
167static DECLCALLBACK(bool) pdmR3IoApicHlp_LockIsOwner(PPDMDEVINS pDevIns)
168{
169 PDMDEV_ASSERT_DEVINS(pDevIns);
170 LogFlow(("pdmR3IoApicHlp_LockIsOwner: caller='%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
171 return pdmLockIsOwner(pDevIns->Internal.s.pVMR3);
172}
173
174
175/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
176static DECLCALLBACK(int) pdmR3IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
177{
178 PDMDEV_ASSERT_DEVINS(pDevIns);
179 LogFlow(("pdmR3IoApicHlp_IommuRemapMsi: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
180 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
181
182#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
183 if (pdmIommuIsPresent(pDevIns))
184 return pdmIommuMsiRemap(pDevIns, idDevice, pMsiIn, pMsiOut);
185#else
186 RT_NOREF(pDevIns, idDevice, pMsiIn, pMsiOut);
187#endif
188 return VERR_IOMMU_NOT_PRESENT;
189}
190
191
192/**
193 * I/O APIC Device Helpers.
194 */
195const PDMIOAPICHLP g_pdmR3DevIoApicHlp =
196{
197 PDM_IOAPICHLP_VERSION,
198 pdmR3IoApicHlp_ApicBusDeliver,
199 pdmR3IoApicHlp_Lock,
200 pdmR3IoApicHlp_Unlock,
201 pdmR3IoApicHlp_LockIsOwner,
202 pdmR3IoApicHlp_IommuMsiRemap,
203 PDM_IOAPICHLP_VERSION /* the end */
204};
205
206/** @} */
207
208
209
210
211/** @name Ring-3 PCI Bus Helpers
212 * @{
213 */
214
215/** @interface_method_impl{PDMPCIHLPR3,pfnIsaSetIrq} */
216static DECLCALLBACK(void) pdmR3PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
217{
218 PDMDEV_ASSERT_DEVINS(pDevIns);
219 Log4(("pdmR3PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
220 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel, uTagSrc);
221}
222
223
224/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSetIrq} */
225static DECLCALLBACK(void) pdmR3PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
226{
227 PDMDEV_ASSERT_DEVINS(pDevIns);
228 Log4(("pdmR3PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc));
229 PDMIoApicSetIrq(pDevIns->Internal.s.pVMR3, uBusDevFn, iIrq, iLevel, uTagSrc);
230}
231
232
233/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSendMsi} */
234static DECLCALLBACK(void) pdmR3PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
235{
236 PDMDEV_ASSERT_DEVINS(pDevIns);
237 Assert(PCIBDF_IS_VALID(uBusDevFn));
238 Log4(("pdmR3PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi (Addr=%#RX64 Data=%#x) uTagSrc=%#x\n", uBusDevFn,
239 pMsi->Addr.u64, pMsi->Data.u32, uTagSrc));
240 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, uBusDevFn, pMsi, uTagSrc);
241}
242
243
244/** @interface_method_impl{PDMPCIHLPR3,pfnLock} */
245static DECLCALLBACK(int) pdmR3PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
246{
247 PDMDEV_ASSERT_DEVINS(pDevIns);
248 LogFlow(("pdmR3PciHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
249 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
250}
251
252
253/** @interface_method_impl{PDMPCIHLPR3,pfnUnlock} */
254static DECLCALLBACK(void) pdmR3PciHlp_Unlock(PPDMDEVINS pDevIns)
255{
256 PDMDEV_ASSERT_DEVINS(pDevIns);
257 LogFlow(("pdmR3PciHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
258 pdmUnlock(pDevIns->Internal.s.pVMR3);
259}
260
261
262/** @interface_method_impl{PDMPCIHLPR3,pfnGetBusByNo} */
263static DECLCALLBACK(PPDMDEVINS) pdmR3PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
264{
265 PDMDEV_ASSERT_DEVINS(pDevIns);
266 PVM pVM = pDevIns->Internal.s.pVMR3;
267 AssertReturn(idxPdmBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), NULL);
268 PPDMDEVINS pRetDevIns = pVM->pdm.s.aPciBuses[idxPdmBus].pDevInsR3;
269 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
270 return pRetDevIns;
271}
272
273
274/**
275 * PCI Bus Device Helpers.
276 */
277const PDMPCIHLPR3 g_pdmR3DevPciHlp =
278{
279 PDM_PCIHLPR3_VERSION,
280 pdmR3PciHlp_IsaSetIrq,
281 pdmR3PciHlp_IoApicSetIrq,
282 pdmR3PciHlp_IoApicSendMsi,
283 pdmR3PciHlp_Lock,
284 pdmR3PciHlp_Unlock,
285 pdmR3PciHlp_GetBusByNo,
286 PDM_PCIHLPR3_VERSION, /* the end */
287};
288
289/** @} */
290
291
292/** @name Ring-3 IOMMU Helpers
293 * @{
294 */
295
296/** @interface_method_impl{PDMIOMMUHLPR3,pfnLock} */
297static DECLCALLBACK(int) pdmR3IommuHlp_Lock(PPDMDEVINS pDevIns, int rc)
298{
299 PDMDEV_ASSERT_DEVINS(pDevIns);
300 LogFlowFunc(("caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
301 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
302}
303
304
305/** @interface_method_impl{PDMIOMMUHLPR3,pfnUnlock} */
306static DECLCALLBACK(void) pdmR3IommuHlp_Unlock(PPDMDEVINS pDevIns)
307{
308 PDMDEV_ASSERT_DEVINS(pDevIns);
309 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
310 pdmUnlock(pDevIns->Internal.s.pVMR3);
311}
312
313
314/** @interface_method_impl{PDMIOMMUHLPR3,pfnLockIsOwner} */
315static DECLCALLBACK(bool) pdmR3IommuHlp_LockIsOwner(PPDMDEVINS pDevIns)
316{
317 PDMDEV_ASSERT_DEVINS(pDevIns);
318 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
319 return pdmLockIsOwner(pDevIns->Internal.s.pVMR3);
320}
321
322
323/** @interface_method_impl{PDMIOMMUHLPR3,pfnSendMsi} */
324static DECLCALLBACK(void) pdmR3IommuHlp_SendMsi(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc)
325{
326 PDMDEV_ASSERT_DEVINS(pDevIns);
327 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
328 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, NIL_PCIBDF, pMsi, uTagSrc);
329}
330
331
332/**
333 * IOMMU Device Helpers.
334 */
335const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp =
336{
337 PDM_IOMMUHLPR3_VERSION,
338 pdmR3IommuHlp_Lock,
339 pdmR3IommuHlp_Unlock,
340 pdmR3IommuHlp_LockIsOwner,
341 pdmR3IommuHlp_SendMsi,
342 PDM_IOMMUHLPR3_VERSION /* the end */
343};
344
345/** @} */
346
347
348/** @name Ring-3 HPET Helpers
349 * @{
350 */
351
352/** @interface_method_impl{PDMHPETHLPR3,pfnSetLegacyMode} */
353static DECLCALLBACK(int) pdmR3HpetHlp_SetLegacyMode(PPDMDEVINS pDevIns, bool fActivated)
354{
355 PDMDEV_ASSERT_DEVINS(pDevIns);
356 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: fActivated=%RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance, fActivated));
357
358 size_t i;
359 int rc = VINF_SUCCESS;
360 static const char * const s_apszDevsToNotify[] =
361 {
362 "i8254",
363 "mc146818"
364 };
365 for (i = 0; i < RT_ELEMENTS(s_apszDevsToNotify); i++)
366 {
367 PPDMIBASE pBase;
368 rc = PDMR3QueryDevice(pDevIns->Internal.s.pVMR3->pUVM, "i8254", 0, &pBase);
369 if (RT_SUCCESS(rc))
370 {
371 PPDMIHPETLEGACYNOTIFY pPort = PDMIBASE_QUERY_INTERFACE(pBase, PDMIHPETLEGACYNOTIFY);
372 AssertLogRelMsgBreakStmt(pPort, ("%s\n", s_apszDevsToNotify[i]), rc = VERR_PDM_HPET_LEGACY_NOTIFY_MISSING);
373 pPort->pfnModeChanged(pPort, fActivated);
374 }
375 else if ( rc == VERR_PDM_DEVICE_NOT_FOUND
376 || rc == VERR_PDM_DEVICE_INSTANCE_NOT_FOUND)
377 rc = VINF_SUCCESS; /* the device isn't configured, ignore. */
378 else
379 AssertLogRelMsgFailedBreak(("%s -> %Rrc\n", s_apszDevsToNotify[i], rc));
380 }
381
382 /* Don't bother cleaning up, any failure here will cause a guru meditation. */
383
384 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
385 return rc;
386}
387
388
389/** @interface_method_impl{PDMHPETHLPR3,pfnSetIrq} */
390static DECLCALLBACK(int) pdmR3HpetHlp_SetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
391{
392 PDMDEV_ASSERT_DEVINS(pDevIns);
393 LogFlow(("pdmR3HpetHlp_SetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
394 PVM pVM = pDevIns->Internal.s.pVMR3;
395
396 pdmLock(pVM);
397 uint32_t uTagSrc;
398 if (iLevel & PDM_IRQ_LEVEL_HIGH)
399 {
400 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
401 if (iLevel == PDM_IRQ_LEVEL_HIGH)
402 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
403 else
404 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
405 }
406 else
407 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
408
409 PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
410
411 if (iLevel == PDM_IRQ_LEVEL_LOW)
412 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
413 pdmUnlock(pVM);
414 return 0;
415}
416
417
418/**
419 * HPET Device Helpers.
420 */
421const PDMHPETHLPR3 g_pdmR3DevHpetHlp =
422{
423 PDM_HPETHLPR3_VERSION,
424 pdmR3HpetHlp_SetLegacyMode,
425 pdmR3HpetHlp_SetIrq,
426 PDM_HPETHLPR3_VERSION, /* the end */
427};
428
429/** @} */
430
431
432/** @name Ring-3 Raw PCI Device Helpers
433 * @{
434 */
435
436/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetRCHelpers} */
437static DECLCALLBACK(PCPDMPCIRAWHLPRC) pdmR3PciRawHlp_GetRCHelpers(PPDMDEVINS pDevIns)
438{
439 PDMDEV_ASSERT_DEVINS(pDevIns);
440 PVM pVM = pDevIns->Internal.s.pVMR3;
441 VM_ASSERT_EMT(pVM);
442
443 RTRCPTR pRCHelpers = NIL_RTRCPTR;
444#if 0
445 if (VM_IS_RAW_MODE_ENABLED(pVM))
446 {
447 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_pdmRCPciRawHlp", &pRCHelpers);
448 AssertReleaseRC(rc);
449 AssertRelease(pRCHelpers);
450 }
451#else
452 RT_NOREF(pVM, pDevIns);
453#endif
454
455 LogFlow(("pdmR3PciRawHlp_GetGCHelpers: caller='%s'/%d: returns %RRv\n",
456 pDevIns->pReg->szName, pDevIns->iInstance, pRCHelpers));
457 return pRCHelpers;
458}
459
460
461/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetR0Helpers} */
462static DECLCALLBACK(PCPDMPCIRAWHLPR0) pdmR3PciRawHlp_GetR0Helpers(PPDMDEVINS pDevIns)
463{
464 PDMDEV_ASSERT_DEVINS(pDevIns);
465 PVM pVM = pDevIns->Internal.s.pVMR3;
466 VM_ASSERT_EMT(pVM);
467 PCPDMHPETHLPR0 pR0Helpers = NIL_RTR0PTR;
468 int rc = PDMR3LdrGetSymbolR0(pVM, NULL, "g_pdmR0PciRawHlp", &pR0Helpers);
469 AssertReleaseRC(rc);
470 AssertRelease(pR0Helpers);
471 LogFlow(("pdmR3PciRawHlp_GetR0Helpers: caller='%s'/%d: returns %RHv\n",
472 pDevIns->pReg->szName, pDevIns->iInstance, pR0Helpers));
473 return pR0Helpers;
474}
475
476
477/**
478 * Raw PCI Device Helpers.
479 */
480const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp =
481{
482 PDM_PCIRAWHLPR3_VERSION,
483 pdmR3PciRawHlp_GetRCHelpers,
484 pdmR3PciRawHlp_GetR0Helpers,
485 PDM_PCIRAWHLPR3_VERSION, /* the end */
486};
487
488/** @} */
489
490
491/* none yet */
492
493/**
494 * Firmware Device Helpers.
495 */
496const PDMFWHLPR3 g_pdmR3DevFirmwareHlp =
497{
498 PDM_FWHLPR3_VERSION,
499 PDM_FWHLPR3_VERSION
500};
501
502/**
503 * DMAC Device Helpers.
504 */
505const PDMDMACHLP g_pdmR3DevDmacHlp =
506{
507 PDM_DMACHLP_VERSION
508};
509
510
511
512
513/* none yet */
514
515/**
516 * RTC Device Helpers.
517 */
518const PDMRTCHLP g_pdmR3DevRtcHlp =
519{
520 PDM_RTCHLP_VERSION
521};
522
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