VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp@ 77241

Last change on this file since 77241 was 77241, checked in by vboxsync, 5 years ago

VMM: Added dev helps for bulk page mapping locking. VMMDev will be using this for a new variation on the HGCM page list parameter type. bugref:9172
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File size: 165.7 KB
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1/* $Id: PDMDevHlp.cpp 77241 2019-02-10 22:30:33Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, Device Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/mm.h>
27#include <VBox/vmm/hm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/iom.h>
30#ifdef VBOX_WITH_REM
31# include <VBox/vmm/rem.h>
32#endif
33#include <VBox/vmm/dbgf.h>
34#include <VBox/vmm/vmapi.h>
35#include <VBox/vmm/vm.h>
36#include <VBox/vmm/uvm.h>
37#include <VBox/vmm/vmm.h>
38
39#include <VBox/version.h>
40#include <VBox/log.h>
41#include <VBox/err.h>
42#include <iprt/asm.h>
43#include <iprt/assert.h>
44#include <iprt/ctype.h>
45#include <iprt/string.h>
46#include <iprt/thread.h>
47
48#include "dtrace/VBoxVMM.h"
49#include "PDMInline.h"
50
51
52/*********************************************************************************************************************************
53* Defined Constants And Macros *
54*********************************************************************************************************************************/
55/** @def PDM_DEVHLP_DEADLOCK_DETECTION
56 * Define this to enable the deadlock detection when accessing physical memory.
57 */
58#if /*defined(DEBUG_bird) ||*/ defined(DOXYGEN_RUNNING)
59# define PDM_DEVHLP_DEADLOCK_DETECTION /**< @todo enable DevHlp deadlock detection! */
60#endif
61
62
63
64/**
65 * Wrapper around PDMR3LdrGetSymbolRCLazy.
66 */
67DECLINLINE(int) pdmR3DevGetSymbolRCLazy(PPDMDEVINS pDevIns, const char *pszSymbol, PRTRCPTR ppvValue)
68{
69 PVM pVM = pDevIns->Internal.s.pVMR3;
70 if (!VM_IS_RAW_MODE_ENABLED(pVM))
71 {
72 *ppvValue = NIL_RTRCPTR;
73 return VINF_SUCCESS;
74 }
75 return PDMR3LdrGetSymbolRCLazy(pVM,
76 pDevIns->Internal.s.pDevR3->pReg->szRCMod,
77 pDevIns->Internal.s.pDevR3->pszRCSearchPath,
78 pszSymbol, ppvValue);
79}
80
81
82/**
83 * Wrapper around PDMR3LdrGetSymbolR0Lazy.
84 */
85DECLINLINE(int) pdmR3DevGetSymbolR0Lazy(PPDMDEVINS pDevIns, const char *pszSymbol, PRTR0PTR ppvValue)
86{
87 return PDMR3LdrGetSymbolR0Lazy(pDevIns->Internal.s.pVMR3,
88 pDevIns->Internal.s.pDevR3->pReg->szR0Mod,
89 pDevIns->Internal.s.pDevR3->pszR0SearchPath,
90 pszSymbol, ppvValue);
91}
92
93
94/** @name R3 DevHlp
95 * @{
96 */
97
98
99/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegister} */
100static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTHCPTR pvUser, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
101 PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc)
102{
103 PDMDEV_ASSERT_DEVINS(pDevIns);
104 LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p p32_tszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
105 Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc, pszDesc));
106 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
107
108#if 0 /** @todo needs a real string cache for this */
109 if (pDevIns->iInstance > 0)
110 {
111 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
112 if (pszDesc2)
113 pszDesc = pszDesc2;
114 }
115#endif
116
117 int rc = IOMR3IOPortRegisterR3(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser,
118 pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc);
119
120 LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
121 return rc;
122}
123
124
125/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegisterRC} */
126static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterRC(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTRCPTR pvUser,
127 const char *pszOut, const char *pszIn,
128 const char *pszOutStr, const char *pszInStr, const char *pszDesc)
129{
130 PDMDEV_ASSERT_DEVINS(pDevIns);
131 PVM pVM = pDevIns->Internal.s.pVMR3;
132 VM_ASSERT_EMT(pVM);
133 LogFlow(("pdmR3DevHlp_IOPortRegisterRC: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
134 Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc));
135
136 /*
137 * Resolve the functions (one of the can be NULL).
138 */
139 int rc = VINF_SUCCESS;
140 if ( pDevIns->pReg->szRCMod[0]
141 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
142 && VM_IS_RAW_MODE_ENABLED(pVM))
143 {
144 RTRCPTR RCPtrIn = NIL_RTRCPTR;
145 if (pszIn)
146 {
147 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszIn, &RCPtrIn);
148 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pReg->szRCMod, pszIn));
149 }
150 RTRCPTR RCPtrOut = NIL_RTRCPTR;
151 if (pszOut && RT_SUCCESS(rc))
152 {
153 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszOut, &RCPtrOut);
154 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pReg->szRCMod, pszOut));
155 }
156 RTRCPTR RCPtrInStr = NIL_RTRCPTR;
157 if (pszInStr && RT_SUCCESS(rc))
158 {
159 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszInStr, &RCPtrInStr);
160 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pReg->szRCMod, pszInStr));
161 }
162 RTRCPTR RCPtrOutStr = NIL_RTRCPTR;
163 if (pszOutStr && RT_SUCCESS(rc))
164 {
165 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszOutStr, &RCPtrOutStr);
166 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pReg->szRCMod, pszOutStr));
167 }
168
169 if (RT_SUCCESS(rc))
170 {
171#if 0 /** @todo needs a real string cache for this */
172 if (pDevIns->iInstance > 0)
173 {
174 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
175 if (pszDesc2)
176 pszDesc = pszDesc2;
177 }
178#endif
179
180 rc = IOMR3IOPortRegisterRC(pVM, pDevIns, Port, cPorts, pvUser, RCPtrOut, RCPtrIn, RCPtrOutStr, RCPtrInStr, pszDesc);
181 }
182 }
183 else if (VM_IS_RAW_MODE_ENABLED(pVM))
184 {
185 AssertMsgFailed(("No RC module for this driver!\n"));
186 rc = VERR_INVALID_PARAMETER;
187 }
188
189 LogFlow(("pdmR3DevHlp_IOPortRegisterRC: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
190 return rc;
191}
192
193
194/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegisterR0} */
195static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterR0(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTR0PTR pvUser,
196 const char *pszOut, const char *pszIn,
197 const char *pszOutStr, const char *pszInStr, const char *pszDesc)
198{
199 PDMDEV_ASSERT_DEVINS(pDevIns);
200 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
201 LogFlow(("pdmR3DevHlp_IOPortRegisterR0: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
202 Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc));
203
204 /*
205 * Resolve the functions (one of the can be NULL).
206 */
207 int rc = VINF_SUCCESS;
208 if ( pDevIns->pReg->szR0Mod[0]
209 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
210 {
211 R0PTRTYPE(PFNIOMIOPORTIN) pfnR0PtrIn = 0;
212 if (pszIn)
213 {
214 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszIn, &pfnR0PtrIn);
215 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pReg->szR0Mod, pszIn));
216 }
217 R0PTRTYPE(PFNIOMIOPORTOUT) pfnR0PtrOut = 0;
218 if (pszOut && RT_SUCCESS(rc))
219 {
220 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszOut, &pfnR0PtrOut);
221 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pReg->szR0Mod, pszOut));
222 }
223 R0PTRTYPE(PFNIOMIOPORTINSTRING) pfnR0PtrInStr = 0;
224 if (pszInStr && RT_SUCCESS(rc))
225 {
226 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszInStr, &pfnR0PtrInStr);
227 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pReg->szR0Mod, pszInStr));
228 }
229 R0PTRTYPE(PFNIOMIOPORTOUTSTRING) pfnR0PtrOutStr = 0;
230 if (pszOutStr && RT_SUCCESS(rc))
231 {
232 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszOutStr, &pfnR0PtrOutStr);
233 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pReg->szR0Mod, pszOutStr));
234 }
235
236 if (RT_SUCCESS(rc))
237 {
238#if 0 /** @todo needs a real string cache for this */
239 if (pDevIns->iInstance > 0)
240 {
241 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
242 if (pszDesc2)
243 pszDesc = pszDesc2;
244 }
245#endif
246
247 rc = IOMR3IOPortRegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser, pfnR0PtrOut, pfnR0PtrIn, pfnR0PtrOutStr, pfnR0PtrInStr, pszDesc);
248 }
249 }
250 else
251 {
252 AssertMsgFailed(("No R0 module for this driver!\n"));
253 rc = VERR_INVALID_PARAMETER;
254 }
255
256 LogFlow(("pdmR3DevHlp_IOPortRegisterR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
257 return rc;
258}
259
260
261/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortDeregister} */
262static DECLCALLBACK(int) pdmR3DevHlp_IOPortDeregister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts)
263{
264 PDMDEV_ASSERT_DEVINS(pDevIns);
265 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
266 LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: Port=%#x cPorts=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance,
267 Port, cPorts));
268
269 int rc = IOMR3IOPortDeregister(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts);
270
271 LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
272 return rc;
273}
274
275
276/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegister} */
277static DECLCALLBACK(int) pdmR3DevHlp_MMIORegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
278 PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill,
279 uint32_t fFlags, const char *pszDesc)
280{
281 PDMDEV_ASSERT_DEVINS(pDevIns);
282 PVM pVM = pDevIns->Internal.s.pVMR3;
283 VM_ASSERT_EMT(pVM);
284 LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp pvUser=%p pfnWrite=%p pfnRead=%p pfnFill=%p fFlags=%#x pszDesc=%p:{%s}\n",
285 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill, pszDesc, fFlags, pszDesc));
286
287 if (pDevIns->iInstance > 0)
288 {
289 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
290 if (pszDesc2)
291 pszDesc = pszDesc2;
292 }
293
294 int rc = IOMR3MmioRegisterR3(pVM, pDevIns, GCPhysStart, cbRange, pvUser,
295 pfnWrite, pfnRead, pfnFill, fFlags, pszDesc);
296
297 LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
298 return rc;
299}
300
301
302/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegisterRC} */
303static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterRC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
304 const char *pszWrite, const char *pszRead, const char *pszFill)
305{
306 PDMDEV_ASSERT_DEVINS(pDevIns);
307 PVM pVM = pDevIns->Internal.s.pVMR3;
308 VM_ASSERT_EMT(pVM);
309 LogFlow(("pdmR3DevHlp_MMIORegisterRC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n",
310 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill));
311
312
313 /*
314 * Resolve the functions.
315 * Not all function have to present, leave it to IOM to enforce this.
316 */
317 int rc = VINF_SUCCESS;
318 if ( pDevIns->pReg->szRCMod[0]
319 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
320 && VM_IS_RAW_MODE_ENABLED(pVM))
321 {
322 RTRCPTR RCPtrWrite = NIL_RTRCPTR;
323 if (pszWrite)
324 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszWrite, &RCPtrWrite);
325
326 RTRCPTR RCPtrRead = NIL_RTRCPTR;
327 int rc2 = VINF_SUCCESS;
328 if (pszRead)
329 rc2 = pdmR3DevGetSymbolRCLazy(pDevIns, pszRead, &RCPtrRead);
330
331 RTRCPTR RCPtrFill = NIL_RTRCPTR;
332 int rc3 = VINF_SUCCESS;
333 if (pszFill)
334 rc3 = pdmR3DevGetSymbolRCLazy(pDevIns, pszFill, &RCPtrFill);
335
336 if (RT_SUCCESS(rc) && RT_SUCCESS(rc2) && RT_SUCCESS(rc3))
337 rc = IOMR3MmioRegisterRC(pVM, pDevIns, GCPhysStart, cbRange, pvUser, RCPtrWrite, RCPtrRead, RCPtrFill);
338 else
339 {
340 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszWrite)\n", pDevIns->pReg->szRCMod, pszWrite));
341 AssertMsgRC(rc2, ("Failed to resolve %s.%s (pszRead)\n", pDevIns->pReg->szRCMod, pszRead));
342 AssertMsgRC(rc3, ("Failed to resolve %s.%s (pszFill)\n", pDevIns->pReg->szRCMod, pszFill));
343 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
344 rc = rc2;
345 if (RT_FAILURE(rc3) && RT_SUCCESS(rc))
346 rc = rc3;
347 }
348 }
349 else if (VM_IS_RAW_MODE_ENABLED(pVM))
350 {
351 AssertMsgFailed(("No RC module for this driver!\n"));
352 rc = VERR_INVALID_PARAMETER;
353 }
354
355 LogFlow(("pdmR3DevHlp_MMIORegisterRC: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
356 return rc;
357}
358
359/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegisterR0} */
360static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterR0(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
361 const char *pszWrite, const char *pszRead, const char *pszFill)
362{
363 PDMDEV_ASSERT_DEVINS(pDevIns);
364 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
365 LogFlow(("pdmR3DevHlp_MMIORegisterHC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n",
366 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill));
367
368 /*
369 * Resolve the functions.
370 * Not all function have to present, leave it to IOM to enforce this.
371 */
372 int rc = VINF_SUCCESS;
373 if ( pDevIns->pReg->szR0Mod[0]
374 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
375 {
376 R0PTRTYPE(PFNIOMMMIOWRITE) pfnR0PtrWrite = 0;
377 if (pszWrite)
378 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszWrite, &pfnR0PtrWrite);
379 R0PTRTYPE(PFNIOMMMIOREAD) pfnR0PtrRead = 0;
380 int rc2 = VINF_SUCCESS;
381 if (pszRead)
382 rc2 = pdmR3DevGetSymbolR0Lazy(pDevIns, pszRead, &pfnR0PtrRead);
383 R0PTRTYPE(PFNIOMMMIOFILL) pfnR0PtrFill = 0;
384 int rc3 = VINF_SUCCESS;
385 if (pszFill)
386 rc3 = pdmR3DevGetSymbolR0Lazy(pDevIns, pszFill, &pfnR0PtrFill);
387 if (RT_SUCCESS(rc) && RT_SUCCESS(rc2) && RT_SUCCESS(rc3))
388 rc = IOMR3MmioRegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvUser,
389 pfnR0PtrWrite, pfnR0PtrRead, pfnR0PtrFill);
390 else
391 {
392 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszWrite)\n", pDevIns->pReg->szR0Mod, pszWrite));
393 AssertMsgRC(rc2, ("Failed to resolve %s.%s (pszRead)\n", pDevIns->pReg->szR0Mod, pszRead));
394 AssertMsgRC(rc3, ("Failed to resolve %s.%s (pszFill)\n", pDevIns->pReg->szR0Mod, pszFill));
395 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
396 rc = rc2;
397 if (RT_FAILURE(rc3) && RT_SUCCESS(rc))
398 rc = rc3;
399 }
400 }
401 else
402 {
403 AssertMsgFailed(("No R0 module for this driver!\n"));
404 rc = VERR_INVALID_PARAMETER;
405 }
406
407 LogFlow(("pdmR3DevHlp_MMIORegisterR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
408 return rc;
409}
410
411
412/** @interface_method_impl{PDMDEVHLPR3,pfnMMIODeregister} */
413static DECLCALLBACK(int) pdmR3DevHlp_MMIODeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange)
414{
415 PDMDEV_ASSERT_DEVINS(pDevIns);
416 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
417 LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp\n",
418 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange));
419
420 int rc = IOMR3MmioDeregister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange);
421
422 LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
423 return rc;
424}
425
426
427/**
428 * @copydoc PDMDEVHLPR3::pfnMMIO2Register
429 */
430static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Register(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cb,
431 uint32_t fFlags, void **ppv, const char *pszDesc)
432{
433 PDMDEV_ASSERT_DEVINS(pDevIns);
434 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
435 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: pPciDev=%p (%#x) iRegion=%#x cb=%#RGp fFlags=%RX32 ppv=%p pszDescp=%p:{%s}\n",
436 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion,
437 cb, fFlags, ppv, pszDesc, pszDesc));
438 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
439
440/** @todo PGMR3PhysMMIO2Register mangles the description, move it here and
441 * use a real string cache. */
442 int rc = PGMR3PhysMMIO2Register(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion,
443 cb, fFlags, ppv, pszDesc);
444
445 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
446 return rc;
447}
448
449
450/**
451 * @interface_method_impl{PDMDEVHLPR3,pfnMMIOExPreRegister}
452 */
453static DECLCALLBACK(int)
454pdmR3DevHlp_MMIOExPreRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion, uint32_t fFlags,
455 const char *pszDesc,
456 RTHCPTR pvUser, PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill,
457 RTR0PTR pvUserR0, const char *pszWriteR0, const char *pszReadR0, const char *pszFillR0,
458 RTRCPTR pvUserRC, const char *pszWriteRC, const char *pszReadRC, const char *pszFillRC)
459{
460 PDMDEV_ASSERT_DEVINS(pDevIns);
461 PVM pVM = pDevIns->Internal.s.pVMR3;
462 VM_ASSERT_EMT(pVM);
463 LogFlow(("pdmR3DevHlp_MMIOExPreRegister: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x cbRegion=%#RGp fFlags=%RX32 pszDesc=%p:{%s}\n"
464 " pvUser=%p pfnWrite=%p pfnRead=%p pfnFill=%p\n"
465 " pvUserR0=%p pszWriteR0=%s pszReadR0=%s pszFillR0=%s\n"
466 " pvUserRC=%p pszWriteRC=%s pszReadRC=%s pszFillRC=%s\n",
467 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, cbRegion,
468 fFlags, pszDesc, pszDesc,
469 pvUser, pfnWrite, pfnRead, pfnFill,
470 pvUserR0, pszWriteR0, pszReadR0, pszFillR0,
471 pvUserRC, pszWriteRC, pszReadRC, pszFillRC));
472 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
473
474 /*
475 * Resolve the functions.
476 */
477 AssertLogRelReturn( (!pszWriteR0 && !pszReadR0 && !pszFillR0)
478 || (pDevIns->pReg->szR0Mod[0] && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)),
479 VERR_INVALID_PARAMETER);
480 AssertLogRelReturn( (!pszWriteRC && !pszReadRC && !pszFillRC)
481 || (pDevIns->pReg->szRCMod[0] && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)),
482 VERR_INVALID_PARAMETER);
483
484 /* Ring-0 */
485 int rc;
486 R0PTRTYPE(PFNIOMMMIOWRITE) pfnWriteR0 = 0;
487 if (pszWriteR0)
488 {
489 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszWriteR0, &pfnWriteR0);
490 AssertLogRelMsgRCReturn(rc, ("pszWriteR0=%s rc=%Rrc\n", pszWriteR0, rc), rc);
491 }
492
493 R0PTRTYPE(PFNIOMMMIOREAD) pfnReadR0 = 0;
494 if (pszReadR0)
495 {
496 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszReadR0, &pfnReadR0);
497 AssertLogRelMsgRCReturn(rc, ("pszReadR0=%s rc=%Rrc\n", pszReadR0, rc), rc);
498 }
499 R0PTRTYPE(PFNIOMMMIOFILL) pfnFillR0 = 0;
500 if (pszFillR0)
501 {
502 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszFillR0, &pfnFillR0);
503 AssertLogRelMsgRCReturn(rc, ("pszFillR0=%s rc=%Rrc\n", pszFillR0, rc), rc);
504 }
505
506 /* Raw-mode */
507 rc = VINF_SUCCESS;
508 RCPTRTYPE(PFNIOMMMIOWRITE) pfnWriteRC = 0;
509 if (pszWriteRC)
510 {
511 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszWriteRC, &pfnWriteRC);
512 AssertLogRelMsgRCReturn(rc, ("pszWriteRC=%s rc=%Rrc\n", pszWriteRC, rc), rc);
513 }
514
515 RCPTRTYPE(PFNIOMMMIOREAD) pfnReadRC = 0;
516 if (pszReadRC)
517 {
518 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszReadRC, &pfnReadRC);
519 AssertLogRelMsgRCReturn(rc, ("pszReadRC=%s rc=%Rrc\n", pszReadRC, rc), rc);
520 }
521 RCPTRTYPE(PFNIOMMMIOFILL) pfnFillRC = 0;
522 if (pszFillRC)
523 {
524 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszFillRC, &pfnFillRC);
525 AssertLogRelMsgRCReturn(rc, ("pszFillRC=%s rc=%Rrc\n", pszFillRC, rc), rc);
526 }
527
528 /*
529 * Call IOM to make the registration.
530 */
531 rc = IOMR3MmioExPreRegister(pVM, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, cbRegion, fFlags, pszDesc,
532 pvUser, pfnWrite, pfnRead, pfnFill,
533 pvUserR0, pfnWriteR0, pfnReadR0, pfnFillR0,
534 pvUserRC, pfnWriteRC, pfnReadRC, pfnFillRC);
535
536 LogFlow(("pdmR3DevHlp_MMIOExPreRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
537 return rc;
538}
539
540
541/**
542 * @copydoc PDMDEVHLPR3::pfnMMIOExDeregister
543 */
544static DECLCALLBACK(int) pdmR3DevHlp_MMIOExDeregister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion)
545{
546 PDMDEV_ASSERT_DEVINS(pDevIns);
547 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
548 LogFlow(("pdmR3DevHlp_MMIOExDeregister: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x\n",
549 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion));
550
551 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
552 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
553
554 int rc = PGMR3PhysMMIOExDeregister(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion);
555
556 LogFlow(("pdmR3DevHlp_MMIOExDeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
557 return rc;
558}
559
560
561/**
562 * @copydoc PDMDEVHLPR3::pfnMMIOExMap
563 */
564static DECLCALLBACK(int) pdmR3DevHlp_MMIOExMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
565{
566 PDMDEV_ASSERT_DEVINS(pDevIns);
567 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
568 LogFlow(("pdmR3DevHlp_MMIOExMap: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x GCPhys=%#RGp\n",
569 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, GCPhys));
570 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 != NULL, VERR_INVALID_PARAMETER);
571
572 int rc = PGMR3PhysMMIOExMap(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, GCPhys);
573
574 LogFlow(("pdmR3DevHlp_MMIOExMap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
575 return rc;
576}
577
578
579/**
580 * @copydoc PDMDEVHLPR3::pfnMMIOExUnmap
581 */
582static DECLCALLBACK(int) pdmR3DevHlp_MMIOExUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
583{
584 PDMDEV_ASSERT_DEVINS(pDevIns);
585 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
586 LogFlow(("pdmR3DevHlp_MMIOExUnmap: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x GCPhys=%#RGp\n",
587 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, GCPhys));
588 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 != NULL, VERR_INVALID_PARAMETER);
589
590 int rc = PGMR3PhysMMIOExUnmap(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, GCPhys);
591
592 LogFlow(("pdmR3DevHlp_MMIOExUnmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
593 return rc;
594}
595
596
597/**
598 * @copydoc PDMDEVHLPR3::pfnMMIOExReduce
599 */
600static DECLCALLBACK(int) pdmR3DevHlp_MMIOExReduce(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion)
601{
602 PDMDEV_ASSERT_DEVINS(pDevIns);
603 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
604 LogFlow(("pdmR3DevHlp_MMIOExReduce: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x cbRegion=%RGp\n",
605 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, cbRegion));
606 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 != NULL, VERR_INVALID_PARAMETER);
607
608 int rc = PGMR3PhysMMIOExReduce(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, cbRegion);
609
610 LogFlow(("pdmR3DevHlp_MMIOExReduce: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
611 return rc;
612}
613
614
615/**
616 * @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2
617 */
618static DECLCALLBACK(int) pdmR3DevHlp_MMHyperMapMMIO2(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
619 RTGCPHYS cb, const char *pszDesc, PRTRCPTR pRCPtr)
620{
621 PDMDEV_ASSERT_DEVINS(pDevIns);
622 PVM pVM = pDevIns->Internal.s.pVMR3;
623 VM_ASSERT_EMT(pVM);
624 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pRCPtr=%p\n",
625 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, off, cb, pszDesc, pszDesc, pRCPtr));
626 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
627
628 if (pDevIns->iInstance > 0)
629 {
630 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
631 if (pszDesc2)
632 pszDesc = pszDesc2;
633 }
634
635 int rc = MMR3HyperMapMMIO2(pVM, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, off, cb, pszDesc, pRCPtr);
636
637 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: returns %Rrc *pRCPtr=%RRv\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *pRCPtr));
638 return rc;
639}
640
641
642/**
643 * @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel
644 */
645static DECLCALLBACK(int) pdmR3DevHlp_MMIO2MapKernel(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
646 RTGCPHYS cb,const char *pszDesc, PRTR0PTR pR0Ptr)
647{
648 PDMDEV_ASSERT_DEVINS(pDevIns);
649 PVM pVM = pDevIns->Internal.s.pVMR3;
650 VM_ASSERT_EMT(pVM);
651 LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pR0Ptr=%p\n",
652 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, off, cb, pszDesc, pszDesc, pR0Ptr));
653 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
654
655 if (pDevIns->iInstance > 0)
656 {
657 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
658 if (pszDesc2)
659 pszDesc = pszDesc2;
660 }
661
662 int rc = PGMR3PhysMMIO2MapKernel(pVM, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, off, cb, pszDesc, pR0Ptr);
663
664 LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: returns %Rrc *pR0Ptr=%RHv\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *pR0Ptr));
665 return rc;
666}
667
668
669/** @interface_method_impl{PDMDEVHLPR3,pfnROMRegister} */
670static DECLCALLBACK(int) pdmR3DevHlp_ROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
671 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc)
672{
673 PDMDEV_ASSERT_DEVINS(pDevIns);
674 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
675 LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvBinary=%p cbBinary=%#x fFlags=%#RX32 pszDesc=%p:{%s}\n",
676 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc, pszDesc));
677
678/** @todo can we mangle pszDesc? */
679 int rc = PGMR3PhysRomRegister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
680
681 LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
682 return rc;
683}
684
685
686/** @interface_method_impl{PDMDEVHLPR3,pfnROMProtectShadow} */
687static DECLCALLBACK(int) pdmR3DevHlp_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
688{
689 PDMDEV_ASSERT_DEVINS(pDevIns);
690 LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x enmProt=%d\n",
691 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, enmProt));
692
693 int rc = PGMR3PhysRomProtect(pDevIns->Internal.s.pVMR3, GCPhysStart, cbRange, enmProt);
694
695 LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
696 return rc;
697}
698
699
700/** @interface_method_impl{PDMDEVHLPR3,pfnSSMRegister} */
701static DECLCALLBACK(int) pdmR3DevHlp_SSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
702 PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
703 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
704 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
705{
706 PDMDEV_ASSERT_DEVINS(pDevIns);
707 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
708 LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: uVersion=%#x cbGuess=%#x pszBefore=%p:{%s}\n"
709 " pfnLivePrep=%p pfnLiveExec=%p pfnLiveVote=%p pfnSavePrep=%p pfnSaveExec=%p pfnSaveDone=%p pszLoadPrep=%p pfnLoadExec=%p pfnLoadDone=%p\n",
710 pDevIns->pReg->szName, pDevIns->iInstance, uVersion, cbGuess, pszBefore, pszBefore,
711 pfnLivePrep, pfnLiveExec, pfnLiveVote,
712 pfnSavePrep, pfnSaveExec, pfnSaveDone,
713 pfnLoadPrep, pfnLoadExec, pfnLoadDone));
714
715 int rc = SSMR3RegisterDevice(pDevIns->Internal.s.pVMR3, pDevIns, pDevIns->pReg->szName, pDevIns->iInstance,
716 uVersion, cbGuess, pszBefore,
717 pfnLivePrep, pfnLiveExec, pfnLiveVote,
718 pfnSavePrep, pfnSaveExec, pfnSaveDone,
719 pfnLoadPrep, pfnLoadExec, pfnLoadDone);
720
721 LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
722 return rc;
723}
724
725
726/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimerCreate} */
727static DECLCALLBACK(int) pdmR3DevHlp_TMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser, uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer)
728{
729 PDMDEV_ASSERT_DEVINS(pDevIns);
730 PVM pVM = pDevIns->Internal.s.pVMR3;
731 VM_ASSERT_EMT(pVM);
732 LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: enmClock=%d pfnCallback=%p pvUser=%p fFlags=%#x pszDesc=%p:{%s} ppTimer=%p\n",
733 pDevIns->pReg->szName, pDevIns->iInstance, enmClock, pfnCallback, pvUser, fFlags, pszDesc, pszDesc, ppTimer));
734
735 if (pDevIns->iInstance > 0) /** @todo use a string cache here later. */
736 {
737 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
738 if (pszDesc2)
739 pszDesc = pszDesc2;
740 }
741
742 int rc = TMR3TimerCreateDevice(pVM, pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
743
744 LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
745 return rc;
746}
747
748
749/** @interface_method_impl{PDMDEVHLPR3,pfnTMUtcNow} */
750static DECLCALLBACK(PRTTIMESPEC) pdmR3DevHlp_TMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
751{
752 PDMDEV_ASSERT_DEVINS(pDevIns);
753 LogFlow(("pdmR3DevHlp_TMUtcNow: caller='%s'/%d: pTime=%p\n",
754 pDevIns->pReg->szName, pDevIns->iInstance, pTime));
755
756 pTime = TMR3UtcNow(pDevIns->Internal.s.pVMR3, pTime);
757
758 LogFlow(("pdmR3DevHlp_TMUtcNow: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, RTTimeSpecGetNano(pTime)));
759 return pTime;
760}
761
762
763/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGet} */
764static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
765{
766 PDMDEV_ASSERT_DEVINS(pDevIns);
767 LogFlow(("pdmR3DevHlp_TMTimeVirtGet: caller='%s'/%d\n",
768 pDevIns->pReg->szName, pDevIns->iInstance));
769
770 uint64_t u64Time = TMVirtualSyncGet(pDevIns->Internal.s.pVMR3);
771
772 LogFlow(("pdmR3DevHlp_TMTimeVirtGet: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Time));
773 return u64Time;
774}
775
776
777/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGetFreq} */
778static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
779{
780 PDMDEV_ASSERT_DEVINS(pDevIns);
781 LogFlow(("pdmR3DevHlp_TMTimeVirtGetFreq: caller='%s'/%d\n",
782 pDevIns->pReg->szName, pDevIns->iInstance));
783
784 uint64_t u64Freq = TMVirtualGetFreq(pDevIns->Internal.s.pVMR3);
785
786 LogFlow(("pdmR3DevHlp_TMTimeVirtGetFreq: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Freq));
787 return u64Freq;
788}
789
790
791/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGetNano} */
792static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
793{
794 PDMDEV_ASSERT_DEVINS(pDevIns);
795 LogFlow(("pdmR3DevHlp_TMTimeVirtGetNano: caller='%s'/%d\n",
796 pDevIns->pReg->szName, pDevIns->iInstance));
797
798 uint64_t u64Time = TMVirtualGet(pDevIns->Internal.s.pVMR3);
799 uint64_t u64Nano = TMVirtualToNano(pDevIns->Internal.s.pVMR3, u64Time);
800
801 LogFlow(("pdmR3DevHlp_TMTimeVirtGetNano: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Nano));
802 return u64Nano;
803}
804
805
806/** @interface_method_impl{PDMDEVHLPR3,pfnGetSupDrvSession} */
807static DECLCALLBACK(PSUPDRVSESSION) pdmR3DevHlp_GetSupDrvSession(PPDMDEVINS pDevIns)
808{
809 PDMDEV_ASSERT_DEVINS(pDevIns);
810 LogFlow(("pdmR3DevHlp_GetSupDrvSession: caller='%s'/%d\n",
811 pDevIns->pReg->szName, pDevIns->iInstance));
812
813 PSUPDRVSESSION pSession = pDevIns->Internal.s.pVMR3->pSession;
814
815 LogFlow(("pdmR3DevHlp_GetSupDrvSession: caller='%s'/%d: returns %#p\n", pDevIns->pReg->szName, pDevIns->iInstance, pSession));
816 return pSession;
817}
818
819
820/** @interface_method_impl{PDMDEVHLPR3,pfnQueryGenericUserObject} */
821static DECLCALLBACK(void *) pdmR3DevHlp_QueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
822{
823 PDMDEV_ASSERT_DEVINS(pDevIns);
824 LogFlow(("pdmR3DevHlp_QueryGenericUserObject: caller='%s'/%d: pUuid=%p:%RTuuid\n",
825 pDevIns->pReg->szName, pDevIns->iInstance, pUuid, pUuid));
826
827#if defined(DEBUG_bird) || defined(DEBUG_ramshankar) || defined(DEBUG_sunlover) || defined(DEBUG_michael) || defined(DEBUG_andy)
828 AssertMsgFailed(("'%s' wants %RTuuid - external only interface!\n", pDevIns->pReg->szName, pUuid));
829#endif
830
831 void *pvRet;
832 PUVM pUVM = pDevIns->Internal.s.pVMR3->pUVM;
833 if (pUVM->pVmm2UserMethods->pfnQueryGenericObject)
834 pvRet = pUVM->pVmm2UserMethods->pfnQueryGenericObject(pUVM->pVmm2UserMethods, pUVM, pUuid);
835 else
836 pvRet = NULL;
837
838 LogRel(("pdmR3DevHlp_QueryGenericUserObject: caller='%s'/%d: returns %#p for %RTuuid\n",
839 pDevIns->pReg->szName, pDevIns->iInstance, pvRet, pUuid));
840 return pvRet;
841}
842
843
844/** @interface_method_impl{PDMDEVHLPR3,pfnPhysRead} */
845static DECLCALLBACK(int) pdmR3DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
846{
847 PDMDEV_ASSERT_DEVINS(pDevIns);
848 PVM pVM = pDevIns->Internal.s.pVMR3;
849 LogFlow(("pdmR3DevHlp_PhysRead: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
850 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
851
852#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
853 if (!VM_IS_EMT(pVM))
854 {
855 char szNames[128];
856 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
857 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
858 }
859#endif
860
861 VBOXSTRICTRC rcStrict;
862 if (VM_IS_EMT(pVM))
863 rcStrict = PGMPhysRead(pVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
864 else
865 rcStrict = PGMR3PhysReadExternal(pVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
866 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
867
868 Log(("pdmR3DevHlp_PhysRead: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
869 return VBOXSTRICTRC_VAL(rcStrict);
870}
871
872
873/** @interface_method_impl{PDMDEVHLPR3,pfnPhysWrite} */
874static DECLCALLBACK(int) pdmR3DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
875{
876 PDMDEV_ASSERT_DEVINS(pDevIns);
877 PVM pVM = pDevIns->Internal.s.pVMR3;
878 LogFlow(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
879 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
880
881#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
882 if (!VM_IS_EMT(pVM))
883 {
884 char szNames[128];
885 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
886 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
887 }
888#endif
889
890 VBOXSTRICTRC rcStrict;
891 if (VM_IS_EMT(pVM))
892 rcStrict = PGMPhysWrite(pVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
893 else
894 rcStrict = PGMR3PhysWriteExternal(pVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
895 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
896
897 Log(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
898 return VBOXSTRICTRC_VAL(rcStrict);
899}
900
901
902/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtr} */
903static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
904{
905 PDMDEV_ASSERT_DEVINS(pDevIns);
906 PVM pVM = pDevIns->Internal.s.pVMR3;
907 LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
908 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
909 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
910
911#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
912 if (!VM_IS_EMT(pVM))
913 {
914 char szNames[128];
915 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
916 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
917 }
918#endif
919
920 int rc = PGMR3PhysGCPhys2CCPtrExternal(pVM, GCPhys, ppv, pLock);
921
922 Log(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
923 return rc;
924}
925
926
927/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtrReadOnly} */
928static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, const void **ppv, PPGMPAGEMAPLOCK pLock)
929{
930 PDMDEV_ASSERT_DEVINS(pDevIns);
931 PVM pVM = pDevIns->Internal.s.pVMR3;
932 LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
933 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
934 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
935
936#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
937 if (!VM_IS_EMT(pVM))
938 {
939 char szNames[128];
940 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
941 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
942 }
943#endif
944
945 int rc = PGMR3PhysGCPhys2CCPtrReadOnlyExternal(pVM, GCPhys, ppv, pLock);
946
947 Log(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
948 return rc;
949}
950
951
952/** @interface_method_impl{PDMDEVHLPR3,pfnPhysReleasePageMappingLock} */
953static DECLCALLBACK(void) pdmR3DevHlp_PhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
954{
955 PDMDEV_ASSERT_DEVINS(pDevIns);
956 PVM pVM = pDevIns->Internal.s.pVMR3;
957 LogFlow(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: pLock=%p\n",
958 pDevIns->pReg->szName, pDevIns->iInstance, pLock));
959
960 PGMPhysReleasePageMappingLock(pVM, pLock);
961
962 Log(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
963}
964
965
966/** @interface_method_impl{PDMDEVHLPR3,pfnPhysBulkGCPhys2CCPtr} */
967static DECLCALLBACK(int) pdmR3DevHlp_PhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
968 uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
969{
970 PDMDEV_ASSERT_DEVINS(pDevIns);
971 PVM pVM = pDevIns->Internal.s.pVMR3;
972 LogFlow(("pdmR3DevHlp_PhysBulkGCPhys2CCPtr: caller='%s'/%d: cPages=%#x paGCPhysPages=%p (%RGp,..) fFlags=%#x papvPages=%p paLocks=%p\n",
973 pDevIns->pReg->szName, pDevIns->iInstance, cPages, paGCPhysPages, paGCPhysPages[0], fFlags, papvPages, paLocks));
974 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
975 AssertReturn(cPages > 0, VERR_INVALID_PARAMETER);
976
977#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
978 if (!VM_IS_EMT(pVM))
979 {
980 char szNames[128];
981 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
982 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
983 }
984#endif
985
986 int rc = PGMR3PhysBulkGCPhys2CCPtrExternal(pVM, cPages, paGCPhysPages, papvPages, paLocks);
987
988 Log(("pdmR3DevHlp_PhysBulkGCPhys2CCPtr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
989 return rc;
990}
991
992
993/** @interface_method_impl{PDMDEVHLPR3,pfnPhysBulkGCPhys2CCPtrReadOnly} */
994static DECLCALLBACK(int) pdmR3DevHlp_PhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
995 uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks)
996{
997 PDMDEV_ASSERT_DEVINS(pDevIns);
998 PVM pVM = pDevIns->Internal.s.pVMR3;
999 LogFlow(("pdmR3DevHlp_PhysBulkGCPhys2CCPtrReadOnly: caller='%s'/%d: cPages=%#x paGCPhysPages=%p (%RGp,...) fFlags=%#x papvPages=%p paLocks=%p\n",
1000 pDevIns->pReg->szName, pDevIns->iInstance, cPages, paGCPhysPages, paGCPhysPages[0], fFlags, papvPages, paLocks));
1001 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1002 AssertReturn(cPages > 0, VERR_INVALID_PARAMETER);
1003
1004#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1005 if (!VM_IS_EMT(pVM))
1006 {
1007 char szNames[128];
1008 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
1009 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
1010 }
1011#endif
1012
1013 int rc = PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(pVM, cPages, paGCPhysPages, papvPages, paLocks);
1014
1015 Log(("pdmR3DevHlp_PhysBulkGCPhys2CCPtrReadOnly: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1016 return rc;
1017}
1018
1019
1020/** @interface_method_impl{PDMDEVHLPR3,pfnPhysReleasePageMappingLocks} */
1021static DECLCALLBACK(void) pdmR3DevHlp_PhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
1022{
1023 PDMDEV_ASSERT_DEVINS(pDevIns);
1024 PVM pVM = pDevIns->Internal.s.pVMR3;
1025 LogFlow(("pdmR3DevHlp_PhysBulkReleasePageMappingLocks: caller='%s'/%d: cPages=%#x paLocks=%p\n",
1026 pDevIns->pReg->szName, pDevIns->iInstance, cPages, paLocks));
1027 Assert(cPages > 0);
1028
1029 PGMPhysBulkReleasePageMappingLocks(pVM, cPages, paLocks);
1030
1031 Log(("pdmR3DevHlp_PhysBulkReleasePageMappingLocks: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1032}
1033
1034
1035/** @interface_method_impl{PDMDEVHLPR3,pfnPhysReadGCVirt} */
1036static DECLCALLBACK(int) pdmR3DevHlp_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
1037{
1038 PDMDEV_ASSERT_DEVINS(pDevIns);
1039 PVM pVM = pDevIns->Internal.s.pVMR3;
1040 VM_ASSERT_EMT(pVM);
1041 LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: pvDst=%p GCVirt=%RGv cb=%#x\n",
1042 pDevIns->pReg->szName, pDevIns->iInstance, pvDst, GCVirtSrc, cb));
1043
1044 PVMCPU pVCpu = VMMGetCpu(pVM);
1045 if (!pVCpu)
1046 return VERR_ACCESS_DENIED;
1047#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1048 /** @todo SMP. */
1049#endif
1050
1051 int rc = PGMPhysSimpleReadGCPtr(pVCpu, pvDst, GCVirtSrc, cb);
1052
1053 LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1054
1055 return rc;
1056}
1057
1058
1059/** @interface_method_impl{PDMDEVHLPR3,pfnPhysWriteGCVirt} */
1060static DECLCALLBACK(int) pdmR3DevHlp_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
1061{
1062 PDMDEV_ASSERT_DEVINS(pDevIns);
1063 PVM pVM = pDevIns->Internal.s.pVMR3;
1064 VM_ASSERT_EMT(pVM);
1065 LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: GCVirtDst=%RGv pvSrc=%p cb=%#x\n",
1066 pDevIns->pReg->szName, pDevIns->iInstance, GCVirtDst, pvSrc, cb));
1067
1068 PVMCPU pVCpu = VMMGetCpu(pVM);
1069 if (!pVCpu)
1070 return VERR_ACCESS_DENIED;
1071#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1072 /** @todo SMP. */
1073#endif
1074
1075 int rc = PGMPhysSimpleWriteGCPtr(pVCpu, GCVirtDst, pvSrc, cb);
1076
1077 LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1078
1079 return rc;
1080}
1081
1082
1083/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPtr2GCPhys} */
1084static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
1085{
1086 PDMDEV_ASSERT_DEVINS(pDevIns);
1087 PVM pVM = pDevIns->Internal.s.pVMR3;
1088 VM_ASSERT_EMT(pVM);
1089 LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: GCPtr=%RGv pGCPhys=%p\n",
1090 pDevIns->pReg->szName, pDevIns->iInstance, GCPtr, pGCPhys));
1091
1092 PVMCPU pVCpu = VMMGetCpu(pVM);
1093 if (!pVCpu)
1094 return VERR_ACCESS_DENIED;
1095#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1096 /** @todo SMP. */
1097#endif
1098
1099 int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, pGCPhys);
1100
1101 LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: returns %Rrc *pGCPhys=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *pGCPhys));
1102
1103 return rc;
1104}
1105
1106
1107/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAlloc} */
1108static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
1109{
1110 PDMDEV_ASSERT_DEVINS(pDevIns);
1111 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: cb=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cb));
1112
1113 void *pv = MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
1114
1115 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1116 return pv;
1117}
1118
1119
1120/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAllocZ} */
1121static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
1122{
1123 PDMDEV_ASSERT_DEVINS(pDevIns);
1124 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: cb=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cb));
1125
1126 void *pv = MMR3HeapAllocZ(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
1127
1128 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1129 return pv;
1130}
1131
1132
1133/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapFree} */
1134static DECLCALLBACK(void) pdmR3DevHlp_MMHeapFree(PPDMDEVINS pDevIns, void *pv)
1135{
1136 PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
1137 LogFlow(("pdmR3DevHlp_MMHeapFree: caller='%s'/%d: pv=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1138
1139 MMR3HeapFree(pv);
1140
1141 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1142}
1143
1144
1145/** @interface_method_impl{PDMDEVHLPR3,pfnVMState} */
1146static DECLCALLBACK(VMSTATE) pdmR3DevHlp_VMState(PPDMDEVINS pDevIns)
1147{
1148 PDMDEV_ASSERT_DEVINS(pDevIns);
1149
1150 VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3);
1151
1152 LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %d (%s)\n", pDevIns->pReg->szName, pDevIns->iInstance,
1153 enmVMState, VMR3GetStateName(enmVMState)));
1154 return enmVMState;
1155}
1156
1157
1158/** @interface_method_impl{PDMDEVHLPR3,pfnVMTeleportedAndNotFullyResumedYet} */
1159static DECLCALLBACK(bool) pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
1160{
1161 PDMDEV_ASSERT_DEVINS(pDevIns);
1162
1163 bool fRc = VMR3TeleportedAndNotFullyResumedYet(pDevIns->Internal.s.pVMR3);
1164
1165 LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance,
1166 fRc));
1167 return fRc;
1168}
1169
1170
1171/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetError} */
1172static DECLCALLBACK(int) pdmR3DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
1173{
1174 PDMDEV_ASSERT_DEVINS(pDevIns);
1175 va_list args;
1176 va_start(args, pszFormat);
1177 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
1178 va_end(args);
1179 return rc;
1180}
1181
1182
1183/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetErrorV} */
1184static DECLCALLBACK(int) pdmR3DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
1185{
1186 PDMDEV_ASSERT_DEVINS(pDevIns);
1187 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
1188 return rc;
1189}
1190
1191
1192/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeError} */
1193static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
1194{
1195 PDMDEV_ASSERT_DEVINS(pDevIns);
1196 va_list args;
1197 va_start(args, pszFormat);
1198 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, args);
1199 va_end(args);
1200 return rc;
1201}
1202
1203
1204/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeErrorV} */
1205static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
1206{
1207 PDMDEV_ASSERT_DEVINS(pDevIns);
1208 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, va);
1209 return rc;
1210}
1211
1212
1213/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFStopV} */
1214static DECLCALLBACK(int) pdmR3DevHlp_DBGFStopV(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction, const char *pszFormat, va_list args)
1215{
1216 PDMDEV_ASSERT_DEVINS(pDevIns);
1217#ifdef LOG_ENABLED
1218 va_list va2;
1219 va_copy(va2, args);
1220 LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: pszFile=%p:{%s} iLine=%d pszFunction=%p:{%s} pszFormat=%p:{%s} (%N)\n",
1221 pDevIns->pReg->szName, pDevIns->iInstance, pszFile, pszFile, iLine, pszFunction, pszFunction, pszFormat, pszFormat, pszFormat, &va2));
1222 va_end(va2);
1223#endif
1224
1225 PVM pVM = pDevIns->Internal.s.pVMR3;
1226 VM_ASSERT_EMT(pVM);
1227 int rc = DBGFR3EventSrcV(pVM, DBGFEVENT_DEV_STOP, pszFile, iLine, pszFunction, pszFormat, args);
1228 if (rc == VERR_DBGF_NOT_ATTACHED)
1229 rc = VINF_SUCCESS;
1230
1231 LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1232 return rc;
1233}
1234
1235
1236/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFInfoRegister} */
1237static DECLCALLBACK(int) pdmR3DevHlp_DBGFInfoRegister(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler)
1238{
1239 PDMDEV_ASSERT_DEVINS(pDevIns);
1240 LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: pszName=%p:{%s} pszDesc=%p:{%s} pfnHandler=%p\n",
1241 pDevIns->pReg->szName, pDevIns->iInstance, pszName, pszName, pszDesc, pszDesc, pfnHandler));
1242
1243 PVM pVM = pDevIns->Internal.s.pVMR3;
1244 VM_ASSERT_EMT(pVM);
1245 int rc = DBGFR3InfoRegisterDevice(pVM, pszName, pszDesc, pfnHandler, pDevIns);
1246
1247 LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1248 return rc;
1249}
1250
1251
1252/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFRegRegister} */
1253static DECLCALLBACK(int) pdmR3DevHlp_DBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
1254{
1255 PDMDEV_ASSERT_DEVINS(pDevIns);
1256 LogFlow(("pdmR3DevHlp_DBGFRegRegister: caller='%s'/%d: paRegisters=%p\n",
1257 pDevIns->pReg->szName, pDevIns->iInstance, paRegisters));
1258
1259 PVM pVM = pDevIns->Internal.s.pVMR3;
1260 VM_ASSERT_EMT(pVM);
1261 int rc = DBGFR3RegRegisterDevice(pVM, paRegisters, pDevIns, pDevIns->pReg->szName, pDevIns->iInstance);
1262
1263 LogFlow(("pdmR3DevHlp_DBGFRegRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1264 return rc;
1265}
1266
1267
1268/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFTraceBuf} */
1269static DECLCALLBACK(RTTRACEBUF) pdmR3DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
1270{
1271 PDMDEV_ASSERT_DEVINS(pDevIns);
1272 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMR3->hTraceBufR3;
1273 LogFlow(("pdmR3DevHlp_DBGFTraceBuf: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, hTraceBuf));
1274 return hTraceBuf;
1275}
1276
1277
1278/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegister} */
1279static DECLCALLBACK(void) pdmR3DevHlp_STAMRegister(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName,
1280 STAMUNIT enmUnit, const char *pszDesc)
1281{
1282 PDMDEV_ASSERT_DEVINS(pDevIns);
1283 PVM pVM = pDevIns->Internal.s.pVMR3;
1284 VM_ASSERT_EMT(pVM);
1285
1286 STAM_REG(pVM, pvSample, enmType, pszName, enmUnit, pszDesc);
1287 RT_NOREF_PV(pVM); RT_NOREF6(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
1288}
1289
1290
1291
1292/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterF} */
1293static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,
1294 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, ...)
1295{
1296 PDMDEV_ASSERT_DEVINS(pDevIns);
1297 PVM pVM = pDevIns->Internal.s.pVMR3;
1298 VM_ASSERT_EMT(pVM);
1299
1300 va_list args;
1301 va_start(args, pszName);
1302 int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);
1303 va_end(args);
1304 AssertRC(rc);
1305
1306 NOREF(pVM);
1307}
1308
1309
1310/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterV} */
1311static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterV(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,
1312 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, va_list args)
1313{
1314 PDMDEV_ASSERT_DEVINS(pDevIns);
1315 PVM pVM = pDevIns->Internal.s.pVMR3;
1316 VM_ASSERT_EMT(pVM);
1317
1318 int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);
1319 AssertRC(rc);
1320
1321 NOREF(pVM);
1322}
1323
1324
1325/**
1326 * @interface_method_impl{PDMDEVHLPR3,pfnPCIRegister}
1327 */
1328static DECLCALLBACK(int) pdmR3DevHlp_PCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t idxDevCfg, uint32_t fFlags,
1329 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
1330{
1331 PDMDEV_ASSERT_DEVINS(pDevIns);
1332 PVM pVM = pDevIns->Internal.s.pVMR3;
1333 VM_ASSERT_EMT(pVM);
1334 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: pPciDev=%p:{.config={%#.256Rhxs} idxDevCfg=%d fFlags=%#x uPciDevNo=%#x uPciFunNo=%#x pszName=%p:{%s}\n",
1335 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->abConfig, idxDevCfg, fFlags, uPciDevNo, uPciFunNo, pszName, pszName ? pszName : ""));
1336
1337 /*
1338 * Validate input.
1339 */
1340 AssertLogRelMsgReturn(RT_VALID_PTR(pPciDev),
1341 ("'%s'/%d: Invalid pPciDev value: %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pPciDev),
1342 VERR_INVALID_POINTER);
1343 AssertLogRelMsgReturn(PDMPciDevGetVendorId(pPciDev),
1344 ("'%s'/%d: Vendor ID is not set!\n", pDevIns->pReg->szName, pDevIns->iInstance),
1345 VERR_INVALID_POINTER);
1346 AssertLogRelMsgReturn(idxDevCfg < 256 || idxDevCfg == PDMPCIDEVREG_CFG_NEXT,
1347 ("'%s'/%d: Invalid config selector: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1348 VERR_OUT_OF_RANGE);
1349 AssertLogRelMsgReturn( uPciDevNo < 32
1350 || uPciDevNo == PDMPCIDEVREG_DEV_NO_FIRST_UNUSED
1351 || uPciDevNo == PDMPCIDEVREG_DEV_NO_SAME_AS_PREV,
1352 ("'%s'/%d: Invalid PCI device number: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, uPciDevNo),
1353 VERR_INVALID_PARAMETER);
1354 AssertLogRelMsgReturn( uPciFunNo < 8
1355 || uPciFunNo == PDMPCIDEVREG_FUN_NO_FIRST_UNUSED,
1356 ("'%s'/%d: Invalid PCI funcion number: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, uPciFunNo),
1357 VERR_INVALID_PARAMETER);
1358 AssertLogRelMsgReturn(!(fFlags & ~PDMPCIDEVREG_F_VALID_MASK),
1359 ("'%s'/%d: Invalid flags: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, fFlags),
1360 VERR_INVALID_FLAGS);
1361 if (!pszName)
1362 pszName = pDevIns->pReg->szName;
1363 AssertLogRelReturn(RT_VALID_PTR(pszName), VERR_INVALID_POINTER);
1364
1365 /*
1366 * Find the last(/previous) registered PCI device (for linking and more),
1367 * checking for duplicate registration attempts while doing so.
1368 */
1369 uint32_t idxDevCfgNext = 0;
1370 PPDMPCIDEV pPrevPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1371 while (pPrevPciDev)
1372 {
1373 AssertLogRelMsgReturn(pPrevPciDev != pPciDev,
1374 ("'%s'/%d attempted to register the same PCI device (%p) twice\n",
1375 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev),
1376 VERR_DUPLICATE);
1377 AssertLogRelMsgReturn(pPrevPciDev->Int.s.idxDevCfg != idxDevCfg,
1378 ("'%s'/%d attempted to use the same device config index (%u) twice\n",
1379 pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1380 VERR_ALREADY_LOADED);
1381 if (pPrevPciDev->Int.s.idxDevCfg >= idxDevCfgNext)
1382 idxDevCfgNext = pPrevPciDev->Int.s.idxDevCfg + 1;
1383
1384 if (!pPrevPciDev->Int.s.pNextR3)
1385 break;
1386 pPrevPciDev = pPrevPciDev->Int.s.pNextR3;
1387 }
1388
1389 /*
1390 * Resolve the PCI configuration node for the device. The default (zero'th)
1391 * is the same as the PDM device, the rest are "PciCfg1..255" CFGM sub-nodes.
1392 */
1393 if (idxDevCfg == PDMPCIDEVREG_CFG_NEXT)
1394 {
1395 idxDevCfg = idxDevCfgNext;
1396 AssertLogRelMsgReturn(idxDevCfg < 256, ("'%s'/%d: PDMPCIDEVREG_IDX_DEV_CFG_NEXT ran out of valid indexes (ends at 255)\n",
1397 pDevIns->pReg->szName, pDevIns->iInstance),
1398 VERR_OUT_OF_RANGE);
1399 }
1400
1401 PCFGMNODE pCfg = pDevIns->Internal.s.pCfgHandle;
1402 if (idxDevCfg != 0)
1403 pCfg = CFGMR3GetChildF(pDevIns->Internal.s.pCfgHandle, "PciCfg%u", idxDevCfg);
1404
1405 /*
1406 * We resolve PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, the PCI bus handles
1407 * PDMPCIDEVREG_DEV_NO_FIRST_UNUSED and PDMPCIDEVREG_FUN_NO_FIRST_UNUSED.
1408 */
1409 uint8_t const uPciDevNoRaw = uPciDevNo;
1410 uint32_t uDefPciBusNo = 0;
1411 if (uPciDevNo == PDMPCIDEVREG_DEV_NO_SAME_AS_PREV)
1412 {
1413 if (pPrevPciDev)
1414 {
1415 uPciDevNo = pPrevPciDev->uDevFn >> 3;
1416 uDefPciBusNo = pPrevPciDev->Int.s.pPdmBusR3->iBus;
1417 }
1418 else
1419 {
1420 /* Look for PCI device registered with an earlier device instance so we can more
1421 easily have multiple functions spanning multiple PDM device instances. */
1422 PPDMPCIDEV pOtherPciDev = NULL;
1423 PPDMDEVINS pPrevIns = pDevIns->Internal.s.pDevR3->pInstances;
1424 while (pPrevIns != pDevIns && pPrevIns)
1425 {
1426 pOtherPciDev = pPrevIns->Internal.s.pHeadPciDevR3;
1427 pPrevIns = pPrevIns->Internal.s.pNextR3;
1428 }
1429 Assert(pPrevIns == pDevIns);
1430 AssertLogRelMsgReturn(pOtherPciDev,
1431 ("'%s'/%d: Can't use PDMPCIDEVREG_DEV_NO_SAME_AS_PREV without a previously registered PCI device by the same or earlier PDM device instance!\n",
1432 pDevIns->pReg->szName, pDevIns->iInstance),
1433 VERR_WRONG_ORDER);
1434
1435 while (pOtherPciDev->Int.s.pNextR3)
1436 pOtherPciDev = pOtherPciDev->Int.s.pNextR3;
1437 uPciDevNo = pOtherPciDev->uDevFn >> 3;
1438 uDefPciBusNo = pOtherPciDev->Int.s.pPdmBusR3->iBus;
1439 }
1440 }
1441
1442 /*
1443 * Choose the PCI bus for the device.
1444 *
1445 * This is simple. If the device was configured for a particular bus, the PCIBusNo
1446 * configuration value will be set. If not the default bus is 0.
1447 */
1448 /** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIBusNo, uint8_t, 0, 7, 0}
1449 * Selects the PCI bus number of a device. The default value isn't necessarily
1450 * zero if the device is registered using PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, it
1451 * will then also inherit the bus number from the previously registered device.
1452 */
1453 uint8_t u8Bus;
1454 int rc = CFGMR3QueryU8Def(pCfg, "PCIBusNo", &u8Bus, (uint8_t)uDefPciBusNo);
1455 AssertLogRelMsgRCReturn(rc, ("Configuration error: PCIBusNo query failed with rc=%Rrc (%s/%d)\n",
1456 rc, pDevIns->pReg->szName, pDevIns->iInstance), rc);
1457 AssertLogRelMsgReturn(u8Bus < RT_ELEMENTS(pVM->pdm.s.aPciBuses),
1458 ("Configuration error: PCIBusNo=%d, max is %d. (%s/%d)\n", u8Bus,
1459 RT_ELEMENTS(pVM->pdm.s.aPciBuses), pDevIns->pReg->szName, pDevIns->iInstance),
1460 VERR_PDM_NO_PCI_BUS);
1461 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3 = &pVM->pdm.s.aPciBuses[u8Bus];
1462 if (pBus->pDevInsR3)
1463 {
1464 /*
1465 * Check the configuration for PCI device and function assignment.
1466 */
1467 /** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIDeviceNo, uint8_t, 0, 31}
1468 * Overrides the default PCI device number of a device.
1469 */
1470 uint8_t uCfgDevice;
1471 rc = CFGMR3QueryU8(pCfg, "PCIDeviceNo", &uCfgDevice);
1472 if (RT_SUCCESS(rc))
1473 {
1474 AssertMsgReturn(uCfgDevice <= 31,
1475 ("Configuration error: PCIDeviceNo=%d, max is 31. (%s/%d/%d)\n",
1476 uCfgDevice, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1477 VERR_PDM_BAD_PCI_CONFIG);
1478 uPciDevNo = uCfgDevice;
1479 }
1480 else
1481 AssertMsgReturn(rc == VERR_CFGM_VALUE_NOT_FOUND || rc == VERR_CFGM_NO_PARENT,
1482 ("Configuration error: PCIDeviceNo query failed with rc=%Rrc (%s/%d/%d)\n",
1483 rc, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1484 rc);
1485
1486 /** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIFunctionNo, uint8_t, 0, 7}
1487 * Overrides the default PCI function number of a device.
1488 */
1489 uint8_t uCfgFunction;
1490 rc = CFGMR3QueryU8(pCfg, "PCIFunctionNo", &uCfgFunction);
1491 if (RT_SUCCESS(rc))
1492 {
1493 AssertMsgReturn(uCfgFunction <= 7,
1494 ("Configuration error: PCIFunctionNo=%#x, max is 7. (%s/%d/%d)\n",
1495 uCfgFunction, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1496 VERR_PDM_BAD_PCI_CONFIG);
1497 uPciFunNo = uCfgFunction;
1498 }
1499 else
1500 AssertMsgReturn(rc == VERR_CFGM_VALUE_NOT_FOUND || rc == VERR_CFGM_NO_PARENT,
1501 ("Configuration error: PCIFunctionNo query failed with rc=%Rrc (%s/%d/%d)\n",
1502 rc, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1503 rc);
1504
1505
1506 /*
1507 * Initialize the internal data. We only do the wipe and the members
1508 * owned by PDM, the PCI bus does the rest in the registration call.
1509 */
1510 RT_ZERO(pPciDev->Int);
1511
1512 pPciDev->Int.s.idxDevCfg = idxDevCfg;
1513 pPciDev->Int.s.fReassignableDevNo = uPciDevNoRaw >= VBOX_PCI_MAX_DEVICES;
1514 pPciDev->Int.s.fReassignableFunNo = uPciFunNo >= VBOX_PCI_MAX_FUNCTIONS;
1515 pPciDev->Int.s.pDevInsR3 = pDevIns;
1516 pPciDev->Int.s.pPdmBusR3 = pBus;
1517 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1518 {
1519 pPciDev->Int.s.pDevInsR0 = MMHyperR3ToR0(pVM, pDevIns);
1520 pPciDev->Int.s.pPdmBusR0 = MMHyperR3ToR0(pVM, pBus);
1521 }
1522 else
1523 {
1524 pPciDev->Int.s.pDevInsR0 = NIL_RTR0PTR;
1525 pPciDev->Int.s.pPdmBusR0 = NIL_RTR0PTR;
1526 }
1527
1528 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1529 {
1530 pPciDev->Int.s.pDevInsRC = MMHyperR3ToRC(pVM, pDevIns);
1531 pPciDev->Int.s.pPdmBusRC = MMHyperR3ToRC(pVM, pBus);
1532 }
1533 else
1534 {
1535 pPciDev->Int.s.pDevInsRC = NIL_RTRCPTR;
1536 pPciDev->Int.s.pPdmBusRC = NIL_RTRCPTR;
1537 }
1538
1539 /* Set some of the public members too. */
1540 pPciDev->pszNameR3 = pszName;
1541
1542 /*
1543 * Call the pci bus device to do the actual registration.
1544 */
1545 pdmLock(pVM);
1546 rc = pBus->pfnRegisterR3(pBus->pDevInsR3, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
1547 pdmUnlock(pVM);
1548 if (RT_SUCCESS(rc))
1549 {
1550
1551 /*
1552 * Link it.
1553 */
1554 if (pPrevPciDev)
1555 {
1556 Assert(!pPrevPciDev->Int.s.pNextR3);
1557 pPrevPciDev->Int.s.pNextR3 = pPciDev;
1558 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1559 pPrevPciDev->Int.s.pNextR0 = MMHyperR3ToR0(pVM, pPciDev);
1560 else
1561 pPrevPciDev->Int.s.pNextR0 = NIL_RTR0PTR;
1562 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1563 pPrevPciDev->Int.s.pNextRC = MMHyperR3ToRC(pVM, pPciDev);
1564 else
1565 pPrevPciDev->Int.s.pNextRC = NIL_RTRCPTR;
1566 }
1567 else
1568 {
1569 Assert(!pDevIns->Internal.s.pHeadPciDevR3);
1570 pDevIns->Internal.s.pHeadPciDevR3 = pPciDev;
1571 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1572 pDevIns->Internal.s.pHeadPciDevR0 = MMHyperR3ToR0(pVM, pPciDev);
1573 else
1574 pDevIns->Internal.s.pHeadPciDevR0 = NIL_RTR0PTR;
1575 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1576 pDevIns->Internal.s.pHeadPciDevRC = MMHyperR3ToRC(pVM, pPciDev);
1577 else
1578 pDevIns->Internal.s.pHeadPciDevRC = NIL_RTRCPTR;
1579 }
1580
1581 Log(("PDM: Registered device '%s'/%d as PCI device %d on bus %d\n",
1582 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev->uDevFn, pBus->iBus));
1583 }
1584 }
1585 else
1586 {
1587 AssertLogRelMsgFailed(("Configuration error: No PCI bus available. This could be related to init order too!\n"));
1588 rc = VERR_PDM_NO_PCI_BUS;
1589 }
1590
1591 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1592 return rc;
1593}
1594
1595
1596/** @interface_method_impl{PDMDEVHLPR3,pfnPCIRegisterMsi} */
1597static DECLCALLBACK(int) pdmR3DevHlp_PCIRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
1598{
1599 PDMDEV_ASSERT_DEVINS(pDevIns);
1600 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1601 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1602 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1603 LogFlow(("pdmR3DevHlp_PCIRegisterMsi: caller='%s'/%d: pPciDev=%p:{%#x} pMsgReg=%p:{cMsiVectors=%d, cMsixVectors=%d}\n",
1604 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, pMsiReg, pMsiReg->cMsiVectors, pMsiReg->cMsixVectors));
1605
1606 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3; Assert(pBus);
1607 PVM pVM = pDevIns->Internal.s.pVMR3;
1608 pdmLock(pVM);
1609 int rc;
1610 if (pBus->pfnRegisterMsiR3)
1611 rc = pBus->pfnRegisterMsiR3(pBus->pDevInsR3, pPciDev, pMsiReg);
1612 else
1613 rc = VERR_NOT_IMPLEMENTED;
1614 pdmUnlock(pVM);
1615
1616 LogFlow(("pdmR3DevHlp_PCIRegisterMsi: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1617 return rc;
1618}
1619
1620
1621/** @interface_method_impl{PDMDEVHLPR3,pfnPCIIORegionRegister} */
1622static DECLCALLBACK(int) pdmR3DevHlp_PCIIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
1623 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1624{
1625 PDMDEV_ASSERT_DEVINS(pDevIns);
1626 PVM pVM = pDevIns->Internal.s.pVMR3;
1627 VM_ASSERT_EMT(pVM);
1628 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1629 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1630 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1631 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%d cbRegion=%RGp enmType=%d pfnCallback=%p\n",
1632 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iRegion, cbRegion, enmType, pfnCallback));
1633
1634 /*
1635 * Validate input.
1636 */
1637 if (iRegion >= VBOX_PCI_NUM_REGIONS)
1638 {
1639 Assert(iRegion < VBOX_PCI_NUM_REGIONS);
1640 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (iRegion)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1641 return VERR_INVALID_PARAMETER;
1642 }
1643
1644 switch ((int)enmType)
1645 {
1646 case PCI_ADDRESS_SPACE_IO:
1647 /*
1648 * Sanity check: don't allow to register more than 32K of the PCI I/O space.
1649 */
1650 AssertLogRelMsgReturn(cbRegion <= _32K,
1651 ("caller='%s'/%d: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cbRegion),
1652 VERR_INVALID_PARAMETER);
1653 break;
1654
1655 case PCI_ADDRESS_SPACE_MEM:
1656 case PCI_ADDRESS_SPACE_MEM_PREFETCH:
1657 /*
1658 * Sanity check: Don't allow to register more than 2GB of the PCI MMIO space.
1659 */
1660 AssertLogRelMsgReturn(cbRegion <= MM_MMIO_32_MAX,
1661 ("caller='%s'/%d: %RGp (max %RGp)\n",
1662 pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, (RTGCPHYS)MM_MMIO_32_MAX),
1663 VERR_OUT_OF_RANGE);
1664 break;
1665
1666 case PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_MEM:
1667 case PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_MEM_PREFETCH:
1668 /*
1669 * Sanity check: Don't allow to register more than 64GB of the 64-bit PCI MMIO space.
1670 */
1671 AssertLogRelMsgReturn(cbRegion <= MM_MMIO_64_MAX,
1672 ("caller='%s'/%d: %RGp (max %RGp)\n",
1673 pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, MM_MMIO_64_MAX),
1674 VERR_OUT_OF_RANGE);
1675 break;
1676
1677 default:
1678 AssertMsgFailed(("enmType=%#x is unknown\n", enmType));
1679 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (enmType)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1680 return VERR_INVALID_PARAMETER;
1681 }
1682 if (!pfnCallback)
1683 {
1684 Assert(pfnCallback);
1685 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (callback)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1686 return VERR_INVALID_PARAMETER;
1687 }
1688 AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
1689
1690 /*
1691 * We're currently restricted to page aligned MMIO regions.
1692 */
1693 if ( ((enmType & ~(PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_MEM_PREFETCH)) == PCI_ADDRESS_SPACE_MEM)
1694 && cbRegion != RT_ALIGN_64(cbRegion, PAGE_SIZE))
1695 {
1696 Log(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: aligning cbRegion %RGp -> %RGp\n",
1697 pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, RT_ALIGN_64(cbRegion, PAGE_SIZE)));
1698 cbRegion = RT_ALIGN_64(cbRegion, PAGE_SIZE);
1699 }
1700
1701 /*
1702 * For registering PCI MMIO memory or PCI I/O memory, the size of the region must be a power of 2!
1703 */
1704 int iLastSet = ASMBitLastSetU64(cbRegion);
1705 Assert(iLastSet > 0);
1706 uint64_t cbRegionAligned = RT_BIT_64(iLastSet - 1);
1707 if (cbRegion > cbRegionAligned)
1708 cbRegion = cbRegionAligned * 2; /* round up */
1709
1710 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
1711 Assert(pBus);
1712 pdmLock(pVM);
1713 int rc = pBus->pfnIORegionRegisterR3(pBus->pDevInsR3, pPciDev, iRegion, cbRegion, enmType, pfnCallback);
1714 pdmUnlock(pVM);
1715
1716 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1717 return rc;
1718}
1719
1720
1721/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetConfigCallbacks} */
1722static DECLCALLBACK(void) pdmR3DevHlp_PCISetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1723 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1724{
1725 PDMDEV_ASSERT_DEVINS(pDevIns);
1726 PVM pVM = pDevIns->Internal.s.pVMR3;
1727 VM_ASSERT_EMT(pVM);
1728 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1729 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1730 AssertReturnVoid(pPciDev);
1731 LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: pPciDev=%p pfnRead=%p ppfnReadOld=%p pfnWrite=%p ppfnWriteOld=%p\n",
1732 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld));
1733
1734 /*
1735 * Validate input and resolve defaults.
1736 */
1737 AssertPtr(pfnRead);
1738 AssertPtr(pfnWrite);
1739 AssertPtrNull(ppfnReadOld);
1740 AssertPtrNull(ppfnWriteOld);
1741 AssertPtrNull(pPciDev);
1742
1743 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
1744 AssertRelease(pBus);
1745 AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
1746
1747 /*
1748 * Do the job.
1749 */
1750 pdmLock(pVM);
1751 pBus->pfnSetConfigCallbacksR3(pBus->pDevInsR3, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld);
1752 pdmUnlock(pVM);
1753
1754 LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1755}
1756
1757
1758/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysRead} */
1759static DECLCALLBACK(int)
1760pdmR3DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
1761{
1762 PDMDEV_ASSERT_DEVINS(pDevIns);
1763 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1764 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1765 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1766
1767#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
1768 /*
1769 * Just check the busmaster setting here and forward the request to the generic read helper.
1770 */
1771 if (PCIDevIsBusmaster(pPciDev))
1772 { /* likely */ }
1773 else
1774 {
1775 Log(("pdmR3DevHlp_PCIPhysRead: caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
1776 pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
1777 memset(pvBuf, 0xff, cbRead);
1778 return VERR_PDM_NOT_PCI_BUS_MASTER;
1779 }
1780#endif
1781
1782 return pDevIns->pHlpR3->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
1783}
1784
1785
1786/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysWrite} */
1787static DECLCALLBACK(int)
1788pdmR3DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
1789{
1790 PDMDEV_ASSERT_DEVINS(pDevIns);
1791 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1792 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1793 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1794
1795#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
1796 /*
1797 * Just check the busmaster setting here and forward the request to the generic read helper.
1798 */
1799 if (PCIDevIsBusmaster(pPciDev))
1800 { /* likely */ }
1801 else
1802 {
1803 Log(("pdmR3DevHlp_PCIPhysWrite: caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
1804 pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
1805 return VERR_PDM_NOT_PCI_BUS_MASTER;
1806 }
1807#endif
1808
1809 return pDevIns->pHlpR3->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
1810}
1811
1812
1813/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrq} */
1814static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
1815{
1816 PDMDEV_ASSERT_DEVINS(pDevIns);
1817 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1818 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1819 AssertReturnVoid(pPciDev);
1820 LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
1821 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
1822
1823 /*
1824 * Validate input.
1825 */
1826 Assert(iIrq == 0);
1827 Assert((uint32_t)iLevel <= PDM_IRQ_LEVEL_FLIP_FLOP);
1828
1829 /*
1830 * Must have a PCI device registered!
1831 */
1832 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
1833 Assert(pBus);
1834 PVM pVM = pDevIns->Internal.s.pVMR3;
1835
1836 pdmLock(pVM);
1837 uint32_t uTagSrc;
1838 if (iLevel & PDM_IRQ_LEVEL_HIGH)
1839 {
1840 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
1841 if (iLevel == PDM_IRQ_LEVEL_HIGH)
1842 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1843 else
1844 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1845 }
1846 else
1847 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
1848
1849 pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, iIrq, iLevel, uTagSrc);
1850
1851 if (iLevel == PDM_IRQ_LEVEL_LOW)
1852 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1853 pdmUnlock(pVM);
1854
1855 LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1856}
1857
1858
1859/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrqNoWait} */
1860static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
1861{
1862 pdmR3DevHlp_PCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
1863}
1864
1865
1866/** @interface_method_impl{PDMDEVHLPR3,pfnISASetIrq} */
1867static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
1868{
1869 PDMDEV_ASSERT_DEVINS(pDevIns);
1870 LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
1871
1872 /*
1873 * Validate input.
1874 */
1875 Assert(iIrq < 16);
1876 Assert((uint32_t)iLevel <= PDM_IRQ_LEVEL_FLIP_FLOP);
1877
1878 PVM pVM = pDevIns->Internal.s.pVMR3;
1879
1880 /*
1881 * Do the job.
1882 */
1883 pdmLock(pVM);
1884 uint32_t uTagSrc;
1885 if (iLevel & PDM_IRQ_LEVEL_HIGH)
1886 {
1887 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
1888 if (iLevel == PDM_IRQ_LEVEL_HIGH)
1889 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1890 else
1891 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1892 }
1893 else
1894 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
1895
1896 PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
1897
1898 if (iLevel == PDM_IRQ_LEVEL_LOW)
1899 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1900 pdmUnlock(pVM);
1901
1902 LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1903}
1904
1905
1906/** @interface_method_impl{PDMDEVHLPR3,pfnISASetIrqNoWait} */
1907static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
1908{
1909 pdmR3DevHlp_ISASetIrq(pDevIns, iIrq, iLevel);
1910}
1911
1912
1913/** @interface_method_impl{PDMDEVHLPR3,pfnIoApicSendMsi} */
1914static DECLCALLBACK(void) pdmR3DevHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue)
1915{
1916 PDMDEV_ASSERT_DEVINS(pDevIns);
1917 LogFlow(("pdmR3DevHlp_IoApicSendMsi: caller='%s'/%d: GCPhys=%RGp uValue=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, uValue));
1918
1919 /*
1920 * Validate input.
1921 */
1922 Assert(GCPhys != 0);
1923 Assert(uValue != 0);
1924
1925 PVM pVM = pDevIns->Internal.s.pVMR3;
1926
1927 /*
1928 * Do the job.
1929 */
1930 pdmLock(pVM);
1931 uint32_t uTagSrc;
1932 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
1933 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1934
1935 PDMIoApicSendMsi(pVM, GCPhys, uValue, uTagSrc); /* (The API takes the lock recursively.) */
1936
1937 pdmUnlock(pVM);
1938
1939 LogFlow(("pdmR3DevHlp_IoApicSendMsi: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1940}
1941
1942
1943/** @interface_method_impl{PDMDEVHLPR3,pfnDriverAttach} */
1944static DECLCALLBACK(int) pdmR3DevHlp_DriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE *ppBaseInterface, const char *pszDesc)
1945{
1946 PDMDEV_ASSERT_DEVINS(pDevIns);
1947 PVM pVM = pDevIns->Internal.s.pVMR3;
1948 VM_ASSERT_EMT(pVM);
1949 LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: iLun=%d pBaseInterface=%p ppBaseInterface=%p pszDesc=%p:{%s}\n",
1950 pDevIns->pReg->szName, pDevIns->iInstance, iLun, pBaseInterface, ppBaseInterface, pszDesc, pszDesc));
1951
1952 /*
1953 * Lookup the LUN, it might already be registered.
1954 */
1955 PPDMLUN pLunPrev = NULL;
1956 PPDMLUN pLun = pDevIns->Internal.s.pLunsR3;
1957 for (; pLun; pLunPrev = pLun, pLun = pLun->pNext)
1958 if (pLun->iLun == iLun)
1959 break;
1960
1961 /*
1962 * Create the LUN if if wasn't found, else check if driver is already attached to it.
1963 */
1964 if (!pLun)
1965 {
1966 if ( !pBaseInterface
1967 || !pszDesc
1968 || !*pszDesc)
1969 {
1970 Assert(pBaseInterface);
1971 Assert(pszDesc || *pszDesc);
1972 return VERR_INVALID_PARAMETER;
1973 }
1974
1975 pLun = (PPDMLUN)MMR3HeapAlloc(pVM, MM_TAG_PDM_LUN, sizeof(*pLun));
1976 if (!pLun)
1977 return VERR_NO_MEMORY;
1978
1979 pLun->iLun = iLun;
1980 pLun->pNext = pLunPrev ? pLunPrev->pNext : NULL;
1981 pLun->pTop = NULL;
1982 pLun->pBottom = NULL;
1983 pLun->pDevIns = pDevIns;
1984 pLun->pUsbIns = NULL;
1985 pLun->pszDesc = pszDesc;
1986 pLun->pBase = pBaseInterface;
1987 if (!pLunPrev)
1988 pDevIns->Internal.s.pLunsR3 = pLun;
1989 else
1990 pLunPrev->pNext = pLun;
1991 Log(("pdmR3DevHlp_DriverAttach: Registered LUN#%d '%s' with device '%s'/%d.\n",
1992 iLun, pszDesc, pDevIns->pReg->szName, pDevIns->iInstance));
1993 }
1994 else if (pLun->pTop)
1995 {
1996 AssertMsgFailed(("Already attached! The device should keep track of such things!\n"));
1997 LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_DRIVER_ALREADY_ATTACHED));
1998 return VERR_PDM_DRIVER_ALREADY_ATTACHED;
1999 }
2000 Assert(pLun->pBase == pBaseInterface);
2001
2002
2003 /*
2004 * Get the attached driver configuration.
2005 */
2006 int rc;
2007 PCFGMNODE pNode = CFGMR3GetChildF(pDevIns->Internal.s.pCfgHandle, "LUN#%u", iLun);
2008 if (pNode)
2009 rc = pdmR3DrvInstantiate(pVM, pNode, pBaseInterface, NULL /*pDrvAbove*/, pLun, ppBaseInterface);
2010 else
2011 rc = VERR_PDM_NO_ATTACHED_DRIVER;
2012
2013 LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2014 return rc;
2015}
2016
2017
2018/** @interface_method_impl{PDMDEVHLPR3,pfnDriverDetach} */
2019static DECLCALLBACK(int) pdmR3DevHlp_DriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
2020{
2021 PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
2022 LogFlow(("pdmR3DevHlp_DriverDetach: caller='%s'/%d: pDrvIns=%p\n",
2023 pDevIns->pReg->szName, pDevIns->iInstance, pDrvIns));
2024
2025#ifdef VBOX_STRICT
2026 PVM pVM = pDevIns->Internal.s.pVMR3;
2027 VM_ASSERT_EMT(pVM);
2028#endif
2029
2030 int rc = pdmR3DrvDetach(pDrvIns, fFlags);
2031
2032 LogFlow(("pdmR3DevHlp_DriverDetach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2033 return rc;
2034}
2035
2036
2037/** @interface_method_impl{PDMDEVHLPR3,pfnQueueCreate} */
2038static DECLCALLBACK(int) pdmR3DevHlp_QueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
2039 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName, PPDMQUEUE *ppQueue)
2040{
2041 PDMDEV_ASSERT_DEVINS(pDevIns);
2042 LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: cbItem=%#x cItems=%#x cMilliesInterval=%u pfnCallback=%p fRZEnabled=%RTbool pszName=%p:{%s} ppQueue=%p\n",
2043 pDevIns->pReg->szName, pDevIns->iInstance, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, pszName, ppQueue));
2044
2045 PVM pVM = pDevIns->Internal.s.pVMR3;
2046 VM_ASSERT_EMT(pVM);
2047
2048 if (pDevIns->iInstance > 0)
2049 {
2050 pszName = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s_%u", pszName, pDevIns->iInstance);
2051 AssertLogRelReturn(pszName, VERR_NO_MEMORY);
2052 }
2053
2054 int rc = PDMR3QueueCreateDevice(pVM, pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
2055
2056 LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: returns %Rrc *ppQueue=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppQueue));
2057 return rc;
2058}
2059
2060
2061/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectInit} */
2062static DECLCALLBACK(int) pdmR3DevHlp_CritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
2063 const char *pszNameFmt, va_list va)
2064{
2065 PDMDEV_ASSERT_DEVINS(pDevIns);
2066 LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: pCritSect=%p pszNameFmt=%p:{%s}\n",
2067 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pszNameFmt, pszNameFmt));
2068
2069 PVM pVM = pDevIns->Internal.s.pVMR3;
2070 VM_ASSERT_EMT(pVM);
2071 int rc = pdmR3CritSectInitDevice(pVM, pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
2072
2073 LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2074 return rc;
2075}
2076
2077
2078/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNop} */
2079static DECLCALLBACK(PPDMCRITSECT) pdmR3DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
2080{
2081 PDMDEV_ASSERT_DEVINS(pDevIns);
2082 PVM pVM = pDevIns->Internal.s.pVMR3;
2083 VM_ASSERT_EMT(pVM);
2084
2085 PPDMCRITSECT pCritSect = PDMR3CritSectGetNop(pVM);
2086 LogFlow(("pdmR3DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n",
2087 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
2088 return pCritSect;
2089}
2090
2091
2092/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNopR0} */
2093static DECLCALLBACK(R0PTRTYPE(PPDMCRITSECT)) pdmR3DevHlp_CritSectGetNopR0(PPDMDEVINS pDevIns)
2094{
2095 PDMDEV_ASSERT_DEVINS(pDevIns);
2096 PVM pVM = pDevIns->Internal.s.pVMR3;
2097 VM_ASSERT_EMT(pVM);
2098
2099 R0PTRTYPE(PPDMCRITSECT) pCritSect = PDMR3CritSectGetNopR0(pVM);
2100 LogFlow(("pdmR3DevHlp_CritSectGetNopR0: caller='%s'/%d: return %RHv\n",
2101 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
2102 return pCritSect;
2103}
2104
2105
2106/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNopRC} */
2107static DECLCALLBACK(RCPTRTYPE(PPDMCRITSECT)) pdmR3DevHlp_CritSectGetNopRC(PPDMDEVINS pDevIns)
2108{
2109 PDMDEV_ASSERT_DEVINS(pDevIns);
2110 PVM pVM = pDevIns->Internal.s.pVMR3;
2111 VM_ASSERT_EMT(pVM);
2112
2113 RCPTRTYPE(PPDMCRITSECT) pCritSect = PDMR3CritSectGetNopRC(pVM);
2114 LogFlow(("pdmR3DevHlp_CritSectGetNopRC: caller='%s'/%d: return %RRv\n",
2115 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
2116 return pCritSect;
2117}
2118
2119
2120/** @interface_method_impl{PDMDEVHLPR3,pfnSetDeviceCritSect} */
2121static DECLCALLBACK(int) pdmR3DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
2122{
2123 /*
2124 * Validate input.
2125 *
2126 * Note! We only allow the automatically created default critical section
2127 * to be replaced by this API.
2128 */
2129 PDMDEV_ASSERT_DEVINS(pDevIns);
2130 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
2131 LogFlow(("pdmR3DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
2132 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
2133 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
2134 PVM pVM = pDevIns->Internal.s.pVMR3;
2135 AssertReturn(pCritSect->s.pVMR3 == pVM, VERR_INVALID_PARAMETER);
2136
2137 VM_ASSERT_EMT(pVM);
2138 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
2139
2140 AssertReturn(pDevIns->pCritSectRoR3, VERR_PDM_DEV_IPE_1);
2141 AssertReturn(pDevIns->pCritSectRoR3->s.fAutomaticDefaultCritsect, VERR_WRONG_ORDER);
2142 AssertReturn(!pDevIns->pCritSectRoR3->s.fUsedByTimerOrSimilar, VERR_WRONG_ORDER);
2143 AssertReturn(pDevIns->pCritSectRoR3 != pCritSect, VERR_INVALID_PARAMETER);
2144
2145 /*
2146 * Replace the critical section and destroy the automatic default section.
2147 */
2148 PPDMCRITSECT pOldCritSect = pDevIns->pCritSectRoR3;
2149 pDevIns->pCritSectRoR3 = pCritSect;
2150 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
2151 pDevIns->pCritSectRoR0 = MMHyperCCToR0(pVM, pDevIns->pCritSectRoR3);
2152 else
2153 Assert(pDevIns->pCritSectRoR0 == NIL_RTRCPTR);
2154
2155 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
2156 pDevIns->pCritSectRoRC = MMHyperCCToRC(pVM, pDevIns->pCritSectRoR3);
2157 else
2158 Assert(pDevIns->pCritSectRoRC == NIL_RTRCPTR);
2159
2160 PDMR3CritSectDelete(pOldCritSect);
2161 if (pDevIns->pReg->fFlags & (PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0))
2162 MMHyperFree(pVM, pOldCritSect);
2163 else
2164 MMR3HeapFree(pOldCritSect);
2165
2166 LogFlow(("pdmR3DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2167 return VINF_SUCCESS;
2168}
2169
2170
2171/** @interface_method_impl{PDMDEVHLPR3,pfnThreadCreate} */
2172static DECLCALLBACK(int) pdmR3DevHlp_ThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
2173 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
2174{
2175 PDMDEV_ASSERT_DEVINS(pDevIns);
2176 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2177 LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: ppThread=%p pvUser=%p pfnThread=%p pfnWakeup=%p cbStack=%#zx enmType=%d pszName=%p:{%s}\n",
2178 pDevIns->pReg->szName, pDevIns->iInstance, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName, pszName));
2179
2180 int rc = pdmR3ThreadCreateDevice(pDevIns->Internal.s.pVMR3, pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
2181
2182 LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: returns %Rrc *ppThread=%RTthrd\n", pDevIns->pReg->szName, pDevIns->iInstance,
2183 rc, *ppThread));
2184 return rc;
2185}
2186
2187
2188/** @interface_method_impl{PDMDEVHLPR3,pfnSetAsyncNotification} */
2189static DECLCALLBACK(int) pdmR3DevHlp_SetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
2190{
2191 PDMDEV_ASSERT_DEVINS(pDevIns);
2192 VM_ASSERT_EMT0(pDevIns->Internal.s.pVMR3);
2193 LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: pfnAsyncNotify=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pfnAsyncNotify));
2194
2195 int rc = VINF_SUCCESS;
2196 AssertStmt(pfnAsyncNotify, rc = VERR_INVALID_PARAMETER);
2197 AssertStmt(!pDevIns->Internal.s.pfnAsyncNotify, rc = VERR_WRONG_ORDER);
2198 AssertStmt(pDevIns->Internal.s.fIntFlags & (PDMDEVINSINT_FLAGS_SUSPENDED | PDMDEVINSINT_FLAGS_RESET), rc = VERR_WRONG_ORDER);
2199 VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3);
2200 AssertStmt( enmVMState == VMSTATE_SUSPENDING
2201 || enmVMState == VMSTATE_SUSPENDING_EXT_LS
2202 || enmVMState == VMSTATE_SUSPENDING_LS
2203 || enmVMState == VMSTATE_RESETTING
2204 || enmVMState == VMSTATE_RESETTING_LS
2205 || enmVMState == VMSTATE_POWERING_OFF
2206 || enmVMState == VMSTATE_POWERING_OFF_LS,
2207 rc = VERR_INVALID_STATE);
2208
2209 if (RT_SUCCESS(rc))
2210 pDevIns->Internal.s.pfnAsyncNotify = pfnAsyncNotify;
2211
2212 LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2213 return rc;
2214}
2215
2216
2217/** @interface_method_impl{PDMDEVHLPR3,pfnAsyncNotificationCompleted} */
2218static DECLCALLBACK(void) pdmR3DevHlp_AsyncNotificationCompleted(PPDMDEVINS pDevIns)
2219{
2220 PDMDEV_ASSERT_DEVINS(pDevIns);
2221 PVM pVM = pDevIns->Internal.s.pVMR3;
2222
2223 VMSTATE enmVMState = VMR3GetState(pVM);
2224 if ( enmVMState == VMSTATE_SUSPENDING
2225 || enmVMState == VMSTATE_SUSPENDING_EXT_LS
2226 || enmVMState == VMSTATE_SUSPENDING_LS
2227 || enmVMState == VMSTATE_RESETTING
2228 || enmVMState == VMSTATE_RESETTING_LS
2229 || enmVMState == VMSTATE_POWERING_OFF
2230 || enmVMState == VMSTATE_POWERING_OFF_LS)
2231 {
2232 LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
2233 VMR3AsyncPdmNotificationWakeupU(pVM->pUVM);
2234 }
2235 else
2236 LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d: enmVMState=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, enmVMState));
2237}
2238
2239
2240/** @interface_method_impl{PDMDEVHLPR3,pfnRTCRegister} */
2241static DECLCALLBACK(int) pdmR3DevHlp_RTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
2242{
2243 PDMDEV_ASSERT_DEVINS(pDevIns);
2244 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2245 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: pRtcReg=%p:{.u32Version=%#x, .pfnWrite=%p, .pfnRead=%p} ppRtcHlp=%p\n",
2246 pDevIns->pReg->szName, pDevIns->iInstance, pRtcReg, pRtcReg->u32Version, pRtcReg->pfnWrite,
2247 pRtcReg->pfnWrite, ppRtcHlp));
2248
2249 /*
2250 * Validate input.
2251 */
2252 if (pRtcReg->u32Version != PDM_RTCREG_VERSION)
2253 {
2254 AssertMsgFailed(("u32Version=%#x expected %#x\n", pRtcReg->u32Version,
2255 PDM_RTCREG_VERSION));
2256 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (version)\n",
2257 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2258 return VERR_INVALID_PARAMETER;
2259 }
2260 if ( !pRtcReg->pfnWrite
2261 || !pRtcReg->pfnRead)
2262 {
2263 Assert(pRtcReg->pfnWrite);
2264 Assert(pRtcReg->pfnRead);
2265 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
2266 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2267 return VERR_INVALID_PARAMETER;
2268 }
2269
2270 if (!ppRtcHlp)
2271 {
2272 Assert(ppRtcHlp);
2273 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (ppRtcHlp)\n",
2274 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2275 return VERR_INVALID_PARAMETER;
2276 }
2277
2278 /*
2279 * Only one DMA device.
2280 */
2281 PVM pVM = pDevIns->Internal.s.pVMR3;
2282 if (pVM->pdm.s.pRtc)
2283 {
2284 AssertMsgFailed(("Only one RTC device is supported!\n"));
2285 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",
2286 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2287 return VERR_INVALID_PARAMETER;
2288 }
2289
2290 /*
2291 * Allocate and initialize pci bus structure.
2292 */
2293 int rc = VINF_SUCCESS;
2294 PPDMRTC pRtc = (PPDMRTC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pRtc));
2295 if (pRtc)
2296 {
2297 pRtc->pDevIns = pDevIns;
2298 pRtc->Reg = *pRtcReg;
2299 pVM->pdm.s.pRtc = pRtc;
2300
2301 /* set the helper pointer. */
2302 *ppRtcHlp = &g_pdmR3DevRtcHlp;
2303 Log(("PDM: Registered RTC device '%s'/%d pDevIns=%p\n",
2304 pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2305 }
2306 else
2307 rc = VERR_NO_MEMORY;
2308
2309 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",
2310 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2311 return rc;
2312}
2313
2314
2315/** @interface_method_impl{PDMDEVHLPR3,pfnDMARegister} */
2316static DECLCALLBACK(int) pdmR3DevHlp_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
2317{
2318 PDMDEV_ASSERT_DEVINS(pDevIns);
2319 PVM pVM = pDevIns->Internal.s.pVMR3;
2320 VM_ASSERT_EMT(pVM);
2321 LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: uChannel=%d pfnTransferHandler=%p pvUser=%p\n",
2322 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pfnTransferHandler, pvUser));
2323 int rc = VINF_SUCCESS;
2324 if (pVM->pdm.s.pDmac)
2325 pVM->pdm.s.pDmac->Reg.pfnRegister(pVM->pdm.s.pDmac->pDevIns, uChannel, pfnTransferHandler, pvUser);
2326 else
2327 {
2328 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2329 rc = VERR_PDM_NO_DMAC_INSTANCE;
2330 }
2331 LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: returns %Rrc\n",
2332 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2333 return rc;
2334}
2335
2336
2337/** @interface_method_impl{PDMDEVHLPR3,pfnDMAReadMemory} */
2338static DECLCALLBACK(int) pdmR3DevHlp_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead)
2339{
2340 PDMDEV_ASSERT_DEVINS(pDevIns);
2341 PVM pVM = pDevIns->Internal.s.pVMR3;
2342 VM_ASSERT_EMT(pVM);
2343 LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbRead=%p\n",
2344 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbRead));
2345 int rc = VINF_SUCCESS;
2346 if (pVM->pdm.s.pDmac)
2347 {
2348 uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnReadMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
2349 if (pcbRead)
2350 *pcbRead = cb;
2351 }
2352 else
2353 {
2354 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2355 rc = VERR_PDM_NO_DMAC_INSTANCE;
2356 }
2357 LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: returns %Rrc\n",
2358 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2359 return rc;
2360}
2361
2362
2363/** @interface_method_impl{PDMDEVHLPR3,pfnDMAWriteMemory} */
2364static DECLCALLBACK(int) pdmR3DevHlp_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten)
2365{
2366 PDMDEV_ASSERT_DEVINS(pDevIns);
2367 PVM pVM = pDevIns->Internal.s.pVMR3;
2368 VM_ASSERT_EMT(pVM);
2369 LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbWritten=%p\n",
2370 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbWritten));
2371 int rc = VINF_SUCCESS;
2372 if (pVM->pdm.s.pDmac)
2373 {
2374 uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnWriteMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
2375 if (pcbWritten)
2376 *pcbWritten = cb;
2377 }
2378 else
2379 {
2380 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2381 rc = VERR_PDM_NO_DMAC_INSTANCE;
2382 }
2383 LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: returns %Rrc\n",
2384 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2385 return rc;
2386}
2387
2388
2389/** @interface_method_impl{PDMDEVHLPR3,pfnDMASetDREQ} */
2390static DECLCALLBACK(int) pdmR3DevHlp_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
2391{
2392 PDMDEV_ASSERT_DEVINS(pDevIns);
2393 PVM pVM = pDevIns->Internal.s.pVMR3;
2394 VM_ASSERT_EMT(pVM);
2395 LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: uChannel=%d uLevel=%d\n",
2396 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, uLevel));
2397 int rc = VINF_SUCCESS;
2398 if (pVM->pdm.s.pDmac)
2399 pVM->pdm.s.pDmac->Reg.pfnSetDREQ(pVM->pdm.s.pDmac->pDevIns, uChannel, uLevel);
2400 else
2401 {
2402 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2403 rc = VERR_PDM_NO_DMAC_INSTANCE;
2404 }
2405 LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: returns %Rrc\n",
2406 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2407 return rc;
2408}
2409
2410/** @interface_method_impl{PDMDEVHLPR3,pfnDMAGetChannelMode} */
2411static DECLCALLBACK(uint8_t) pdmR3DevHlp_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
2412{
2413 PDMDEV_ASSERT_DEVINS(pDevIns);
2414 PVM pVM = pDevIns->Internal.s.pVMR3;
2415 VM_ASSERT_EMT(pVM);
2416 LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: uChannel=%d\n",
2417 pDevIns->pReg->szName, pDevIns->iInstance, uChannel));
2418 uint8_t u8Mode;
2419 if (pVM->pdm.s.pDmac)
2420 u8Mode = pVM->pdm.s.pDmac->Reg.pfnGetChannelMode(pVM->pdm.s.pDmac->pDevIns, uChannel);
2421 else
2422 {
2423 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2424 u8Mode = 3 << 2 /* illegal mode type */;
2425 }
2426 LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: returns %#04x\n",
2427 pDevIns->pReg->szName, pDevIns->iInstance, u8Mode));
2428 return u8Mode;
2429}
2430
2431/** @interface_method_impl{PDMDEVHLPR3,pfnDMASchedule} */
2432static DECLCALLBACK(void) pdmR3DevHlp_DMASchedule(PPDMDEVINS pDevIns)
2433{
2434 PDMDEV_ASSERT_DEVINS(pDevIns);
2435 PVM pVM = pDevIns->Internal.s.pVMR3;
2436 VM_ASSERT_EMT(pVM);
2437 LogFlow(("pdmR3DevHlp_DMASchedule: caller='%s'/%d: VM_FF_PDM_DMA %d -> 1\n",
2438 pDevIns->pReg->szName, pDevIns->iInstance, VM_FF_IS_SET(pVM, VM_FF_PDM_DMA)));
2439
2440 AssertMsg(pVM->pdm.s.pDmac, ("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2441 VM_FF_SET(pVM, VM_FF_PDM_DMA);
2442#ifdef VBOX_WITH_REM
2443 REMR3NotifyDmaPending(pVM);
2444#endif
2445 VMR3NotifyGlobalFFU(pVM->pUVM, VMNOTIFYFF_FLAGS_DONE_REM);
2446}
2447
2448
2449/** @interface_method_impl{PDMDEVHLPR3,pfnCMOSWrite} */
2450static DECLCALLBACK(int) pdmR3DevHlp_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
2451{
2452 PDMDEV_ASSERT_DEVINS(pDevIns);
2453 PVM pVM = pDevIns->Internal.s.pVMR3;
2454 VM_ASSERT_EMT(pVM);
2455
2456 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x u8Value=%#04x\n",
2457 pDevIns->pReg->szName, pDevIns->iInstance, iReg, u8Value));
2458 int rc;
2459 if (pVM->pdm.s.pRtc)
2460 {
2461 PPDMDEVINS pDevInsRtc = pVM->pdm.s.pRtc->pDevIns;
2462 rc = PDMCritSectEnter(pDevInsRtc->pCritSectRoR3, VERR_IGNORED);
2463 if (RT_SUCCESS(rc))
2464 {
2465 rc = pVM->pdm.s.pRtc->Reg.pfnWrite(pDevInsRtc, iReg, u8Value);
2466 PDMCritSectLeave(pDevInsRtc->pCritSectRoR3);
2467 }
2468 }
2469 else
2470 rc = VERR_PDM_NO_RTC_INSTANCE;
2471
2472 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
2473 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2474 return rc;
2475}
2476
2477
2478/** @interface_method_impl{PDMDEVHLPR3,pfnCMOSRead} */
2479static DECLCALLBACK(int) pdmR3DevHlp_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
2480{
2481 PDMDEV_ASSERT_DEVINS(pDevIns);
2482 PVM pVM = pDevIns->Internal.s.pVMR3;
2483 VM_ASSERT_EMT(pVM);
2484
2485 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x pu8Value=%p\n",
2486 pDevIns->pReg->szName, pDevIns->iInstance, iReg, pu8Value));
2487 int rc;
2488 if (pVM->pdm.s.pRtc)
2489 {
2490 PPDMDEVINS pDevInsRtc = pVM->pdm.s.pRtc->pDevIns;
2491 rc = PDMCritSectEnter(pDevInsRtc->pCritSectRoR3, VERR_IGNORED);
2492 if (RT_SUCCESS(rc))
2493 {
2494 rc = pVM->pdm.s.pRtc->Reg.pfnRead(pDevInsRtc, iReg, pu8Value);
2495 PDMCritSectLeave(pDevInsRtc->pCritSectRoR3);
2496 }
2497 }
2498 else
2499 rc = VERR_PDM_NO_RTC_INSTANCE;
2500
2501 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
2502 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2503 return rc;
2504}
2505
2506
2507/** @interface_method_impl{PDMDEVHLPR3,pfnAssertEMT} */
2508static DECLCALLBACK(bool) pdmR3DevHlp_AssertEMT(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction)
2509{
2510 PDMDEV_ASSERT_DEVINS(pDevIns);
2511 if (VM_IS_EMT(pDevIns->Internal.s.pVMR3))
2512 return true;
2513
2514 char szMsg[100];
2515 RTStrPrintf(szMsg, sizeof(szMsg), "AssertEMT '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance);
2516 RTAssertMsg1Weak(szMsg, iLine, pszFile, pszFunction);
2517 AssertBreakpoint();
2518 return false;
2519}
2520
2521
2522/** @interface_method_impl{PDMDEVHLPR3,pfnAssertOther} */
2523static DECLCALLBACK(bool) pdmR3DevHlp_AssertOther(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction)
2524{
2525 PDMDEV_ASSERT_DEVINS(pDevIns);
2526 if (!VM_IS_EMT(pDevIns->Internal.s.pVMR3))
2527 return true;
2528
2529 char szMsg[100];
2530 RTStrPrintf(szMsg, sizeof(szMsg), "AssertOther '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance);
2531 RTAssertMsg1Weak(szMsg, iLine, pszFile, pszFunction);
2532 AssertBreakpoint();
2533 return false;
2534}
2535
2536
2537/** @interface_method_impl{PDMDEVHLPR3,pfnLdrGetRCInterfaceSymbols} */
2538static DECLCALLBACK(int) pdmR3DevHlp_LdrGetRCInterfaceSymbols(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
2539 const char *pszSymPrefix, const char *pszSymList)
2540{
2541 PDMDEV_ASSERT_DEVINS(pDevIns);
2542 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2543 LogFlow(("pdmR3DevHlp_PDMLdrGetRCInterfaceSymbols: caller='%s'/%d: pvInterface=%p cbInterface=%zu pszSymPrefix=%p:{%s} pszSymList=%p:{%s}\n",
2544 pDevIns->pReg->szName, pDevIns->iInstance, pvInterface, cbInterface, pszSymPrefix, pszSymPrefix, pszSymList, pszSymList));
2545
2546 int rc;
2547 if ( strncmp(pszSymPrefix, "dev", 3) == 0
2548 && RTStrIStr(pszSymPrefix + 3, pDevIns->pReg->szName) != NULL)
2549 {
2550 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
2551 rc = PDMR3LdrGetInterfaceSymbols(pDevIns->Internal.s.pVMR3,
2552 pvInterface, cbInterface,
2553 pDevIns->pReg->szRCMod, pDevIns->Internal.s.pDevR3->pszRCSearchPath,
2554 pszSymPrefix, pszSymList,
2555 false /*fRing0OrRC*/);
2556 else
2557 {
2558 AssertMsgFailed(("Not a raw-mode enabled driver\n"));
2559 rc = VERR_PERMISSION_DENIED;
2560 }
2561 }
2562 else
2563 {
2564 AssertMsgFailed(("Invalid prefix '%s' for '%s'; must start with 'dev' and contain the driver name!\n",
2565 pszSymPrefix, pDevIns->pReg->szName));
2566 rc = VERR_INVALID_NAME;
2567 }
2568
2569 LogFlow(("pdmR3DevHlp_PDMLdrGetRCInterfaceSymbols: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2570 pDevIns->iInstance, rc));
2571 return rc;
2572}
2573
2574
2575/** @interface_method_impl{PDMDEVHLPR3,pfnLdrGetR0InterfaceSymbols} */
2576static DECLCALLBACK(int) pdmR3DevHlp_LdrGetR0InterfaceSymbols(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
2577 const char *pszSymPrefix, const char *pszSymList)
2578{
2579 PDMDEV_ASSERT_DEVINS(pDevIns);
2580 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2581 LogFlow(("pdmR3DevHlp_PDMLdrGetR0InterfaceSymbols: caller='%s'/%d: pvInterface=%p cbInterface=%zu pszSymPrefix=%p:{%s} pszSymList=%p:{%s}\n",
2582 pDevIns->pReg->szName, pDevIns->iInstance, pvInterface, cbInterface, pszSymPrefix, pszSymPrefix, pszSymList, pszSymList));
2583
2584 int rc;
2585 if ( strncmp(pszSymPrefix, "dev", 3) == 0
2586 && RTStrIStr(pszSymPrefix + 3, pDevIns->pReg->szName) != NULL)
2587 {
2588 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
2589 rc = PDMR3LdrGetInterfaceSymbols(pDevIns->Internal.s.pVMR3,
2590 pvInterface, cbInterface,
2591 pDevIns->pReg->szR0Mod, pDevIns->Internal.s.pDevR3->pszR0SearchPath,
2592 pszSymPrefix, pszSymList,
2593 true /*fRing0OrRC*/);
2594 else
2595 {
2596 AssertMsgFailed(("Not a ring-0 enabled driver\n"));
2597 rc = VERR_PERMISSION_DENIED;
2598 }
2599 }
2600 else
2601 {
2602 AssertMsgFailed(("Invalid prefix '%s' for '%s'; must start with 'dev' and contain the driver name!\n",
2603 pszSymPrefix, pDevIns->pReg->szName));
2604 rc = VERR_INVALID_NAME;
2605 }
2606
2607 LogFlow(("pdmR3DevHlp_PDMLdrGetR0InterfaceSymbols: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2608 pDevIns->iInstance, rc));
2609 return rc;
2610}
2611
2612
2613/** @interface_method_impl{PDMDEVHLPR3,pfnCallR0} */
2614static DECLCALLBACK(int) pdmR3DevHlp_CallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
2615{
2616 PDMDEV_ASSERT_DEVINS(pDevIns);
2617 PVM pVM = pDevIns->Internal.s.pVMR3;
2618 VM_ASSERT_EMT(pVM);
2619 LogFlow(("pdmR3DevHlp_CallR0: caller='%s'/%d: uOperation=%#x u64Arg=%#RX64\n",
2620 pDevIns->pReg->szName, pDevIns->iInstance, uOperation, u64Arg));
2621
2622 /*
2623 * Resolve the ring-0 entry point. There is not need to remember this like
2624 * we do for drivers since this is mainly for construction time hacks and
2625 * other things that aren't performance critical.
2626 */
2627 int rc;
2628 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
2629 {
2630 char szSymbol[ sizeof("devR0") + sizeof(pDevIns->pReg->szName) + sizeof("ReqHandler")];
2631 strcat(strcat(strcpy(szSymbol, "devR0"), pDevIns->pReg->szName), "ReqHandler");
2632 szSymbol[sizeof("devR0") - 1] = RT_C_TO_UPPER(szSymbol[sizeof("devR0") - 1]);
2633
2634 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
2635 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, szSymbol, &pfnReqHandlerR0);
2636 if (RT_SUCCESS(rc))
2637 {
2638 /*
2639 * Make the ring-0 call.
2640 */
2641 PDMDEVICECALLREQHANDLERREQ Req;
2642 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2643 Req.Hdr.cbReq = sizeof(Req);
2644 Req.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2645 Req.pfnReqHandlerR0 = pfnReqHandlerR0;
2646 Req.uOperation = uOperation;
2647 Req.u32Alignment = 0;
2648 Req.u64Arg = u64Arg;
2649 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, NIL_VMCPUID, VMMR0_DO_PDM_DEVICE_CALL_REQ_HANDLER, 0, &Req.Hdr);
2650 }
2651 else
2652 pfnReqHandlerR0 = NIL_RTR0PTR;
2653 }
2654 else
2655 rc = VERR_ACCESS_DENIED;
2656 LogFlow(("pdmR3DevHlp_CallR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2657 pDevIns->iInstance, rc));
2658 return rc;
2659}
2660
2661
2662/** @interface_method_impl{PDMDEVHLPR3,pfnVMGetSuspendReason} */
2663static DECLCALLBACK(VMSUSPENDREASON) pdmR3DevHlp_VMGetSuspendReason(PPDMDEVINS pDevIns)
2664{
2665 PDMDEV_ASSERT_DEVINS(pDevIns);
2666 PVM pVM = pDevIns->Internal.s.pVMR3;
2667 VM_ASSERT_EMT(pVM);
2668 VMSUSPENDREASON enmReason = VMR3GetSuspendReason(pVM->pUVM);
2669 LogFlow(("pdmR3DevHlp_VMGetSuspendReason: caller='%s'/%d: returns %d\n",
2670 pDevIns->pReg->szName, pDevIns->iInstance, enmReason));
2671 return enmReason;
2672}
2673
2674
2675/** @interface_method_impl{PDMDEVHLPR3,pfnVMGetResumeReason} */
2676static DECLCALLBACK(VMRESUMEREASON) pdmR3DevHlp_VMGetResumeReason(PPDMDEVINS pDevIns)
2677{
2678 PDMDEV_ASSERT_DEVINS(pDevIns);
2679 PVM pVM = pDevIns->Internal.s.pVMR3;
2680 VM_ASSERT_EMT(pVM);
2681 VMRESUMEREASON enmReason = VMR3GetResumeReason(pVM->pUVM);
2682 LogFlow(("pdmR3DevHlp_VMGetResumeReason: caller='%s'/%d: returns %d\n",
2683 pDevIns->pReg->szName, pDevIns->iInstance, enmReason));
2684 return enmReason;
2685}
2686
2687
2688/** @interface_method_impl{PDMDEVHLPR3,pfnGetUVM} */
2689static DECLCALLBACK(PUVM) pdmR3DevHlp_GetUVM(PPDMDEVINS pDevIns)
2690{
2691 PDMDEV_ASSERT_DEVINS(pDevIns);
2692 LogFlow(("pdmR3DevHlp_GetUVM: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3));
2693 return pDevIns->Internal.s.pVMR3->pUVM;
2694}
2695
2696
2697/** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */
2698static DECLCALLBACK(PVM) pdmR3DevHlp_GetVM(PPDMDEVINS pDevIns)
2699{
2700 PDMDEV_ASSERT_DEVINS(pDevIns);
2701 LogFlow(("pdmR3DevHlp_GetVM: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3));
2702 return pDevIns->Internal.s.pVMR3;
2703}
2704
2705
2706/** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */
2707static DECLCALLBACK(PVMCPU) pdmR3DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
2708{
2709 PDMDEV_ASSERT_DEVINS(pDevIns);
2710 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2711 LogFlow(("pdmR3DevHlp_GetVMCPU: caller='%s'/%d for CPU %u\n", pDevIns->pReg->szName, pDevIns->iInstance, VMMGetCpuId(pDevIns->Internal.s.pVMR3)));
2712 return VMMGetCpu(pDevIns->Internal.s.pVMR3);
2713}
2714
2715
2716/** @interface_method_impl{PDMDEVHLPR3,pfnGetCurrentCpuId} */
2717static DECLCALLBACK(VMCPUID) pdmR3DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
2718{
2719 PDMDEV_ASSERT_DEVINS(pDevIns);
2720 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pVMR3);
2721 LogFlow(("pdmR3DevHlp_GetCurrentCpuId: caller='%s'/%d for CPU %u\n", pDevIns->pReg->szName, pDevIns->iInstance, idCpu));
2722 return idCpu;
2723}
2724
2725
2726/** @interface_method_impl{PDMDEVHLPR3,pfnPCIBusRegister} */
2727static DECLCALLBACK(int) pdmR3DevHlp_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg,
2728 PCPDMPCIHLPR3 *ppPciHlpR3, uint32_t *piBus)
2729{
2730 PDMDEV_ASSERT_DEVINS(pDevIns);
2731 PVM pVM = pDevIns->Internal.s.pVMR3;
2732 VM_ASSERT_EMT(pVM);
2733 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: pPciBusReg=%p:{.u32Version=%#x, .pfnRegisterR3=%p, .pfnIORegionRegisterR3=%p, "
2734 ".pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppPciHlpR3=%p piBus=%p\n",
2735 pDevIns->pReg->szName, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->pfnRegisterR3,
2736 pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnSetIrqR3, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqRC,
2737 pPciBusReg->pszSetIrqR0, pPciBusReg->pszSetIrqR0, ppPciHlpR3, piBus));
2738
2739 /*
2740 * Validate the structure.
2741 */
2742 if (pPciBusReg->u32Version != PDM_PCIBUSREG_VERSION)
2743 {
2744 AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREG_VERSION));
2745 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2746 return VERR_INVALID_PARAMETER;
2747 }
2748 if ( !pPciBusReg->pfnRegisterR3
2749 || !pPciBusReg->pfnIORegionRegisterR3
2750 || !pPciBusReg->pfnSetIrqR3)
2751 {
2752 Assert(pPciBusReg->pfnRegisterR3);
2753 Assert(pPciBusReg->pfnIORegionRegisterR3);
2754 Assert(pPciBusReg->pfnSetIrqR3);
2755 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2756 return VERR_INVALID_PARAMETER;
2757 }
2758 if ( pPciBusReg->pszSetIrqRC
2759 && !VALID_PTR(pPciBusReg->pszSetIrqRC))
2760 {
2761 Assert(VALID_PTR(pPciBusReg->pszSetIrqRC));
2762 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2763 return VERR_INVALID_PARAMETER;
2764 }
2765 if ( pPciBusReg->pszSetIrqR0
2766 && !VALID_PTR(pPciBusReg->pszSetIrqR0))
2767 {
2768 Assert(VALID_PTR(pPciBusReg->pszSetIrqR0));
2769 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2770 return VERR_INVALID_PARAMETER;
2771 }
2772 if (!ppPciHlpR3)
2773 {
2774 Assert(ppPciHlpR3);
2775 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (ppPciHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2776 return VERR_INVALID_PARAMETER;
2777 }
2778 AssertLogRelMsgReturn(RT_VALID_PTR(piBus) || !piBus,
2779 ("caller='%s'/%d: piBus=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, piBus),
2780 VERR_INVALID_POINTER);
2781
2782 /*
2783 * Find free PCI bus entry.
2784 */
2785 unsigned iBus = 0;
2786 for (iBus = 0; iBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses); iBus++)
2787 if (!pVM->pdm.s.aPciBuses[iBus].pDevInsR3)
2788 break;
2789 if (iBus >= RT_ELEMENTS(pVM->pdm.s.aPciBuses))
2790 {
2791 AssertMsgFailed(("Too many PCI buses. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aPciBuses)));
2792 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (pci bus)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2793 return VERR_INVALID_PARAMETER;
2794 }
2795 PPDMPCIBUS pPciBus = &pVM->pdm.s.aPciBuses[iBus];
2796
2797 /*
2798 * Resolve and init the RC bits.
2799 */
2800 if (pPciBusReg->pszSetIrqRC)
2801 {
2802 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPciBusReg->pszSetIrqRC, &pPciBus->pfnSetIrqRC);
2803 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPciBusReg->pszSetIrqRC, rc));
2804 if (RT_FAILURE(rc))
2805 {
2806 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2807 return rc;
2808 }
2809 pPciBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2810 }
2811 else
2812 {
2813 pPciBus->pfnSetIrqRC = 0;
2814 pPciBus->pDevInsRC = 0;
2815 }
2816
2817 /*
2818 * Resolve and init the R0 bits.
2819 */
2820 if (pPciBusReg->pszSetIrqR0)
2821 {
2822 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPciBusReg->pszSetIrqR0, &pPciBus->pfnSetIrqR0);
2823 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPciBusReg->pszSetIrqR0, rc));
2824 if (RT_FAILURE(rc))
2825 {
2826 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2827 return rc;
2828 }
2829 pPciBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2830 }
2831 else
2832 {
2833 pPciBus->pfnSetIrqR0 = 0;
2834 pPciBus->pDevInsR0 = 0;
2835 }
2836
2837 /*
2838 * Init the R3 bits.
2839 */
2840 pPciBus->iBus = iBus;
2841 pPciBus->pDevInsR3 = pDevIns;
2842 pPciBus->pfnRegisterR3 = pPciBusReg->pfnRegisterR3;
2843 pPciBus->pfnRegisterMsiR3 = pPciBusReg->pfnRegisterMsiR3;
2844 pPciBus->pfnIORegionRegisterR3 = pPciBusReg->pfnIORegionRegisterR3;
2845 pPciBus->pfnSetConfigCallbacksR3 = pPciBusReg->pfnSetConfigCallbacksR3;
2846 pPciBus->pfnSetIrqR3 = pPciBusReg->pfnSetIrqR3;
2847
2848 Log(("PDM: Registered PCI bus device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2849
2850 /* set the helper pointer and return. */
2851 *ppPciHlpR3 = &g_pdmR3DevPciHlp;
2852 if (piBus)
2853 *piBus = iBus;
2854 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc *piBus=%u\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS, iBus));
2855 return VINF_SUCCESS;
2856}
2857
2858
2859/** @interface_method_impl{PDMDEVHLPR3,pfnPICRegister} */
2860static DECLCALLBACK(int) pdmR3DevHlp_PICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3)
2861{
2862 PDMDEV_ASSERT_DEVINS(pDevIns);
2863 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2864 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pfnGetInterruptR3=%p, .pszGetIrqRC=%p:{%s}, .pszGetInterruptRC=%p:{%s}, .pszGetIrqR0=%p:{%s}, .pszGetInterruptR0=%p:{%s} } ppPicHlpR3=%p\n",
2865 pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrqR3, pPicReg->pfnGetInterruptR3,
2866 pPicReg->pszSetIrqRC, pPicReg->pszSetIrqRC, pPicReg->pszGetInterruptRC, pPicReg->pszGetInterruptRC,
2867 pPicReg->pszSetIrqR0, pPicReg->pszSetIrqR0, pPicReg->pszGetInterruptR0, pPicReg->pszGetInterruptR0,
2868 ppPicHlpR3));
2869
2870 /*
2871 * Validate input.
2872 */
2873 if (pPicReg->u32Version != PDM_PICREG_VERSION)
2874 {
2875 AssertMsgFailed(("u32Version=%#x expected %#x\n", pPicReg->u32Version, PDM_PICREG_VERSION));
2876 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2877 return VERR_INVALID_PARAMETER;
2878 }
2879 if ( !pPicReg->pfnSetIrqR3
2880 || !pPicReg->pfnGetInterruptR3)
2881 {
2882 Assert(pPicReg->pfnSetIrqR3);
2883 Assert(pPicReg->pfnGetInterruptR3);
2884 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2885 return VERR_INVALID_PARAMETER;
2886 }
2887 if ( ( pPicReg->pszSetIrqRC
2888 || pPicReg->pszGetInterruptRC)
2889 && ( !VALID_PTR(pPicReg->pszSetIrqRC)
2890 || !VALID_PTR(pPicReg->pszGetInterruptRC))
2891 )
2892 {
2893 Assert(VALID_PTR(pPicReg->pszSetIrqRC));
2894 Assert(VALID_PTR(pPicReg->pszGetInterruptRC));
2895 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (RC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2896 return VERR_INVALID_PARAMETER;
2897 }
2898 if ( pPicReg->pszSetIrqRC
2899 && !(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC))
2900 {
2901 Assert(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC);
2902 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (RC flag)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2903 return VERR_INVALID_PARAMETER;
2904 }
2905 if ( pPicReg->pszSetIrqR0
2906 && !(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
2907 {
2908 Assert(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0);
2909 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (R0 flag)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2910 return VERR_INVALID_PARAMETER;
2911 }
2912 if (!ppPicHlpR3)
2913 {
2914 Assert(ppPicHlpR3);
2915 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (ppPicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2916 return VERR_INVALID_PARAMETER;
2917 }
2918
2919 /*
2920 * Only one PIC device.
2921 */
2922 PVM pVM = pDevIns->Internal.s.pVMR3;
2923 if (pVM->pdm.s.Pic.pDevInsR3)
2924 {
2925 AssertMsgFailed(("Only one pic device is supported!\n"));
2926 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2927 return VERR_INVALID_PARAMETER;
2928 }
2929
2930 /*
2931 * RC stuff.
2932 */
2933 if (pPicReg->pszSetIrqRC)
2934 {
2935 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPicReg->pszSetIrqRC, &pVM->pdm.s.Pic.pfnSetIrqRC);
2936 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPicReg->pszSetIrqRC, rc));
2937 if (RT_SUCCESS(rc))
2938 {
2939 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPicReg->pszGetInterruptRC, &pVM->pdm.s.Pic.pfnGetInterruptRC);
2940 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPicReg->pszGetInterruptRC, rc));
2941 }
2942 if (RT_FAILURE(rc))
2943 {
2944 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2945 return rc;
2946 }
2947 pVM->pdm.s.Pic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2948 }
2949 else
2950 {
2951 pVM->pdm.s.Pic.pDevInsRC = 0;
2952 pVM->pdm.s.Pic.pfnSetIrqRC = 0;
2953 pVM->pdm.s.Pic.pfnGetInterruptRC = 0;
2954 }
2955
2956 /*
2957 * R0 stuff.
2958 */
2959 if (pPicReg->pszSetIrqR0)
2960 {
2961 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPicReg->pszSetIrqR0, &pVM->pdm.s.Pic.pfnSetIrqR0);
2962 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPicReg->pszSetIrqR0, rc));
2963 if (RT_SUCCESS(rc))
2964 {
2965 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPicReg->pszGetInterruptR0, &pVM->pdm.s.Pic.pfnGetInterruptR0);
2966 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPicReg->pszGetInterruptR0, rc));
2967 }
2968 if (RT_FAILURE(rc))
2969 {
2970 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2971 return rc;
2972 }
2973 pVM->pdm.s.Pic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2974 Assert(pVM->pdm.s.Pic.pDevInsR0);
2975 }
2976 else
2977 {
2978 pVM->pdm.s.Pic.pfnSetIrqR0 = 0;
2979 pVM->pdm.s.Pic.pfnGetInterruptR0 = 0;
2980 pVM->pdm.s.Pic.pDevInsR0 = 0;
2981 }
2982
2983 /*
2984 * R3 stuff.
2985 */
2986 pVM->pdm.s.Pic.pDevInsR3 = pDevIns;
2987 pVM->pdm.s.Pic.pfnSetIrqR3 = pPicReg->pfnSetIrqR3;
2988 pVM->pdm.s.Pic.pfnGetInterruptR3 = pPicReg->pfnGetInterruptR3;
2989 Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2990
2991 /* set the helper pointer and return. */
2992 *ppPicHlpR3 = &g_pdmR3DevPicHlp;
2993 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2994 return VINF_SUCCESS;
2995}
2996
2997
2998/** @interface_method_impl{PDMDEVHLPR3,pfnAPICRegister} */
2999static DECLCALLBACK(int) pdmR3DevHlp_APICRegister(PPDMDEVINS pDevIns)
3000{
3001 PDMDEV_ASSERT_DEVINS(pDevIns);
3002 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3003
3004 /*
3005 * Only one APIC device. On SMP we have single logical device covering all LAPICs,
3006 * as they need to communicate and share state easily.
3007 */
3008 PVM pVM = pDevIns->Internal.s.pVMR3;
3009 if (pVM->pdm.s.Apic.pDevInsR3)
3010 {
3011 AssertMsgFailed(("Only one APIC device is supported!\n"));
3012 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3013 return VERR_INVALID_PARAMETER;
3014 }
3015
3016 /*
3017 * Initialize the RC, R0 and HC bits.
3018 */
3019 pVM->pdm.s.Apic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3020 Assert(pVM->pdm.s.Apic.pDevInsRC);
3021
3022 pVM->pdm.s.Apic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3023 Assert(pVM->pdm.s.Apic.pDevInsR0);
3024
3025 pVM->pdm.s.Apic.pDevInsR3 = pDevIns;
3026 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3027 return VINF_SUCCESS;
3028}
3029
3030
3031/** @interface_method_impl{PDMDEVHLPR3,pfnIOAPICRegister} */
3032static DECLCALLBACK(int) pdmR3DevHlp_IOAPICRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3)
3033{
3034 PDMDEV_ASSERT_DEVINS(pDevIns);
3035 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3036 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppIoApicHlpR3=%p\n",
3037 pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrqR3,
3038 pIoApicReg->pszSetIrqRC, pIoApicReg->pszSetIrqRC, pIoApicReg->pszSetIrqR0, pIoApicReg->pszSetIrqR0, ppIoApicHlpR3));
3039
3040 /*
3041 * Validate input.
3042 */
3043 if (pIoApicReg->u32Version != PDM_IOAPICREG_VERSION)
3044 {
3045 AssertMsgFailed(("u32Version=%#x expected %#x\n", pIoApicReg->u32Version, PDM_IOAPICREG_VERSION));
3046 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3047 return VERR_INVALID_PARAMETER;
3048 }
3049 if (!pIoApicReg->pfnSetIrqR3 || !pIoApicReg->pfnSendMsiR3 || !pIoApicReg->pfnSetEoiR3)
3050 {
3051 Assert(pIoApicReg->pfnSetIrqR3);
3052 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3053 return VERR_INVALID_PARAMETER;
3054 }
3055 if ( pIoApicReg->pszSetIrqRC
3056 && !VALID_PTR(pIoApicReg->pszSetIrqRC))
3057 {
3058 Assert(VALID_PTR(pIoApicReg->pszSetIrqRC));
3059 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3060 return VERR_INVALID_PARAMETER;
3061 }
3062 if ( pIoApicReg->pszSendMsiRC
3063 && !VALID_PTR(pIoApicReg->pszSendMsiRC))
3064 {
3065 Assert(VALID_PTR(pIoApicReg->pszSendMsiRC));
3066 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3067 return VERR_INVALID_PARAMETER;
3068 }
3069 if ( pIoApicReg->pszSetEoiRC
3070 && !VALID_PTR(pIoApicReg->pszSetEoiRC))
3071 {
3072 Assert(VALID_PTR(pIoApicReg->pszSetEoiRC));
3073 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3074 return VERR_INVALID_PARAMETER;
3075 }
3076 if ( pIoApicReg->pszSetIrqR0
3077 && !VALID_PTR(pIoApicReg->pszSetIrqR0))
3078 {
3079 Assert(VALID_PTR(pIoApicReg->pszSetIrqR0));
3080 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3081 return VERR_INVALID_PARAMETER;
3082 }
3083 if ( pIoApicReg->pszSendMsiR0
3084 && !VALID_PTR(pIoApicReg->pszSendMsiR0))
3085 {
3086 Assert(VALID_PTR(pIoApicReg->pszSendMsiR0));
3087 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3088 return VERR_INVALID_PARAMETER;
3089 }
3090 if ( pIoApicReg->pszSetEoiR0
3091 && !VALID_PTR(pIoApicReg->pszSetEoiR0))
3092 {
3093 Assert(VALID_PTR(pIoApicReg->pszSetEoiR0));
3094 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3095 return VERR_INVALID_PARAMETER;
3096 }
3097 if (!ppIoApicHlpR3)
3098 {
3099 Assert(ppIoApicHlpR3);
3100 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (ppApicHlp)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3101 return VERR_INVALID_PARAMETER;
3102 }
3103
3104 /*
3105 * The I/O APIC requires the APIC to be present (hacks++).
3106 * If the I/O APIC does GC stuff so must the APIC.
3107 */
3108 PVM pVM = pDevIns->Internal.s.pVMR3;
3109 if (!pVM->pdm.s.Apic.pDevInsR3)
3110 {
3111 AssertMsgFailed(("Configuration error / Init order error! No APIC!\n"));
3112 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (no APIC)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3113 return VERR_INVALID_PARAMETER;
3114 }
3115 if ( pIoApicReg->pszSetIrqRC
3116 && !pVM->pdm.s.Apic.pDevInsRC)
3117 {
3118 AssertMsgFailed(("Configuration error! APIC doesn't do GC, I/O APIC does!\n"));
3119 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (no GC APIC)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3120 return VERR_INVALID_PARAMETER;
3121 }
3122
3123 /*
3124 * Only one I/O APIC device.
3125 */
3126 if (pVM->pdm.s.IoApic.pDevInsR3)
3127 {
3128 AssertMsgFailed(("Only one ioapic device is supported!\n"));
3129 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (only one)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3130 return VERR_INVALID_PARAMETER;
3131 }
3132
3133 /*
3134 * Resolve & initialize the GC bits.
3135 */
3136 if (pIoApicReg->pszSetIrqRC)
3137 {
3138 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pIoApicReg->pszSetIrqRC, &pVM->pdm.s.IoApic.pfnSetIrqRC);
3139 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pIoApicReg->pszSetIrqRC, rc));
3140 if (RT_FAILURE(rc))
3141 {
3142 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3143 return rc;
3144 }
3145 pVM->pdm.s.IoApic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3146 }
3147 else
3148 {
3149 pVM->pdm.s.IoApic.pDevInsRC = 0;
3150 pVM->pdm.s.IoApic.pfnSetIrqRC = 0;
3151 }
3152
3153 if (pIoApicReg->pszSendMsiRC)
3154 {
3155 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pIoApicReg->pszSendMsiRC, &pVM->pdm.s.IoApic.pfnSendMsiRC);
3156 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pIoApicReg->pszSendMsiRC, rc));
3157 if (RT_FAILURE(rc))
3158 {
3159 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3160 return rc;
3161 }
3162 }
3163 else
3164 {
3165 pVM->pdm.s.IoApic.pfnSendMsiRC = 0;
3166 }
3167
3168 if (pIoApicReg->pszSetEoiRC)
3169 {
3170 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pIoApicReg->pszSetEoiRC, &pVM->pdm.s.IoApic.pfnSetEoiRC);
3171 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pIoApicReg->pszSetEoiRC, rc));
3172 if (RT_FAILURE(rc))
3173 {
3174 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3175 return rc;
3176 }
3177 }
3178 else
3179 {
3180 pVM->pdm.s.IoApic.pfnSetEoiRC = 0;
3181 }
3182
3183 /*
3184 * Resolve & initialize the R0 bits.
3185 */
3186 if (pIoApicReg->pszSetIrqR0)
3187 {
3188 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pIoApicReg->pszSetIrqR0, &pVM->pdm.s.IoApic.pfnSetIrqR0);
3189 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pIoApicReg->pszSetIrqR0, rc));
3190 if (RT_FAILURE(rc))
3191 {
3192 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3193 return rc;
3194 }
3195 pVM->pdm.s.IoApic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3196 Assert(pVM->pdm.s.IoApic.pDevInsR0);
3197 }
3198 else
3199 {
3200 pVM->pdm.s.IoApic.pfnSetIrqR0 = 0;
3201 pVM->pdm.s.IoApic.pDevInsR0 = 0;
3202 }
3203
3204 if (pIoApicReg->pszSendMsiR0)
3205 {
3206 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pIoApicReg->pszSendMsiR0, &pVM->pdm.s.IoApic.pfnSendMsiR0);
3207 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pIoApicReg->pszSendMsiR0, rc));
3208 if (RT_FAILURE(rc))
3209 {
3210 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3211 return rc;
3212 }
3213 }
3214 else
3215 {
3216 pVM->pdm.s.IoApic.pfnSendMsiR0 = 0;
3217 }
3218
3219 if (pIoApicReg->pszSetEoiR0)
3220 {
3221 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pIoApicReg->pszSetEoiR0, &pVM->pdm.s.IoApic.pfnSetEoiR0);
3222 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pIoApicReg->pszSetEoiR0, rc));
3223 if (RT_FAILURE(rc))
3224 {
3225 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3226 return rc;
3227 }
3228 }
3229 else
3230 {
3231 pVM->pdm.s.IoApic.pfnSetEoiR0 = 0;
3232 }
3233
3234
3235 /*
3236 * Initialize the R3 bits.
3237 */
3238 pVM->pdm.s.IoApic.pDevInsR3 = pDevIns;
3239 pVM->pdm.s.IoApic.pfnSetIrqR3 = pIoApicReg->pfnSetIrqR3;
3240 pVM->pdm.s.IoApic.pfnSendMsiR3 = pIoApicReg->pfnSendMsiR3;
3241 pVM->pdm.s.IoApic.pfnSetEoiR3 = pIoApicReg->pfnSetEoiR3;
3242 Log(("PDM: Registered I/O APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3243
3244 /* set the helper pointer and return. */
3245 *ppIoApicHlpR3 = &g_pdmR3DevIoApicHlp;
3246 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3247 return VINF_SUCCESS;
3248}
3249
3250
3251/** @interface_method_impl{PDMDEVHLPR3,pfnHPETRegister} */
3252static DECLCALLBACK(int) pdmR3DevHlp_HPETRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
3253{
3254 PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
3255 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3256 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
3257
3258 /*
3259 * Validate input.
3260 */
3261 if (pHpetReg->u32Version != PDM_HPETREG_VERSION)
3262 {
3263 AssertMsgFailed(("u32Version=%#x expected %#x\n", pHpetReg->u32Version, PDM_HPETREG_VERSION));
3264 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3265 return VERR_INVALID_PARAMETER;
3266 }
3267
3268 if (!ppHpetHlpR3)
3269 {
3270 Assert(ppHpetHlpR3);
3271 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc (ppApicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3272 return VERR_INVALID_PARAMETER;
3273 }
3274
3275 /* set the helper pointer and return. */
3276 *ppHpetHlpR3 = &g_pdmR3DevHpetHlp;
3277 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3278 return VINF_SUCCESS;
3279}
3280
3281
3282/** @interface_method_impl{PDMDEVHLPR3,pfnPciRawRegister} */
3283static DECLCALLBACK(int) pdmR3DevHlp_PciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
3284{
3285 PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
3286 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3287 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
3288
3289 /*
3290 * Validate input.
3291 */
3292 if (pPciRawReg->u32Version != PDM_PCIRAWREG_VERSION)
3293 {
3294 AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciRawReg->u32Version, PDM_PCIRAWREG_VERSION));
3295 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3296 return VERR_INVALID_PARAMETER;
3297 }
3298
3299 if (!ppPciRawHlpR3)
3300 {
3301 Assert(ppPciRawHlpR3);
3302 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc (ppPciRawHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3303 return VERR_INVALID_PARAMETER;
3304 }
3305
3306 /* set the helper pointer and return. */
3307 *ppPciRawHlpR3 = &g_pdmR3DevPciRawHlp;
3308 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3309 return VINF_SUCCESS;
3310}
3311
3312
3313/** @interface_method_impl{PDMDEVHLPR3,pfnDMACRegister} */
3314static DECLCALLBACK(int) pdmR3DevHlp_DMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
3315{
3316 PDMDEV_ASSERT_DEVINS(pDevIns);
3317 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3318 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: pDmacReg=%p:{.u32Version=%#x, .pfnRun=%p, .pfnRegister=%p, .pfnReadMemory=%p, .pfnWriteMemory=%p, .pfnSetDREQ=%p, .pfnGetChannelMode=%p} ppDmacHlp=%p\n",
3319 pDevIns->pReg->szName, pDevIns->iInstance, pDmacReg, pDmacReg->u32Version, pDmacReg->pfnRun, pDmacReg->pfnRegister,
3320 pDmacReg->pfnReadMemory, pDmacReg->pfnWriteMemory, pDmacReg->pfnSetDREQ, pDmacReg->pfnGetChannelMode, ppDmacHlp));
3321
3322 /*
3323 * Validate input.
3324 */
3325 if (pDmacReg->u32Version != PDM_DMACREG_VERSION)
3326 {
3327 AssertMsgFailed(("u32Version=%#x expected %#x\n", pDmacReg->u32Version,
3328 PDM_DMACREG_VERSION));
3329 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (version)\n",
3330 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3331 return VERR_INVALID_PARAMETER;
3332 }
3333 if ( !pDmacReg->pfnRun
3334 || !pDmacReg->pfnRegister
3335 || !pDmacReg->pfnReadMemory
3336 || !pDmacReg->pfnWriteMemory
3337 || !pDmacReg->pfnSetDREQ
3338 || !pDmacReg->pfnGetChannelMode)
3339 {
3340 Assert(pDmacReg->pfnRun);
3341 Assert(pDmacReg->pfnRegister);
3342 Assert(pDmacReg->pfnReadMemory);
3343 Assert(pDmacReg->pfnWriteMemory);
3344 Assert(pDmacReg->pfnSetDREQ);
3345 Assert(pDmacReg->pfnGetChannelMode);
3346 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
3347 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3348 return VERR_INVALID_PARAMETER;
3349 }
3350
3351 if (!ppDmacHlp)
3352 {
3353 Assert(ppDmacHlp);
3354 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (ppDmacHlp)\n",
3355 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3356 return VERR_INVALID_PARAMETER;
3357 }
3358
3359 /*
3360 * Only one DMA device.
3361 */
3362 PVM pVM = pDevIns->Internal.s.pVMR3;
3363 if (pVM->pdm.s.pDmac)
3364 {
3365 AssertMsgFailed(("Only one DMA device is supported!\n"));
3366 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc\n",
3367 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3368 return VERR_INVALID_PARAMETER;
3369 }
3370
3371 /*
3372 * Allocate and initialize pci bus structure.
3373 */
3374 int rc = VINF_SUCCESS;
3375 PPDMDMAC pDmac = (PPDMDMAC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pDmac));
3376 if (pDmac)
3377 {
3378 pDmac->pDevIns = pDevIns;
3379 pDmac->Reg = *pDmacReg;
3380 pVM->pdm.s.pDmac = pDmac;
3381
3382 /* set the helper pointer. */
3383 *ppDmacHlp = &g_pdmR3DevDmacHlp;
3384 Log(("PDM: Registered DMAC device '%s'/%d pDevIns=%p\n",
3385 pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3386 }
3387 else
3388 rc = VERR_NO_MEMORY;
3389
3390 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc\n",
3391 pDevIns->pReg->szName, pDevIns->iInstance, rc));
3392 return rc;
3393}
3394
3395
3396/**
3397 * @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
3398 */
3399static DECLCALLBACK(int) pdmR3DevHlp_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
3400{
3401 PDMDEV_ASSERT_DEVINS(pDevIns);
3402 PVM pVM = pDevIns->Internal.s.pVMR3;
3403 VM_ASSERT_EMT(pVM);
3404 LogFlow(("pdmR3DevHlp_RegisterVMMDevHeap: caller='%s'/%d: GCPhys=%RGp pvHeap=%p cbHeap=%#x\n",
3405 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvHeap, cbHeap));
3406
3407 if (pVM->pdm.s.pvVMMDevHeap == NULL)
3408 {
3409 pVM->pdm.s.pvVMMDevHeap = pvHeap;
3410 pVM->pdm.s.GCPhysVMMDevHeap = GCPhys;
3411 pVM->pdm.s.cbVMMDevHeap = cbHeap;
3412 pVM->pdm.s.cbVMMDevHeapLeft = cbHeap;
3413 }
3414 else
3415 {
3416 Assert(pVM->pdm.s.pvVMMDevHeap == pvHeap);
3417 Assert(pVM->pdm.s.cbVMMDevHeap == cbHeap);
3418 Assert(pVM->pdm.s.GCPhysVMMDevHeap != GCPhys || GCPhys == NIL_RTGCPHYS);
3419 if (pVM->pdm.s.GCPhysVMMDevHeap != GCPhys)
3420 {
3421 pVM->pdm.s.GCPhysVMMDevHeap = GCPhys;
3422 if (pVM->pdm.s.pfnVMMDevHeapNotify)
3423 pVM->pdm.s.pfnVMMDevHeapNotify(pVM, pvHeap, GCPhys);
3424 }
3425 }
3426
3427 LogFlow(("pdmR3DevHlp_RegisterVMMDevHeap: caller='%s'/%d: returns %Rrc\n",
3428 pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3429 return VINF_SUCCESS;
3430}
3431
3432
3433/**
3434 * @interface_method_impl{PDMDEVHLPR3,pfnFirmwareRegister}
3435 */
3436static DECLCALLBACK(int) pdmR3DevHlp_FirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
3437{
3438 PDMDEV_ASSERT_DEVINS(pDevIns);
3439 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3440 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: pFWReg=%p:{.u32Version=%#x, .pfnIsHardReset=%p, .u32TheEnd=%#x} ppFwHlp=%p\n",
3441 pDevIns->pReg->szName, pDevIns->iInstance, pFwReg, pFwReg->u32Version, pFwReg->pfnIsHardReset, pFwReg->u32TheEnd, ppFwHlp));
3442
3443 /*
3444 * Validate input.
3445 */
3446 if (pFwReg->u32Version != PDM_FWREG_VERSION)
3447 {
3448 AssertMsgFailed(("u32Version=%#x expected %#x\n", pFwReg->u32Version, PDM_FWREG_VERSION));
3449 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (version)\n",
3450 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3451 return VERR_INVALID_PARAMETER;
3452 }
3453 if (!pFwReg->pfnIsHardReset)
3454 {
3455 Assert(pFwReg->pfnIsHardReset);
3456 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
3457 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3458 return VERR_INVALID_PARAMETER;
3459 }
3460
3461 if (!ppFwHlp)
3462 {
3463 Assert(ppFwHlp);
3464 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (ppFwHlp)\n",
3465 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3466 return VERR_INVALID_PARAMETER;
3467 }
3468
3469 /*
3470 * Only one DMA device.
3471 */
3472 PVM pVM = pDevIns->Internal.s.pVMR3;
3473 if (pVM->pdm.s.pFirmware)
3474 {
3475 AssertMsgFailed(("Only one firmware device is supported!\n"));
3476 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc\n",
3477 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3478 return VERR_INVALID_PARAMETER;
3479 }
3480
3481 /*
3482 * Allocate and initialize pci bus structure.
3483 */
3484 int rc = VINF_SUCCESS;
3485 PPDMFW pFirmware = (PPDMFW)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pFirmware));
3486 if (pFirmware)
3487 {
3488 pFirmware->pDevIns = pDevIns;
3489 pFirmware->Reg = *pFwReg;
3490 pVM->pdm.s.pFirmware = pFirmware;
3491
3492 /* set the helper pointer. */
3493 *ppFwHlp = &g_pdmR3DevFirmwareHlp;
3494 Log(("PDM: Registered firmware device '%s'/%d pDevIns=%p\n",
3495 pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3496 }
3497 else
3498 rc = VERR_NO_MEMORY;
3499
3500 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc\n",
3501 pDevIns->pReg->szName, pDevIns->iInstance, rc));
3502 return rc;
3503}
3504
3505
3506/** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */
3507static DECLCALLBACK(int) pdmR3DevHlp_VMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
3508{
3509 PDMDEV_ASSERT_DEVINS(pDevIns);
3510 PVM pVM = pDevIns->Internal.s.pVMR3;
3511 VM_ASSERT_EMT(pVM);
3512 LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: fFlags=%#x VM_FF_RESET %d -> 1\n",
3513 pDevIns->pReg->szName, pDevIns->iInstance, fFlags, VM_FF_IS_SET(pVM, VM_FF_RESET)));
3514
3515 /*
3516 * We postpone this operation because we're likely to be inside a I/O instruction
3517 * and the EIP will be updated when we return.
3518 * We still return VINF_EM_RESET to break out of any execution loops and force FF evaluation.
3519 */
3520 bool fHaltOnReset;
3521 int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
3522 if (RT_SUCCESS(rc) && fHaltOnReset)
3523 {
3524 Log(("pdmR3DevHlp_VMReset: Halt On Reset!\n"));
3525 rc = VINF_EM_HALT;
3526 }
3527 else
3528 {
3529 pVM->pdm.s.fResetFlags = fFlags;
3530 VM_FF_SET(pVM, VM_FF_RESET);
3531 rc = VINF_EM_RESET;
3532 }
3533
3534 LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3535 return rc;
3536}
3537
3538
3539/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */
3540static DECLCALLBACK(int) pdmR3DevHlp_VMSuspend(PPDMDEVINS pDevIns)
3541{
3542 int rc;
3543 PDMDEV_ASSERT_DEVINS(pDevIns);
3544 PVM pVM = pDevIns->Internal.s.pVMR3;
3545 VM_ASSERT_EMT(pVM);
3546 LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d:\n",
3547 pDevIns->pReg->szName, pDevIns->iInstance));
3548
3549 /** @todo Always take the SMP path - fewer code paths. */
3550 if (pVM->cCpus > 1)
3551 {
3552 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
3553 rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)VMR3Suspend, 2, pVM->pUVM, VMSUSPENDREASON_VM);
3554 AssertRC(rc);
3555 rc = VINF_EM_SUSPEND;
3556 }
3557 else
3558 rc = VMR3Suspend(pVM->pUVM, VMSUSPENDREASON_VM);
3559
3560 LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3561 return rc;
3562}
3563
3564
3565/**
3566 * Worker for pdmR3DevHlp_VMSuspendSaveAndPowerOff that is invoked via a queued
3567 * EMT request to avoid deadlocks.
3568 *
3569 * @returns VBox status code fit for scheduling.
3570 * @param pVM The cross context VM structure.
3571 * @param pDevIns The device that triggered this action.
3572 */
3573static DECLCALLBACK(int) pdmR3DevHlp_VMSuspendSaveAndPowerOffWorker(PVM pVM, PPDMDEVINS pDevIns)
3574{
3575 /*
3576 * Suspend the VM first then do the saving.
3577 */
3578 int rc = VMR3Suspend(pVM->pUVM, VMSUSPENDREASON_VM);
3579 if (RT_SUCCESS(rc))
3580 {
3581 PUVM pUVM = pVM->pUVM;
3582 rc = pUVM->pVmm2UserMethods->pfnSaveState(pVM->pUVM->pVmm2UserMethods, pUVM);
3583
3584 /*
3585 * On success, power off the VM, on failure we'll leave it suspended.
3586 */
3587 if (RT_SUCCESS(rc))
3588 {
3589 rc = VMR3PowerOff(pVM->pUVM);
3590 if (RT_FAILURE(rc))
3591 LogRel(("%s/SSP: VMR3PowerOff failed: %Rrc\n", pDevIns->pReg->szName, rc));
3592 }
3593 else
3594 LogRel(("%s/SSP: pfnSaveState failed: %Rrc\n", pDevIns->pReg->szName, rc));
3595 }
3596 else
3597 LogRel(("%s/SSP: Suspend failed: %Rrc\n", pDevIns->pReg->szName, rc));
3598 return rc;
3599}
3600
3601
3602/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspendSaveAndPowerOff} */
3603static DECLCALLBACK(int) pdmR3DevHlp_VMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
3604{
3605 PDMDEV_ASSERT_DEVINS(pDevIns);
3606 PVM pVM = pDevIns->Internal.s.pVMR3;
3607 VM_ASSERT_EMT(pVM);
3608 LogFlow(("pdmR3DevHlp_VMSuspendSaveAndPowerOff: caller='%s'/%d:\n",
3609 pDevIns->pReg->szName, pDevIns->iInstance));
3610
3611 int rc;
3612 if ( pVM->pUVM->pVmm2UserMethods
3613 && pVM->pUVM->pVmm2UserMethods->pfnSaveState)
3614 {
3615 rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pdmR3DevHlp_VMSuspendSaveAndPowerOffWorker, 2, pVM, pDevIns);
3616 if (RT_SUCCESS(rc))
3617 {
3618 LogRel(("%s: Suspending, Saving and Powering Off the VM\n", pDevIns->pReg->szName));
3619 rc = VINF_EM_SUSPEND;
3620 }
3621 }
3622 else
3623 rc = VERR_NOT_SUPPORTED;
3624
3625 LogFlow(("pdmR3DevHlp_VMSuspendSaveAndPowerOff: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3626 return rc;
3627}
3628
3629
3630/** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */
3631static DECLCALLBACK(int) pdmR3DevHlp_VMPowerOff(PPDMDEVINS pDevIns)
3632{
3633 int rc;
3634 PDMDEV_ASSERT_DEVINS(pDevIns);
3635 PVM pVM = pDevIns->Internal.s.pVMR3;
3636 VM_ASSERT_EMT(pVM);
3637 LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d:\n",
3638 pDevIns->pReg->szName, pDevIns->iInstance));
3639
3640 /** @todo Always take the SMP path - fewer code paths. */
3641 if (pVM->cCpus > 1)
3642 {
3643 /* We might be holding locks here and could cause a deadlock since
3644 VMR3PowerOff rendezvous with the other CPUs. */
3645 rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)VMR3PowerOff, 1, pVM->pUVM);
3646 AssertRC(rc);
3647 /* Set the VCPU state to stopped here as well to make sure no
3648 inconsistency with the EM state occurs. */
3649 VMCPU_SET_STATE(VMMGetCpu(pVM), VMCPUSTATE_STOPPED);
3650 rc = VINF_EM_OFF;
3651 }
3652 else
3653 rc = VMR3PowerOff(pVM->pUVM);
3654
3655 LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3656 return rc;
3657}
3658
3659
3660/** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */
3661static DECLCALLBACK(bool) pdmR3DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
3662{
3663 PDMDEV_ASSERT_DEVINS(pDevIns);
3664 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3665
3666 bool fRc = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR3));
3667
3668 LogFlow(("pdmR3DevHlp_A20IsEnabled: caller='%s'/%d: returns %d\n", pDevIns->pReg->szName, pDevIns->iInstance, fRc));
3669 return fRc;
3670}
3671
3672
3673/** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */
3674static DECLCALLBACK(void) pdmR3DevHlp_A20Set(PPDMDEVINS pDevIns, bool fEnable)
3675{
3676 PDMDEV_ASSERT_DEVINS(pDevIns);
3677 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3678 LogFlow(("pdmR3DevHlp_A20Set: caller='%s'/%d: fEnable=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, fEnable));
3679 PGMR3PhysSetA20(VMMGetCpu(pDevIns->Internal.s.pVMR3), fEnable);
3680}
3681
3682
3683/** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */
3684static DECLCALLBACK(void) pdmR3DevHlp_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
3685 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
3686{
3687 PDMDEV_ASSERT_DEVINS(pDevIns);
3688 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3689
3690 LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: iLeaf=%d pEax=%p pEbx=%p pEcx=%p pEdx=%p\n",
3691 pDevIns->pReg->szName, pDevIns->iInstance, iLeaf, pEax, pEbx, pEcx, pEdx));
3692 AssertPtr(pEax); AssertPtr(pEbx); AssertPtr(pEcx); AssertPtr(pEdx);
3693
3694 CPUMGetGuestCpuId(VMMGetCpu(pDevIns->Internal.s.pVMR3), iLeaf, 0 /*iSubLeaf*/, pEax, pEbx, pEcx, pEdx);
3695
3696 LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: returns void - *pEax=%#x *pEbx=%#x *pEcx=%#x *pEdx=%#x\n",
3697 pDevIns->pReg->szName, pDevIns->iInstance, *pEax, *pEbx, *pEcx, *pEdx));
3698}
3699
3700
3701/**
3702 * The device helper structure for trusted devices.
3703 */
3704const PDMDEVHLPR3 g_pdmR3DevHlpTrusted =
3705{
3706 PDM_DEVHLPR3_VERSION,
3707 pdmR3DevHlp_IOPortRegister,
3708 pdmR3DevHlp_IOPortRegisterRC,
3709 pdmR3DevHlp_IOPortRegisterR0,
3710 pdmR3DevHlp_IOPortDeregister,
3711 pdmR3DevHlp_MMIORegister,
3712 pdmR3DevHlp_MMIORegisterRC,
3713 pdmR3DevHlp_MMIORegisterR0,
3714 pdmR3DevHlp_MMIODeregister,
3715 pdmR3DevHlp_MMIO2Register,
3716 pdmR3DevHlp_MMIOExPreRegister,
3717 pdmR3DevHlp_MMIOExDeregister,
3718 pdmR3DevHlp_MMIOExMap,
3719 pdmR3DevHlp_MMIOExUnmap,
3720 pdmR3DevHlp_MMIOExReduce,
3721 pdmR3DevHlp_MMHyperMapMMIO2,
3722 pdmR3DevHlp_MMIO2MapKernel,
3723 pdmR3DevHlp_ROMRegister,
3724 pdmR3DevHlp_ROMProtectShadow,
3725 pdmR3DevHlp_SSMRegister,
3726 pdmR3DevHlp_TMTimerCreate,
3727 pdmR3DevHlp_TMUtcNow,
3728 pdmR3DevHlp_PhysRead,
3729 pdmR3DevHlp_PhysWrite,
3730 pdmR3DevHlp_PhysGCPhys2CCPtr,
3731 pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
3732 pdmR3DevHlp_PhysReleasePageMappingLock,
3733 pdmR3DevHlp_PhysReadGCVirt,
3734 pdmR3DevHlp_PhysWriteGCVirt,
3735 pdmR3DevHlp_PhysGCPtr2GCPhys,
3736 pdmR3DevHlp_MMHeapAlloc,
3737 pdmR3DevHlp_MMHeapAllocZ,
3738 pdmR3DevHlp_MMHeapFree,
3739 pdmR3DevHlp_VMState,
3740 pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,
3741 pdmR3DevHlp_VMSetError,
3742 pdmR3DevHlp_VMSetErrorV,
3743 pdmR3DevHlp_VMSetRuntimeError,
3744 pdmR3DevHlp_VMSetRuntimeErrorV,
3745 pdmR3DevHlp_DBGFStopV,
3746 pdmR3DevHlp_DBGFInfoRegister,
3747 pdmR3DevHlp_DBGFRegRegister,
3748 pdmR3DevHlp_DBGFTraceBuf,
3749 pdmR3DevHlp_STAMRegister,
3750 pdmR3DevHlp_STAMRegisterF,
3751 pdmR3DevHlp_STAMRegisterV,
3752 pdmR3DevHlp_PCIRegister,
3753 pdmR3DevHlp_PCIRegisterMsi,
3754 pdmR3DevHlp_PCIIORegionRegister,
3755 pdmR3DevHlp_PCISetConfigCallbacks,
3756 pdmR3DevHlp_PCIPhysRead,
3757 pdmR3DevHlp_PCIPhysWrite,
3758 pdmR3DevHlp_PCISetIrq,
3759 pdmR3DevHlp_PCISetIrqNoWait,
3760 pdmR3DevHlp_ISASetIrq,
3761 pdmR3DevHlp_ISASetIrqNoWait,
3762 pdmR3DevHlp_IoApicSendMsi,
3763 pdmR3DevHlp_DriverAttach,
3764 pdmR3DevHlp_DriverDetach,
3765 pdmR3DevHlp_QueueCreate,
3766 pdmR3DevHlp_CritSectInit,
3767 pdmR3DevHlp_CritSectGetNop,
3768 pdmR3DevHlp_CritSectGetNopR0,
3769 pdmR3DevHlp_CritSectGetNopRC,
3770 pdmR3DevHlp_SetDeviceCritSect,
3771 pdmR3DevHlp_ThreadCreate,
3772 pdmR3DevHlp_SetAsyncNotification,
3773 pdmR3DevHlp_AsyncNotificationCompleted,
3774 pdmR3DevHlp_RTCRegister,
3775 pdmR3DevHlp_PCIBusRegister,
3776 pdmR3DevHlp_PICRegister,
3777 pdmR3DevHlp_APICRegister,
3778 pdmR3DevHlp_IOAPICRegister,
3779 pdmR3DevHlp_HPETRegister,
3780 pdmR3DevHlp_PciRawRegister,
3781 pdmR3DevHlp_DMACRegister,
3782 pdmR3DevHlp_DMARegister,
3783 pdmR3DevHlp_DMAReadMemory,
3784 pdmR3DevHlp_DMAWriteMemory,
3785 pdmR3DevHlp_DMASetDREQ,
3786 pdmR3DevHlp_DMAGetChannelMode,
3787 pdmR3DevHlp_DMASchedule,
3788 pdmR3DevHlp_CMOSWrite,
3789 pdmR3DevHlp_CMOSRead,
3790 pdmR3DevHlp_AssertEMT,
3791 pdmR3DevHlp_AssertOther,
3792 pdmR3DevHlp_LdrGetRCInterfaceSymbols,
3793 pdmR3DevHlp_LdrGetR0InterfaceSymbols,
3794 pdmR3DevHlp_CallR0,
3795 pdmR3DevHlp_VMGetSuspendReason,
3796 pdmR3DevHlp_VMGetResumeReason,
3797 pdmR3DevHlp_PhysBulkGCPhys2CCPtr,
3798 pdmR3DevHlp_PhysBulkGCPhys2CCPtrReadOnly,
3799 pdmR3DevHlp_PhysBulkReleasePageMappingLocks,
3800 0,
3801 0,
3802 0,
3803 0,
3804 0,
3805 0,
3806 0,
3807 pdmR3DevHlp_GetUVM,
3808 pdmR3DevHlp_GetVM,
3809 pdmR3DevHlp_GetVMCPU,
3810 pdmR3DevHlp_GetCurrentCpuId,
3811 pdmR3DevHlp_RegisterVMMDevHeap,
3812 pdmR3DevHlp_FirmwareRegister,
3813 pdmR3DevHlp_VMReset,
3814 pdmR3DevHlp_VMSuspend,
3815 pdmR3DevHlp_VMSuspendSaveAndPowerOff,
3816 pdmR3DevHlp_VMPowerOff,
3817 pdmR3DevHlp_A20IsEnabled,
3818 pdmR3DevHlp_A20Set,
3819 pdmR3DevHlp_GetCpuId,
3820 pdmR3DevHlp_TMTimeVirtGet,
3821 pdmR3DevHlp_TMTimeVirtGetFreq,
3822 pdmR3DevHlp_TMTimeVirtGetNano,
3823 pdmR3DevHlp_GetSupDrvSession,
3824 pdmR3DevHlp_QueryGenericUserObject,
3825 PDM_DEVHLPR3_VERSION /* the end */
3826};
3827
3828
3829
3830
3831/** @interface_method_impl{PDMDEVHLPR3,pfnGetUVM} */
3832static DECLCALLBACK(PUVM) pdmR3DevHlp_Untrusted_GetUVM(PPDMDEVINS pDevIns)
3833{
3834 PDMDEV_ASSERT_DEVINS(pDevIns);
3835 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3836 return NULL;
3837}
3838
3839
3840/** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */
3841static DECLCALLBACK(PVM) pdmR3DevHlp_Untrusted_GetVM(PPDMDEVINS pDevIns)
3842{
3843 PDMDEV_ASSERT_DEVINS(pDevIns);
3844 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3845 return NULL;
3846}
3847
3848
3849/** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */
3850static DECLCALLBACK(PVMCPU) pdmR3DevHlp_Untrusted_GetVMCPU(PPDMDEVINS pDevIns)
3851{
3852 PDMDEV_ASSERT_DEVINS(pDevIns);
3853 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3854 return NULL;
3855}
3856
3857
3858/** @interface_method_impl{PDMDEVHLPR3,pfnGetCurrentCpuId} */
3859static DECLCALLBACK(VMCPUID) pdmR3DevHlp_Untrusted_GetCurrentCpuId(PPDMDEVINS pDevIns)
3860{
3861 PDMDEV_ASSERT_DEVINS(pDevIns);
3862 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3863 return NIL_VMCPUID;
3864}
3865
3866
3867/** @interface_method_impl{PDMDEVHLPR3,pfnRegisterVMMDevHeap} */
3868static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys,
3869 RTR3PTR pvHeap, unsigned cbHeap)
3870{
3871 PDMDEV_ASSERT_DEVINS(pDevIns);
3872 NOREF(GCPhys); NOREF(pvHeap); NOREF(cbHeap);
3873 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3874 return VERR_ACCESS_DENIED;
3875}
3876
3877
3878/** @interface_method_impl{PDMDEVHLPR3,pfnFirmwareRegister} */
3879static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_FirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
3880{
3881 PDMDEV_ASSERT_DEVINS(pDevIns);
3882 NOREF(pFwReg); NOREF(ppFwHlp);
3883 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3884 return VERR_ACCESS_DENIED;
3885}
3886
3887
3888/** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */
3889static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
3890{
3891 PDMDEV_ASSERT_DEVINS(pDevIns); NOREF(fFlags);
3892 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3893 return VERR_ACCESS_DENIED;
3894}
3895
3896
3897/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */
3898static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspend(PPDMDEVINS pDevIns)
3899{
3900 PDMDEV_ASSERT_DEVINS(pDevIns);
3901 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3902 return VERR_ACCESS_DENIED;
3903}
3904
3905
3906/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspendSaveAndPowerOff} */
3907static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
3908{
3909 PDMDEV_ASSERT_DEVINS(pDevIns);
3910 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3911 return VERR_ACCESS_DENIED;
3912}
3913
3914
3915/** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */
3916static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMPowerOff(PPDMDEVINS pDevIns)
3917{
3918 PDMDEV_ASSERT_DEVINS(pDevIns);
3919 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3920 return VERR_ACCESS_DENIED;
3921}
3922
3923
3924/** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */
3925static DECLCALLBACK(bool) pdmR3DevHlp_Untrusted_A20IsEnabled(PPDMDEVINS pDevIns)
3926{
3927 PDMDEV_ASSERT_DEVINS(pDevIns);
3928 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3929 return false;
3930}
3931
3932
3933/** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */
3934static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_A20Set(PPDMDEVINS pDevIns, bool fEnable)
3935{
3936 PDMDEV_ASSERT_DEVINS(pDevIns);
3937 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3938 NOREF(fEnable);
3939}
3940
3941
3942/** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */
3943static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
3944 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
3945{
3946 PDMDEV_ASSERT_DEVINS(pDevIns);
3947 NOREF(iLeaf); NOREF(pEax); NOREF(pEbx); NOREF(pEcx); NOREF(pEdx);
3948 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3949}
3950
3951
3952/** @interface_method_impl{PDMDEVHLPR3,pfnGetSupDrvSession} */
3953static DECLCALLBACK(PSUPDRVSESSION) pdmR3DevHlp_Untrusted_GetSupDrvSession(PPDMDEVINS pDevIns)
3954{
3955 PDMDEV_ASSERT_DEVINS(pDevIns);
3956 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3957 return (PSUPDRVSESSION)0;
3958}
3959
3960
3961/** @interface_method_impl{PDMDEVHLPR3,pfnQueryGenericUserObject} */
3962static DECLCALLBACK(void *) pdmR3DevHlp_Untrusted_QueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
3963{
3964 PDMDEV_ASSERT_DEVINS(pDevIns);
3965 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d %RTuuid\n",
3966 pDevIns->pReg->szName, pDevIns->iInstance, pUuid));
3967 return NULL;
3968}
3969
3970
3971/**
3972 * The device helper structure for non-trusted devices.
3973 */
3974const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted =
3975{
3976 PDM_DEVHLPR3_VERSION,
3977 pdmR3DevHlp_IOPortRegister,
3978 pdmR3DevHlp_IOPortRegisterRC,
3979 pdmR3DevHlp_IOPortRegisterR0,
3980 pdmR3DevHlp_IOPortDeregister,
3981 pdmR3DevHlp_MMIORegister,
3982 pdmR3DevHlp_MMIORegisterRC,
3983 pdmR3DevHlp_MMIORegisterR0,
3984 pdmR3DevHlp_MMIODeregister,
3985 pdmR3DevHlp_MMIO2Register,
3986 pdmR3DevHlp_MMIOExPreRegister,
3987 pdmR3DevHlp_MMIOExDeregister,
3988 pdmR3DevHlp_MMIOExMap,
3989 pdmR3DevHlp_MMIOExUnmap,
3990 pdmR3DevHlp_MMIOExReduce,
3991 pdmR3DevHlp_MMHyperMapMMIO2,
3992 pdmR3DevHlp_MMIO2MapKernel,
3993 pdmR3DevHlp_ROMRegister,
3994 pdmR3DevHlp_ROMProtectShadow,
3995 pdmR3DevHlp_SSMRegister,
3996 pdmR3DevHlp_TMTimerCreate,
3997 pdmR3DevHlp_TMUtcNow,
3998 pdmR3DevHlp_PhysRead,
3999 pdmR3DevHlp_PhysWrite,
4000 pdmR3DevHlp_PhysGCPhys2CCPtr,
4001 pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
4002 pdmR3DevHlp_PhysReleasePageMappingLock,
4003 pdmR3DevHlp_PhysReadGCVirt,
4004 pdmR3DevHlp_PhysWriteGCVirt,
4005 pdmR3DevHlp_PhysGCPtr2GCPhys,
4006 pdmR3DevHlp_MMHeapAlloc,
4007 pdmR3DevHlp_MMHeapAllocZ,
4008 pdmR3DevHlp_MMHeapFree,
4009 pdmR3DevHlp_VMState,
4010 pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,
4011 pdmR3DevHlp_VMSetError,
4012 pdmR3DevHlp_VMSetErrorV,
4013 pdmR3DevHlp_VMSetRuntimeError,
4014 pdmR3DevHlp_VMSetRuntimeErrorV,
4015 pdmR3DevHlp_DBGFStopV,
4016 pdmR3DevHlp_DBGFInfoRegister,
4017 pdmR3DevHlp_DBGFRegRegister,
4018 pdmR3DevHlp_DBGFTraceBuf,
4019 pdmR3DevHlp_STAMRegister,
4020 pdmR3DevHlp_STAMRegisterF,
4021 pdmR3DevHlp_STAMRegisterV,
4022 pdmR3DevHlp_PCIRegister,
4023 pdmR3DevHlp_PCIRegisterMsi,
4024 pdmR3DevHlp_PCIIORegionRegister,
4025 pdmR3DevHlp_PCISetConfigCallbacks,
4026 pdmR3DevHlp_PCIPhysRead,
4027 pdmR3DevHlp_PCIPhysWrite,
4028 pdmR3DevHlp_PCISetIrq,
4029 pdmR3DevHlp_PCISetIrqNoWait,
4030 pdmR3DevHlp_ISASetIrq,
4031 pdmR3DevHlp_ISASetIrqNoWait,
4032 pdmR3DevHlp_IoApicSendMsi,
4033 pdmR3DevHlp_DriverAttach,
4034 pdmR3DevHlp_DriverDetach,
4035 pdmR3DevHlp_QueueCreate,
4036 pdmR3DevHlp_CritSectInit,
4037 pdmR3DevHlp_CritSectGetNop,
4038 pdmR3DevHlp_CritSectGetNopR0,
4039 pdmR3DevHlp_CritSectGetNopRC,
4040 pdmR3DevHlp_SetDeviceCritSect,
4041 pdmR3DevHlp_ThreadCreate,
4042 pdmR3DevHlp_SetAsyncNotification,
4043 pdmR3DevHlp_AsyncNotificationCompleted,
4044 pdmR3DevHlp_RTCRegister,
4045 pdmR3DevHlp_PCIBusRegister,
4046 pdmR3DevHlp_PICRegister,
4047 pdmR3DevHlp_APICRegister,
4048 pdmR3DevHlp_IOAPICRegister,
4049 pdmR3DevHlp_HPETRegister,
4050 pdmR3DevHlp_PciRawRegister,
4051 pdmR3DevHlp_DMACRegister,
4052 pdmR3DevHlp_DMARegister,
4053 pdmR3DevHlp_DMAReadMemory,
4054 pdmR3DevHlp_DMAWriteMemory,
4055 pdmR3DevHlp_DMASetDREQ,
4056 pdmR3DevHlp_DMAGetChannelMode,
4057 pdmR3DevHlp_DMASchedule,
4058 pdmR3DevHlp_CMOSWrite,
4059 pdmR3DevHlp_CMOSRead,
4060 pdmR3DevHlp_AssertEMT,
4061 pdmR3DevHlp_AssertOther,
4062 pdmR3DevHlp_LdrGetRCInterfaceSymbols,
4063 pdmR3DevHlp_LdrGetR0InterfaceSymbols,
4064 pdmR3DevHlp_CallR0,
4065 pdmR3DevHlp_VMGetSuspendReason,
4066 pdmR3DevHlp_VMGetResumeReason,
4067 pdmR3DevHlp_PhysBulkGCPhys2CCPtr,
4068 pdmR3DevHlp_PhysBulkGCPhys2CCPtrReadOnly,
4069 pdmR3DevHlp_PhysBulkReleasePageMappingLocks,
4070 0,
4071 0,
4072 0,
4073 0,
4074 0,
4075 0,
4076 0,
4077 pdmR3DevHlp_Untrusted_GetUVM,
4078 pdmR3DevHlp_Untrusted_GetVM,
4079 pdmR3DevHlp_Untrusted_GetVMCPU,
4080 pdmR3DevHlp_Untrusted_GetCurrentCpuId,
4081 pdmR3DevHlp_Untrusted_RegisterVMMDevHeap,
4082 pdmR3DevHlp_Untrusted_FirmwareRegister,
4083 pdmR3DevHlp_Untrusted_VMReset,
4084 pdmR3DevHlp_Untrusted_VMSuspend,
4085 pdmR3DevHlp_Untrusted_VMSuspendSaveAndPowerOff,
4086 pdmR3DevHlp_Untrusted_VMPowerOff,
4087 pdmR3DevHlp_Untrusted_A20IsEnabled,
4088 pdmR3DevHlp_Untrusted_A20Set,
4089 pdmR3DevHlp_Untrusted_GetCpuId,
4090 pdmR3DevHlp_TMTimeVirtGet,
4091 pdmR3DevHlp_TMTimeVirtGetFreq,
4092 pdmR3DevHlp_TMTimeVirtGetNano,
4093 pdmR3DevHlp_Untrusted_GetSupDrvSession,
4094 pdmR3DevHlp_Untrusted_QueryGenericUserObject,
4095 PDM_DEVHLPR3_VERSION /* the end */
4096};
4097
4098
4099
4100/**
4101 * Queue consumer callback for internal component.
4102 *
4103 * @returns Success indicator.
4104 * If false the item will not be removed and the flushing will stop.
4105 * @param pVM The cross context VM structure.
4106 * @param pItem The item to consume. Upon return this item will be freed.
4107 */
4108DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem)
4109{
4110 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)pItem;
4111 LogFlow(("pdmR3DevHlpQueueConsumer: enmOp=%d pDevIns=%p\n", pTask->enmOp, pTask->pDevInsR3));
4112 switch (pTask->enmOp)
4113 {
4114 case PDMDEVHLPTASKOP_ISA_SET_IRQ:
4115 PDMIsaSetIrq(pVM, pTask->u.IsaSetIRQ.iIrq, pTask->u.IsaSetIRQ.iLevel, pTask->u.IsaSetIRQ.uTagSrc);
4116 break;
4117
4118 case PDMDEVHLPTASKOP_PCI_SET_IRQ:
4119 {
4120 /* Same as pdmR3DevHlp_PCISetIrq, except we've got a tag already. */
4121 PPDMPCIDEV pPciDev = pTask->u.PciSetIRQ.pPciDevR3;
4122 if (pPciDev)
4123 {
4124 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
4125 Assert(pBus);
4126
4127 pdmLock(pVM);
4128 pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, pTask->u.PciSetIRQ.iIrq,
4129 pTask->u.PciSetIRQ.iLevel, pTask->u.PciSetIRQ.uTagSrc);
4130 pdmUnlock(pVM);
4131 }
4132 else
4133 AssertReleaseMsgFailed(("No PCI device registered!\n"));
4134 break;
4135 }
4136
4137 case PDMDEVHLPTASKOP_IOAPIC_SET_IRQ:
4138 PDMIoApicSetIrq(pVM, pTask->u.IoApicSetIRQ.iIrq, pTask->u.IoApicSetIRQ.iLevel, pTask->u.IoApicSetIRQ.uTagSrc);
4139 break;
4140
4141 default:
4142 AssertReleaseMsgFailed(("Invalid operation %d\n", pTask->enmOp));
4143 break;
4144 }
4145 return true;
4146}
4147
4148/** @} */
4149
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