NEMR3Native-darwin-armv8.cpp@ 99739

Last change on this file since 99739 was 99739, checked in by vboxsync, 2 years ago
*: doxygen corrections (mostly about removing @returns from functions returning void).
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1	/* $Id: NEMR3Native-darwin-armv8.cpp 99739 2023-05-11 01:01:08Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-3 macOS backend using Hypervisor.framework, ARMv8 variant.
4	*
5	* Log group 2: Exit logging.
6	* Log group 3: Log context on exit.
7	* Log group 5: Ring-3 memory management
8	*/
9
10	/*
11	* Copyright (C) 2023 Oracle and/or its affiliates.
12	*
13	* This file is part of VirtualBox base platform packages, as
14	* available from https://www.virtualbox.org.
15	*
16	* This program is free software; you can redistribute it and/or
17	* modify it under the terms of the GNU General Public License
18	* as published by the Free Software Foundation, in version 3 of the
19	* License.
20	*
21	* This program is distributed in the hope that it will be useful, but
22	* WITHOUT ANY WARRANTY; without even the implied warranty of
23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24	* General Public License for more details.
25	*
26	* You should have received a copy of the GNU General Public License
27	* along with this program; if not, see <https://www.gnu.org/licenses>.
28	*
29	* SPDX-License-Identifier: GPL-3.0-only
30	*/
31
32
33	/*********************************************************************************************************************************
34	* Header Files *
35	*********************************************************************************************************************************/
36	#define LOG_GROUP LOG_GROUP_NEM
37	#define VMCPU_INCL_CPUM_GST_CTX
38	#define CPUM_WITH_NONCONST_HOST_FEATURES /* required for initializing parts of the g_CpumHostFeatures structure here. */
39	#include <VBox/vmm/nem.h>
40	#include <VBox/vmm/iem.h>
41	#include <VBox/vmm/em.h>
42	#include <VBox/vmm/gic.h>
43	#include <VBox/vmm/pdm.h>
44	#include <VBox/vmm/dbgftrace.h>
45	#include <VBox/vmm/gcm.h>
46	#include "NEMInternal.h"
47	#include <VBox/vmm/vmcc.h>
48	#include "dtrace/VBoxVMM.h"
49
50	#include <iprt/armv8.h>
51	#include <iprt/asm.h>
52	#include <iprt/ldr.h>
53	#include <iprt/mem.h>
54	#include <iprt/path.h>
55	#include <iprt/string.h>
56	#include <iprt/system.h>
57	#include <iprt/utf16.h>
58
59	#include <mach/mach_time.h>
60	#include <mach/kern_return.h>
61
62	#include <Hypervisor/Hypervisor.h>
63
64
65	/*********************************************************************************************************************************
66	* Defined Constants And Macros *
67	*********************************************************************************************************************************/
68
69
70	/** @todo The vTimer PPI for the virt platform, make it configurable. */
71	#define NEM_DARWIN_VTIMER_GIC_PPI_IRQ 11
72
73
74	/*********************************************************************************************************************************
75	* Structures and Typedefs *
76	*********************************************************************************************************************************/
77
78
79	/*********************************************************************************************************************************
80	* Global Variables *
81	*********************************************************************************************************************************/
82	/** NEM_DARWIN_PAGE_STATE_XXX names. */
83	NEM_TMPL_STATIC const char * const g_apszPageStates[4] = { "not-set", "unmapped", "readable", "writable" };
84	/** The general registers. */
85	static const struct
86	{
87	hv_reg_t enmHvReg;
88	uint32_t fCpumExtrn;
89	uint32_t offCpumCtx;
90	} s_aCpumRegs[] =
91	{
92	#define CPUM_GREG_EMIT_X0_X3(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X ## a_Idx, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
93	#define CPUM_GREG_EMIT_X4_X28(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X4_X28, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
94	CPUM_GREG_EMIT_X0_X3(0),
95	CPUM_GREG_EMIT_X0_X3(1),
96	CPUM_GREG_EMIT_X0_X3(2),
97	CPUM_GREG_EMIT_X0_X3(3),
98	CPUM_GREG_EMIT_X4_X28(4),
99	CPUM_GREG_EMIT_X4_X28(5),
100	CPUM_GREG_EMIT_X4_X28(6),
101	CPUM_GREG_EMIT_X4_X28(7),
102	CPUM_GREG_EMIT_X4_X28(8),
103	CPUM_GREG_EMIT_X4_X28(9),
104	CPUM_GREG_EMIT_X4_X28(10),
105	CPUM_GREG_EMIT_X4_X28(11),
106	CPUM_GREG_EMIT_X4_X28(12),
107	CPUM_GREG_EMIT_X4_X28(13),
108	CPUM_GREG_EMIT_X4_X28(14),
109	CPUM_GREG_EMIT_X4_X28(15),
110	CPUM_GREG_EMIT_X4_X28(16),
111	CPUM_GREG_EMIT_X4_X28(17),
112	CPUM_GREG_EMIT_X4_X28(18),
113	CPUM_GREG_EMIT_X4_X28(19),
114	CPUM_GREG_EMIT_X4_X28(20),
115	CPUM_GREG_EMIT_X4_X28(21),
116	CPUM_GREG_EMIT_X4_X28(22),
117	CPUM_GREG_EMIT_X4_X28(23),
118	CPUM_GREG_EMIT_X4_X28(24),
119	CPUM_GREG_EMIT_X4_X28(25),
120	CPUM_GREG_EMIT_X4_X28(26),
121	CPUM_GREG_EMIT_X4_X28(27),
122	CPUM_GREG_EMIT_X4_X28(28),
123	{ HV_REG_FP, CPUMCTX_EXTRN_FP, RT_UOFFSETOF(CPUMCTX, aGRegs[29].x) },
124	{ HV_REG_LR, CPUMCTX_EXTRN_LR, RT_UOFFSETOF(CPUMCTX, aGRegs[30].x) },
125	{ HV_REG_PC, CPUMCTX_EXTRN_PC, RT_UOFFSETOF(CPUMCTX, Pc.u64) },
126	{ HV_REG_FPCR, CPUMCTX_EXTRN_FPCR, RT_UOFFSETOF(CPUMCTX, fpcr) },
127	{ HV_REG_FPSR, CPUMCTX_EXTRN_FPSR, RT_UOFFSETOF(CPUMCTX, fpsr) }
128	#undef CPUM_GREG_EMIT_X0_X3
129	#undef CPUM_GREG_EMIT_X4_X28
130	};
131	/** SIMD/FP registers. */
132	static const struct
133	{
134	hv_simd_fp_reg_t enmHvReg;
135	uint32_t offCpumCtx;
136	} s_aCpumFpRegs[] =
137	{
138	#define CPUM_VREG_EMIT(a_Idx) { HV_SIMD_FP_REG_Q ## a_Idx, RT_UOFFSETOF(CPUMCTX, aVRegs[a_Idx].v) }
139	CPUM_VREG_EMIT(0),
140	CPUM_VREG_EMIT(1),
141	CPUM_VREG_EMIT(2),
142	CPUM_VREG_EMIT(3),
143	CPUM_VREG_EMIT(4),
144	CPUM_VREG_EMIT(5),
145	CPUM_VREG_EMIT(6),
146	CPUM_VREG_EMIT(7),
147	CPUM_VREG_EMIT(8),
148	CPUM_VREG_EMIT(9),
149	CPUM_VREG_EMIT(10),
150	CPUM_VREG_EMIT(11),
151	CPUM_VREG_EMIT(12),
152	CPUM_VREG_EMIT(13),
153	CPUM_VREG_EMIT(14),
154	CPUM_VREG_EMIT(15),
155	CPUM_VREG_EMIT(16),
156	CPUM_VREG_EMIT(17),
157	CPUM_VREG_EMIT(18),
158	CPUM_VREG_EMIT(19),
159	CPUM_VREG_EMIT(20),
160	CPUM_VREG_EMIT(21),
161	CPUM_VREG_EMIT(22),
162	CPUM_VREG_EMIT(23),
163	CPUM_VREG_EMIT(24),
164	CPUM_VREG_EMIT(25),
165	CPUM_VREG_EMIT(26),
166	CPUM_VREG_EMIT(27),
167	CPUM_VREG_EMIT(28),
168	CPUM_VREG_EMIT(29),
169	CPUM_VREG_EMIT(30),
170	CPUM_VREG_EMIT(31)
171	#undef CPUM_VREG_EMIT
172	};
173	/** System registers. */
174	static const struct
175	{
176	hv_sys_reg_t enmHvReg;
177	uint32_t fCpumExtrn;
178	uint32_t offCpumCtx;
179	} s_aCpumSysRegs[] =
180	{
181	{ HV_SYS_REG_SP_EL0, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64) },
182	{ HV_SYS_REG_SP_EL1, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64) },
183	{ HV_SYS_REG_SPSR_EL1, CPUMCTX_EXTRN_SPSR, RT_UOFFSETOF(CPUMCTX, Spsr.u64) },
184	{ HV_SYS_REG_ELR_EL1, CPUMCTX_EXTRN_ELR, RT_UOFFSETOF(CPUMCTX, Elr.u64) },
185	{ HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Sctlr.u64) },
186	{ HV_SYS_REG_TCR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Tcr.u64) },
187	{ HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr0.u64) },
188	{ HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr1.u64) },
189	};
190
191
192	/*********************************************************************************************************************************
193	* Internal Functions *
194	*********************************************************************************************************************************/
195
196
197	/**
198	* Converts a HV return code to a VBox status code.
199	*
200	* @returns VBox status code.
201	* @param hrc The HV return code to convert.
202	*/
203	DECLINLINE(int) nemR3DarwinHvSts2Rc(hv_return_t hrc)
204	{
205	if (hrc == HV_SUCCESS)
206	return VINF_SUCCESS;
207
208	switch (hrc)
209	{
210	case HV_ERROR: return VERR_INVALID_STATE;
211	case HV_BUSY: return VERR_RESOURCE_BUSY;
212	case HV_BAD_ARGUMENT: return VERR_INVALID_PARAMETER;
213	case HV_NO_RESOURCES: return VERR_OUT_OF_RESOURCES;
214	case HV_NO_DEVICE: return VERR_NOT_FOUND;
215	case HV_UNSUPPORTED: return VERR_NOT_SUPPORTED;
216	}
217
218	return VERR_IPE_UNEXPECTED_STATUS;
219	}
220
221
222	/**
223	* Returns a human readable string of the given exception class.
224	*
225	* @returns Pointer to the string matching the given EC.
226	* @param u32Ec The exception class to return the string for.
227	*/
228	static const char *nemR3DarwinEsrEl2EcStringify(uint32_t u32Ec)
229	{
230	switch (u32Ec)
231	{
232	#define ARMV8_EC_CASE(a_Ec) case a_Ec: return #a_Ec
233	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_UNKNOWN);
234	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TRAPPED_WFX);
235	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15);
236	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15);
237	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14);
238	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC);
239	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON);
240	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS);
241	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN);
242	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_LS64_EXCEPTION);
243	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14);
244	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION);
245	ARMV8_EC_CASE(ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE);
246	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN);
247	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN);
248	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN);
249	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN);
250	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN);
251	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN);
252	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN);
253	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SVE_TRAPPED);
254	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB);
255	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION);
256	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION);
257	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS);
258	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION);
259	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL);
260	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2);
261	ARMV8_EC_CASE(ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION);
262	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL);
263	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2);
264	ARMV8_EC_CASE(ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION);
265	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_MOPS_EXCEPTION);
266	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION);
267	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION);
268	ARMV8_EC_CASE(ARMV8_ESR_EL2_SERROR_INTERRUPT);
269	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL);
270	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2);
271	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL);
272	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2);
273	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL);
274	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2);
275	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN);
276	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION);
277	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN);
278	#undef ARMV8_EC_CASE
279	default:
280	break;
281	}
282
283	return "<INVALID>";
284	}
285
286
287	/**
288	* Resolves a NEM page state from the given protection flags.
289	*
290	* @returns NEM page state.
291	* @param fPageProt The page protection flags.
292	*/
293	DECLINLINE(uint8_t) nemR3DarwinPageStateFromProt(uint32_t fPageProt)
294	{
295	switch (fPageProt)
296	{
297	case NEM_PAGE_PROT_NONE:
298	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
299	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE:
300	return NEM_DARWIN_PAGE_STATE_RX;
301	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE:
302	return NEM_DARWIN_PAGE_STATE_RW;
303	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE:
304	return NEM_DARWIN_PAGE_STATE_RWX;
305	default:
306	break;
307	}
308
309	AssertLogRelMsgFailed(("Invalid combination of page protection flags %#x, can't map to page state!\n", fPageProt));
310	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
311	}
312
313
314	/**
315	* Unmaps the given guest physical address range (page aligned).
316	*
317	* @returns VBox status code.
318	* @param pVM The cross context VM structure.
319	* @param GCPhys The guest physical address to start unmapping at.
320	* @param cb The size of the range to unmap in bytes.
321	* @param pu2State Where to store the new state of the unmappd page, optional.
322	*/
323	DECLINLINE(int) nemR3DarwinUnmap(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint8_t *pu2State)
324	{
325	if (*pu2State <= NEM_DARWIN_PAGE_STATE_UNMAPPED)
326	{
327	Log5(("nemR3DarwinUnmap: %RGp == unmapped\n", GCPhys));
328	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
329	return VINF_SUCCESS;
330	}
331
332	LogFlowFunc(("Unmapping %RGp LB %zu\n", GCPhys, cb));
333	hv_return_t hrc = hv_vm_unmap(GCPhys, cb);
334	if (RT_LIKELY(hrc == HV_SUCCESS))
335	{
336	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
337	if (pu2State)
338	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
339	Log5(("nemR3DarwinUnmap: %RGp => unmapped\n", GCPhys));
340	return VINF_SUCCESS;
341	}
342
343	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
344	LogRel(("nemR3DarwinUnmap(%RGp): failed! hrc=%#x\n",
345	GCPhys, hrc));
346	return VERR_NEM_IPE_6;
347	}
348
349
350	/**
351	* Maps a given guest physical address range backed by the given memory with the given
352	* protection flags.
353	*
354	* @returns VBox status code.
355	* @param pVM The cross context VM structure.
356	* @param GCPhys The guest physical address to start mapping.
357	* @param pvRam The R3 pointer of the memory to back the range with.
358	* @param cb The size of the range, page aligned.
359	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
360	* @param pu2State Where to store the state for the new page, optional.
361	*/
362	DECLINLINE(int) nemR3DarwinMap(PVM pVM, RTGCPHYS GCPhys, const void pvRam, size_t cb, uint32_t fPageProt, uint8_t pu2State)
363	{
364	LogFlowFunc(("Mapping %RGp LB %zu fProt=%#x\n", GCPhys, cb, fPageProt));
365
366	Assert(fPageProt != NEM_PAGE_PROT_NONE);
367	RT_NOREF(pVM);
368
369	hv_memory_flags_t fHvMemProt = 0;
370	if (fPageProt & NEM_PAGE_PROT_READ)
371	fHvMemProt \|= HV_MEMORY_READ;
372	if (fPageProt & NEM_PAGE_PROT_WRITE)
373	fHvMemProt \|= HV_MEMORY_WRITE;
374	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
375	fHvMemProt \|= HV_MEMORY_EXEC;
376
377	hv_return_t hrc = hv_vm_map((void *)pvRam, GCPhys, cb, fHvMemProt);
378	if (hrc == HV_SUCCESS)
379	{
380	if (pu2State)
381	*pu2State = nemR3DarwinPageStateFromProt(fPageProt);
382	return VINF_SUCCESS;
383	}
384
385	return nemR3DarwinHvSts2Rc(hrc);
386	}
387
388	#if 0 /* unused */
389	DECLINLINE(int) nemR3DarwinProtectPage(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint32_t fPageProt)
390	{
391	hv_memory_flags_t fHvMemProt = 0;
392	if (fPageProt & NEM_PAGE_PROT_READ)
393	fHvMemProt \|= HV_MEMORY_READ;
394	if (fPageProt & NEM_PAGE_PROT_WRITE)
395	fHvMemProt \|= HV_MEMORY_WRITE;
396	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
397	fHvMemProt \|= HV_MEMORY_EXEC;
398
399	hv_return_t hrc;
400	if (pVM->nem.s.fCreatedAsid)
401	hrc = hv_vm_protect_space(pVM->nem.s.uVmAsid, GCPhys, cb, fHvMemProt);
402	else
403	hrc = hv_vm_protect(GCPhys, cb, fHvMemProt);
404
405	return nemR3DarwinHvSts2Rc(hrc);
406	}
407	#endif
408
409	DECLINLINE(int) nemR3NativeGCPhys2R3PtrReadOnly(PVM pVM, RTGCPHYS GCPhys, const void **ppv)
410	{
411	PGMPAGEMAPLOCK Lock;
412	int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, ppv, &Lock);
413	if (RT_SUCCESS(rc))
414	PGMPhysReleasePageMappingLock(pVM, &Lock);
415	return rc;
416	}
417
418
419	DECLINLINE(int) nemR3NativeGCPhys2R3PtrWriteable(PVM pVM, RTGCPHYS GCPhys, void **ppv)
420	{
421	PGMPAGEMAPLOCK Lock;
422	int rc = PGMPhysGCPhys2CCPtr(pVM, GCPhys, ppv, &Lock);
423	if (RT_SUCCESS(rc))
424	PGMPhysReleasePageMappingLock(pVM, &Lock);
425	return rc;
426	}
427
428
429	#ifdef LOG_ENABLED
430	/**
431	* Logs the current CPU state.
432	*/
433	static void nemR3DarwinLogState(PVMCC pVM, PVMCPUCC pVCpu)
434	{
435	if (LogIs3Enabled())
436	{
437	char szRegs[4096];
438	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
439	"x0=%016VR{x0} x1=%016VR{x1} x2=%016VR{x2} x3=%016VR{x3}\n"
440	"x4=%016VR{x4} x5=%016VR{x5} x6=%016VR{x6} x7=%016VR{x7}\n"
441	"x8=%016VR{x8} x9=%016VR{x9} x10=%016VR{x10} x11=%016VR{x11}\n"
442	"x12=%016VR{x12} x13=%016VR{x13} x14=%016VR{x14} x15=%016VR{x15}\n"
443	"x16=%016VR{x16} x17=%016VR{x17} x18=%016VR{x18} x19=%016VR{x19}\n"
444	"x20=%016VR{x20} x21=%016VR{x21} x22=%016VR{x22} x23=%016VR{x23}\n"
445	"x24=%016VR{x24} x25=%016VR{x25} x26=%016VR{x26} x27=%016VR{x27}\n"
446	"x28=%016VR{x28} x29=%016VR{x29} x30=%016VR{x30}\n"
447	"pc=%016VR{pc} pstate=%016VR{pstate}\n"
448	"sp_el0=%016VR{sp_el0} sp_el1=%016VR{sp_el1} elr_el1=%016VR{elr_el1}\n"
449	"sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n"
450	"ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
451	);
452	char szInstr[256]; RT_ZERO(szInstr);
453	#if 0
454	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
455	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
456	szInstr, sizeof(szInstr), NULL);
457	#endif
458	Log3(("%s%s\n", szRegs, szInstr));
459	}
460	}
461	#endif /* LOG_ENABLED */
462
463
464	static int nemR3DarwinCopyStateFromHv(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
465	{
466	RT_NOREF(pVM);
467	hv_return_t hrc = HV_SUCCESS;
468
469	if (fWhat & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
470	{
471	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
472	{
473	if (s_aCpumRegs[i].fCpumExtrn & fWhat)
474	{
475	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
476	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, pu64);
477	}
478	}
479	}
480
481	if ( hrc == HV_SUCCESS
482	&& (fWhat & CPUMCTX_EXTRN_V0_V31))
483	{
484	/* SIMD/FP registers. */
485	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
486	{
487	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
488	hrc \|= hv_vcpu_get_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, pu128);
489	}
490	}
491
492	if ( hrc == HV_SUCCESS
493	&& (fWhat & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR)))
494	{
495	/* System registers. */
496	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
497	{
498	if (s_aCpumSysRegs[i].fCpumExtrn & fWhat)
499	{
500	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
501	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, pu64);
502	}
503	}
504	}
505
506	if ( hrc == HV_SUCCESS
507	&& (fWhat & CPUMCTX_EXTRN_PSTATE))
508	{
509	uint64_t u64Tmp;
510	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
511	if (hrc == HV_SUCCESS)
512	pVCpu->cpum.GstCtx.fPState = (uint32_t)u64Tmp;
513	}
514
515	/* Almost done, just update extern flags. */
516	pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
517	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
518	pVCpu->cpum.GstCtx.fExtrn = 0;
519
520	return nemR3DarwinHvSts2Rc(hrc);
521	}
522
523
524	/**
525	* Exports the guest state to HV for execution.
526	*
527	* @returns VBox status code.
528	* @param pVM The cross context VM structure.
529	* @param pVCpu The cross context virtual CPU structure of the
530	* calling EMT.
531	*/
532	static int nemR3DarwinExportGuestState(PVMCC pVM, PVMCPUCC pVCpu)
533	{
534	RT_NOREF(pVM);
535	hv_return_t hrc = HV_SUCCESS;
536
537	if ( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
538	!= (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
539	{
540	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
541	{
542	if (!(s_aCpumRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
543	{
544	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
545	hrc \|= hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, *pu64);
546	}
547	}
548	}
549
550	if ( hrc == HV_SUCCESS
551	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_V0_V31))
552	{
553	/* SIMD/FP registers. */
554	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
555	{
556	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
557	hrc \|= hv_vcpu_set_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, *pu128);
558	}
559	}
560
561	if ( hrc == HV_SUCCESS
562	&& (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR))
563	!= (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR))
564	{
565	/* System registers. */
566	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
567	{
568	if (!(s_aCpumSysRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
569	{
570	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
571	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, *pu64);
572	}
573	}
574	}
575
576	if ( hrc == HV_SUCCESS
577	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_PSTATE))
578	hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, pVCpu->cpum.GstCtx.fPState);
579
580	pVCpu->cpum.GstCtx.fExtrn \|= CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_NEM;
581	return nemR3DarwinHvSts2Rc(hrc);
582	}
583
584
585	/**
586	* Try initialize the native API.
587	*
588	* This may only do part of the job, more can be done in
589	* nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
590	*
591	* @returns VBox status code.
592	* @param pVM The cross context VM structure.
593	* @param fFallback Whether we're in fallback mode or use-NEM mode. In
594	* the latter we'll fail if we cannot initialize.
595	* @param fForced Whether the HMForced flag is set and we should
596	* fail if we cannot initialize.
597	*/
598	int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
599	{
600	AssertReturn(!pVM->nem.s.fCreatedVm, VERR_WRONG_ORDER);
601
602	/*
603	* Some state init.
604	*/
605	PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
606	RT_NOREF(pCfgNem);
607
608	/*
609	* Error state.
610	* The error message will be non-empty on failure and 'rc' will be set too.
611	*/
612	RTERRINFOSTATIC ErrInfo;
613	PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
614
615	int rc = VINF_SUCCESS;
616	hv_return_t hrc = hv_vm_create(NULL);
617	if (hrc == HV_SUCCESS)
618	{
619	pVM->nem.s.fCreatedVm = true;
620	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
621	Log(("NEM: Marked active!\n"));
622	PGMR3EnableNemMode(pVM);
623	}
624	else
625	rc = RTErrInfoSetF(pErrInfo, VERR_NEM_INIT_FAILED,
626	"hv_vm_create() failed: %#x", hrc);
627
628	/*
629	* We only fail if in forced mode, otherwise just log the complaint and return.
630	*/
631	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API \|\| RTErrInfoIsSet(pErrInfo));
632	if ( (fForced \|\| !fFallback)
633	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
634	return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
635
636	if (RTErrInfoIsSet(pErrInfo))
637	LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
638	return VINF_SUCCESS;
639	}
640
641
642	/**
643	* Worker to create the vCPU handle on the EMT running it later on (as required by HV).
644	*
645	* @returns VBox status code
646	* @param pVM The VM handle.
647	* @param pVCpu The vCPU handle.
648	* @param idCpu ID of the CPU to create.
649	*/
650	static DECLCALLBACK(int) nemR3DarwinNativeInitVCpuOnEmt(PVM pVM, PVMCPU pVCpu, VMCPUID idCpu)
651	{
652	hv_return_t hrc = hv_vcpu_create(&pVCpu->nem.s.hVCpu, &pVCpu->nem.s.pHvExit, NULL);
653	if (hrc != HV_SUCCESS)
654	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
655	"Call to hv_vcpu_create failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
656
657	if (idCpu == 0)
658	{
659	/** @todo */
660	}
661
662	return VINF_SUCCESS;
663	}
664
665
666	/**
667	* Worker to destroy the vCPU handle on the EMT running it later on (as required by HV).
668	*
669	* @returns VBox status code
670	* @param pVCpu The vCPU handle.
671	*/
672	static DECLCALLBACK(int) nemR3DarwinNativeTermVCpuOnEmt(PVMCPU pVCpu)
673	{
674	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
675	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
676	return VINF_SUCCESS;
677	}
678
679
680	/**
681	* This is called after CPUMR3Init is done.
682	*
683	* @returns VBox status code.
684	* @param pVM The VM handle..
685	*/
686	int nemR3NativeInitAfterCPUM(PVM pVM)
687	{
688	/*
689	* Validate sanity.
690	*/
691	AssertReturn(!pVM->nem.s.fCreatedEmts, VERR_WRONG_ORDER);
692	AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
693
694	/*
695	* Setup the EMTs.
696	*/
697	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
698	{
699	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
700
701	int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitVCpuOnEmt, 3, pVM, pVCpu, idCpu);
702	if (RT_FAILURE(rc))
703	{
704	/* Rollback. */
705	while (idCpu--)
706	VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeTermVCpuOnEmt, 1, pVCpu);
707
708	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Call to hv_vcpu_create failed: %Rrc", rc);
709	}
710	}
711
712	pVM->nem.s.fCreatedEmts = true;
713	return VINF_SUCCESS;
714	}
715
716
717	int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
718	{
719	RT_NOREF(pVM, enmWhat);
720	return VINF_SUCCESS;
721	}
722
723
724	int nemR3NativeTerm(PVM pVM)
725	{
726	/*
727	* Delete the VM.
728	*/
729
730	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu--)
731	{
732	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
733
734	/*
735	* Apple's documentation states that the vCPU should be destroyed
736	* on the thread running the vCPU but as all the other EMTs are gone
737	* at this point, destroying the VM would hang.
738	*
739	* We seem to be at luck here though as destroying apparently works
740	* from EMT(0) as well.
741	*/
742	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
743	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
744	}
745
746	pVM->nem.s.fCreatedEmts = false;
747	if (pVM->nem.s.fCreatedVm)
748	{
749	hv_return_t hrc = hv_vm_destroy();
750	if (hrc != HV_SUCCESS)
751	LogRel(("NEM: hv_vm_destroy() failed with %#x\n", hrc));
752
753	pVM->nem.s.fCreatedVm = false;
754	}
755	return VINF_SUCCESS;
756	}
757
758
759	/**
760	* VM reset notification.
761	*
762	* @param pVM The cross context VM structure.
763	*/
764	void nemR3NativeReset(PVM pVM)
765	{
766	RT_NOREF(pVM);
767	}
768
769
770	/**
771	* Reset CPU due to INIT IPI or hot (un)plugging.
772	*
773	* @param pVCpu The cross context virtual CPU structure of the CPU being
774	* reset.
775	* @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
776	*/
777	void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
778	{
779	RT_NOREF(pVCpu, fInitIpi);
780	}
781
782
783	/**
784	* Returns the byte size from the given access SAS value.
785	*
786	* @returns Number of bytes to transfer.
787	* @param uSas The SAS value to convert.
788	*/
789	DECLINLINE(size_t) nemR3DarwinGetByteCountFromSas(uint8_t uSas)
790	{
791	switch (uSas)
792	{
793	case ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE: return sizeof(uint8_t);
794	case ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD: return sizeof(uint16_t);
795	case ARMV8_EC_ISS_DATA_ABRT_SAS_WORD: return sizeof(uint32_t);
796	case ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD: return sizeof(uint64_t);
797	default:
798	AssertReleaseFailed();
799	}
800
801	return 0;
802	}
803
804
805	/**
806	* Sets the given general purpose register to the given value.
807	*
808	* @param pVCpu The cross context virtual CPU structure of the
809	* calling EMT.
810	* @param uReg The register index.
811	* @param f64BitReg Flag whether to operate on a 64-bit or 32-bit register.
812	* @param fSignExtend Flag whether to sign extend the value.
813	* @param u64Val The value.
814	*/
815	DECLINLINE(void) nemR3DarwinSetGReg(PVMCPU pVCpu, uint8_t uReg, bool f64BitReg, bool fSignExtend, uint64_t u64Val)
816	{
817	AssertReturnVoid(uReg < 31);
818
819	if (f64BitReg)
820	pVCpu->cpum.GstCtx.aGRegs[uReg].x = fSignExtend ? (int64_t)u64Val : u64Val;
821	else
822	pVCpu->cpum.GstCtx.aGRegs[uReg].w = fSignExtend ? (int32_t)u64Val : u64Val; /** @todo Does this clear the upper half on real hardware? */
823
824	/* Mark the register as not extern anymore. */
825	switch (uReg)
826	{
827	case 0:
828	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X0;
829	break;
830	case 1:
831	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X1;
832	break;
833	case 2:
834	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X2;
835	break;
836	case 3:
837	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X3;
838	break;
839	default:
840	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_X4_X28));
841	/** @todo We need to import all missing registers in order to clear this flag (or just set it in HV from here). */
842	}
843	}
844
845
846	/**
847	* Gets the given general purpose register and returns the value.
848	*
849	* @returns Value from the given register.
850	* @param pVCpu The cross context virtual CPU structure of the
851	* calling EMT.
852	* @param uReg The register index.
853	*/
854	DECLINLINE(uint64_t) nemR3DarwinGetGReg(PVMCPU pVCpu, uint8_t uReg)
855	{
856	AssertReturn(uReg <= ARMV8_AARCH64_REG_ZR, 0);
857
858	if (uReg == ARMV8_AARCH64_REG_ZR)
859	return 0;
860
861	/** @todo Import the register if extern. */
862	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_GPRS_MASK));
863
864	return pVCpu->cpum.GstCtx.aGRegs[uReg].x;
865	}
866
867
868	/**
869	* Works on the data abort exception (which will be a MMIO access most of the time).
870	*
871	* @returns VBox strict status code.
872	* @param pVM The cross context VM structure.
873	* @param pVCpu The cross context virtual CPU structure of the
874	* calling EMT.
875	* @param uIss The instruction specific syndrome value.
876	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
877	* @param GCPtrDataAbrt The virtual GC address causing the data abort.
878	* @param GCPhysDataAbrt The physical GC address which caused the data abort.
879	*/
880	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionDataAbort(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit,
881	RTGCPTR GCPtrDataAbrt, RTGCPHYS GCPhysDataAbrt)
882	{
883	bool fIsv = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_ISV);
884	bool fL2Fault = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_S1PTW);
885	bool fWrite = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_WNR);
886	bool f64BitReg = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SF);
887	bool fSignExtend = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SSE);
888	uint8_t uReg = ARMV8_EC_ISS_DATA_ABRT_SRT_GET(uIss);
889	uint8_t uAcc = ARMV8_EC_ISS_DATA_ABRT_SAS_GET(uIss);
890	size_t cbAcc = nemR3DarwinGetByteCountFromSas(uAcc);
891	LogFlowFunc(("fIsv=%RTbool fL2Fault=%RTbool fWrite=%RTbool f64BitReg=%RTbool fSignExtend=%RTbool uReg=%u uAcc=%u GCPtrDataAbrt=%RGv GCPhysDataAbrt=%RGp\n",
892	fIsv, fL2Fault, fWrite, f64BitReg, fSignExtend, uReg, uAcc, GCPtrDataAbrt, GCPhysDataAbrt));
893
894	AssertReturn(fIsv, VERR_NOT_SUPPORTED); /** @todo Implement using IEM when this should occur. */
895
896	EMHistoryAddExit(pVCpu,
897	fWrite
898	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
899	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
900	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
901
902	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
903	uint64_t u64Val = 0;
904	if (fWrite)
905	{
906	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
907	rcStrict = PGMPhysWrite(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
908	Log4(("MmioExit/%u: %08RX64: WRITE %#x LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
909	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
910	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
911	}
912	else
913	{
914	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
915	Log4(("MmioExit/%u: %08RX64: READ %#x LB %u -> %.*Rhxs rcStrict=%Rrc\n",
916	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
917	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
918	if (rcStrict == VINF_SUCCESS)
919	nemR3DarwinSetGReg(pVCpu, uReg, f64BitReg, fSignExtend, u64Val);
920	}
921
922	if (rcStrict == VINF_SUCCESS)
923	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
924
925	return rcStrict;
926	}
927
928
929	/**
930	* Works on the trapped MRS, MSR and system instruction exception.
931	*
932	* @returns VBox strict status code.
933	* @param pVM The cross context VM structure.
934	* @param pVCpu The cross context virtual CPU structure of the
935	* calling EMT.
936	* @param uIss The instruction specific syndrome value.
937	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
938	*/
939	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedSysInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit)
940	{
941	bool fRead = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(uIss);
942	uint8_t uCRm = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(uIss);
943	uint8_t uReg = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(uIss);
944	uint8_t uCRn = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(uIss);
945	uint8_t uOp1 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(uIss);
946	uint8_t uOp2 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(uIss);
947	uint8_t uOp0 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(uIss);
948	uint16_t idSysReg = ARMV8_AARCH64_SYSREG_ID_CREATE(uOp0, uOp1, uCRn, uCRm, uOp2);
949	LogFlowFunc(("fRead=%RTbool uCRm=%u uReg=%u uCRn=%u uOp1=%u uOp2=%u uOp0=%u idSysReg=%#x\n",
950	fRead, uCRm, uReg, uCRn, uOp1, uOp2, uOp0, idSysReg));
951
952	/** @todo EMEXITTYPE_MSR_READ/EMEXITTYPE_MSR_WRITE are misnomers. */
953	EMHistoryAddExit(pVCpu,
954	fRead
955	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
956	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
957	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
958
959	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
960	uint64_t u64Val = 0;
961	if (fRead)
962	{
963	RT_NOREF(pVM);
964	rcStrict = CPUMQueryGuestSysReg(pVCpu, idSysReg, &u64Val);
965	Log4(("SysInsnExit/%u: %08RX64: READ %u:%u:%u:%u:%u -> %#RX64 rcStrict=%Rrc\n",
966	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
967	VBOXSTRICTRC_VAL(rcStrict) ));
968	if (rcStrict == VINF_SUCCESS)
969	nemR3DarwinSetGReg(pVCpu, uReg, true /f64BitReg/, false /fSignExtend/, u64Val);
970	}
971	else
972	{
973	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
974	rcStrict = CPUMSetGuestSysReg(pVCpu, idSysReg, u64Val);
975	Log4(("SysInsnExit/%u: %08RX64: WRITE %u:%u:%u:%u:%u %#RX64 -> rcStrict=%Rrc\n",
976	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
977	VBOXSTRICTRC_VAL(rcStrict) ));
978	}
979
980	if (rcStrict == VINF_SUCCESS)
981	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
982
983	return rcStrict;
984	}
985
986
987	/**
988	* Works on the trapped HVC instruction exception.
989	*
990	* @returns VBox strict status code.
991	* @param pVM The cross context VM structure.
992	* @param pVCpu The cross context virtual CPU structure of the
993	* calling EMT.
994	* @param uIss The instruction specific syndrome value.
995	*/
996	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedHvcInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss)
997	{
998	uint16_t u16Imm = ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(uIss);
999	LogFlowFunc(("u16Imm=%#RX16\n", u16Imm));
1000
1001	#if 0 /** @todo For later */
1002	EMHistoryAddExit(pVCpu,
1003	fRead
1004	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1005	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1006	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1007	#endif
1008
1009	RT_NOREF(pVM);
1010	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1011	/** @todo Raise exception to EL1 if PSCI not configured. */
1012	/** @todo Need a generic mechanism here to pass this to, GIM maybe?. Always return -1 for now (PSCI). */
1013	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, true /f64BitReg/, false /fSignExtend/, (uint64_t)-1);
1014
1015	return rcStrict;
1016	}
1017
1018
1019	/**
1020	* Handles an exception VM exit.
1021	*
1022	* @returns VBox strict status code.
1023	* @param pVM The cross context VM structure.
1024	* @param pVCpu The cross context virtual CPU structure of the
1025	* calling EMT.
1026	* @param pExit Pointer to the exit information.
1027	*/
1028	static VBOXSTRICTRC nemR3DarwinHandleExitException(PVM pVM, PVMCPU pVCpu, const hv_vcpu_exit_t *pExit)
1029	{
1030	uint32_t uEc = ARMV8_ESR_EL2_EC_GET(pExit->exception.syndrome);
1031	uint32_t uIss = ARMV8_ESR_EL2_ISS_GET(pExit->exception.syndrome);
1032	bool fInsn32Bit = ARMV8_ESR_EL2_IL_IS_32BIT(pExit->exception.syndrome);
1033
1034	LogFlowFunc(("pVM=%p pVCpu=%p{.idCpu=%u} uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
1035	pVM, pVCpu, pVCpu->idCpu, uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
1036
1037	switch (uEc)
1038	{
1039	case ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL:
1040	return nemR3DarwinHandleExitExceptionDataAbort(pVM, pVCpu, uIss, fInsn32Bit, pExit->exception.virtual_address,
1041	pExit->exception.physical_address);
1042	case ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN:
1043	return nemR3DarwinHandleExitExceptionTrappedSysInsn(pVM, pVCpu, uIss, fInsn32Bit);
1044	case ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN:
1045	return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss);
1046	case ARMV8_ESR_EL2_EC_TRAPPED_WFX:
1047	return VINF_EM_HALT;
1048	case ARMV8_ESR_EL2_EC_UNKNOWN:
1049	default:
1050	LogRel(("NEM/Darwin: Unknown Exception Class in syndrome: uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
1051	uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
1052	AssertReleaseFailed();
1053	return VERR_NOT_IMPLEMENTED;
1054	}
1055
1056	return VINF_SUCCESS;
1057	}
1058
1059
1060	/**
1061	* Handles an exit from hv_vcpu_run().
1062	*
1063	* @returns VBox strict status code.
1064	* @param pVM The cross context VM structure.
1065	* @param pVCpu The cross context virtual CPU structure of the
1066	* calling EMT.
1067	*/
1068	static VBOXSTRICTRC nemR3DarwinHandleExit(PVM pVM, PVMCPU pVCpu)
1069	{
1070	int rc = nemR3DarwinCopyStateFromHv(pVM, pVCpu, CPUMCTX_EXTRN_ALL);
1071	if (RT_FAILURE(rc))
1072	return rc;
1073
1074	#ifdef LOG_ENABLED
1075	if (LogIs3Enabled())
1076	nemR3DarwinLogState(pVM, pVCpu);
1077	#endif
1078
1079	hv_vcpu_exit_t *pExit = pVCpu->nem.s.pHvExit;
1080	switch (pExit->reason)
1081	{
1082	case HV_EXIT_REASON_CANCELED:
1083	return VINF_EM_RAW_INTERRUPT;
1084	case HV_EXIT_REASON_EXCEPTION:
1085	return nemR3DarwinHandleExitException(pVM, pVCpu, pExit);
1086	case HV_EXIT_REASON_VTIMER_ACTIVATED:
1087	pVCpu->nem.s.fVTimerActivated = true;
1088	return GICPpiSet(pVCpu, NEM_DARWIN_VTIMER_GIC_PPI_IRQ, true /fAsserted/);
1089	default:
1090	AssertReleaseFailed();
1091	break;
1092	}
1093
1094	return VERR_INVALID_STATE;
1095	}
1096
1097
1098	/**
1099	* Runs the guest once until an exit occurs.
1100	*
1101	* @returns HV status code.
1102	* @param pVM The cross context VM structure.
1103	* @param pVCpu The cross context virtual CPU structure.
1104	*/
1105	static hv_return_t nemR3DarwinRunGuest(PVM pVM, PVMCPU pVCpu)
1106	{
1107	TMNotifyStartOfExecution(pVM, pVCpu);
1108
1109	hv_return_t hrc = hv_vcpu_run(pVCpu->nem.s.hVCpu);
1110
1111	TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
1112
1113	return hrc;
1114	}
1115
1116
1117	/**
1118	* Prepares the VM to run the guest.
1119	*
1120	* @returns Strict VBox status code.
1121	* @param pVM The cross context VM structure.
1122	* @param pVCpu The cross context virtual CPU structure.
1123	* @param fSingleStepping Flag whether we run in single stepping mode.
1124	*/
1125	static VBOXSTRICTRC nemR3DarwinPreRunGuest(PVM pVM, PVMCPU pVCpu, bool fSingleStepping)
1126	{
1127	#ifdef LOG_ENABLED
1128	bool fIrq = false;
1129	bool fFiq = false;
1130
1131	if (LogIs3Enabled())
1132	nemR3DarwinLogState(pVM, pVCpu);
1133	#endif
1134
1135	/** @todo */ RT_NOREF(fSingleStepping);
1136	int rc = nemR3DarwinExportGuestState(pVM, pVCpu);
1137	AssertRCReturn(rc, rc);
1138
1139	/* Check whether the vTimer interrupt was handled by the guest and we can unmask the vTimer. */
1140	if (pVCpu->nem.s.fVTimerActivated)
1141	{
1142	/* Read the CNTV_CTL_EL0 register. */
1143	uint64_t u64CntvCtl = 0;
1144
1145	hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &u64CntvCtl);
1146	AssertRCReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1147
1148	if ( (u64CntvCtl & (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_IMASK \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
1149	!= (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
1150	{
1151	/* Clear the interrupt. */
1152	GICPpiSet(pVCpu, NEM_DARWIN_VTIMER_GIC_PPI_IRQ, false /fAsserted/);
1153
1154	pVCpu->nem.s.fVTimerActivated = false;
1155	hrc = hv_vcpu_set_vtimer_mask(pVCpu->nem.s.hVCpu, false /vtimer_is_masked/);
1156	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1157	}
1158	}
1159
1160	/* Set the pending interrupt state. */
1161	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ))
1162	{
1163	hv_return_t hrc = HV_SUCCESS;
1164
1165	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ))
1166	{
1167	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, true);
1168	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1169	#ifdef LOG_ENABLED
1170	fIrq = true;
1171	#endif
1172	}
1173
1174	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ))
1175	{
1176	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, true);
1177	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1178	#ifdef LOG_ENABLED
1179	fFiq = true;
1180	#endif
1181	}
1182	}
1183	else
1184	{
1185	hv_return_t hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, false);
1186	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1187
1188	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, false);
1189	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
1190	}
1191
1192	LogFlowFunc(("Running vCPU [%s,%s]\n", fIrq ? "I" : "nI", fFiq ? "F" : "nF"));
1193	pVCpu->nem.s.fEventPending = false;
1194	return VINF_SUCCESS;
1195	}
1196
1197
1198	/**
1199	* The normal runloop (no debugging features enabled).
1200	*
1201	* @returns Strict VBox status code.
1202	* @param pVM The cross context VM structure.
1203	* @param pVCpu The cross context virtual CPU structure.
1204	*/
1205	static VBOXSTRICTRC nemR3DarwinRunGuestNormal(PVM pVM, PVMCPU pVCpu)
1206	{
1207	/*
1208	* The run loop.
1209	*
1210	* Current approach to state updating to use the sledgehammer and sync
1211	* everything every time. This will be optimized later.
1212	*/
1213
1214	/*
1215	* Poll timers and run for a bit.
1216	*/
1217	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
1218	* the whole polling job when timers have changed... */
1219	uint64_t offDeltaIgnored;
1220	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
1221	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1222	for (unsigned iLoop = 0;; iLoop++)
1223	{
1224	rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, false /* fSingleStepping */);
1225	if (rcStrict != VINF_SUCCESS)
1226	break;
1227
1228	hv_return_t hrc = nemR3DarwinRunGuest(pVM, pVCpu);
1229	if (hrc == HV_SUCCESS)
1230	{
1231	/*
1232	* Deal with the message.
1233	*/
1234	rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
1235	if (rcStrict == VINF_SUCCESS)
1236	{ /* hopefully likely */ }
1237	else
1238	{
1239	LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
1240	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
1241	break;
1242	}
1243	}
1244	else
1245	{
1246	AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
1247	pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
1248	}
1249	} /* the run loop */
1250
1251	return rcStrict;
1252	}
1253
1254
1255	VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
1256	{
1257	#ifdef LOG_ENABLED
1258	if (LogIs3Enabled())
1259	nemR3DarwinLogState(pVM, pVCpu);
1260	#endif
1261
1262	AssertReturn(NEMR3CanExecuteGuest(pVM, pVCpu), VERR_NEM_IPE_9);
1263
1264	/*
1265	* Try switch to NEM runloop state.
1266	*/
1267	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
1268	{ /* likely */ }
1269	else
1270	{
1271	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
1272	LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
1273	return VINF_SUCCESS;
1274	}
1275
1276	VBOXSTRICTRC rcStrict;
1277	#if 0
1278	if ( !pVCpu->nem.s.fUseDebugLoop
1279	&& !nemR3DarwinAnyExpensiveProbesEnabled()
1280	&& !DBGFIsStepping(pVCpu)
1281	&& !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1282	#endif
1283	rcStrict = nemR3DarwinRunGuestNormal(pVM, pVCpu);
1284	#if 0
1285	else
1286	rcStrict = nemR3DarwinRunGuestDebug(pVM, pVCpu);
1287	#endif
1288
1289	if (rcStrict == VINF_EM_RAW_TO_R3)
1290	rcStrict = VINF_SUCCESS;
1291
1292	/*
1293	* Convert any pending HM events back to TRPM due to premature exits.
1294	*
1295	* This is because execution may continue from IEM and we would need to inject
1296	* the event from there (hence place it back in TRPM).
1297	*/
1298	if (pVCpu->nem.s.fEventPending)
1299	{
1300	/** @todo */
1301	}
1302
1303
1304	if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
1305	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
1306
1307	if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL))
1308	{
1309	/* Try anticipate what we might need. */
1310	uint64_t fImport = NEM_DARWIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
1311	if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
1312	\|\| RT_FAILURE(rcStrict))
1313	fImport = CPUMCTX_EXTRN_ALL;
1314	else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ
1315	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
1316	fImport \|= IEM_CPUMCTX_EXTRN_XCPT_MASK;
1317
1318	if (pVCpu->cpum.GstCtx.fExtrn & fImport)
1319	{
1320	/* Only import what is external currently. */
1321	int rc2 = nemR3DarwinCopyStateFromHv(pVM, pVCpu, fImport);
1322	if (RT_SUCCESS(rc2))
1323	pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
1324	else if (RT_SUCCESS(rcStrict))
1325	rcStrict = rc2;
1326	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1327	pVCpu->cpum.GstCtx.fExtrn = 0;
1328	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
1329	}
1330	else
1331	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
1332	}
1333	else
1334	{
1335	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
1336	pVCpu->cpum.GstCtx.fExtrn = 0;
1337	}
1338
1339	return rcStrict;
1340	}
1341
1342
1343	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
1344	{
1345	RT_NOREF(pVM, pVCpu);
1346	return true; /** @todo Are there any cases where we have to emulate? */
1347	}
1348
1349
1350	bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
1351	{
1352	VMCPU_ASSERT_EMT(pVCpu);
1353	bool fOld = pVCpu->nem.s.fSingleInstruction;
1354	pVCpu->nem.s.fSingleInstruction = fEnable;
1355	pVCpu->nem.s.fUseDebugLoop = fEnable \|\| pVM->nem.s.fUseDebugLoop;
1356	return fOld;
1357	}
1358
1359
1360	void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
1361	{
1362	LogFlowFunc(("pVM=%p pVCpu=%p fFlags=%#x\n", pVM, pVCpu, fFlags));
1363
1364	RT_NOREF(pVM, fFlags);
1365
1366	hv_return_t hrc = hv_vcpus_exit(&pVCpu->nem.s.hVCpu, 1);
1367	if (hrc != HV_SUCCESS)
1368	LogRel(("NEM: hv_vcpus_exit(%u, 1) failed with %#x\n", pVCpu->nem.s.hVCpu, hrc));
1369	}
1370
1371
1372	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChanged(PVM pVM, bool fUseDebugLoop)
1373	{
1374	RT_NOREF(pVM, fUseDebugLoop);
1375	AssertReleaseFailed();
1376	return false;
1377	}
1378
1379
1380	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu, bool fUseDebugLoop)
1381	{
1382	RT_NOREF(pVM, pVCpu, fUseDebugLoop);
1383	return fUseDebugLoop;
1384	}
1385
1386
1387	VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
1388	uint8_t pu2State, uint32_t puNemRange)
1389	{
1390	RT_NOREF(pVM, puNemRange);
1391
1392	Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p\n", GCPhys, cb, pvR3));
1393	#if defined(VBOX_WITH_PGM_NEM_MODE)
1394	if (pvR3)
1395	{
1396	int rc = nemR3DarwinMap(pVM, GCPhys, pvR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
1397	if (RT_FAILURE(rc))
1398	{
1399	LogRel(("NEMR3NotifyPhysRamRegister: GCPhys=%RGp LB %RGp pvR3=%p rc=%Rrc\n", GCPhys, cb, pvR3, rc));
1400	return VERR_NEM_MAP_PAGES_FAILED;
1401	}
1402	}
1403	return VINF_SUCCESS;
1404	#else
1405	RT_NOREF(pVM, GCPhys, cb, pvR3);
1406	return VERR_NEM_MAP_PAGES_FAILED;
1407	#endif
1408	}
1409
1410
1411	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
1412	{
1413	RT_NOREF(pVM);
1414	return false;
1415	}
1416
1417
1418	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
1419	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
1420	{
1421	RT_NOREF(pVM, puNemRange, pvRam, fFlags);
1422
1423	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d)\n",
1424	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State));
1425
1426	#if defined(VBOX_WITH_PGM_NEM_MODE)
1427	/*
1428	* Unmap the RAM we're replacing.
1429	*/
1430	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
1431	{
1432	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
1433	if (RT_SUCCESS(rc))
1434	{ /* likely */ }
1435	else if (pvMmio2)
1436	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rc(ignored)\n",
1437	GCPhys, cb, fFlags, rc));
1438	else
1439	{
1440	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
1441	GCPhys, cb, fFlags, rc));
1442	return VERR_NEM_UNMAP_PAGES_FAILED;
1443	}
1444	}
1445
1446	/*
1447	* Map MMIO2 if any.
1448	*/
1449	if (pvMmio2)
1450	{
1451	Assert(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2);
1452	int rc = nemR3DarwinMap(pVM, GCPhys, pvMmio2, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
1453	if (RT_FAILURE(rc))
1454	{
1455	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x pvMmio2=%p: Map -> rc=%Rrc\n",
1456	GCPhys, cb, fFlags, pvMmio2, rc));
1457	return VERR_NEM_MAP_PAGES_FAILED;
1458	}
1459	}
1460	else
1461	Assert(!(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2));
1462
1463	#else
1464	RT_NOREF(pVM, GCPhys, cb, pvRam, pvMmio2);
1465	*pu2State = (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE) ? UINT8_MAX : NEM_DARWIN_PAGE_STATE_UNMAPPED;
1466	#endif
1467	return VINF_SUCCESS;
1468	}
1469
1470
1471	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
1472	void pvRam, void pvMmio2, uint32_t *puNemRange)
1473	{
1474	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
1475	return VINF_SUCCESS;
1476	}
1477
1478
1479	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
1480	void pvMmio2, uint8_t pu2State, uint32_t *puNemRange)
1481	{
1482	RT_NOREF(pVM, puNemRange);
1483
1484	Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p uNemRange=%#x (%#x)\n",
1485	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
1486
1487	int rc = VINF_SUCCESS;
1488	#if defined(VBOX_WITH_PGM_NEM_MODE)
1489	/*
1490	* Unmap the MMIO2 pages.
1491	*/
1492	/** @todo If we implement aliasing (MMIO2 page aliased into MMIO range),
1493	* we may have more stuff to unmap even in case of pure MMIO... */
1494	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
1495	{
1496	rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
1497	if (RT_FAILURE(rc))
1498	{
1499	LogRel2(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
1500	GCPhys, cb, fFlags, rc));
1501	rc = VERR_NEM_UNMAP_PAGES_FAILED;
1502	}
1503	}
1504
1505	/* Ensure the page is masked as unmapped if relevant. */
1506	Assert(!pu2State \|\| *pu2State == NEM_DARWIN_PAGE_STATE_UNMAPPED);
1507
1508	/*
1509	* Restore the RAM we replaced.
1510	*/
1511	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
1512	{
1513	AssertPtr(pvRam);
1514	rc = nemR3DarwinMap(pVM, GCPhys, pvRam, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
1515	if (RT_SUCCESS(rc))
1516	{ /* likely */ }
1517	else
1518	{
1519	LogRel(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp pvMmio2=%p rc=%Rrc\n", GCPhys, cb, pvMmio2, rc));
1520	rc = VERR_NEM_MAP_PAGES_FAILED;
1521	}
1522	}
1523
1524	RT_NOREF(pvMmio2);
1525	#else
1526	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
1527	if (pu2State)
1528	*pu2State = UINT8_MAX;
1529	rc = VERR_NEM_UNMAP_PAGES_FAILED;
1530	#endif
1531	return rc;
1532	}
1533
1534
1535	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
1536	void *pvBitmap, size_t cbBitmap)
1537	{
1538	RT_NOREF(pVM, GCPhys, cb, uNemRange, pvBitmap, cbBitmap);
1539	AssertReleaseFailed();
1540	return VERR_NOT_IMPLEMENTED;
1541	}
1542
1543
1544	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
1545	uint8_t pu2State, uint32_t puNemRange)
1546	{
1547	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
1548
1549	Log5(("nemR3NativeNotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
1550	*pu2State = UINT8_MAX;
1551	*puNemRange = 0;
1552	return VINF_SUCCESS;
1553	}
1554
1555
1556	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
1557	uint32_t fFlags, uint8_t pu2State, uint32_t puNemRange)
1558	{
1559	Log5(("nemR3NativeNotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
1560	GCPhys, cb, pvPages, fFlags, pu2State, pu2State, puNemRange, puNemRange));
1561	*pu2State = UINT8_MAX;
1562
1563	#if defined(VBOX_WITH_PGM_NEM_MODE)
1564	/*
1565	* (Re-)map readonly.
1566	*/
1567	AssertPtrReturn(pvPages, VERR_INVALID_POINTER);
1568	int rc = nemR3DarwinMap(pVM, GCPhys, pvPages, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE, pu2State);
1569	if (RT_FAILURE(rc))
1570	{
1571	LogRel(("nemR3NativeNotifyPhysRomRegisterLate: GCPhys=%RGp LB %RGp pvPages=%p fFlags=%#x rc=%Rrc\n",
1572	GCPhys, cb, pvPages, fFlags, rc));
1573	return VERR_NEM_MAP_PAGES_FAILED;
1574	}
1575	RT_NOREF(fFlags, puNemRange);
1576	return VINF_SUCCESS;
1577	#else
1578	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
1579	return VERR_NEM_MAP_PAGES_FAILED;
1580	#endif
1581	}
1582
1583
1584	VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
1585	RTR3PTR pvMemR3, uint8_t *pu2State)
1586	{
1587	RT_NOREF(pVM);
1588
1589	Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
1590	GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
1591
1592	*pu2State = UINT8_MAX;
1593	#if defined(VBOX_WITH_PGM_NEM_MODE)
1594	if (pvMemR3)
1595	{
1596	int rc = nemR3DarwinMap(pVM, GCPhys, pvMemR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
1597	AssertLogRelMsgRC(rc, ("NEMHCNotifyHandlerPhysicalDeregister: nemR3DarwinMap(,%p,%RGp,%RGp,) -> %Rrc\n",
1598	pvMemR3, GCPhys, cb, rc));
1599	}
1600	RT_NOREF(enmKind);
1601	#else
1602	RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
1603	AssertFailed();
1604	#endif
1605	}
1606
1607
1608	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
1609	{
1610	Log(("NEMR3NotifySetA20: fEnabled=%RTbool\n", fEnabled));
1611	RT_NOREF(pVCpu, fEnabled);
1612	}
1613
1614
1615	void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
1616	{
1617	Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
1618	NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
1619	}
1620
1621
1622	void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
1623	RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
1624	{
1625	Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
1626	GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
1627	NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
1628	}
1629
1630
1631	int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
1632	PGMPAGETYPE enmType, uint8_t *pu2State)
1633	{
1634	Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
1635	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
1636	RT_NOREF(HCPhys, fPageProt, enmType);
1637
1638	return nemR3DarwinUnmap(pVM, GCPhys, GUEST_PAGE_SIZE, pu2State);
1639	}
1640
1641
1642	VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
1643	PGMPAGETYPE enmType, uint8_t *pu2State)
1644	{
1645	Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
1646	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
1647	RT_NOREF(HCPhys, pvR3, fPageProt, enmType)
1648
1649	nemR3DarwinUnmap(pVM, GCPhys, GUEST_PAGE_SIZE, pu2State);
1650	}
1651
1652
1653	VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
1654	RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
1655	{
1656	Log5(("NEMHCNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
1657	GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
1658	RT_NOREF(HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType);
1659
1660	nemR3DarwinUnmap(pVM, GCPhys, GUEST_PAGE_SIZE, pu2State);
1661	}
1662
1663
1664	/**
1665	* Interface for importing state on demand (used by IEM).
1666	*
1667	* @returns VBox status code.
1668	* @param pVCpu The cross context CPU structure.
1669	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1670	*/
1671	VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1672	{
1673	LogFlowFunc(("pVCpu=%p fWhat=%RX64\n", pVCpu, fWhat));
1674	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
1675
1676	return nemR3DarwinCopyStateFromHv(pVCpu->pVMR3, pVCpu, fWhat);
1677	}
1678
1679
1680	/**
1681	* Query the CPU tick counter and optionally the TSC_AUX MSR value.
1682	*
1683	* @returns VBox status code.
1684	* @param pVCpu The cross context CPU structure.
1685	* @param pcTicks Where to return the CPU tick count.
1686	* @param puAux Where to return the TSC_AUX register value.
1687	*/
1688	VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t pcTicks, uint32_t puAux)
1689	{
1690	LogFlowFunc(("pVCpu=%p pcTicks=%RX64 puAux=%RX32\n", pVCpu, pcTicks, puAux));
1691	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
1692
1693	AssertReleaseFailed();
1694	return VERR_NOT_IMPLEMENTED;
1695	}
1696
1697
1698	/**
1699	* Resumes CPU clock (TSC) on all virtual CPUs.
1700	*
1701	* This is called by TM when the VM is started, restored, resumed or similar.
1702	*
1703	* @returns VBox status code.
1704	* @param pVM The cross context VM structure.
1705	* @param pVCpu The cross context CPU structure of the calling EMT.
1706	* @param uPausedTscValue The TSC value at the time of pausing.
1707	*/
1708	VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
1709	{
1710	LogFlowFunc(("pVM=%p pVCpu=%p uPausedTscValue=%RX64\n", pVCpu, uPausedTscValue));
1711	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
1712	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
1713
1714	//AssertReleaseFailed();
1715	return VINF_SUCCESS;
1716	}
1717
1718
1719	/**
1720	* Returns features supported by the NEM backend.
1721	*
1722	* @returns Flags of features supported by the native NEM backend.
1723	* @param pVM The cross context VM structure.
1724	*/
1725	VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
1726	{
1727	RT_NOREF(pVM);
1728	/*
1729	* Apple's Hypervisor.framework is not supported if the CPU doesn't support nested paging
1730	* and unrestricted guest execution support so we can safely return these flags here always.
1731	*/
1732	return NEM_FEAT_F_NESTED_PAGING \| NEM_FEAT_F_FULL_GST_EXEC \| NEM_FEAT_F_XSAVE_XRSTOR;
1733	}
1734
1735
1736	/** @page pg_nem_darwin NEM/darwin - Native Execution Manager, macOS.
1737	*
1738	* @todo Add notes as the implementation progresses...
1739	*/
1740

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp@ 99739

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