[99052] | 1 | /* $Id: NEMR3Native-darwin-armv8.cpp 103298 2024-02-11 19:36:49Z vboxsync $ */
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| 2 | /** @file
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| 3 | * NEM - Native execution manager, native ring-3 macOS backend using Hypervisor.framework, ARMv8 variant.
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| 4 | *
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| 5 | * Log group 2: Exit logging.
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| 6 | * Log group 3: Log context on exit.
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| 7 | * Log group 5: Ring-3 memory management
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| 8 | */
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| 9 |
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| 10 | /*
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| 11 | * Copyright (C) 2023 Oracle and/or its affiliates.
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| 12 | *
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| 13 | * This file is part of VirtualBox base platform packages, as
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| 14 | * available from https://www.virtualbox.org.
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| 15 | *
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| 16 | * This program is free software; you can redistribute it and/or
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| 17 | * modify it under the terms of the GNU General Public License
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| 18 | * as published by the Free Software Foundation, in version 3 of the
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| 19 | * License.
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| 20 | *
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| 21 | * This program is distributed in the hope that it will be useful, but
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| 22 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 24 | * General Public License for more details.
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| 25 | *
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| 26 | * You should have received a copy of the GNU General Public License
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| 27 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 28 | *
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| 29 | * SPDX-License-Identifier: GPL-3.0-only
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| 30 | */
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| 31 |
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| 32 |
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| 33 | /*********************************************************************************************************************************
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| 34 | * Header Files *
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| 35 | *********************************************************************************************************************************/
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| 36 | #define LOG_GROUP LOG_GROUP_NEM
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| 37 | #define VMCPU_INCL_CPUM_GST_CTX
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| 38 | #include <VBox/vmm/nem.h>
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| 39 | #include <VBox/vmm/iem.h>
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| 40 | #include <VBox/vmm/em.h>
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[99735] | 41 | #include <VBox/vmm/gic.h>
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[99052] | 42 | #include <VBox/vmm/pdm.h>
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| 43 | #include <VBox/vmm/dbgftrace.h>
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| 44 | #include <VBox/vmm/gcm.h>
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| 45 | #include "NEMInternal.h"
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| 46 | #include <VBox/vmm/vmcc.h>
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[100102] | 47 | #include <VBox/vmm/vmm.h>
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[99052] | 48 | #include "dtrace/VBoxVMM.h"
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| 49 |
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[99078] | 50 | #include <iprt/armv8.h>
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[99052] | 51 | #include <iprt/asm.h>
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[99976] | 52 | #include <iprt/asm-arm.h>
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[100001] | 53 | #include <iprt/asm-math.h>
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[99052] | 54 | #include <iprt/ldr.h>
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| 55 | #include <iprt/mem.h>
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| 56 | #include <iprt/path.h>
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| 57 | #include <iprt/string.h>
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| 58 | #include <iprt/system.h>
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| 59 | #include <iprt/utf16.h>
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| 60 |
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[100102] | 61 | #include <iprt/formats/arm-psci.h>
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| 62 |
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[99052] | 63 | #include <mach/mach_time.h>
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| 64 | #include <mach/kern_return.h>
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| 65 |
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| 66 | #include <Hypervisor/Hypervisor.h>
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| 67 |
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[99054] | 68 |
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[99052] | 69 | /*********************************************************************************************************************************
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| 70 | * Defined Constants And Macros *
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| 71 | *********************************************************************************************************************************/
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| 72 |
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| 73 |
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| 74 | /*********************************************************************************************************************************
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| 75 | * Structures and Typedefs *
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| 76 | *********************************************************************************************************************************/
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| 77 |
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| 78 |
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| 79 | /*********************************************************************************************************************************
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| 80 | * Global Variables *
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| 81 | *********************************************************************************************************************************/
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| 82 | /** The general registers. */
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| 83 | static const struct
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| 84 | {
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| 85 | hv_reg_t enmHvReg;
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| 86 | uint32_t fCpumExtrn;
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| 87 | uint32_t offCpumCtx;
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| 88 | } s_aCpumRegs[] =
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| 89 | {
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| 90 | #define CPUM_GREG_EMIT_X0_X3(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X ## a_Idx, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
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| 91 | #define CPUM_GREG_EMIT_X4_X28(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X4_X28, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
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| 92 | CPUM_GREG_EMIT_X0_X3(0),
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| 93 | CPUM_GREG_EMIT_X0_X3(1),
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| 94 | CPUM_GREG_EMIT_X0_X3(2),
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| 95 | CPUM_GREG_EMIT_X0_X3(3),
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| 96 | CPUM_GREG_EMIT_X4_X28(4),
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| 97 | CPUM_GREG_EMIT_X4_X28(5),
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| 98 | CPUM_GREG_EMIT_X4_X28(6),
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| 99 | CPUM_GREG_EMIT_X4_X28(7),
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| 100 | CPUM_GREG_EMIT_X4_X28(8),
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| 101 | CPUM_GREG_EMIT_X4_X28(9),
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| 102 | CPUM_GREG_EMIT_X4_X28(10),
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| 103 | CPUM_GREG_EMIT_X4_X28(11),
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| 104 | CPUM_GREG_EMIT_X4_X28(12),
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| 105 | CPUM_GREG_EMIT_X4_X28(13),
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| 106 | CPUM_GREG_EMIT_X4_X28(14),
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| 107 | CPUM_GREG_EMIT_X4_X28(15),
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| 108 | CPUM_GREG_EMIT_X4_X28(16),
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| 109 | CPUM_GREG_EMIT_X4_X28(17),
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| 110 | CPUM_GREG_EMIT_X4_X28(18),
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| 111 | CPUM_GREG_EMIT_X4_X28(19),
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| 112 | CPUM_GREG_EMIT_X4_X28(20),
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| 113 | CPUM_GREG_EMIT_X4_X28(21),
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| 114 | CPUM_GREG_EMIT_X4_X28(22),
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| 115 | CPUM_GREG_EMIT_X4_X28(23),
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| 116 | CPUM_GREG_EMIT_X4_X28(24),
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| 117 | CPUM_GREG_EMIT_X4_X28(25),
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| 118 | CPUM_GREG_EMIT_X4_X28(26),
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| 119 | CPUM_GREG_EMIT_X4_X28(27),
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| 120 | CPUM_GREG_EMIT_X4_X28(28),
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| 121 | { HV_REG_FP, CPUMCTX_EXTRN_FP, RT_UOFFSETOF(CPUMCTX, aGRegs[29].x) },
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| 122 | { HV_REG_LR, CPUMCTX_EXTRN_LR, RT_UOFFSETOF(CPUMCTX, aGRegs[30].x) },
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| 123 | { HV_REG_PC, CPUMCTX_EXTRN_PC, RT_UOFFSETOF(CPUMCTX, Pc.u64) },
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| 124 | { HV_REG_FPCR, CPUMCTX_EXTRN_FPCR, RT_UOFFSETOF(CPUMCTX, fpcr) },
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| 125 | { HV_REG_FPSR, CPUMCTX_EXTRN_FPSR, RT_UOFFSETOF(CPUMCTX, fpsr) }
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| 126 | #undef CPUM_GREG_EMIT_X0_X3
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| 127 | #undef CPUM_GREG_EMIT_X4_X28
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| 128 | };
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| 129 | /** SIMD/FP registers. */
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| 130 | static const struct
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| 131 | {
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| 132 | hv_simd_fp_reg_t enmHvReg;
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| 133 | uint32_t offCpumCtx;
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| 134 | } s_aCpumFpRegs[] =
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| 135 | {
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| 136 | #define CPUM_VREG_EMIT(a_Idx) { HV_SIMD_FP_REG_Q ## a_Idx, RT_UOFFSETOF(CPUMCTX, aVRegs[a_Idx].v) }
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| 137 | CPUM_VREG_EMIT(0),
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| 138 | CPUM_VREG_EMIT(1),
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| 139 | CPUM_VREG_EMIT(2),
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| 140 | CPUM_VREG_EMIT(3),
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| 141 | CPUM_VREG_EMIT(4),
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| 142 | CPUM_VREG_EMIT(5),
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| 143 | CPUM_VREG_EMIT(6),
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| 144 | CPUM_VREG_EMIT(7),
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| 145 | CPUM_VREG_EMIT(8),
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| 146 | CPUM_VREG_EMIT(9),
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| 147 | CPUM_VREG_EMIT(10),
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| 148 | CPUM_VREG_EMIT(11),
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| 149 | CPUM_VREG_EMIT(12),
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| 150 | CPUM_VREG_EMIT(13),
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| 151 | CPUM_VREG_EMIT(14),
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| 152 | CPUM_VREG_EMIT(15),
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| 153 | CPUM_VREG_EMIT(16),
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| 154 | CPUM_VREG_EMIT(17),
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| 155 | CPUM_VREG_EMIT(18),
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| 156 | CPUM_VREG_EMIT(19),
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| 157 | CPUM_VREG_EMIT(20),
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| 158 | CPUM_VREG_EMIT(21),
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| 159 | CPUM_VREG_EMIT(22),
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| 160 | CPUM_VREG_EMIT(23),
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| 161 | CPUM_VREG_EMIT(24),
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| 162 | CPUM_VREG_EMIT(25),
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| 163 | CPUM_VREG_EMIT(26),
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| 164 | CPUM_VREG_EMIT(27),
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| 165 | CPUM_VREG_EMIT(28),
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| 166 | CPUM_VREG_EMIT(29),
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| 167 | CPUM_VREG_EMIT(30),
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| 168 | CPUM_VREG_EMIT(31)
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| 169 | #undef CPUM_VREG_EMIT
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| 170 | };
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[100723] | 171 | /** Debug system registers. */
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| 172 | static const struct
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| 173 | {
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| 174 | hv_sys_reg_t enmHvReg;
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| 175 | uint32_t offCpumCtx;
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| 176 | } s_aCpumDbgRegs[] =
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| 177 | {
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| 178 | #define CPUM_DBGREG_EMIT(a_BorW, a_Idx) \
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| 179 | { HV_SYS_REG_DBG ## a_BorW ## CR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Ctrl.u64) }, \
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| 180 | { HV_SYS_REG_DBG ## a_BorW ## VR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Value.u64) }
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| 181 | /* Breakpoint registers. */
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| 182 | CPUM_DBGREG_EMIT(B, 0),
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| 183 | CPUM_DBGREG_EMIT(B, 1),
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| 184 | CPUM_DBGREG_EMIT(B, 2),
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| 185 | CPUM_DBGREG_EMIT(B, 3),
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| 186 | CPUM_DBGREG_EMIT(B, 4),
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| 187 | CPUM_DBGREG_EMIT(B, 5),
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| 188 | CPUM_DBGREG_EMIT(B, 6),
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| 189 | CPUM_DBGREG_EMIT(B, 7),
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| 190 | CPUM_DBGREG_EMIT(B, 8),
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| 191 | CPUM_DBGREG_EMIT(B, 9),
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| 192 | CPUM_DBGREG_EMIT(B, 10),
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| 193 | CPUM_DBGREG_EMIT(B, 11),
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| 194 | CPUM_DBGREG_EMIT(B, 12),
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| 195 | CPUM_DBGREG_EMIT(B, 13),
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| 196 | CPUM_DBGREG_EMIT(B, 14),
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| 197 | CPUM_DBGREG_EMIT(B, 15),
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| 198 | /* Watchpoint registers. */
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| 199 | CPUM_DBGREG_EMIT(W, 0),
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| 200 | CPUM_DBGREG_EMIT(W, 1),
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| 201 | CPUM_DBGREG_EMIT(W, 2),
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| 202 | CPUM_DBGREG_EMIT(W, 3),
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| 203 | CPUM_DBGREG_EMIT(W, 4),
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| 204 | CPUM_DBGREG_EMIT(W, 5),
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| 205 | CPUM_DBGREG_EMIT(W, 6),
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| 206 | CPUM_DBGREG_EMIT(W, 7),
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| 207 | CPUM_DBGREG_EMIT(W, 8),
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| 208 | CPUM_DBGREG_EMIT(W, 9),
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| 209 | CPUM_DBGREG_EMIT(W, 10),
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| 210 | CPUM_DBGREG_EMIT(W, 11),
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| 211 | CPUM_DBGREG_EMIT(W, 12),
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| 212 | CPUM_DBGREG_EMIT(W, 13),
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| 213 | CPUM_DBGREG_EMIT(W, 14),
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[100725] | 214 | CPUM_DBGREG_EMIT(W, 15),
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| 215 | { HV_SYS_REG_MDSCR_EL1, RT_UOFFSETOF(CPUMCTX, Mdscr.u64) }
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[100723] | 216 | #undef CPUM_DBGREG_EMIT
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| 217 | };
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[100724] | 218 | /** PAuth key system registers. */
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| 219 | static const struct
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| 220 | {
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| 221 | hv_sys_reg_t enmHvReg;
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| 222 | uint32_t offCpumCtx;
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| 223 | } s_aCpumPAuthKeyRegs[] =
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| 224 | {
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| 225 | { HV_SYS_REG_APDAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apda.Low.u64) },
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| 226 | { HV_SYS_REG_APDAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apda.High.u64) },
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| 227 | { HV_SYS_REG_APDBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.Low.u64) },
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| 228 | { HV_SYS_REG_APDBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.High.u64) },
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| 229 | { HV_SYS_REG_APGAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apga.Low.u64) },
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| 230 | { HV_SYS_REG_APGAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apga.High.u64) },
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| 231 | { HV_SYS_REG_APIAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apia.Low.u64) },
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| 232 | { HV_SYS_REG_APIAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apia.High.u64) },
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| 233 | { HV_SYS_REG_APIBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apib.Low.u64) },
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| 234 | { HV_SYS_REG_APIBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apib.High.u64) }
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| 235 | };
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[99052] | 236 | /** System registers. */
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| 237 | static const struct
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| 238 | {
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| 239 | hv_sys_reg_t enmHvReg;
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| 240 | uint32_t fCpumExtrn;
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| 241 | uint32_t offCpumCtx;
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| 242 | } s_aCpumSysRegs[] =
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| 243 | {
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[100725] | 244 | { HV_SYS_REG_SP_EL0, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64) },
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| 245 | { HV_SYS_REG_SP_EL1, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64) },
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| 246 | { HV_SYS_REG_SPSR_EL1, CPUMCTX_EXTRN_SPSR, RT_UOFFSETOF(CPUMCTX, Spsr.u64) },
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| 247 | { HV_SYS_REG_ELR_EL1, CPUMCTX_EXTRN_ELR, RT_UOFFSETOF(CPUMCTX, Elr.u64) },
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| 248 | { HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Sctlr.u64) },
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| 249 | { HV_SYS_REG_TCR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Tcr.u64) },
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| 250 | { HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr0.u64) },
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| 251 | { HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr1.u64) },
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| 252 | { HV_SYS_REG_VBAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, VBar.u64) },
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| 253 | { HV_SYS_REG_AFSR0_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr0.u64) },
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| 254 | { HV_SYS_REG_AFSR1_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr1.u64) },
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| 255 | { HV_SYS_REG_AMAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Amair.u64) },
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| 256 | { HV_SYS_REG_CNTKCTL_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, CntKCtl.u64) },
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| 257 | { HV_SYS_REG_CONTEXTIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, ContextIdr.u64) },
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| 258 | { HV_SYS_REG_CPACR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Cpacr.u64) },
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| 259 | { HV_SYS_REG_CSSELR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Csselr.u64) },
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| 260 | { HV_SYS_REG_ESR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Esr.u64) },
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| 261 | { HV_SYS_REG_FAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Far.u64) },
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| 262 | { HV_SYS_REG_MAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Mair.u64) },
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| 263 | { HV_SYS_REG_PAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Par.u64) },
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| 264 | { HV_SYS_REG_TPIDRRO_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, TpIdrRoEl0.u64) },
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| 265 | { HV_SYS_REG_TPIDR_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[0].u64) },
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| 266 | { HV_SYS_REG_TPIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[1].u64) },
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| 267 | { HV_SYS_REG_MDCCINT_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, MDccInt.u64) }
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| 268 |
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[99052] | 269 | };
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[100708] | 270 | /** ID registers. */
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| 271 | static const struct
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| 272 | {
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| 273 | hv_feature_reg_t enmHvReg;
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| 274 | uint32_t offIdStruct;
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| 275 | } s_aIdRegs[] =
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| 276 | {
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[101104] | 277 | { HV_FEATURE_REG_ID_AA64DFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Dfr0El1) },
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| 278 | { HV_FEATURE_REG_ID_AA64DFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Dfr1El1) },
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| 279 | { HV_FEATURE_REG_ID_AA64ISAR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Isar0El1) },
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| 280 | { HV_FEATURE_REG_ID_AA64ISAR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Isar1El1) },
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| 281 | { HV_FEATURE_REG_ID_AA64MMFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr0El1) },
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| 282 | { HV_FEATURE_REG_ID_AA64MMFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr1El1) },
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| 283 | { HV_FEATURE_REG_ID_AA64MMFR2_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr2El1) },
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| 284 | { HV_FEATURE_REG_ID_AA64PFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Pfr0El1) },
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| 285 | { HV_FEATURE_REG_ID_AA64PFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Pfr1El1) },
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| 286 | { HV_FEATURE_REG_CLIDR_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegClidrEl1) },
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| 287 | { HV_FEATURE_REG_CTR_EL0, RT_UOFFSETOF(CPUMIDREGS, u64RegCtrEl0) },
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| 288 | { HV_FEATURE_REG_DCZID_EL0, RT_UOFFSETOF(CPUMIDREGS, u64RegDczidEl0) }
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[100708] | 289 | };
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[99052] | 290 |
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| 291 |
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| 292 | /*********************************************************************************************************************************
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| 293 | * Internal Functions *
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| 294 | *********************************************************************************************************************************/
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| 295 |
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| 296 |
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| 297 | /**
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| 298 | * Converts a HV return code to a VBox status code.
|
---|
| 299 | *
|
---|
| 300 | * @returns VBox status code.
|
---|
| 301 | * @param hrc The HV return code to convert.
|
---|
| 302 | */
|
---|
| 303 | DECLINLINE(int) nemR3DarwinHvSts2Rc(hv_return_t hrc)
|
---|
| 304 | {
|
---|
| 305 | if (hrc == HV_SUCCESS)
|
---|
| 306 | return VINF_SUCCESS;
|
---|
| 307 |
|
---|
| 308 | switch (hrc)
|
---|
| 309 | {
|
---|
| 310 | case HV_ERROR: return VERR_INVALID_STATE;
|
---|
| 311 | case HV_BUSY: return VERR_RESOURCE_BUSY;
|
---|
| 312 | case HV_BAD_ARGUMENT: return VERR_INVALID_PARAMETER;
|
---|
| 313 | case HV_NO_RESOURCES: return VERR_OUT_OF_RESOURCES;
|
---|
| 314 | case HV_NO_DEVICE: return VERR_NOT_FOUND;
|
---|
| 315 | case HV_UNSUPPORTED: return VERR_NOT_SUPPORTED;
|
---|
| 316 | }
|
---|
| 317 |
|
---|
| 318 | return VERR_IPE_UNEXPECTED_STATUS;
|
---|
| 319 | }
|
---|
| 320 |
|
---|
| 321 |
|
---|
| 322 | /**
|
---|
[99078] | 323 | * Returns a human readable string of the given exception class.
|
---|
| 324 | *
|
---|
| 325 | * @returns Pointer to the string matching the given EC.
|
---|
| 326 | * @param u32Ec The exception class to return the string for.
|
---|
| 327 | */
|
---|
| 328 | static const char *nemR3DarwinEsrEl2EcStringify(uint32_t u32Ec)
|
---|
| 329 | {
|
---|
| 330 | switch (u32Ec)
|
---|
| 331 | {
|
---|
| 332 | #define ARMV8_EC_CASE(a_Ec) case a_Ec: return #a_Ec
|
---|
| 333 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_UNKNOWN);
|
---|
| 334 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TRAPPED_WFX);
|
---|
| 335 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15);
|
---|
| 336 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15);
|
---|
| 337 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14);
|
---|
| 338 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC);
|
---|
| 339 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON);
|
---|
| 340 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS);
|
---|
| 341 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN);
|
---|
| 342 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_LS64_EXCEPTION);
|
---|
| 343 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14);
|
---|
| 344 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION);
|
---|
| 345 | ARMV8_EC_CASE(ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE);
|
---|
| 346 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN);
|
---|
| 347 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN);
|
---|
| 348 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN);
|
---|
| 349 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN);
|
---|
| 350 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN);
|
---|
| 351 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN);
|
---|
| 352 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN);
|
---|
| 353 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SVE_TRAPPED);
|
---|
| 354 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB);
|
---|
| 355 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION);
|
---|
| 356 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION);
|
---|
| 357 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS);
|
---|
| 358 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION);
|
---|
| 359 | ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL);
|
---|
| 360 | ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2);
|
---|
| 361 | ARMV8_EC_CASE(ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION);
|
---|
| 362 | ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL);
|
---|
| 363 | ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2);
|
---|
| 364 | ARMV8_EC_CASE(ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION);
|
---|
| 365 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_MOPS_EXCEPTION);
|
---|
| 366 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION);
|
---|
| 367 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION);
|
---|
| 368 | ARMV8_EC_CASE(ARMV8_ESR_EL2_SERROR_INTERRUPT);
|
---|
| 369 | ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL);
|
---|
| 370 | ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2);
|
---|
| 371 | ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL);
|
---|
| 372 | ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2);
|
---|
| 373 | ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL);
|
---|
| 374 | ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2);
|
---|
| 375 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN);
|
---|
| 376 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION);
|
---|
| 377 | ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN);
|
---|
| 378 | #undef ARMV8_EC_CASE
|
---|
| 379 | default:
|
---|
| 380 | break;
|
---|
| 381 | }
|
---|
| 382 |
|
---|
| 383 | return "<INVALID>";
|
---|
| 384 | }
|
---|
| 385 |
|
---|
| 386 |
|
---|
| 387 | /**
|
---|
[99575] | 388 | * Resolves a NEM page state from the given protection flags.
|
---|
| 389 | *
|
---|
| 390 | * @returns NEM page state.
|
---|
| 391 | * @param fPageProt The page protection flags.
|
---|
| 392 | */
|
---|
| 393 | DECLINLINE(uint8_t) nemR3DarwinPageStateFromProt(uint32_t fPageProt)
|
---|
| 394 | {
|
---|
| 395 | switch (fPageProt)
|
---|
| 396 | {
|
---|
| 397 | case NEM_PAGE_PROT_NONE:
|
---|
| 398 | return NEM_DARWIN_PAGE_STATE_UNMAPPED;
|
---|
| 399 | case NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE:
|
---|
| 400 | return NEM_DARWIN_PAGE_STATE_RX;
|
---|
| 401 | case NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE:
|
---|
| 402 | return NEM_DARWIN_PAGE_STATE_RW;
|
---|
| 403 | case NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE:
|
---|
| 404 | return NEM_DARWIN_PAGE_STATE_RWX;
|
---|
| 405 | default:
|
---|
| 406 | break;
|
---|
| 407 | }
|
---|
| 408 |
|
---|
| 409 | AssertLogRelMsgFailed(("Invalid combination of page protection flags %#x, can't map to page state!\n", fPageProt));
|
---|
| 410 | return NEM_DARWIN_PAGE_STATE_UNMAPPED;
|
---|
| 411 | }
|
---|
| 412 |
|
---|
| 413 |
|
---|
| 414 | /**
|
---|
[99052] | 415 | * Unmaps the given guest physical address range (page aligned).
|
---|
| 416 | *
|
---|
| 417 | * @returns VBox status code.
|
---|
| 418 | * @param pVM The cross context VM structure.
|
---|
| 419 | * @param GCPhys The guest physical address to start unmapping at.
|
---|
| 420 | * @param cb The size of the range to unmap in bytes.
|
---|
| 421 | * @param pu2State Where to store the new state of the unmappd page, optional.
|
---|
| 422 | */
|
---|
| 423 | DECLINLINE(int) nemR3DarwinUnmap(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint8_t *pu2State)
|
---|
| 424 | {
|
---|
| 425 | if (*pu2State <= NEM_DARWIN_PAGE_STATE_UNMAPPED)
|
---|
| 426 | {
|
---|
| 427 | Log5(("nemR3DarwinUnmap: %RGp == unmapped\n", GCPhys));
|
---|
| 428 | *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
|
---|
| 429 | return VINF_SUCCESS;
|
---|
| 430 | }
|
---|
| 431 |
|
---|
| 432 | LogFlowFunc(("Unmapping %RGp LB %zu\n", GCPhys, cb));
|
---|
| 433 | hv_return_t hrc = hv_vm_unmap(GCPhys, cb);
|
---|
| 434 | if (RT_LIKELY(hrc == HV_SUCCESS))
|
---|
| 435 | {
|
---|
| 436 | STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
|
---|
| 437 | if (pu2State)
|
---|
| 438 | *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
|
---|
| 439 | Log5(("nemR3DarwinUnmap: %RGp => unmapped\n", GCPhys));
|
---|
| 440 | return VINF_SUCCESS;
|
---|
| 441 | }
|
---|
| 442 |
|
---|
| 443 | STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
|
---|
| 444 | LogRel(("nemR3DarwinUnmap(%RGp): failed! hrc=%#x\n",
|
---|
| 445 | GCPhys, hrc));
|
---|
| 446 | return VERR_NEM_IPE_6;
|
---|
| 447 | }
|
---|
| 448 |
|
---|
| 449 |
|
---|
| 450 | /**
|
---|
| 451 | * Maps a given guest physical address range backed by the given memory with the given
|
---|
| 452 | * protection flags.
|
---|
| 453 | *
|
---|
| 454 | * @returns VBox status code.
|
---|
| 455 | * @param pVM The cross context VM structure.
|
---|
| 456 | * @param GCPhys The guest physical address to start mapping.
|
---|
| 457 | * @param pvRam The R3 pointer of the memory to back the range with.
|
---|
| 458 | * @param cb The size of the range, page aligned.
|
---|
| 459 | * @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
|
---|
| 460 | * @param pu2State Where to store the state for the new page, optional.
|
---|
| 461 | */
|
---|
| 462 | DECLINLINE(int) nemR3DarwinMap(PVM pVM, RTGCPHYS GCPhys, const void *pvRam, size_t cb, uint32_t fPageProt, uint8_t *pu2State)
|
---|
| 463 | {
|
---|
| 464 | LogFlowFunc(("Mapping %RGp LB %zu fProt=%#x\n", GCPhys, cb, fPageProt));
|
---|
| 465 |
|
---|
| 466 | Assert(fPageProt != NEM_PAGE_PROT_NONE);
|
---|
| 467 | RT_NOREF(pVM);
|
---|
| 468 |
|
---|
| 469 | hv_memory_flags_t fHvMemProt = 0;
|
---|
| 470 | if (fPageProt & NEM_PAGE_PROT_READ)
|
---|
| 471 | fHvMemProt |= HV_MEMORY_READ;
|
---|
| 472 | if (fPageProt & NEM_PAGE_PROT_WRITE)
|
---|
| 473 | fHvMemProt |= HV_MEMORY_WRITE;
|
---|
| 474 | if (fPageProt & NEM_PAGE_PROT_EXECUTE)
|
---|
| 475 | fHvMemProt |= HV_MEMORY_EXEC;
|
---|
| 476 |
|
---|
| 477 | hv_return_t hrc = hv_vm_map((void *)pvRam, GCPhys, cb, fHvMemProt);
|
---|
| 478 | if (hrc == HV_SUCCESS)
|
---|
| 479 | {
|
---|
| 480 | if (pu2State)
|
---|
[99575] | 481 | *pu2State = nemR3DarwinPageStateFromProt(fPageProt);
|
---|
[99052] | 482 | return VINF_SUCCESS;
|
---|
| 483 | }
|
---|
| 484 |
|
---|
| 485 | return nemR3DarwinHvSts2Rc(hrc);
|
---|
| 486 | }
|
---|
| 487 |
|
---|
[100705] | 488 |
|
---|
| 489 | /**
|
---|
| 490 | * Changes the protection flags for the given guest physical address range.
|
---|
| 491 | *
|
---|
| 492 | * @returns VBox status code.
|
---|
| 493 | * @param GCPhys The guest physical address to start mapping.
|
---|
| 494 | * @param cb The size of the range, page aligned.
|
---|
| 495 | * @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
|
---|
| 496 | * @param pu2State Where to store the state for the new page, optional.
|
---|
| 497 | */
|
---|
| 498 | DECLINLINE(int) nemR3DarwinProtect(RTGCPHYS GCPhys, size_t cb, uint32_t fPageProt, uint8_t *pu2State)
|
---|
[99052] | 499 | {
|
---|
| 500 | hv_memory_flags_t fHvMemProt = 0;
|
---|
| 501 | if (fPageProt & NEM_PAGE_PROT_READ)
|
---|
| 502 | fHvMemProt |= HV_MEMORY_READ;
|
---|
| 503 | if (fPageProt & NEM_PAGE_PROT_WRITE)
|
---|
| 504 | fHvMemProt |= HV_MEMORY_WRITE;
|
---|
| 505 | if (fPageProt & NEM_PAGE_PROT_EXECUTE)
|
---|
| 506 | fHvMemProt |= HV_MEMORY_EXEC;
|
---|
| 507 |
|
---|
[100705] | 508 | hv_return_t hrc = hv_vm_protect(GCPhys, cb, fHvMemProt);
|
---|
| 509 | if (hrc == HV_SUCCESS)
|
---|
| 510 | {
|
---|
| 511 | if (pu2State)
|
---|
| 512 | *pu2State = nemR3DarwinPageStateFromProt(fPageProt);
|
---|
| 513 | return VINF_SUCCESS;
|
---|
| 514 | }
|
---|
[99052] | 515 |
|
---|
[100705] | 516 | LogRel(("nemR3DarwinProtect(%RGp,%zu,%#x): failed! hrc=%#x\n",
|
---|
| 517 | GCPhys, cb, fPageProt, hrc));
|
---|
[99052] | 518 | return nemR3DarwinHvSts2Rc(hrc);
|
---|
| 519 | }
|
---|
| 520 |
|
---|
[100705] | 521 |
|
---|
[99052] | 522 | #ifdef LOG_ENABLED
|
---|
| 523 | /**
|
---|
| 524 | * Logs the current CPU state.
|
---|
| 525 | */
|
---|
| 526 | static void nemR3DarwinLogState(PVMCC pVM, PVMCPUCC pVCpu)
|
---|
| 527 | {
|
---|
| 528 | if (LogIs3Enabled())
|
---|
| 529 | {
|
---|
| 530 | char szRegs[4096];
|
---|
| 531 | DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
|
---|
[99070] | 532 | "x0=%016VR{x0} x1=%016VR{x1} x2=%016VR{x2} x3=%016VR{x3}\n"
|
---|
| 533 | "x4=%016VR{x4} x5=%016VR{x5} x6=%016VR{x6} x7=%016VR{x7}\n"
|
---|
| 534 | "x8=%016VR{x8} x9=%016VR{x9} x10=%016VR{x10} x11=%016VR{x11}\n"
|
---|
| 535 | "x12=%016VR{x12} x13=%016VR{x13} x14=%016VR{x14} x15=%016VR{x15}\n"
|
---|
| 536 | "x16=%016VR{x16} x17=%016VR{x17} x18=%016VR{x18} x19=%016VR{x19}\n"
|
---|
| 537 | "x20=%016VR{x20} x21=%016VR{x21} x22=%016VR{x22} x23=%016VR{x23}\n"
|
---|
| 538 | "x24=%016VR{x24} x25=%016VR{x25} x26=%016VR{x26} x27=%016VR{x27}\n"
|
---|
| 539 | "x28=%016VR{x28} x29=%016VR{x29} x30=%016VR{x30}\n"
|
---|
| 540 | "pc=%016VR{pc} pstate=%016VR{pstate}\n"
|
---|
| 541 | "sp_el0=%016VR{sp_el0} sp_el1=%016VR{sp_el1} elr_el1=%016VR{elr_el1}\n"
|
---|
[99379] | 542 | "sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n"
|
---|
| 543 | "ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
|
---|
[100118] | 544 | "vbar_el1=%016VR{vbar_el1}\n"
|
---|
[99052] | 545 | );
|
---|
[99070] | 546 | char szInstr[256]; RT_ZERO(szInstr);
|
---|
| 547 | #if 0
|
---|
[99052] | 548 | DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
|
---|
| 549 | DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
|
---|
| 550 | szInstr, sizeof(szInstr), NULL);
|
---|
[99070] | 551 | #endif
|
---|
[99052] | 552 | Log3(("%s%s\n", szRegs, szInstr));
|
---|
| 553 | }
|
---|
| 554 | }
|
---|
| 555 | #endif /* LOG_ENABLED */
|
---|
| 556 |
|
---|
| 557 |
|
---|
| 558 | static int nemR3DarwinCopyStateFromHv(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
|
---|
| 559 | {
|
---|
| 560 | RT_NOREF(pVM);
|
---|
| 561 |
|
---|
[99976] | 562 | hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &pVCpu->cpum.GstCtx.CntvCtlEl0);
|
---|
| 563 | if (hrc == HV_SUCCESS)
|
---|
| 564 | hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, &pVCpu->cpum.GstCtx.CntvCValEl0);
|
---|
| 565 |
|
---|
| 566 | if ( hrc == HV_SUCCESS
|
---|
| 567 | && (fWhat & (CPUMCTX_EXTRN_GPRS_MASK | CPUMCTX_EXTRN_PC | CPUMCTX_EXTRN_FPCR | CPUMCTX_EXTRN_FPSR)))
|
---|
[99052] | 568 | {
|
---|
| 569 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
|
---|
| 570 | {
|
---|
| 571 | if (s_aCpumRegs[i].fCpumExtrn & fWhat)
|
---|
| 572 | {
|
---|
| 573 | uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
|
---|
| 574 | hrc |= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, pu64);
|
---|
| 575 | }
|
---|
| 576 | }
|
---|
| 577 | }
|
---|
| 578 |
|
---|
| 579 | if ( hrc == HV_SUCCESS
|
---|
| 580 | && (fWhat & CPUMCTX_EXTRN_V0_V31))
|
---|
| 581 | {
|
---|
| 582 | /* SIMD/FP registers. */
|
---|
| 583 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
|
---|
| 584 | {
|
---|
| 585 | hv_simd_fp_uchar16_t *pu128 = (hv_simd_fp_uchar16_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
|
---|
| 586 | hrc |= hv_vcpu_get_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, pu128);
|
---|
| 587 | }
|
---|
| 588 | }
|
---|
| 589 |
|
---|
| 590 | if ( hrc == HV_SUCCESS
|
---|
[100723] | 591 | && (fWhat & CPUMCTX_EXTRN_SYSREG_DEBUG))
|
---|
[99052] | 592 | {
|
---|
[100723] | 593 | /* Debug registers. */
|
---|
| 594 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
|
---|
| 595 | {
|
---|
| 596 | uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
|
---|
| 597 | hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, pu64);
|
---|
| 598 | }
|
---|
| 599 | }
|
---|
| 600 |
|
---|
| 601 | if ( hrc == HV_SUCCESS
|
---|
[100724] | 602 | && (fWhat & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
|
---|
| 603 | {
|
---|
| 604 | /* Debug registers. */
|
---|
| 605 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
|
---|
| 606 | {
|
---|
| 607 | uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
|
---|
| 608 | hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, pu64);
|
---|
| 609 | }
|
---|
| 610 | }
|
---|
| 611 |
|
---|
| 612 | if ( hrc == HV_SUCCESS
|
---|
[100723] | 613 | && (fWhat & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC)))
|
---|
| 614 | {
|
---|
[99052] | 615 | /* System registers. */
|
---|
| 616 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
|
---|
| 617 | {
|
---|
| 618 | if (s_aCpumSysRegs[i].fCpumExtrn & fWhat)
|
---|
| 619 | {
|
---|
| 620 | uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
|
---|
| 621 | hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, pu64);
|
---|
| 622 | }
|
---|
| 623 | }
|
---|
| 624 | }
|
---|
| 625 |
|
---|
| 626 | if ( hrc == HV_SUCCESS
|
---|
| 627 | && (fWhat & CPUMCTX_EXTRN_PSTATE))
|
---|
| 628 | {
|
---|
| 629 | uint64_t u64Tmp;
|
---|
| 630 | hrc |= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
|
---|
| 631 | if (hrc == HV_SUCCESS)
|
---|
| 632 | pVCpu->cpum.GstCtx.fPState = (uint32_t)u64Tmp;
|
---|
| 633 | }
|
---|
| 634 |
|
---|
| 635 | /* Almost done, just update extern flags. */
|
---|
| 636 | pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
|
---|
| 637 | if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
|
---|
| 638 | pVCpu->cpum.GstCtx.fExtrn = 0;
|
---|
| 639 |
|
---|
| 640 | return nemR3DarwinHvSts2Rc(hrc);
|
---|
| 641 | }
|
---|
| 642 |
|
---|
| 643 |
|
---|
| 644 | /**
|
---|
| 645 | * Exports the guest state to HV for execution.
|
---|
| 646 | *
|
---|
| 647 | * @returns VBox status code.
|
---|
| 648 | * @param pVM The cross context VM structure.
|
---|
| 649 | * @param pVCpu The cross context virtual CPU structure of the
|
---|
| 650 | * calling EMT.
|
---|
| 651 | */
|
---|
| 652 | static int nemR3DarwinExportGuestState(PVMCC pVM, PVMCPUCC pVCpu)
|
---|
| 653 | {
|
---|
| 654 | RT_NOREF(pVM);
|
---|
| 655 | hv_return_t hrc = HV_SUCCESS;
|
---|
| 656 |
|
---|
| 657 | if ( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_GPRS_MASK | CPUMCTX_EXTRN_PC | CPUMCTX_EXTRN_FPCR | CPUMCTX_EXTRN_FPSR))
|
---|
| 658 | != (CPUMCTX_EXTRN_GPRS_MASK | CPUMCTX_EXTRN_PC | CPUMCTX_EXTRN_FPCR | CPUMCTX_EXTRN_FPSR))
|
---|
| 659 | {
|
---|
| 660 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
|
---|
| 661 | {
|
---|
| 662 | if (!(s_aCpumRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
|
---|
| 663 | {
|
---|
| 664 | uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
|
---|
| 665 | hrc |= hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, *pu64);
|
---|
| 666 | }
|
---|
| 667 | }
|
---|
| 668 | }
|
---|
| 669 |
|
---|
| 670 | if ( hrc == HV_SUCCESS
|
---|
| 671 | && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_V0_V31))
|
---|
| 672 | {
|
---|
| 673 | /* SIMD/FP registers. */
|
---|
| 674 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
|
---|
| 675 | {
|
---|
| 676 | hv_simd_fp_uchar16_t *pu128 = (hv_simd_fp_uchar16_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
|
---|
| 677 | hrc |= hv_vcpu_set_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, *pu128);
|
---|
| 678 | }
|
---|
| 679 | }
|
---|
| 680 |
|
---|
| 681 | if ( hrc == HV_SUCCESS
|
---|
[100723] | 682 | && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_DEBUG))
|
---|
[99052] | 683 | {
|
---|
[100723] | 684 | /* Debug registers. */
|
---|
| 685 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
|
---|
| 686 | {
|
---|
| 687 | uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
|
---|
| 688 | hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, *pu64);
|
---|
| 689 | }
|
---|
| 690 | }
|
---|
| 691 |
|
---|
| 692 | if ( hrc == HV_SUCCESS
|
---|
[100724] | 693 | && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
|
---|
| 694 | {
|
---|
| 695 | /* Debug registers. */
|
---|
| 696 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
|
---|
| 697 | {
|
---|
| 698 | uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
|
---|
| 699 | hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, *pu64);
|
---|
| 700 | }
|
---|
| 701 | }
|
---|
| 702 |
|
---|
| 703 | if ( hrc == HV_SUCCESS
|
---|
[100723] | 704 | && (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC))
|
---|
| 705 | != (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC))
|
---|
| 706 | {
|
---|
[99052] | 707 | /* System registers. */
|
---|
| 708 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
|
---|
| 709 | {
|
---|
| 710 | if (!(s_aCpumSysRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
|
---|
| 711 | {
|
---|
| 712 | uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
|
---|
| 713 | hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, *pu64);
|
---|
| 714 | }
|
---|
| 715 | }
|
---|
| 716 | }
|
---|
| 717 |
|
---|
| 718 | if ( hrc == HV_SUCCESS
|
---|
| 719 | && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_PSTATE))
|
---|
| 720 | hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, pVCpu->cpum.GstCtx.fPState);
|
---|
| 721 |
|
---|
| 722 | pVCpu->cpum.GstCtx.fExtrn |= CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_KEEPER_NEM;
|
---|
| 723 | return nemR3DarwinHvSts2Rc(hrc);
|
---|
| 724 | }
|
---|
| 725 |
|
---|
| 726 |
|
---|
| 727 | /**
|
---|
| 728 | * Try initialize the native API.
|
---|
| 729 | *
|
---|
| 730 | * This may only do part of the job, more can be done in
|
---|
| 731 | * nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
|
---|
| 732 | *
|
---|
| 733 | * @returns VBox status code.
|
---|
| 734 | * @param pVM The cross context VM structure.
|
---|
| 735 | * @param fFallback Whether we're in fallback mode or use-NEM mode. In
|
---|
| 736 | * the latter we'll fail if we cannot initialize.
|
---|
| 737 | * @param fForced Whether the HMForced flag is set and we should
|
---|
| 738 | * fail if we cannot initialize.
|
---|
| 739 | */
|
---|
| 740 | int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
|
---|
| 741 | {
|
---|
| 742 | AssertReturn(!pVM->nem.s.fCreatedVm, VERR_WRONG_ORDER);
|
---|
| 743 |
|
---|
| 744 | /*
|
---|
| 745 | * Some state init.
|
---|
| 746 | */
|
---|
| 747 | PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
|
---|
| 748 | RT_NOREF(pCfgNem);
|
---|
| 749 |
|
---|
| 750 | /*
|
---|
| 751 | * Error state.
|
---|
| 752 | * The error message will be non-empty on failure and 'rc' will be set too.
|
---|
| 753 | */
|
---|
| 754 | RTERRINFOSTATIC ErrInfo;
|
---|
| 755 | PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
|
---|
| 756 |
|
---|
| 757 | int rc = VINF_SUCCESS;
|
---|
| 758 | hv_return_t hrc = hv_vm_create(NULL);
|
---|
| 759 | if (hrc == HV_SUCCESS)
|
---|
| 760 | {
|
---|
[99976] | 761 | pVM->nem.s.fCreatedVm = true;
|
---|
| 762 | pVM->nem.s.u64CntFrqHz = ASMReadCntFrqEl0();
|
---|
[100102] | 763 |
|
---|
| 764 | /* Will be initialized in NEMHCResumeCpuTickOnAll() before executing guest code. */
|
---|
| 765 | pVM->nem.s.u64VTimerOff = 0;
|
---|
| 766 |
|
---|
[99052] | 767 | VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
|
---|
| 768 | Log(("NEM: Marked active!\n"));
|
---|
| 769 | PGMR3EnableNemMode(pVM);
|
---|
| 770 | }
|
---|
| 771 | else
|
---|
| 772 | rc = RTErrInfoSetF(pErrInfo, VERR_NEM_INIT_FAILED,
|
---|
| 773 | "hv_vm_create() failed: %#x", hrc);
|
---|
| 774 |
|
---|
| 775 | /*
|
---|
| 776 | * We only fail if in forced mode, otherwise just log the complaint and return.
|
---|
| 777 | */
|
---|
| 778 | Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API || RTErrInfoIsSet(pErrInfo));
|
---|
| 779 | if ( (fForced || !fFallback)
|
---|
| 780 | && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
|
---|
| 781 | return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
|
---|
| 782 |
|
---|
| 783 | if (RTErrInfoIsSet(pErrInfo))
|
---|
| 784 | LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
|
---|
| 785 | return VINF_SUCCESS;
|
---|
| 786 | }
|
---|
| 787 |
|
---|
| 788 |
|
---|
| 789 | /**
|
---|
| 790 | * Worker to create the vCPU handle on the EMT running it later on (as required by HV).
|
---|
| 791 | *
|
---|
| 792 | * @returns VBox status code
|
---|
| 793 | * @param pVM The VM handle.
|
---|
| 794 | * @param pVCpu The vCPU handle.
|
---|
| 795 | * @param idCpu ID of the CPU to create.
|
---|
| 796 | */
|
---|
| 797 | static DECLCALLBACK(int) nemR3DarwinNativeInitVCpuOnEmt(PVM pVM, PVMCPU pVCpu, VMCPUID idCpu)
|
---|
| 798 | {
|
---|
[100708] | 799 | if (idCpu == 0)
|
---|
| 800 | {
|
---|
| 801 | Assert(pVM->nem.s.hVCpuCfg == NULL);
|
---|
| 802 |
|
---|
| 803 | /* Create a new vCPU config and query the ID registers. */
|
---|
| 804 | pVM->nem.s.hVCpuCfg = hv_vcpu_config_create();
|
---|
| 805 | if (!pVM->nem.s.hVCpuCfg)
|
---|
| 806 | return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
|
---|
| 807 | "Call to hv_vcpu_config_create failed on vCPU %u", idCpu);
|
---|
| 808 |
|
---|
[101104] | 809 | /* Query ID registers and hand them to CPUM. */
|
---|
[101115] | 810 | CPUMIDREGS IdRegs; RT_ZERO(IdRegs);
|
---|
[100708] | 811 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aIdRegs); i++)
|
---|
| 812 | {
|
---|
[101104] | 813 | uint64_t *pu64 = (uint64_t *)((uint8_t *)&IdRegs + s_aIdRegs[i].offIdStruct);
|
---|
[100708] | 814 | hv_return_t hrc = hv_vcpu_config_get_feature_reg(pVM->nem.s.hVCpuCfg, s_aIdRegs[i].enmHvReg, pu64);
|
---|
| 815 | if (hrc != HV_SUCCESS)
|
---|
| 816 | return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
|
---|
| 817 | "Call to hv_vcpu_get_feature_reg(, %#x, ) failed: %#x (%Rrc)", hrc, nemR3DarwinHvSts2Rc(hrc));
|
---|
| 818 | }
|
---|
[101104] | 819 |
|
---|
| 820 | int rc = CPUMR3PopulateFeaturesByIdRegisters(pVM, &IdRegs);
|
---|
| 821 | if (RT_FAILURE(rc))
|
---|
| 822 | return rc;
|
---|
[100708] | 823 | }
|
---|
| 824 |
|
---|
| 825 | hv_return_t hrc = hv_vcpu_create(&pVCpu->nem.s.hVCpu, &pVCpu->nem.s.pHvExit, pVM->nem.s.hVCpuCfg);
|
---|
[99052] | 826 | if (hrc != HV_SUCCESS)
|
---|
| 827 | return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
|
---|
| 828 | "Call to hv_vcpu_create failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
|
---|
| 829 |
|
---|
[100102] | 830 | hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MPIDR_EL1, idCpu);
|
---|
| 831 | if (hrc != HV_SUCCESS)
|
---|
| 832 | return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
|
---|
| 833 | "Setting MPIDR_EL1 failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
|
---|
[99976] | 834 |
|
---|
[99052] | 835 | return VINF_SUCCESS;
|
---|
| 836 | }
|
---|
| 837 |
|
---|
| 838 |
|
---|
| 839 | /**
|
---|
| 840 | * Worker to destroy the vCPU handle on the EMT running it later on (as required by HV).
|
---|
| 841 | *
|
---|
[100708] | 842 | * @returns VBox status code.
|
---|
| 843 | * @param pVM The VM handle.
|
---|
[99052] | 844 | * @param pVCpu The vCPU handle.
|
---|
| 845 | */
|
---|
[100708] | 846 | static DECLCALLBACK(int) nemR3DarwinNativeTermVCpuOnEmt(PVM pVM, PVMCPU pVCpu)
|
---|
[99052] | 847 | {
|
---|
| 848 | hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
|
---|
| 849 | Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
|
---|
[100708] | 850 |
|
---|
| 851 | if (pVCpu->idCpu == 0)
|
---|
| 852 | {
|
---|
| 853 | os_release(pVM->nem.s.hVCpuCfg);
|
---|
| 854 | pVM->nem.s.hVCpuCfg = NULL;
|
---|
| 855 | }
|
---|
[99052] | 856 | return VINF_SUCCESS;
|
---|
| 857 | }
|
---|
| 858 |
|
---|
| 859 |
|
---|
| 860 | /**
|
---|
| 861 | * This is called after CPUMR3Init is done.
|
---|
| 862 | *
|
---|
| 863 | * @returns VBox status code.
|
---|
| 864 | * @param pVM The VM handle..
|
---|
| 865 | */
|
---|
| 866 | int nemR3NativeInitAfterCPUM(PVM pVM)
|
---|
| 867 | {
|
---|
| 868 | /*
|
---|
| 869 | * Validate sanity.
|
---|
| 870 | */
|
---|
| 871 | AssertReturn(!pVM->nem.s.fCreatedEmts, VERR_WRONG_ORDER);
|
---|
| 872 | AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
|
---|
| 873 |
|
---|
| 874 | /*
|
---|
| 875 | * Setup the EMTs.
|
---|
| 876 | */
|
---|
| 877 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
| 878 | {
|
---|
| 879 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
|
---|
| 880 |
|
---|
| 881 | int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitVCpuOnEmt, 3, pVM, pVCpu, idCpu);
|
---|
| 882 | if (RT_FAILURE(rc))
|
---|
| 883 | {
|
---|
| 884 | /* Rollback. */
|
---|
| 885 | while (idCpu--)
|
---|
[100708] | 886 | VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeTermVCpuOnEmt, 2, pVM, pVCpu);
|
---|
[99052] | 887 |
|
---|
| 888 | return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Call to hv_vcpu_create failed: %Rrc", rc);
|
---|
| 889 | }
|
---|
| 890 | }
|
---|
| 891 |
|
---|
| 892 | pVM->nem.s.fCreatedEmts = true;
|
---|
| 893 | return VINF_SUCCESS;
|
---|
| 894 | }
|
---|
| 895 |
|
---|
| 896 |
|
---|
| 897 | int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
|
---|
| 898 | {
|
---|
| 899 | RT_NOREF(pVM, enmWhat);
|
---|
| 900 | return VINF_SUCCESS;
|
---|
| 901 | }
|
---|
| 902 |
|
---|
| 903 |
|
---|
| 904 | int nemR3NativeTerm(PVM pVM)
|
---|
| 905 | {
|
---|
| 906 | /*
|
---|
| 907 | * Delete the VM.
|
---|
| 908 | */
|
---|
| 909 |
|
---|
| 910 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu--)
|
---|
| 911 | {
|
---|
| 912 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
|
---|
| 913 |
|
---|
| 914 | /*
|
---|
| 915 | * Apple's documentation states that the vCPU should be destroyed
|
---|
| 916 | * on the thread running the vCPU but as all the other EMTs are gone
|
---|
| 917 | * at this point, destroying the VM would hang.
|
---|
| 918 | *
|
---|
| 919 | * We seem to be at luck here though as destroying apparently works
|
---|
| 920 | * from EMT(0) as well.
|
---|
| 921 | */
|
---|
| 922 | hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
|
---|
| 923 | Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
|
---|
| 924 | }
|
---|
| 925 |
|
---|
| 926 | pVM->nem.s.fCreatedEmts = false;
|
---|
| 927 | if (pVM->nem.s.fCreatedVm)
|
---|
| 928 | {
|
---|
| 929 | hv_return_t hrc = hv_vm_destroy();
|
---|
| 930 | if (hrc != HV_SUCCESS)
|
---|
| 931 | LogRel(("NEM: hv_vm_destroy() failed with %#x\n", hrc));
|
---|
| 932 |
|
---|
| 933 | pVM->nem.s.fCreatedVm = false;
|
---|
| 934 | }
|
---|
| 935 | return VINF_SUCCESS;
|
---|
| 936 | }
|
---|
| 937 |
|
---|
| 938 |
|
---|
| 939 | /**
|
---|
| 940 | * VM reset notification.
|
---|
| 941 | *
|
---|
| 942 | * @param pVM The cross context VM structure.
|
---|
| 943 | */
|
---|
| 944 | void nemR3NativeReset(PVM pVM)
|
---|
| 945 | {
|
---|
| 946 | RT_NOREF(pVM);
|
---|
| 947 | }
|
---|
| 948 |
|
---|
| 949 |
|
---|
| 950 | /**
|
---|
| 951 | * Reset CPU due to INIT IPI or hot (un)plugging.
|
---|
| 952 | *
|
---|
| 953 | * @param pVCpu The cross context virtual CPU structure of the CPU being
|
---|
| 954 | * reset.
|
---|
| 955 | * @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
|
---|
| 956 | */
|
---|
| 957 | void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
|
---|
| 958 | {
|
---|
| 959 | RT_NOREF(pVCpu, fInitIpi);
|
---|
| 960 | }
|
---|
| 961 |
|
---|
| 962 |
|
---|
| 963 | /**
|
---|
[99078] | 964 | * Returns the byte size from the given access SAS value.
|
---|
| 965 | *
|
---|
| 966 | * @returns Number of bytes to transfer.
|
---|
| 967 | * @param uSas The SAS value to convert.
|
---|
| 968 | */
|
---|
| 969 | DECLINLINE(size_t) nemR3DarwinGetByteCountFromSas(uint8_t uSas)
|
---|
| 970 | {
|
---|
| 971 | switch (uSas)
|
---|
| 972 | {
|
---|
| 973 | case ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE: return sizeof(uint8_t);
|
---|
| 974 | case ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD: return sizeof(uint16_t);
|
---|
| 975 | case ARMV8_EC_ISS_DATA_ABRT_SAS_WORD: return sizeof(uint32_t);
|
---|
| 976 | case ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD: return sizeof(uint64_t);
|
---|
| 977 | default:
|
---|
| 978 | AssertReleaseFailed();
|
---|
| 979 | }
|
---|
| 980 |
|
---|
| 981 | return 0;
|
---|
| 982 | }
|
---|
| 983 |
|
---|
| 984 |
|
---|
| 985 | /**
|
---|
| 986 | * Sets the given general purpose register to the given value.
|
---|
| 987 | *
|
---|
| 988 | * @param pVCpu The cross context virtual CPU structure of the
|
---|
| 989 | * calling EMT.
|
---|
| 990 | * @param uReg The register index.
|
---|
| 991 | * @param f64BitReg Flag whether to operate on a 64-bit or 32-bit register.
|
---|
| 992 | * @param fSignExtend Flag whether to sign extend the value.
|
---|
| 993 | * @param u64Val The value.
|
---|
| 994 | */
|
---|
| 995 | DECLINLINE(void) nemR3DarwinSetGReg(PVMCPU pVCpu, uint8_t uReg, bool f64BitReg, bool fSignExtend, uint64_t u64Val)
|
---|
| 996 | {
|
---|
| 997 | AssertReturnVoid(uReg < 31);
|
---|
| 998 |
|
---|
| 999 | if (f64BitReg)
|
---|
| 1000 | pVCpu->cpum.GstCtx.aGRegs[uReg].x = fSignExtend ? (int64_t)u64Val : u64Val;
|
---|
| 1001 | else
|
---|
| 1002 | pVCpu->cpum.GstCtx.aGRegs[uReg].w = fSignExtend ? (int32_t)u64Val : u64Val; /** @todo Does this clear the upper half on real hardware? */
|
---|
| 1003 |
|
---|
| 1004 | /* Mark the register as not extern anymore. */
|
---|
| 1005 | switch (uReg)
|
---|
| 1006 | {
|
---|
| 1007 | case 0:
|
---|
| 1008 | pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X0;
|
---|
| 1009 | break;
|
---|
| 1010 | case 1:
|
---|
| 1011 | pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X1;
|
---|
| 1012 | break;
|
---|
| 1013 | case 2:
|
---|
| 1014 | pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X2;
|
---|
| 1015 | break;
|
---|
| 1016 | case 3:
|
---|
| 1017 | pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X3;
|
---|
| 1018 | break;
|
---|
| 1019 | default:
|
---|
| 1020 | AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_X4_X28));
|
---|
| 1021 | /** @todo We need to import all missing registers in order to clear this flag (or just set it in HV from here). */
|
---|
| 1022 | }
|
---|
| 1023 | }
|
---|
| 1024 |
|
---|
| 1025 |
|
---|
| 1026 | /**
|
---|
| 1027 | * Gets the given general purpose register and returns the value.
|
---|
| 1028 | *
|
---|
| 1029 | * @returns Value from the given register.
|
---|
| 1030 | * @param pVCpu The cross context virtual CPU structure of the
|
---|
| 1031 | * calling EMT.
|
---|
| 1032 | * @param uReg The register index.
|
---|
| 1033 | */
|
---|
| 1034 | DECLINLINE(uint64_t) nemR3DarwinGetGReg(PVMCPU pVCpu, uint8_t uReg)
|
---|
| 1035 | {
|
---|
[99575] | 1036 | AssertReturn(uReg <= ARMV8_AARCH64_REG_ZR, 0);
|
---|
[99078] | 1037 |
|
---|
[99575] | 1038 | if (uReg == ARMV8_AARCH64_REG_ZR)
|
---|
| 1039 | return 0;
|
---|
| 1040 |
|
---|
[99078] | 1041 | /** @todo Import the register if extern. */
|
---|
| 1042 | AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_GPRS_MASK));
|
---|
| 1043 |
|
---|
| 1044 | return pVCpu->cpum.GstCtx.aGRegs[uReg].x;
|
---|
| 1045 | }
|
---|
| 1046 |
|
---|
| 1047 |
|
---|
| 1048 | /**
|
---|
| 1049 | * Works on the data abort exception (which will be a MMIO access most of the time).
|
---|
| 1050 | *
|
---|
| 1051 | * @returns VBox strict status code.
|
---|
| 1052 | * @param pVM The cross context VM structure.
|
---|
| 1053 | * @param pVCpu The cross context virtual CPU structure of the
|
---|
| 1054 | * calling EMT.
|
---|
| 1055 | * @param uIss The instruction specific syndrome value.
|
---|
| 1056 | * @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
|
---|
| 1057 | * @param GCPtrDataAbrt The virtual GC address causing the data abort.
|
---|
| 1058 | * @param GCPhysDataAbrt The physical GC address which caused the data abort.
|
---|
| 1059 | */
|
---|
| 1060 | static VBOXSTRICTRC nemR3DarwinHandleExitExceptionDataAbort(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit,
|
---|
| 1061 | RTGCPTR GCPtrDataAbrt, RTGCPHYS GCPhysDataAbrt)
|
---|
| 1062 | {
|
---|
| 1063 | bool fIsv = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_ISV);
|
---|
| 1064 | bool fL2Fault = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_S1PTW);
|
---|
| 1065 | bool fWrite = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_WNR);
|
---|
| 1066 | bool f64BitReg = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SF);
|
---|
| 1067 | bool fSignExtend = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SSE);
|
---|
| 1068 | uint8_t uReg = ARMV8_EC_ISS_DATA_ABRT_SRT_GET(uIss);
|
---|
| 1069 | uint8_t uAcc = ARMV8_EC_ISS_DATA_ABRT_SAS_GET(uIss);
|
---|
| 1070 | size_t cbAcc = nemR3DarwinGetByteCountFromSas(uAcc);
|
---|
| 1071 | LogFlowFunc(("fIsv=%RTbool fL2Fault=%RTbool fWrite=%RTbool f64BitReg=%RTbool fSignExtend=%RTbool uReg=%u uAcc=%u GCPtrDataAbrt=%RGv GCPhysDataAbrt=%RGp\n",
|
---|
| 1072 | fIsv, fL2Fault, fWrite, f64BitReg, fSignExtend, uReg, uAcc, GCPtrDataAbrt, GCPhysDataAbrt));
|
---|
| 1073 |
|
---|
[100108] | 1074 | RT_NOREF(fL2Fault, GCPtrDataAbrt);
|
---|
[100705] | 1075 |
|
---|
| 1076 | if (fWrite)
|
---|
| 1077 | {
|
---|
| 1078 | /*
|
---|
| 1079 | * Check whether this is one of the dirty tracked regions, mark it as dirty
|
---|
| 1080 | * and enable write support for this region again.
|
---|
| 1081 | *
|
---|
| 1082 | * This is required for proper VRAM tracking or the display might not get updated
|
---|
| 1083 | * and it is impossible to use the PGM generic facility as it operates on guest page sizes
|
---|
| 1084 | * but setting protection flags with Hypervisor.framework works only host page sized regions, so
|
---|
| 1085 | * we have to cook our own. Additionally the VRAM region is marked as prefetchable (write-back)
|
---|
| 1086 | * which doesn't produce a valid instruction syndrome requiring restarting the instruction after enabling
|
---|
| 1087 | * write access again (due to a missing interpreter right now).
|
---|
| 1088 | */
|
---|
| 1089 | for (uint32_t idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
|
---|
| 1090 | {
|
---|
| 1091 | PNEMHVMMIO2REGION pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
|
---|
| 1092 |
|
---|
| 1093 | if ( GCPhysDataAbrt >= pMmio2Region->GCPhysStart
|
---|
| 1094 | && GCPhysDataAbrt <= pMmio2Region->GCPhysLast)
|
---|
| 1095 | {
|
---|
| 1096 | pMmio2Region->fDirty = true;
|
---|
| 1097 |
|
---|
| 1098 | uint8_t u2State;
|
---|
| 1099 | int rc = nemR3DarwinProtect(pMmio2Region->GCPhysStart, pMmio2Region->GCPhysLast - pMmio2Region->GCPhysStart + 1,
|
---|
| 1100 | NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE | NEM_PAGE_PROT_WRITE, &u2State);
|
---|
| 1101 |
|
---|
| 1102 | /* Restart the instruction if there is no instruction syndrome available. */
|
---|
| 1103 | if (RT_FAILURE(rc) || !fIsv)
|
---|
| 1104 | return rc;
|
---|
| 1105 | }
|
---|
| 1106 | }
|
---|
| 1107 | }
|
---|
| 1108 |
|
---|
[99078] | 1109 | AssertReturn(fIsv, VERR_NOT_SUPPORTED); /** @todo Implement using IEM when this should occur. */
|
---|
| 1110 |
|
---|
| 1111 | EMHistoryAddExit(pVCpu,
|
---|
| 1112 | fWrite
|
---|
| 1113 | ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
|
---|
| 1114 | : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
|
---|
| 1115 | pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
|
---|
| 1116 |
|
---|
| 1117 | VBOXSTRICTRC rcStrict = VINF_SUCCESS;
|
---|
[99575] | 1118 | uint64_t u64Val = 0;
|
---|
[99078] | 1119 | if (fWrite)
|
---|
| 1120 | {
|
---|
| 1121 | u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
|
---|
| 1122 | rcStrict = PGMPhysWrite(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
|
---|
| 1123 | Log4(("MmioExit/%u: %08RX64: WRITE %#x LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
|
---|
| 1124 | pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
|
---|
| 1125 | &u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
|
---|
| 1126 | }
|
---|
| 1127 | else
|
---|
| 1128 | {
|
---|
| 1129 | rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
|
---|
| 1130 | Log4(("MmioExit/%u: %08RX64: READ %#x LB %u -> %.*Rhxs rcStrict=%Rrc\n",
|
---|
| 1131 | pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
|
---|
| 1132 | &u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
|
---|
| 1133 | if (rcStrict == VINF_SUCCESS)
|
---|
| 1134 | nemR3DarwinSetGReg(pVCpu, uReg, f64BitReg, fSignExtend, u64Val);
|
---|
| 1135 | }
|
---|
| 1136 |
|
---|
| 1137 | if (rcStrict == VINF_SUCCESS)
|
---|
| 1138 | pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
|
---|
| 1139 |
|
---|
| 1140 | return rcStrict;
|
---|
| 1141 | }
|
---|
| 1142 |
|
---|
| 1143 |
|
---|
| 1144 | /**
|
---|
[99190] | 1145 | * Works on the trapped MRS, MSR and system instruction exception.
|
---|
| 1146 | *
|
---|
| 1147 | * @returns VBox strict status code.
|
---|
| 1148 | * @param pVM The cross context VM structure.
|
---|
| 1149 | * @param pVCpu The cross context virtual CPU structure of the
|
---|
| 1150 | * calling EMT.
|
---|
| 1151 | * @param uIss The instruction specific syndrome value.
|
---|
| 1152 | * @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
|
---|
| 1153 | */
|
---|
| 1154 | static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedSysInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit)
|
---|
| 1155 | {
|
---|
| 1156 | bool fRead = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(uIss);
|
---|
| 1157 | uint8_t uCRm = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(uIss);
|
---|
| 1158 | uint8_t uReg = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(uIss);
|
---|
| 1159 | uint8_t uCRn = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(uIss);
|
---|
| 1160 | uint8_t uOp1 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(uIss);
|
---|
| 1161 | uint8_t uOp2 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(uIss);
|
---|
| 1162 | uint8_t uOp0 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(uIss);
|
---|
| 1163 | uint16_t idSysReg = ARMV8_AARCH64_SYSREG_ID_CREATE(uOp0, uOp1, uCRn, uCRm, uOp2);
|
---|
| 1164 | LogFlowFunc(("fRead=%RTbool uCRm=%u uReg=%u uCRn=%u uOp1=%u uOp2=%u uOp0=%u idSysReg=%#x\n",
|
---|
| 1165 | fRead, uCRm, uReg, uCRn, uOp1, uOp2, uOp0, idSysReg));
|
---|
| 1166 |
|
---|
| 1167 | /** @todo EMEXITTYPE_MSR_READ/EMEXITTYPE_MSR_WRITE are misnomers. */
|
---|
| 1168 | EMHistoryAddExit(pVCpu,
|
---|
| 1169 | fRead
|
---|
| 1170 | ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
|
---|
| 1171 | : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
|
---|
| 1172 | pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
|
---|
| 1173 |
|
---|
| 1174 | VBOXSTRICTRC rcStrict = VINF_SUCCESS;
|
---|
| 1175 | uint64_t u64Val = 0;
|
---|
| 1176 | if (fRead)
|
---|
| 1177 | {
|
---|
| 1178 | RT_NOREF(pVM);
|
---|
[99197] | 1179 | rcStrict = CPUMQueryGuestSysReg(pVCpu, idSysReg, &u64Val);
|
---|
[99190] | 1180 | Log4(("SysInsnExit/%u: %08RX64: READ %u:%u:%u:%u:%u -> %#RX64 rcStrict=%Rrc\n",
|
---|
| 1181 | pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
|
---|
| 1182 | VBOXSTRICTRC_VAL(rcStrict) ));
|
---|
| 1183 | if (rcStrict == VINF_SUCCESS)
|
---|
| 1184 | nemR3DarwinSetGReg(pVCpu, uReg, true /*f64BitReg*/, false /*fSignExtend*/, u64Val);
|
---|
| 1185 | }
|
---|
| 1186 | else
|
---|
| 1187 | {
|
---|
| 1188 | u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
|
---|
[99197] | 1189 | rcStrict = CPUMSetGuestSysReg(pVCpu, idSysReg, u64Val);
|
---|
[99190] | 1190 | Log4(("SysInsnExit/%u: %08RX64: WRITE %u:%u:%u:%u:%u %#RX64 -> rcStrict=%Rrc\n",
|
---|
| 1191 | pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
|
---|
| 1192 | VBOXSTRICTRC_VAL(rcStrict) ));
|
---|
| 1193 | }
|
---|
| 1194 |
|
---|
| 1195 | if (rcStrict == VINF_SUCCESS)
|
---|
| 1196 | pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
|
---|
| 1197 |
|
---|
| 1198 | return rcStrict;
|
---|
| 1199 | }
|
---|
| 1200 |
|
---|
| 1201 |
|
---|
| 1202 | /**
|
---|
[99575] | 1203 | * Works on the trapped HVC instruction exception.
|
---|
| 1204 | *
|
---|
| 1205 | * @returns VBox strict status code.
|
---|
| 1206 | * @param pVM The cross context VM structure.
|
---|
| 1207 | * @param pVCpu The cross context virtual CPU structure of the
|
---|
| 1208 | * calling EMT.
|
---|
| 1209 | * @param uIss The instruction specific syndrome value.
|
---|
| 1210 | */
|
---|
| 1211 | static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedHvcInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss)
|
---|
| 1212 | {
|
---|
| 1213 | uint16_t u16Imm = ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(uIss);
|
---|
| 1214 | LogFlowFunc(("u16Imm=%#RX16\n", u16Imm));
|
---|
| 1215 |
|
---|
| 1216 | #if 0 /** @todo For later */
|
---|
| 1217 | EMHistoryAddExit(pVCpu,
|
---|
| 1218 | fRead
|
---|
| 1219 | ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
|
---|
| 1220 | : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
|
---|
| 1221 | pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
|
---|
| 1222 | #endif
|
---|
| 1223 |
|
---|
| 1224 | VBOXSTRICTRC rcStrict = VINF_SUCCESS;
|
---|
[100102] | 1225 | if (u16Imm == 0)
|
---|
| 1226 | {
|
---|
| 1227 | /** @todo Raise exception to EL1 if PSCI not configured. */
|
---|
| 1228 | /** @todo Need a generic mechanism here to pass this to, GIM maybe?. */
|
---|
| 1229 | uint32_t uFunId = pVCpu->cpum.GstCtx.aGRegs[ARMV8_AARCH64_REG_X0].w;
|
---|
| 1230 | bool fHvc64 = RT_BOOL(uFunId & ARM_SMCCC_FUNC_ID_64BIT); RT_NOREF(fHvc64);
|
---|
| 1231 | uint32_t uEntity = ARM_SMCCC_FUNC_ID_ENTITY_GET(uFunId);
|
---|
| 1232 | uint32_t uFunNum = ARM_SMCCC_FUNC_ID_NUM_GET(uFunId);
|
---|
| 1233 | if (uEntity == ARM_SMCCC_FUNC_ID_ENTITY_STD_SEC_SERVICE)
|
---|
| 1234 | {
|
---|
| 1235 | switch (uFunNum)
|
---|
| 1236 | {
|
---|
| 1237 | case ARM_PSCI_FUNC_ID_PSCI_VERSION:
|
---|
| 1238 | nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /*f64BitReg*/, false /*fSignExtend*/, ARM_PSCI_FUNC_ID_PSCI_VERSION_SET(1, 2));
|
---|
| 1239 | break;
|
---|
| 1240 | case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
|
---|
[100117] | 1241 | rcStrict = VMR3PowerOff(pVM->pUVM);
|
---|
[100102] | 1242 | break;
|
---|
| 1243 | case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
|
---|
[100117] | 1244 | case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
|
---|
| 1245 | {
|
---|
| 1246 | bool fHaltOnReset;
|
---|
| 1247 | int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
|
---|
| 1248 | if (RT_SUCCESS(rc) && fHaltOnReset)
|
---|
| 1249 | {
|
---|
| 1250 | Log(("nemR3DarwinHandleExitExceptionTrappedHvcInsn: Halt On Reset!\n"));
|
---|
| 1251 | rc = VINF_EM_HALT;
|
---|
| 1252 | }
|
---|
| 1253 | else
|
---|
| 1254 | {
|
---|
| 1255 | /** @todo pVM->pdm.s.fResetFlags = fFlags; */
|
---|
| 1256 | VM_FF_SET(pVM, VM_FF_RESET);
|
---|
| 1257 | rc = VINF_EM_RESET;
|
---|
| 1258 | }
|
---|
[100102] | 1259 | break;
|
---|
[100117] | 1260 | }
|
---|
[100102] | 1261 | case ARM_PSCI_FUNC_ID_CPU_ON:
|
---|
| 1262 | {
|
---|
| 1263 | uint64_t u64TgtCpu = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
|
---|
| 1264 | RTGCPHYS GCPhysExecAddr = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X2);
|
---|
| 1265 | uint64_t u64CtxId = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X3);
|
---|
| 1266 | VMMR3CpuOn(pVM, u64TgtCpu & 0xff, GCPhysExecAddr, u64CtxId);
|
---|
| 1267 | nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, true /*f64BitReg*/, false /*fSignExtend*/, ARM_PSCI_STS_SUCCESS);
|
---|
| 1268 | break;
|
---|
| 1269 | }
|
---|
[100166] | 1270 | case ARM_PSCI_FUNC_ID_PSCI_FEATURES:
|
---|
| 1271 | {
|
---|
| 1272 | uint32_t u32FunNum = (uint32_t)nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
|
---|
| 1273 | switch (u32FunNum)
|
---|
| 1274 | {
|
---|
| 1275 | case ARM_PSCI_FUNC_ID_PSCI_VERSION:
|
---|
| 1276 | case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
|
---|
| 1277 | case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
|
---|
| 1278 | case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
|
---|
| 1279 | case ARM_PSCI_FUNC_ID_CPU_ON:
|
---|
| 1280 | nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
|
---|
| 1281 | false /*f64BitReg*/, false /*fSignExtend*/,
|
---|
| 1282 | (uint64_t)ARM_PSCI_STS_SUCCESS);
|
---|
| 1283 | break;
|
---|
| 1284 | default:
|
---|
| 1285 | nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
|
---|
| 1286 | false /*f64BitReg*/, false /*fSignExtend*/,
|
---|
| 1287 | (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
|
---|
| 1288 | }
|
---|
[103298] | 1289 | break;
|
---|
[100166] | 1290 | }
|
---|
[100102] | 1291 | default:
|
---|
| 1292 | nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /*f64BitReg*/, false /*fSignExtend*/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
|
---|
| 1293 | }
|
---|
| 1294 | }
|
---|
| 1295 | else
|
---|
| 1296 | nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /*f64BitReg*/, false /*fSignExtend*/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
|
---|
| 1297 | }
|
---|
| 1298 | /** @todo What to do if immediate is != 0? */
|
---|
[99575] | 1299 |
|
---|
| 1300 | return rcStrict;
|
---|
| 1301 | }
|
---|
| 1302 |
|
---|
| 1303 |
|
---|
| 1304 | /**
|
---|
[99078] | 1305 | * Handles an exception VM exit.
|
---|
| 1306 | *
|
---|
| 1307 | * @returns VBox strict status code.
|
---|
| 1308 | * @param pVM The cross context VM structure.
|
---|
| 1309 | * @param pVCpu The cross context virtual CPU structure of the
|
---|
| 1310 | * calling EMT.
|
---|
| 1311 | * @param pExit Pointer to the exit information.
|
---|
| 1312 | */
|
---|
| 1313 | static VBOXSTRICTRC nemR3DarwinHandleExitException(PVM pVM, PVMCPU pVCpu, const hv_vcpu_exit_t *pExit)
|
---|
| 1314 | {
|
---|
| 1315 | uint32_t uEc = ARMV8_ESR_EL2_EC_GET(pExit->exception.syndrome);
|
---|
| 1316 | uint32_t uIss = ARMV8_ESR_EL2_ISS_GET(pExit->exception.syndrome);
|
---|
| 1317 | bool fInsn32Bit = ARMV8_ESR_EL2_IL_IS_32BIT(pExit->exception.syndrome);
|
---|
| 1318 |
|
---|
| 1319 | LogFlowFunc(("pVM=%p pVCpu=%p{.idCpu=%u} uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
|
---|
| 1320 | pVM, pVCpu, pVCpu->idCpu, uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
|
---|
| 1321 |
|
---|
| 1322 | switch (uEc)
|
---|
| 1323 | {
|
---|
| 1324 | case ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL:
|
---|
| 1325 | return nemR3DarwinHandleExitExceptionDataAbort(pVM, pVCpu, uIss, fInsn32Bit, pExit->exception.virtual_address,
|
---|
| 1326 | pExit->exception.physical_address);
|
---|
[99190] | 1327 | case ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN:
|
---|
| 1328 | return nemR3DarwinHandleExitExceptionTrappedSysInsn(pVM, pVCpu, uIss, fInsn32Bit);
|
---|
[99575] | 1329 | case ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN:
|
---|
| 1330 | return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss);
|
---|
| 1331 | case ARMV8_ESR_EL2_EC_TRAPPED_WFX:
|
---|
[100001] | 1332 | {
|
---|
| 1333 | /* No need to halt if there is an interrupt pending already. */
|
---|
| 1334 | if (VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ)))
|
---|
| 1335 | return VINF_SUCCESS;
|
---|
| 1336 |
|
---|
| 1337 | /* Set the vTimer expiration in order to get out of the halt at the right point in time. */
|
---|
| 1338 | if ( (pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE)
|
---|
| 1339 | && !(pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_IMASK))
|
---|
| 1340 | {
|
---|
[100102] | 1341 | uint64_t cTicksVTimer = mach_absolute_time() - pVM->nem.s.u64VTimerOff;
|
---|
[100001] | 1342 |
|
---|
| 1343 | /* Check whether it expired and start executing guest code. */
|
---|
| 1344 | if (cTicksVTimer >= pVCpu->cpum.GstCtx.CntvCValEl0)
|
---|
| 1345 | return VINF_SUCCESS;
|
---|
| 1346 |
|
---|
| 1347 | uint64_t cTicksVTimerToExpire = pVCpu->cpum.GstCtx.CntvCValEl0 - cTicksVTimer;
|
---|
| 1348 | uint64_t cNanoSecsVTimerToExpire = ASMMultU64ByU32DivByU32(cTicksVTimerToExpire, RT_NS_1SEC, (uint32_t)pVM->nem.s.u64CntFrqHz);
|
---|
| 1349 |
|
---|
[100003] | 1350 | /*
|
---|
| 1351 | * Our halt method doesn't work with sub millisecond granularity at the moment causing a huge slowdown
|
---|
| 1352 | * + scheduling overhead which would increase the wakeup latency.
|
---|
| 1353 | * So only halt when the threshold is exceeded (needs more experimentation but 5ms turned out to be a good compromise
|
---|
| 1354 | * between CPU load when the guest is idle and performance).
|
---|
| 1355 | */
|
---|
[100102] | 1356 | if (cNanoSecsVTimerToExpire < 2 * RT_NS_1MS)
|
---|
[100001] | 1357 | return VINF_SUCCESS;
|
---|
| 1358 |
|
---|
[100076] | 1359 | LogFlowFunc(("Set vTimer activation to cNanoSecsVTimerToExpire=%#RX64 (CntvCValEl0=%#RX64, u64VTimerOff=%#RX64 cTicksVTimer=%#RX64 u64CntFrqHz=%#RX64)\n",
|
---|
[100102] | 1360 | cNanoSecsVTimerToExpire, pVCpu->cpum.GstCtx.CntvCValEl0, pVM->nem.s.u64VTimerOff, cTicksVTimer, pVM->nem.s.u64CntFrqHz));
|
---|
[100001] | 1361 | TMCpuSetVTimerNextActivation(pVCpu, cNanoSecsVTimerToExpire);
|
---|
| 1362 | }
|
---|
| 1363 | else
|
---|
| 1364 | TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
|
---|
| 1365 |
|
---|
| 1366 | return VINF_EM_HALT;
|
---|
| 1367 | }
|
---|
[99078] | 1368 | case ARMV8_ESR_EL2_EC_UNKNOWN:
|
---|
| 1369 | default:
|
---|
| 1370 | LogRel(("NEM/Darwin: Unknown Exception Class in syndrome: uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
|
---|
| 1371 | uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
|
---|
[99575] | 1372 | AssertReleaseFailed();
|
---|
[99078] | 1373 | return VERR_NOT_IMPLEMENTED;
|
---|
| 1374 | }
|
---|
| 1375 |
|
---|
| 1376 | return VINF_SUCCESS;
|
---|
| 1377 | }
|
---|
| 1378 |
|
---|
| 1379 |
|
---|
| 1380 | /**
|
---|
[99052] | 1381 | * Handles an exit from hv_vcpu_run().
|
---|
| 1382 | *
|
---|
| 1383 | * @returns VBox strict status code.
|
---|
| 1384 | * @param pVM The cross context VM structure.
|
---|
| 1385 | * @param pVCpu The cross context virtual CPU structure of the
|
---|
| 1386 | * calling EMT.
|
---|
| 1387 | */
|
---|
| 1388 | static VBOXSTRICTRC nemR3DarwinHandleExit(PVM pVM, PVMCPU pVCpu)
|
---|
| 1389 | {
|
---|
| 1390 | int rc = nemR3DarwinCopyStateFromHv(pVM, pVCpu, CPUMCTX_EXTRN_ALL);
|
---|
| 1391 | if (RT_FAILURE(rc))
|
---|
| 1392 | return rc;
|
---|
| 1393 |
|
---|
[99070] | 1394 | #ifdef LOG_ENABLED
|
---|
| 1395 | if (LogIs3Enabled())
|
---|
| 1396 | nemR3DarwinLogState(pVM, pVCpu);
|
---|
| 1397 | #endif
|
---|
| 1398 |
|
---|
[99052] | 1399 | hv_vcpu_exit_t *pExit = pVCpu->nem.s.pHvExit;
|
---|
| 1400 | switch (pExit->reason)
|
---|
| 1401 | {
|
---|
| 1402 | case HV_EXIT_REASON_CANCELED:
|
---|
| 1403 | return VINF_EM_RAW_INTERRUPT;
|
---|
[99078] | 1404 | case HV_EXIT_REASON_EXCEPTION:
|
---|
| 1405 | return nemR3DarwinHandleExitException(pVM, pVCpu, pExit);
|
---|
[99575] | 1406 | case HV_EXIT_REASON_VTIMER_ACTIVATED:
|
---|
[100001] | 1407 | {
|
---|
| 1408 | LogFlowFunc(("vTimer got activated\n"));
|
---|
| 1409 | TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
|
---|
[99735] | 1410 | pVCpu->nem.s.fVTimerActivated = true;
|
---|
[101496] | 1411 | return GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, true /*fAsserted*/);
|
---|
[100001] | 1412 | }
|
---|
[99052] | 1413 | default:
|
---|
| 1414 | AssertReleaseFailed();
|
---|
| 1415 | break;
|
---|
| 1416 | }
|
---|
| 1417 |
|
---|
| 1418 | return VERR_INVALID_STATE;
|
---|
| 1419 | }
|
---|
| 1420 |
|
---|
| 1421 |
|
---|
| 1422 | /**
|
---|
| 1423 | * Runs the guest once until an exit occurs.
|
---|
| 1424 | *
|
---|
| 1425 | * @returns HV status code.
|
---|
| 1426 | * @param pVM The cross context VM structure.
|
---|
| 1427 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 1428 | */
|
---|
| 1429 | static hv_return_t nemR3DarwinRunGuest(PVM pVM, PVMCPU pVCpu)
|
---|
| 1430 | {
|
---|
| 1431 | TMNotifyStartOfExecution(pVM, pVCpu);
|
---|
| 1432 |
|
---|
| 1433 | hv_return_t hrc = hv_vcpu_run(pVCpu->nem.s.hVCpu);
|
---|
| 1434 |
|
---|
| 1435 | TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
|
---|
| 1436 |
|
---|
| 1437 | return hrc;
|
---|
| 1438 | }
|
---|
| 1439 |
|
---|
| 1440 |
|
---|
| 1441 | /**
|
---|
| 1442 | * Prepares the VM to run the guest.
|
---|
| 1443 | *
|
---|
| 1444 | * @returns Strict VBox status code.
|
---|
| 1445 | * @param pVM The cross context VM structure.
|
---|
| 1446 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 1447 | * @param fSingleStepping Flag whether we run in single stepping mode.
|
---|
| 1448 | */
|
---|
| 1449 | static VBOXSTRICTRC nemR3DarwinPreRunGuest(PVM pVM, PVMCPU pVCpu, bool fSingleStepping)
|
---|
| 1450 | {
|
---|
[99078] | 1451 | #ifdef LOG_ENABLED
|
---|
[99576] | 1452 | bool fIrq = false;
|
---|
| 1453 | bool fFiq = false;
|
---|
| 1454 |
|
---|
[99078] | 1455 | if (LogIs3Enabled())
|
---|
| 1456 | nemR3DarwinLogState(pVM, pVCpu);
|
---|
| 1457 | #endif
|
---|
| 1458 |
|
---|
[99052] | 1459 | /** @todo */ RT_NOREF(fSingleStepping);
|
---|
| 1460 | int rc = nemR3DarwinExportGuestState(pVM, pVCpu);
|
---|
| 1461 | AssertRCReturn(rc, rc);
|
---|
| 1462 |
|
---|
[99735] | 1463 | /* Check whether the vTimer interrupt was handled by the guest and we can unmask the vTimer. */
|
---|
| 1464 | if (pVCpu->nem.s.fVTimerActivated)
|
---|
| 1465 | {
|
---|
| 1466 | /* Read the CNTV_CTL_EL0 register. */
|
---|
| 1467 | uint64_t u64CntvCtl = 0;
|
---|
| 1468 |
|
---|
| 1469 | hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &u64CntvCtl);
|
---|
| 1470 | AssertRCReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
|
---|
| 1471 |
|
---|
| 1472 | if ( (u64CntvCtl & (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE | ARMV8_CNTV_CTL_EL0_AARCH64_IMASK | ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
|
---|
| 1473 | != (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE | ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
|
---|
| 1474 | {
|
---|
| 1475 | /* Clear the interrupt. */
|
---|
[101496] | 1476 | GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, false /*fAsserted*/);
|
---|
[99735] | 1477 |
|
---|
| 1478 | pVCpu->nem.s.fVTimerActivated = false;
|
---|
| 1479 | hrc = hv_vcpu_set_vtimer_mask(pVCpu->nem.s.hVCpu, false /*vtimer_is_masked*/);
|
---|
| 1480 | AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
|
---|
| 1481 | }
|
---|
| 1482 | }
|
---|
| 1483 |
|
---|
[99576] | 1484 | /* Set the pending interrupt state. */
|
---|
[99888] | 1485 | hv_return_t hrc = HV_SUCCESS;
|
---|
| 1486 | if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ))
|
---|
[99576] | 1487 | {
|
---|
[99888] | 1488 | hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, true);
|
---|
| 1489 | AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
|
---|
[99576] | 1490 | #ifdef LOG_ENABLED
|
---|
[99888] | 1491 | fIrq = true;
|
---|
[99576] | 1492 | #endif
|
---|
[99888] | 1493 | }
|
---|
| 1494 | else
|
---|
| 1495 | {
|
---|
| 1496 | hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, false);
|
---|
| 1497 | AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
|
---|
| 1498 | }
|
---|
[99576] | 1499 |
|
---|
[99888] | 1500 | if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ))
|
---|
| 1501 | {
|
---|
| 1502 | hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, true);
|
---|
| 1503 | AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
|
---|
[99576] | 1504 | #ifdef LOG_ENABLED
|
---|
[99888] | 1505 | fFiq = true;
|
---|
[99576] | 1506 | #endif
|
---|
| 1507 | }
|
---|
| 1508 | else
|
---|
| 1509 | {
|
---|
| 1510 | hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, false);
|
---|
| 1511 | AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
|
---|
| 1512 | }
|
---|
| 1513 |
|
---|
| 1514 | LogFlowFunc(("Running vCPU [%s,%s]\n", fIrq ? "I" : "nI", fFiq ? "F" : "nF"));
|
---|
[99052] | 1515 | pVCpu->nem.s.fEventPending = false;
|
---|
| 1516 | return VINF_SUCCESS;
|
---|
| 1517 | }
|
---|
| 1518 |
|
---|
| 1519 |
|
---|
| 1520 | /**
|
---|
| 1521 | * The normal runloop (no debugging features enabled).
|
---|
| 1522 | *
|
---|
| 1523 | * @returns Strict VBox status code.
|
---|
| 1524 | * @param pVM The cross context VM structure.
|
---|
| 1525 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 1526 | */
|
---|
| 1527 | static VBOXSTRICTRC nemR3DarwinRunGuestNormal(PVM pVM, PVMCPU pVCpu)
|
---|
| 1528 | {
|
---|
| 1529 | /*
|
---|
| 1530 | * The run loop.
|
---|
| 1531 | *
|
---|
| 1532 | * Current approach to state updating to use the sledgehammer and sync
|
---|
| 1533 | * everything every time. This will be optimized later.
|
---|
| 1534 | */
|
---|
| 1535 |
|
---|
[99976] | 1536 | /* Update the vTimer offset after resuming if instructed. */
|
---|
| 1537 | if (pVCpu->nem.s.fVTimerOffUpdate)
|
---|
| 1538 | {
|
---|
[100102] | 1539 | hv_return_t hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
|
---|
[99976] | 1540 | if (hrc != HV_SUCCESS)
|
---|
| 1541 | return nemR3DarwinHvSts2Rc(hrc);
|
---|
| 1542 |
|
---|
| 1543 | pVCpu->nem.s.fVTimerOffUpdate = false;
|
---|
[100764] | 1544 |
|
---|
| 1545 | hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, pVCpu->cpum.GstCtx.CntvCtlEl0);
|
---|
| 1546 | if (hrc == HV_SUCCESS)
|
---|
| 1547 | hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, pVCpu->cpum.GstCtx.CntvCValEl0);
|
---|
| 1548 | if (hrc != HV_SUCCESS)
|
---|
| 1549 | return nemR3DarwinHvSts2Rc(hrc);
|
---|
[99976] | 1550 | }
|
---|
| 1551 |
|
---|
[99052] | 1552 | /*
|
---|
| 1553 | * Poll timers and run for a bit.
|
---|
| 1554 | */
|
---|
| 1555 | /** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
|
---|
| 1556 | * the whole polling job when timers have changed... */
|
---|
| 1557 | uint64_t offDeltaIgnored;
|
---|
| 1558 | uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
|
---|
| 1559 | VBOXSTRICTRC rcStrict = VINF_SUCCESS;
|
---|
| 1560 | for (unsigned iLoop = 0;; iLoop++)
|
---|
| 1561 | {
|
---|
| 1562 | rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, false /* fSingleStepping */);
|
---|
| 1563 | if (rcStrict != VINF_SUCCESS)
|
---|
| 1564 | break;
|
---|
| 1565 |
|
---|
| 1566 | hv_return_t hrc = nemR3DarwinRunGuest(pVM, pVCpu);
|
---|
| 1567 | if (hrc == HV_SUCCESS)
|
---|
| 1568 | {
|
---|
| 1569 | /*
|
---|
| 1570 | * Deal with the message.
|
---|
| 1571 | */
|
---|
| 1572 | rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
|
---|
| 1573 | if (rcStrict == VINF_SUCCESS)
|
---|
| 1574 | { /* hopefully likely */ }
|
---|
| 1575 | else
|
---|
| 1576 | {
|
---|
| 1577 | LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
|
---|
| 1578 | STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
|
---|
| 1579 | break;
|
---|
| 1580 | }
|
---|
| 1581 | }
|
---|
| 1582 | else
|
---|
| 1583 | {
|
---|
| 1584 | AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
|
---|
| 1585 | pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
|
---|
| 1586 | }
|
---|
| 1587 | } /* the run loop */
|
---|
| 1588 |
|
---|
| 1589 | return rcStrict;
|
---|
| 1590 | }
|
---|
| 1591 |
|
---|
| 1592 |
|
---|
| 1593 | VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
|
---|
| 1594 | {
|
---|
| 1595 | #ifdef LOG_ENABLED
|
---|
| 1596 | if (LogIs3Enabled())
|
---|
| 1597 | nemR3DarwinLogState(pVM, pVCpu);
|
---|
| 1598 | #endif
|
---|
| 1599 |
|
---|
| 1600 | AssertReturn(NEMR3CanExecuteGuest(pVM, pVCpu), VERR_NEM_IPE_9);
|
---|
| 1601 |
|
---|
[101234] | 1602 | if (RT_UNLIKELY(!pVCpu->nem.s.fIdRegsSynced))
|
---|
| 1603 | {
|
---|
| 1604 | /*
|
---|
| 1605 | * Sync the guest ID registers which are per VM once (they are readonly and stay constant during VM lifetime).
|
---|
| 1606 | * Need to do it here and not during the init because loading a saved state might change the ID registers from what
|
---|
| 1607 | * done in the call to CPUMR3PopulateFeaturesByIdRegisters().
|
---|
| 1608 | */
|
---|
| 1609 | static const struct
|
---|
| 1610 | {
|
---|
| 1611 | const char *pszIdReg;
|
---|
| 1612 | hv_sys_reg_t enmHvReg;
|
---|
| 1613 | uint32_t offIdStruct;
|
---|
| 1614 | } s_aSysIdRegs[] =
|
---|
| 1615 | {
|
---|
| 1616 | #define ID_SYS_REG_CREATE(a_IdReg, a_CpumIdReg) { #a_IdReg, HV_SYS_REG_##a_IdReg, RT_UOFFSETOF(CPUMIDREGS, a_CpumIdReg) }
|
---|
| 1617 | ID_SYS_REG_CREATE(ID_AA64DFR0_EL1, u64RegIdAa64Dfr0El1),
|
---|
| 1618 | ID_SYS_REG_CREATE(ID_AA64DFR1_EL1, u64RegIdAa64Dfr1El1),
|
---|
| 1619 | ID_SYS_REG_CREATE(ID_AA64ISAR0_EL1, u64RegIdAa64Isar0El1),
|
---|
| 1620 | ID_SYS_REG_CREATE(ID_AA64ISAR1_EL1, u64RegIdAa64Isar1El1),
|
---|
| 1621 | ID_SYS_REG_CREATE(ID_AA64MMFR0_EL1, u64RegIdAa64Mmfr0El1),
|
---|
| 1622 | ID_SYS_REG_CREATE(ID_AA64MMFR1_EL1, u64RegIdAa64Mmfr1El1),
|
---|
| 1623 | ID_SYS_REG_CREATE(ID_AA64MMFR2_EL1, u64RegIdAa64Mmfr2El1),
|
---|
| 1624 | ID_SYS_REG_CREATE(ID_AA64PFR0_EL1, u64RegIdAa64Pfr0El1),
|
---|
| 1625 | ID_SYS_REG_CREATE(ID_AA64PFR1_EL1, u64RegIdAa64Pfr1El1),
|
---|
| 1626 | #undef ID_SYS_REG_CREATE
|
---|
| 1627 | };
|
---|
| 1628 |
|
---|
| 1629 | PCCPUMIDREGS pIdRegsGst = NULL;
|
---|
| 1630 | int rc = CPUMR3QueryGuestIdRegs(pVM, &pIdRegsGst);
|
---|
| 1631 | AssertRCReturn(rc, rc);
|
---|
| 1632 |
|
---|
| 1633 | for (uint32_t i = 0; i < RT_ELEMENTS(s_aSysIdRegs); i++)
|
---|
| 1634 | {
|
---|
| 1635 | uint64_t *pu64 = (uint64_t *)((uint8_t *)pIdRegsGst + s_aSysIdRegs[i].offIdStruct);
|
---|
| 1636 | hv_return_t hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aSysIdRegs[i].enmHvReg, *pu64);
|
---|
| 1637 | if (hrc != HV_SUCCESS)
|
---|
| 1638 | return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
|
---|
| 1639 | "Setting %s failed on vCPU %u: %#x (%Rrc)", s_aSysIdRegs[i].pszIdReg, pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
|
---|
| 1640 | }
|
---|
| 1641 |
|
---|
| 1642 | pVCpu->nem.s.fIdRegsSynced = true;
|
---|
| 1643 | }
|
---|
| 1644 |
|
---|
[99052] | 1645 | /*
|
---|
| 1646 | * Try switch to NEM runloop state.
|
---|
| 1647 | */
|
---|
| 1648 | if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
|
---|
| 1649 | { /* likely */ }
|
---|
| 1650 | else
|
---|
| 1651 | {
|
---|
| 1652 | VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
|
---|
| 1653 | LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
|
---|
| 1654 | return VINF_SUCCESS;
|
---|
| 1655 | }
|
---|
| 1656 |
|
---|
| 1657 | VBOXSTRICTRC rcStrict;
|
---|
| 1658 | #if 0
|
---|
| 1659 | if ( !pVCpu->nem.s.fUseDebugLoop
|
---|
| 1660 | && !nemR3DarwinAnyExpensiveProbesEnabled()
|
---|
| 1661 | && !DBGFIsStepping(pVCpu)
|
---|
| 1662 | && !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
|
---|
| 1663 | #endif
|
---|
| 1664 | rcStrict = nemR3DarwinRunGuestNormal(pVM, pVCpu);
|
---|
| 1665 | #if 0
|
---|
| 1666 | else
|
---|
| 1667 | rcStrict = nemR3DarwinRunGuestDebug(pVM, pVCpu);
|
---|
| 1668 | #endif
|
---|
| 1669 |
|
---|
| 1670 | if (rcStrict == VINF_EM_RAW_TO_R3)
|
---|
| 1671 | rcStrict = VINF_SUCCESS;
|
---|
| 1672 |
|
---|
| 1673 | /*
|
---|
| 1674 | * Convert any pending HM events back to TRPM due to premature exits.
|
---|
| 1675 | *
|
---|
| 1676 | * This is because execution may continue from IEM and we would need to inject
|
---|
| 1677 | * the event from there (hence place it back in TRPM).
|
---|
| 1678 | */
|
---|
| 1679 | if (pVCpu->nem.s.fEventPending)
|
---|
| 1680 | {
|
---|
| 1681 | /** @todo */
|
---|
| 1682 | }
|
---|
| 1683 |
|
---|
| 1684 |
|
---|
| 1685 | if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
|
---|
| 1686 | VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
|
---|
| 1687 |
|
---|
| 1688 | if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL))
|
---|
| 1689 | {
|
---|
| 1690 | /* Try anticipate what we might need. */
|
---|
| 1691 | uint64_t fImport = NEM_DARWIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
|
---|
| 1692 | if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
|
---|
| 1693 | || RT_FAILURE(rcStrict))
|
---|
| 1694 | fImport = CPUMCTX_EXTRN_ALL;
|
---|
[99576] | 1695 | else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ
|
---|
[99052] | 1696 | | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
|
---|
| 1697 | fImport |= IEM_CPUMCTX_EXTRN_XCPT_MASK;
|
---|
| 1698 |
|
---|
| 1699 | if (pVCpu->cpum.GstCtx.fExtrn & fImport)
|
---|
| 1700 | {
|
---|
| 1701 | /* Only import what is external currently. */
|
---|
| 1702 | int rc2 = nemR3DarwinCopyStateFromHv(pVM, pVCpu, fImport);
|
---|
| 1703 | if (RT_SUCCESS(rc2))
|
---|
| 1704 | pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
|
---|
| 1705 | else if (RT_SUCCESS(rcStrict))
|
---|
| 1706 | rcStrict = rc2;
|
---|
| 1707 | if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
|
---|
| 1708 | pVCpu->cpum.GstCtx.fExtrn = 0;
|
---|
| 1709 | STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
|
---|
| 1710 | }
|
---|
| 1711 | else
|
---|
| 1712 | STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
|
---|
| 1713 | }
|
---|
| 1714 | else
|
---|
| 1715 | {
|
---|
| 1716 | STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
|
---|
| 1717 | pVCpu->cpum.GstCtx.fExtrn = 0;
|
---|
| 1718 | }
|
---|
| 1719 |
|
---|
| 1720 | return rcStrict;
|
---|
| 1721 | }
|
---|
| 1722 |
|
---|
| 1723 |
|
---|
| 1724 | VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
|
---|
| 1725 | {
|
---|
| 1726 | RT_NOREF(pVM, pVCpu);
|
---|
| 1727 | return true; /** @todo Are there any cases where we have to emulate? */
|
---|
| 1728 | }
|
---|
| 1729 |
|
---|
| 1730 |
|
---|
| 1731 | bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
|
---|
| 1732 | {
|
---|
| 1733 | VMCPU_ASSERT_EMT(pVCpu);
|
---|
| 1734 | bool fOld = pVCpu->nem.s.fSingleInstruction;
|
---|
| 1735 | pVCpu->nem.s.fSingleInstruction = fEnable;
|
---|
| 1736 | pVCpu->nem.s.fUseDebugLoop = fEnable || pVM->nem.s.fUseDebugLoop;
|
---|
| 1737 | return fOld;
|
---|
| 1738 | }
|
---|
| 1739 |
|
---|
| 1740 |
|
---|
| 1741 | void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
|
---|
| 1742 | {
|
---|
| 1743 | LogFlowFunc(("pVM=%p pVCpu=%p fFlags=%#x\n", pVM, pVCpu, fFlags));
|
---|
| 1744 |
|
---|
| 1745 | RT_NOREF(pVM, fFlags);
|
---|
| 1746 |
|
---|
| 1747 | hv_return_t hrc = hv_vcpus_exit(&pVCpu->nem.s.hVCpu, 1);
|
---|
| 1748 | if (hrc != HV_SUCCESS)
|
---|
| 1749 | LogRel(("NEM: hv_vcpus_exit(%u, 1) failed with %#x\n", pVCpu->nem.s.hVCpu, hrc));
|
---|
| 1750 | }
|
---|
| 1751 |
|
---|
| 1752 |
|
---|
| 1753 | DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChanged(PVM pVM, bool fUseDebugLoop)
|
---|
| 1754 | {
|
---|
| 1755 | RT_NOREF(pVM, fUseDebugLoop);
|
---|
[100166] | 1756 | //AssertReleaseFailed();
|
---|
[99052] | 1757 | return false;
|
---|
| 1758 | }
|
---|
| 1759 |
|
---|
| 1760 |
|
---|
| 1761 | DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu, bool fUseDebugLoop)
|
---|
| 1762 | {
|
---|
| 1763 | RT_NOREF(pVM, pVCpu, fUseDebugLoop);
|
---|
| 1764 | return fUseDebugLoop;
|
---|
| 1765 | }
|
---|
| 1766 |
|
---|
| 1767 |
|
---|
| 1768 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
|
---|
| 1769 | uint8_t *pu2State, uint32_t *puNemRange)
|
---|
| 1770 | {
|
---|
| 1771 | RT_NOREF(pVM, puNemRange);
|
---|
| 1772 |
|
---|
| 1773 | Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p\n", GCPhys, cb, pvR3));
|
---|
| 1774 | #if defined(VBOX_WITH_PGM_NEM_MODE)
|
---|
| 1775 | if (pvR3)
|
---|
| 1776 | {
|
---|
| 1777 | int rc = nemR3DarwinMap(pVM, GCPhys, pvR3, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE, pu2State);
|
---|
| 1778 | if (RT_FAILURE(rc))
|
---|
| 1779 | {
|
---|
| 1780 | LogRel(("NEMR3NotifyPhysRamRegister: GCPhys=%RGp LB %RGp pvR3=%p rc=%Rrc\n", GCPhys, cb, pvR3, rc));
|
---|
| 1781 | return VERR_NEM_MAP_PAGES_FAILED;
|
---|
| 1782 | }
|
---|
| 1783 | }
|
---|
| 1784 | return VINF_SUCCESS;
|
---|
| 1785 | #else
|
---|
| 1786 | RT_NOREF(pVM, GCPhys, cb, pvR3);
|
---|
| 1787 | return VERR_NEM_MAP_PAGES_FAILED;
|
---|
| 1788 | #endif
|
---|
| 1789 | }
|
---|
| 1790 |
|
---|
| 1791 |
|
---|
| 1792 | VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
|
---|
| 1793 | {
|
---|
| 1794 | RT_NOREF(pVM);
|
---|
[100705] | 1795 | return true;
|
---|
[99052] | 1796 | }
|
---|
| 1797 |
|
---|
| 1798 |
|
---|
| 1799 | VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
|
---|
| 1800 | void *pvRam, void *pvMmio2, uint8_t *pu2State, uint32_t *puNemRange)
|
---|
| 1801 | {
|
---|
[100705] | 1802 | RT_NOREF(pvRam);
|
---|
[99052] | 1803 |
|
---|
| 1804 | Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d)\n",
|
---|
| 1805 | GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State));
|
---|
| 1806 |
|
---|
| 1807 | #if defined(VBOX_WITH_PGM_NEM_MODE)
|
---|
| 1808 | /*
|
---|
| 1809 | * Unmap the RAM we're replacing.
|
---|
| 1810 | */
|
---|
| 1811 | if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
|
---|
| 1812 | {
|
---|
| 1813 | int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
|
---|
| 1814 | if (RT_SUCCESS(rc))
|
---|
| 1815 | { /* likely */ }
|
---|
| 1816 | else if (pvMmio2)
|
---|
| 1817 | LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rc(ignored)\n",
|
---|
| 1818 | GCPhys, cb, fFlags, rc));
|
---|
| 1819 | else
|
---|
| 1820 | {
|
---|
| 1821 | LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
|
---|
| 1822 | GCPhys, cb, fFlags, rc));
|
---|
| 1823 | return VERR_NEM_UNMAP_PAGES_FAILED;
|
---|
| 1824 | }
|
---|
| 1825 | }
|
---|
| 1826 |
|
---|
| 1827 | /*
|
---|
| 1828 | * Map MMIO2 if any.
|
---|
| 1829 | */
|
---|
| 1830 | if (pvMmio2)
|
---|
| 1831 | {
|
---|
| 1832 | Assert(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2);
|
---|
[100705] | 1833 |
|
---|
| 1834 | /* We need to set up our own dirty tracking due to Hypervisor.framework only working on host page sized aligned regions. */
|
---|
| 1835 | uint32_t fProt = NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE;
|
---|
| 1836 | if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
|
---|
| 1837 | {
|
---|
| 1838 | /* Find a slot for dirty tracking. */
|
---|
| 1839 | PNEMHVMMIO2REGION pMmio2Region = NULL;
|
---|
| 1840 | uint32_t idSlot;
|
---|
| 1841 | for (idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
|
---|
| 1842 | {
|
---|
| 1843 | if ( pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart == 0
|
---|
| 1844 | && pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast == 0)
|
---|
| 1845 | {
|
---|
| 1846 | pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
|
---|
| 1847 | break;
|
---|
| 1848 | }
|
---|
| 1849 | }
|
---|
| 1850 |
|
---|
| 1851 | if (!pMmio2Region)
|
---|
| 1852 | {
|
---|
| 1853 | LogRel(("NEMR3NotifyPhysMmioExMapEarly: Out of dirty tracking structures -> VERR_NEM_MAP_PAGES_FAILED\n"));
|
---|
| 1854 | return VERR_NEM_MAP_PAGES_FAILED;
|
---|
| 1855 | }
|
---|
| 1856 |
|
---|
| 1857 | pMmio2Region->GCPhysStart = GCPhys;
|
---|
| 1858 | pMmio2Region->GCPhysLast = GCPhys + cb - 1;
|
---|
| 1859 | pMmio2Region->fDirty = false;
|
---|
| 1860 | *puNemRange = idSlot;
|
---|
| 1861 | }
|
---|
| 1862 | else
|
---|
| 1863 | fProt |= NEM_PAGE_PROT_WRITE;
|
---|
| 1864 |
|
---|
| 1865 | int rc = nemR3DarwinMap(pVM, GCPhys, pvMmio2, cb, fProt, pu2State);
|
---|
[99052] | 1866 | if (RT_FAILURE(rc))
|
---|
| 1867 | {
|
---|
| 1868 | LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x pvMmio2=%p: Map -> rc=%Rrc\n",
|
---|
| 1869 | GCPhys, cb, fFlags, pvMmio2, rc));
|
---|
| 1870 | return VERR_NEM_MAP_PAGES_FAILED;
|
---|
| 1871 | }
|
---|
| 1872 | }
|
---|
| 1873 | else
|
---|
| 1874 | Assert(!(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2));
|
---|
| 1875 |
|
---|
| 1876 | #else
|
---|
| 1877 | RT_NOREF(pVM, GCPhys, cb, pvRam, pvMmio2);
|
---|
| 1878 | *pu2State = (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE) ? UINT8_MAX : NEM_DARWIN_PAGE_STATE_UNMAPPED;
|
---|
| 1879 | #endif
|
---|
| 1880 | return VINF_SUCCESS;
|
---|
| 1881 | }
|
---|
| 1882 |
|
---|
| 1883 |
|
---|
| 1884 | VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
|
---|
| 1885 | void *pvRam, void *pvMmio2, uint32_t *puNemRange)
|
---|
| 1886 | {
|
---|
| 1887 | RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
|
---|
| 1888 | return VINF_SUCCESS;
|
---|
| 1889 | }
|
---|
| 1890 |
|
---|
| 1891 |
|
---|
| 1892 | VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
|
---|
| 1893 | void *pvMmio2, uint8_t *pu2State, uint32_t *puNemRange)
|
---|
| 1894 | {
|
---|
| 1895 | RT_NOREF(pVM, puNemRange);
|
---|
| 1896 |
|
---|
| 1897 | Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p uNemRange=%#x (%#x)\n",
|
---|
| 1898 | GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
|
---|
| 1899 |
|
---|
| 1900 | int rc = VINF_SUCCESS;
|
---|
| 1901 | #if defined(VBOX_WITH_PGM_NEM_MODE)
|
---|
| 1902 | /*
|
---|
| 1903 | * Unmap the MMIO2 pages.
|
---|
| 1904 | */
|
---|
| 1905 | /** @todo If we implement aliasing (MMIO2 page aliased into MMIO range),
|
---|
| 1906 | * we may have more stuff to unmap even in case of pure MMIO... */
|
---|
| 1907 | if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
|
---|
| 1908 | {
|
---|
| 1909 | rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
|
---|
| 1910 | if (RT_FAILURE(rc))
|
---|
| 1911 | {
|
---|
| 1912 | LogRel2(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
|
---|
| 1913 | GCPhys, cb, fFlags, rc));
|
---|
| 1914 | rc = VERR_NEM_UNMAP_PAGES_FAILED;
|
---|
| 1915 | }
|
---|
[100705] | 1916 |
|
---|
| 1917 | if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
|
---|
| 1918 | {
|
---|
| 1919 | /* Reset tracking structure. */
|
---|
| 1920 | uint32_t idSlot = *puNemRange;
|
---|
| 1921 | *puNemRange = UINT32_MAX;
|
---|
| 1922 |
|
---|
| 1923 | Assert(idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
|
---|
| 1924 | pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart = 0;
|
---|
| 1925 | pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast = 0;
|
---|
| 1926 | pVM->nem.s.aMmio2DirtyTracking[idSlot].fDirty = false;
|
---|
| 1927 | }
|
---|
[99052] | 1928 | }
|
---|
| 1929 |
|
---|
| 1930 | /* Ensure the page is masked as unmapped if relevant. */
|
---|
| 1931 | Assert(!pu2State || *pu2State == NEM_DARWIN_PAGE_STATE_UNMAPPED);
|
---|
| 1932 |
|
---|
| 1933 | /*
|
---|
| 1934 | * Restore the RAM we replaced.
|
---|
| 1935 | */
|
---|
| 1936 | if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
|
---|
| 1937 | {
|
---|
| 1938 | AssertPtr(pvRam);
|
---|
| 1939 | rc = nemR3DarwinMap(pVM, GCPhys, pvRam, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE, pu2State);
|
---|
| 1940 | if (RT_SUCCESS(rc))
|
---|
| 1941 | { /* likely */ }
|
---|
| 1942 | else
|
---|
| 1943 | {
|
---|
| 1944 | LogRel(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp pvMmio2=%p rc=%Rrc\n", GCPhys, cb, pvMmio2, rc));
|
---|
| 1945 | rc = VERR_NEM_MAP_PAGES_FAILED;
|
---|
| 1946 | }
|
---|
| 1947 | }
|
---|
| 1948 |
|
---|
| 1949 | RT_NOREF(pvMmio2);
|
---|
| 1950 | #else
|
---|
| 1951 | RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
|
---|
| 1952 | if (pu2State)
|
---|
| 1953 | *pu2State = UINT8_MAX;
|
---|
| 1954 | rc = VERR_NEM_UNMAP_PAGES_FAILED;
|
---|
| 1955 | #endif
|
---|
| 1956 | return rc;
|
---|
| 1957 | }
|
---|
| 1958 |
|
---|
| 1959 |
|
---|
| 1960 | VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
|
---|
| 1961 | void *pvBitmap, size_t cbBitmap)
|
---|
| 1962 | {
|
---|
[100705] | 1963 | LogFlowFunc(("NEMR3PhysMmio2QueryAndResetDirtyBitmap: %RGp LB %RGp UnemRange=%u\n", GCPhys, cb, uNemRange));
|
---|
| 1964 | Assert(uNemRange < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
|
---|
| 1965 |
|
---|
| 1966 | /* Keep it simple for now and mark everything as dirty if it is. */
|
---|
| 1967 | int rc = VINF_SUCCESS;
|
---|
| 1968 | if (pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty)
|
---|
| 1969 | {
|
---|
| 1970 | ASMBitSetRange(pvBitmap, 0, cbBitmap * 8);
|
---|
| 1971 |
|
---|
| 1972 | pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty = false;
|
---|
| 1973 | /* Restore as RX only. */
|
---|
| 1974 | uint8_t u2State;
|
---|
| 1975 | rc = nemR3DarwinProtect(GCPhys, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE, &u2State);
|
---|
| 1976 | }
|
---|
| 1977 | else
|
---|
| 1978 | ASMBitClearRange(pvBitmap, 0, cbBitmap * 8);
|
---|
| 1979 |
|
---|
| 1980 | return rc;
|
---|
[99052] | 1981 | }
|
---|
| 1982 |
|
---|
| 1983 |
|
---|
| 1984 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
|
---|
| 1985 | uint8_t *pu2State, uint32_t *puNemRange)
|
---|
| 1986 | {
|
---|
| 1987 | RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
|
---|
| 1988 |
|
---|
[100705] | 1989 | Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
|
---|
[99052] | 1990 | *pu2State = UINT8_MAX;
|
---|
| 1991 | *puNemRange = 0;
|
---|
| 1992 | return VINF_SUCCESS;
|
---|
| 1993 | }
|
---|
| 1994 |
|
---|
| 1995 |
|
---|
| 1996 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
|
---|
| 1997 | uint32_t fFlags, uint8_t *pu2State, uint32_t *puNemRange)
|
---|
| 1998 | {
|
---|
[100705] | 1999 | Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
|
---|
[99052] | 2000 | GCPhys, cb, pvPages, fFlags, pu2State, *pu2State, puNemRange, *puNemRange));
|
---|
| 2001 | *pu2State = UINT8_MAX;
|
---|
| 2002 |
|
---|
| 2003 | #if defined(VBOX_WITH_PGM_NEM_MODE)
|
---|
| 2004 | /*
|
---|
| 2005 | * (Re-)map readonly.
|
---|
| 2006 | */
|
---|
| 2007 | AssertPtrReturn(pvPages, VERR_INVALID_POINTER);
|
---|
[100705] | 2008 |
|
---|
| 2009 | int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
|
---|
| 2010 | AssertRC(rc);
|
---|
| 2011 |
|
---|
| 2012 | rc = nemR3DarwinMap(pVM, GCPhys, pvPages, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE, pu2State);
|
---|
[99052] | 2013 | if (RT_FAILURE(rc))
|
---|
| 2014 | {
|
---|
| 2015 | LogRel(("nemR3NativeNotifyPhysRomRegisterLate: GCPhys=%RGp LB %RGp pvPages=%p fFlags=%#x rc=%Rrc\n",
|
---|
| 2016 | GCPhys, cb, pvPages, fFlags, rc));
|
---|
| 2017 | return VERR_NEM_MAP_PAGES_FAILED;
|
---|
| 2018 | }
|
---|
| 2019 | RT_NOREF(fFlags, puNemRange);
|
---|
| 2020 | return VINF_SUCCESS;
|
---|
| 2021 | #else
|
---|
| 2022 | RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
|
---|
| 2023 | return VERR_NEM_MAP_PAGES_FAILED;
|
---|
| 2024 | #endif
|
---|
| 2025 | }
|
---|
| 2026 |
|
---|
| 2027 |
|
---|
| 2028 | VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
|
---|
| 2029 | RTR3PTR pvMemR3, uint8_t *pu2State)
|
---|
| 2030 | {
|
---|
| 2031 | Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
|
---|
| 2032 | GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
|
---|
| 2033 |
|
---|
| 2034 | *pu2State = UINT8_MAX;
|
---|
| 2035 | #if defined(VBOX_WITH_PGM_NEM_MODE)
|
---|
| 2036 | if (pvMemR3)
|
---|
| 2037 | {
|
---|
[100705] | 2038 | /* Unregister what was there before. */
|
---|
| 2039 | int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
|
---|
| 2040 | AssertRC(rc);
|
---|
| 2041 |
|
---|
| 2042 | rc = nemR3DarwinMap(pVM, GCPhys, pvMemR3, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE, pu2State);
|
---|
[99052] | 2043 | AssertLogRelMsgRC(rc, ("NEMHCNotifyHandlerPhysicalDeregister: nemR3DarwinMap(,%p,%RGp,%RGp,) -> %Rrc\n",
|
---|
| 2044 | pvMemR3, GCPhys, cb, rc));
|
---|
| 2045 | }
|
---|
| 2046 | RT_NOREF(enmKind);
|
---|
| 2047 | #else
|
---|
| 2048 | RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
|
---|
| 2049 | AssertFailed();
|
---|
| 2050 | #endif
|
---|
| 2051 | }
|
---|
| 2052 |
|
---|
| 2053 |
|
---|
| 2054 | VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
|
---|
| 2055 | {
|
---|
| 2056 | Log(("NEMR3NotifySetA20: fEnabled=%RTbool\n", fEnabled));
|
---|
| 2057 | RT_NOREF(pVCpu, fEnabled);
|
---|
| 2058 | }
|
---|
| 2059 |
|
---|
| 2060 |
|
---|
| 2061 | void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
|
---|
| 2062 | {
|
---|
| 2063 | Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
|
---|
| 2064 | NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
|
---|
| 2065 | }
|
---|
| 2066 |
|
---|
| 2067 |
|
---|
| 2068 | void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
|
---|
| 2069 | RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
|
---|
| 2070 | {
|
---|
| 2071 | Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
|
---|
| 2072 | GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
|
---|
| 2073 | NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
|
---|
| 2074 | }
|
---|
| 2075 |
|
---|
| 2076 |
|
---|
| 2077 | int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
|
---|
| 2078 | PGMPAGETYPE enmType, uint8_t *pu2State)
|
---|
| 2079 | {
|
---|
| 2080 | Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
|
---|
| 2081 | GCPhys, HCPhys, fPageProt, enmType, *pu2State));
|
---|
[100705] | 2082 | RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
|
---|
[99052] | 2083 |
|
---|
[100705] | 2084 | AssertFailed();
|
---|
| 2085 | return VINF_SUCCESS;
|
---|
[99052] | 2086 | }
|
---|
| 2087 |
|
---|
| 2088 |
|
---|
| 2089 | VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
|
---|
| 2090 | PGMPAGETYPE enmType, uint8_t *pu2State)
|
---|
| 2091 | {
|
---|
| 2092 | Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
|
---|
| 2093 | GCPhys, HCPhys, fPageProt, enmType, *pu2State));
|
---|
[100705] | 2094 | RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
|
---|
[99052] | 2095 | }
|
---|
| 2096 |
|
---|
| 2097 |
|
---|
| 2098 | VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
|
---|
| 2099 | RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
|
---|
| 2100 | {
|
---|
| 2101 | Log5(("NEMHCNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
|
---|
| 2102 | GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
|
---|
[100705] | 2103 | RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
|
---|
[99052] | 2104 |
|
---|
[100705] | 2105 | AssertFailed();
|
---|
[99052] | 2106 | }
|
---|
| 2107 |
|
---|
| 2108 |
|
---|
| 2109 | /**
|
---|
| 2110 | * Interface for importing state on demand (used by IEM).
|
---|
| 2111 | *
|
---|
| 2112 | * @returns VBox status code.
|
---|
| 2113 | * @param pVCpu The cross context CPU structure.
|
---|
| 2114 | * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
|
---|
| 2115 | */
|
---|
| 2116 | VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
|
---|
| 2117 | {
|
---|
| 2118 | LogFlowFunc(("pVCpu=%p fWhat=%RX64\n", pVCpu, fWhat));
|
---|
| 2119 | STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
|
---|
| 2120 |
|
---|
| 2121 | return nemR3DarwinCopyStateFromHv(pVCpu->pVMR3, pVCpu, fWhat);
|
---|
| 2122 | }
|
---|
| 2123 |
|
---|
| 2124 |
|
---|
| 2125 | /**
|
---|
| 2126 | * Query the CPU tick counter and optionally the TSC_AUX MSR value.
|
---|
| 2127 | *
|
---|
| 2128 | * @returns VBox status code.
|
---|
| 2129 | * @param pVCpu The cross context CPU structure.
|
---|
| 2130 | * @param pcTicks Where to return the CPU tick count.
|
---|
| 2131 | * @param puAux Where to return the TSC_AUX register value.
|
---|
| 2132 | */
|
---|
| 2133 | VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t *pcTicks, uint32_t *puAux)
|
---|
| 2134 | {
|
---|
| 2135 | LogFlowFunc(("pVCpu=%p pcTicks=%RX64 puAux=%RX32\n", pVCpu, pcTicks, puAux));
|
---|
| 2136 | STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
|
---|
| 2137 |
|
---|
[99976] | 2138 | if (puAux)
|
---|
| 2139 | *puAux = 0;
|
---|
[100102] | 2140 | *pcTicks = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff; /* This is the host timer minus the offset. */
|
---|
[99976] | 2141 | return VINF_SUCCESS;
|
---|
[99052] | 2142 | }
|
---|
| 2143 |
|
---|
| 2144 |
|
---|
| 2145 | /**
|
---|
| 2146 | * Resumes CPU clock (TSC) on all virtual CPUs.
|
---|
| 2147 | *
|
---|
| 2148 | * This is called by TM when the VM is started, restored, resumed or similar.
|
---|
| 2149 | *
|
---|
| 2150 | * @returns VBox status code.
|
---|
| 2151 | * @param pVM The cross context VM structure.
|
---|
| 2152 | * @param pVCpu The cross context CPU structure of the calling EMT.
|
---|
| 2153 | * @param uPausedTscValue The TSC value at the time of pausing.
|
---|
| 2154 | */
|
---|
| 2155 | VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
|
---|
| 2156 | {
|
---|
[100076] | 2157 | LogFlowFunc(("pVM=%p pVCpu=%p uPausedTscValue=%RX64\n", pVM, pVCpu, uPausedTscValue));
|
---|
[99052] | 2158 | VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
|
---|
| 2159 | AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
|
---|
| 2160 |
|
---|
[100102] | 2161 | /*
|
---|
| 2162 | * Calculate the new offset, first get the new TSC value with the old vTimer offset and then adjust the
|
---|
| 2163 | * the new offset to let the guest not notice the pause.
|
---|
| 2164 | */
|
---|
| 2165 | uint64_t u64TscNew = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff;
|
---|
| 2166 | Assert(u64TscNew >= uPausedTscValue);
|
---|
| 2167 | LogFlowFunc(("u64VTimerOffOld=%#RX64 u64TscNew=%#RX64 u64VTimerValuePaused=%#RX64 -> u64VTimerOff=%#RX64\n",
|
---|
| 2168 | pVM->nem.s.u64VTimerOff, u64TscNew, uPausedTscValue,
|
---|
| 2169 | pVM->nem.s.u64VTimerOff + (u64TscNew - uPausedTscValue)));
|
---|
[99976] | 2170 |
|
---|
[100102] | 2171 | pVM->nem.s.u64VTimerOff += u64TscNew - uPausedTscValue;
|
---|
| 2172 |
|
---|
[99976] | 2173 | /*
|
---|
| 2174 | * Set the flag to update the vTimer offset when the vCPU resumes for the first time
|
---|
| 2175 | * (needs to be done on the actual EMT).
|
---|
| 2176 | */
|
---|
| 2177 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
| 2178 | {
|
---|
| 2179 | PVMCPUCC pVCpuDst = pVM->apCpusR3[idCpu];
|
---|
| 2180 | pVCpuDst->nem.s.fVTimerOffUpdate = true;
|
---|
| 2181 | }
|
---|
| 2182 |
|
---|
[99052] | 2183 | return VINF_SUCCESS;
|
---|
| 2184 | }
|
---|
| 2185 |
|
---|
| 2186 |
|
---|
| 2187 | /**
|
---|
| 2188 | * Returns features supported by the NEM backend.
|
---|
| 2189 | *
|
---|
| 2190 | * @returns Flags of features supported by the native NEM backend.
|
---|
| 2191 | * @param pVM The cross context VM structure.
|
---|
| 2192 | */
|
---|
| 2193 | VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
|
---|
| 2194 | {
|
---|
| 2195 | RT_NOREF(pVM);
|
---|
| 2196 | /*
|
---|
| 2197 | * Apple's Hypervisor.framework is not supported if the CPU doesn't support nested paging
|
---|
| 2198 | * and unrestricted guest execution support so we can safely return these flags here always.
|
---|
| 2199 | */
|
---|
| 2200 | return NEM_FEAT_F_NESTED_PAGING | NEM_FEAT_F_FULL_GST_EXEC | NEM_FEAT_F_XSAVE_XRSTOR;
|
---|
| 2201 | }
|
---|
| 2202 |
|
---|
| 2203 |
|
---|
| 2204 | /** @page pg_nem_darwin NEM/darwin - Native Execution Manager, macOS.
|
---|
| 2205 | *
|
---|
| 2206 | * @todo Add notes as the implementation progresses...
|
---|
| 2207 | */
|
---|
| 2208 |
|
---|