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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3.cpp@ 84044

Last change on this file since 84044 was 82968, checked in by vboxsync, 4 years ago

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1/* $Id: NEMR3.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager.
4 */
5
6/*
7 * Copyright (C) 2018-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_nem NEM - Native Execution Manager.
19 *
20 * This is an alternative execution manage to HM and raw-mode. On one host
21 * (Windows) we're forced to use this, on the others we just do it because we
22 * can. Since this is host specific in nature, information about an
23 * implementation is contained in the NEMR3Native-xxxx.cpp files.
24 *
25 * @ref pg_nem_win
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_NEM
33#include <VBox/vmm/nem.h>
34#include <VBox/vmm/gim.h>
35#include "NEMInternal.h"
36#include <VBox/vmm/vm.h>
37#include <VBox/vmm/uvm.h>
38#include <VBox/err.h>
39
40#include <iprt/asm.h>
41
42
43
44/**
45 * Basic init and configuration reading.
46 *
47 * Always call NEMR3Term after calling this.
48 *
49 * @returns VBox status code.
50 * @param pVM The cross context VM structure.
51 */
52VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
53{
54 LogFlow(("NEMR3Init\n"));
55
56 /*
57 * Assert alignment and sizes.
58 */
59 AssertCompileMemberAlignment(VM, nem.s, 64);
60 AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
61
62 /*
63 * Initialize state info so NEMR3Term will always be happy.
64 * No returning prior to setting magics!
65 */
66 pVM->nem.s.u32Magic = NEM_MAGIC;
67 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
68 {
69 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
70 pVCpu->nem.s.u32Magic = NEMCPU_MAGIC;
71 }
72
73 /*
74 * Read configuration.
75 */
76 PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
77
78 /*
79 * Validate the NEM settings.
80 */
81 int rc = CFGMR3ValidateConfig(pCfgNem,
82 "/NEM/",
83 "Enabled"
84 "|Allow64BitGuests"
85#ifdef RT_OS_WINDOWS
86 "|UseRing0Runloop"
87#endif
88 ,
89 "" /* pszValidNodes */, "NEM" /* pszWho */, 0 /* uInstance */);
90 if (RT_FAILURE(rc))
91 return rc;
92
93 /** @cfgm{/NEM/NEMEnabled, bool, true}
94 * Whether NEM is enabled. */
95 rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
96 AssertLogRelRCReturn(rc, rc);
97
98
99#ifdef VBOX_WITH_64_BITS_GUESTS
100 /** @cfgm{/NEM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
101 * Enables AMD64 CPU features.
102 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
103 * already have the support. */
104 rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
105 AssertLogRelRCReturn(rc, rc);
106#else
107 pVM->nem.s.fAllow64BitGuests = false;
108#endif
109
110#ifdef RT_OS_WINDOWS
111 /** @cfgm{/NEM/UseRing0Runloop, bool, true}
112 * Whether to use the ring-0 runloop (if enabled in the build) or the ring-3 one.
113 * The latter is generally slower. This option serves as a way out in case
114 * something breaks in the ring-0 loop. */
115# ifdef NEM_WIN_USE_RING0_RUNLOOP_BY_DEFAULT
116 bool fUseRing0Runloop = true;
117# else
118 bool fUseRing0Runloop = false;
119# endif
120 rc = CFGMR3QueryBoolDef(pCfgNem, "UseRing0Runloop", &fUseRing0Runloop, fUseRing0Runloop);
121 AssertLogRelRCReturn(rc, rc);
122 pVM->nem.s.fUseRing0Runloop = fUseRing0Runloop;
123#endif
124
125 return VINF_SUCCESS;
126}
127
128
129/**
130 * This is called by HMR3Init() when HM cannot be used.
131 *
132 * Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
133 * native hypervisor API to execute the VM.
134 *
135 * @returns VBox status code.
136 * @param pVM The cross context VM structure.
137 * @param fFallback Whether this is a fallback call. Cleared if the VM is
138 * configured to use NEM instead of HM.
139 * @param fForced Whether /HM/HMForced was set. If set and we fail to
140 * enable NEM, we'll return a failure status code.
141 * Otherwise we'll assume HMR3Init falls back on raw-mode.
142 */
143VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
144{
145 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
146 int rc;
147 if (pVM->nem.s.fEnabled)
148 {
149#ifdef VBOX_WITH_NATIVE_NEM
150 rc = nemR3NativeInit(pVM, fFallback, fForced);
151 ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
152#else
153 RT_NOREF(fFallback);
154 rc = VINF_SUCCESS;
155#endif
156 if (RT_SUCCESS(rc))
157 {
158 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
159 LogRel(("NEM: NEMR3Init: Active.\n"));
160 else
161 {
162 LogRel(("NEM: NEMR3Init: Not available.\n"));
163 if (fForced)
164 rc = VERR_NEM_NOT_AVAILABLE;
165 }
166 }
167 else
168 LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
169 }
170 else
171 {
172 LogRel(("NEM: NEMR3Init: Disabled.\n"));
173 rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
174 }
175 return rc;
176}
177
178
179/**
180 * Perform initialization that depends on CPUM working.
181 *
182 * This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
183 *
184 * @returns VBox status code.
185 * @param pVM The cross context VM structure.
186 */
187VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
188{
189 int rc = VINF_SUCCESS;
190 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
191 {
192 /*
193 * Enable CPU features making general ASSUMPTIONS (there are two similar
194 * blocks of code in HM.cpp), to avoid duplicating this code. The
195 * native backend can make check capabilities and adjust as needed.
196 */
197 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
198 if ( CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD
199 || CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_HYGON)
200 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
201 if (pVM->nem.s.fAllow64BitGuests)
202 {
203 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
204 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
205 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
206 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
207 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
208 }
209 /* Turn on NXE if PAE has been enabled. */
210 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
211 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
212
213 /*
214 * Do native after-CPUM init.
215 */
216#ifdef VBOX_WITH_NATIVE_NEM
217 rc = nemR3NativeInitAfterCPUM(pVM);
218#else
219 RT_NOREF(pVM);
220#endif
221 }
222 return rc;
223}
224
225
226/**
227 * Called when a init phase has completed.
228 *
229 * @returns VBox status code.
230 * @param pVM The cross context VM structure.
231 * @param enmWhat The phase that completed.
232 */
233VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
234{
235 /*
236 * Check if GIM needs #UD, since that applies to everyone.
237 */
238 if (enmWhat == VMINITCOMPLETED_RING3)
239 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
240 {
241 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
242 pVCpu->nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
243 }
244
245 /*
246 * Call native code.
247 */
248 int rc = VINF_SUCCESS;
249#ifdef VBOX_WITH_NATIVE_NEM
250 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
251 rc = nemR3NativeInitCompleted(pVM, enmWhat);
252#else
253 RT_NOREF(pVM, enmWhat);
254#endif
255 return rc;
256}
257
258
259/**
260 *
261 * @returns VBox status code.
262 * @param pVM The cross context VM structure.
263 */
264VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
265{
266 AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
267 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
268 AssertReturn(pVM->apCpusR3[idCpu]->nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
269
270 /* Do native termination. */
271 int rc = VINF_SUCCESS;
272#ifdef VBOX_WITH_NATIVE_NEM
273 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
274 rc = nemR3NativeTerm(pVM);
275#endif
276
277 /* Mark it as terminated. */
278 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
279 {
280 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
281 pVCpu->nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
282 }
283 pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
284 return rc;
285}
286
287/**
288 * External interface for querying whether native execution API is used.
289 *
290 * @returns true if NEM is being used, otherwise false.
291 * @param pUVM The user mode VM handle.
292 * @sa HMR3IsEnabled
293 */
294VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
295{
296 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
297 PVM pVM = pUVM->pVM;
298 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
299 return VM_IS_NEM_ENABLED(pVM);
300}
301
302
303/**
304 * The VM is being reset.
305 *
306 * @param pVM The cross context VM structure.
307 */
308VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
309{
310#ifdef VBOX_WITH_NATIVE_NEM
311 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
312 nemR3NativeReset(pVM);
313#else
314 RT_NOREF(pVM);
315#endif
316}
317
318
319/**
320 * Resets a virtual CPU.
321 *
322 * Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
323 *
324 * @param pVCpu The cross context virtual CPU structure to reset.
325 * @param fInitIpi Set if being reset due to INIT IPI.
326 */
327VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
328{
329#ifdef VBOX_WITH_NATIVE_NEM
330 if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
331 nemR3NativeResetCpu(pVCpu, fInitIpi);
332#else
333 RT_NOREF(pVCpu, fInitIpi);
334#endif
335}
336
337
338/**
339 * Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
340 *
341 * @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
342 * @param pVM The cross context VM structure.
343 */
344VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
345{
346#ifdef VBOX_WITH_NATIVE_NEM
347# ifdef RT_OS_WINDOWS
348 if (VM_IS_NEM_ENABLED(pVM))
349 return true;
350# endif
351#else
352 RT_NOREF(pVM);
353#endif
354 return false;
355}
356
357
358/**
359 * Gets the name of a generic NEM exit code.
360 *
361 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
362 * @param uExit The NEM exit to name.
363 */
364VMMR3DECL(const char *) NEMR3GetExitName(uint32_t uExit)
365{
366 switch ((NEMEXITTYPE)uExit)
367 {
368 case NEMEXITTYPE_UNRECOVERABLE_EXCEPTION: return "NEM unrecoverable exception";
369 case NEMEXITTYPE_INVALID_VP_REGISTER_VALUE: return "NEM invalid vp register value";
370 case NEMEXITTYPE_INTTERRUPT_WINDOW: return "NEM interrupt window";
371 case NEMEXITTYPE_HALT: return "NEM halt";
372 case NEMEXITTYPE_XCPT_UD: return "NEM #UD";
373 case NEMEXITTYPE_XCPT_DB: return "NEM #DB";
374 case NEMEXITTYPE_XCPT_BP: return "NEM #BP";
375 case NEMEXITTYPE_CANCELED: return "NEM canceled";
376 case NEMEXITTYPE_MEMORY_ACCESS: return "NEM memory access";
377 }
378
379 return NULL;
380}
381
382
383VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
384{
385 Assert(VM_IS_NEM_ENABLED(pVM));
386#ifdef VBOX_WITH_NATIVE_NEM
387 return nemR3NativeRunGC(pVM, pVCpu);
388#else
389 NOREF(pVM); NOREF(pVCpu);
390 return VERR_INTERNAL_ERROR_3;
391#endif
392}
393
394
395VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
396{
397 Assert(VM_IS_NEM_ENABLED(pVM));
398#ifdef VBOX_WITH_NATIVE_NEM
399 return nemR3NativeCanExecuteGuest(pVM, pVCpu);
400#else
401 NOREF(pVM); NOREF(pVCpu);
402 return false;
403#endif
404}
405
406
407VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
408{
409 Assert(VM_IS_NEM_ENABLED(pVM));
410#ifdef VBOX_WITH_NATIVE_NEM
411 return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
412#else
413 NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
414 return false;
415#endif
416}
417
418
419VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
420{
421 AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
422#ifdef VBOX_WITH_NATIVE_NEM
423 nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
424#else
425 RT_NOREF(pVM, pVCpu, fFlags);
426#endif
427}
428
429
430
431
432VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
433{
434 int rc = VINF_SUCCESS;
435#ifdef VBOX_WITH_NATIVE_NEM
436 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
437 rc = nemR3NativeNotifyPhysRamRegister(pVM, GCPhys, cb);
438#else
439 NOREF(pVM); NOREF(GCPhys); NOREF(cb);
440#endif
441 return rc;
442}
443
444
445VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvMmio2)
446{
447 int rc = VINF_SUCCESS;
448#ifdef VBOX_WITH_NATIVE_NEM
449 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
450 rc = nemR3NativeNotifyPhysMmioExMap(pVM, GCPhys, cb, fFlags, pvMmio2);
451#else
452 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags); NOREF(pvMmio2);
453#endif
454 return rc;
455}
456
457
458VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
459{
460 int rc = VINF_SUCCESS;
461#ifdef VBOX_WITH_NATIVE_NEM
462 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
463 rc = nemR3NativeNotifyPhysMmioExUnmap(pVM, GCPhys, cb, fFlags);
464#else
465 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
466#endif
467 return rc;
468}
469
470
471VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
472{
473 int rc = VINF_SUCCESS;
474#ifdef VBOX_WITH_NATIVE_NEM
475 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
476 rc = nemR3NativeNotifyPhysRomRegisterEarly(pVM, GCPhys, cb, fFlags);
477#else
478 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
479#endif
480 return rc;
481}
482
483
484/**
485 * Called after the ROM range has been fully completed.
486 *
487 * This will be preceeded by a NEMR3NotifyPhysRomRegisterEarly() call as well a
488 * number of NEMHCNotifyPhysPageProtChanged calls.
489 *
490 * @returns VBox status code
491 * @param pVM The cross context VM structure.
492 * @param GCPhys The ROM address (page aligned).
493 * @param cb The size (page aligned).
494 * @param fFlags NEM_NOTIFY_PHYS_ROM_F_XXX.
495 */
496VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
497{
498 int rc = VINF_SUCCESS;
499#ifdef VBOX_WITH_NATIVE_NEM
500 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
501 rc = nemR3NativeNotifyPhysRomRegisterLate(pVM, GCPhys, cb, fFlags);
502#else
503 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
504#endif
505 return rc;
506}
507
508
509VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
510{
511#ifdef VBOX_WITH_NATIVE_NEM
512 if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
513 nemR3NativeNotifySetA20(pVCpu, fEnabled);
514#else
515 NOREF(pVCpu); NOREF(fEnabled);
516#endif
517}
518
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