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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3.cpp@ 76553

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1/* $Id: NEMR3.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager.
4 */
5
6/*
7 * Copyright (C) 2018-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_nem NEM - Native Execution Manager.
19 *
20 * This is an alternative execution manage to HM and raw-mode. On one host
21 * (Windows) we're forced to use this, on the others we just do it because we
22 * can. Since this is host specific in nature, information about an
23 * implementation is contained in the NEMR3Native-xxxx.cpp files.
24 *
25 * @ref pg_nem_win
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_NEM
33#include <VBox/vmm/nem.h>
34#include <VBox/vmm/gim.h>
35#include "NEMInternal.h"
36#include <VBox/vmm/vm.h>
37#include <VBox/vmm/uvm.h>
38#include <VBox/err.h>
39
40#include <iprt/asm.h>
41
42
43
44/**
45 * Basic init and configuration reading.
46 *
47 * Always call NEMR3Term after calling this.
48 *
49 * @returns VBox status code.
50 * @param pVM The cross context VM structure.
51 */
52VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
53{
54 LogFlow(("NEMR3Init\n"));
55
56 /*
57 * Assert alignment and sizes.
58 */
59 AssertCompileMemberAlignment(VM, nem.s, 64);
60 AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
61
62 /*
63 * Initialize state info so NEMR3Term will always be happy.
64 * No returning prior to setting magics!
65 */
66 pVM->nem.s.u32Magic = NEM_MAGIC;
67 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
68 pVM->aCpus[iCpu].nem.s.u32Magic = NEMCPU_MAGIC;
69
70 /*
71 * Read configuration.
72 */
73 PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
74
75 /*
76 * Validate the NEM settings.
77 */
78 int rc = CFGMR3ValidateConfig(pCfgNem,
79 "/NEM/",
80 "Enabled"
81 "|Allow64BitGuests"
82#ifdef RT_OS_WINDOWS
83 "|UseRing0Runloop"
84#endif
85 ,
86 "" /* pszValidNodes */, "NEM" /* pszWho */, 0 /* uInstance */);
87 if (RT_FAILURE(rc))
88 return rc;
89
90 /** @cfgm{/NEM/NEMEnabled, bool, true}
91 * Whether NEM is enabled. */
92 rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
93 AssertLogRelRCReturn(rc, rc);
94
95
96#ifdef VBOX_WITH_64_BITS_GUESTS
97 /** @cfgm{/NEM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
98 * Enables AMD64 CPU features.
99 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
100 * already have the support. */
101 rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
102 AssertLogRelRCReturn(rc, rc);
103#else
104 pVM->nem.s.fAllow64BitGuests = false;
105#endif
106
107#ifdef RT_OS_WINDOWS
108 /** @cfgm{/NEM/UseRing0Runloop, bool, true}
109 * Whether to use the ring-0 runloop (if enabled in the build) or the ring-3 one.
110 * The latter is generally slower. This option serves as a way out in case
111 * something breaks in the ring-0 loop. */
112# ifdef NEM_WIN_USE_RING0_RUNLOOP_BY_DEFAULT
113 bool fUseRing0Runloop = true;
114# else
115 bool fUseRing0Runloop = false;
116# endif
117 rc = CFGMR3QueryBoolDef(pCfgNem, "UseRing0Runloop", &fUseRing0Runloop, fUseRing0Runloop);
118 AssertLogRelRCReturn(rc, rc);
119 pVM->nem.s.fUseRing0Runloop = fUseRing0Runloop;
120#endif
121
122 return VINF_SUCCESS;
123}
124
125
126/**
127 * This is called by HMR3Init() when HM cannot be used.
128 *
129 * Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
130 * native hypervisor API to execute the VM.
131 *
132 * @returns VBox status code.
133 * @param pVM The cross context VM structure.
134 * @param fFallback Whether this is a fallback call. Cleared if the VM is
135 * configured to use NEM instead of HM.
136 * @param fForced Whether /HM/HMForced was set. If set and we fail to
137 * enable NEM, we'll return a failure status code.
138 * Otherwise we'll assume HMR3Init falls back on raw-mode.
139 */
140VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
141{
142 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
143 int rc;
144 if (pVM->nem.s.fEnabled)
145 {
146#ifdef VBOX_WITH_NATIVE_NEM
147 rc = nemR3NativeInit(pVM, fFallback, fForced);
148 ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
149#else
150 RT_NOREF(fFallback);
151 rc = VINF_SUCCESS;
152#endif
153 if (RT_SUCCESS(rc))
154 {
155 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
156 LogRel(("NEM: NEMR3Init: Active.\n"));
157 else
158 {
159 LogRel(("NEM: NEMR3Init: Not available.\n"));
160 if (fForced)
161 rc = VERR_NEM_NOT_AVAILABLE;
162 }
163 }
164 else
165 LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
166 }
167 else
168 {
169 LogRel(("NEM: NEMR3Init: Disabled.\n"));
170 rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
171 }
172 return rc;
173}
174
175
176/**
177 * Perform initialization that depends on CPUM working.
178 *
179 * This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
180 *
181 * @returns VBox status code.
182 * @param pVM The cross context VM structure.
183 */
184VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
185{
186 int rc = VINF_SUCCESS;
187 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
188 {
189 /*
190 * Enable CPU features making general ASSUMPTIONS (there are two similar
191 * blocks of code in HM.cpp), to avoid duplicating this code. The
192 * native backend can make check capabilities and adjust as needed.
193 */
194 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
195 if (CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD)
196 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
197 if (pVM->nem.s.fAllow64BitGuests)
198 {
199 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
200 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
201 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
202 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
203 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
204 }
205 /* Turn on NXE if PAE has been enabled. */
206 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
207 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
208
209 /*
210 * Do native after-CPUM init.
211 */
212#ifdef VBOX_WITH_NATIVE_NEM
213 rc = nemR3NativeInitAfterCPUM(pVM);
214#else
215 RT_NOREF(pVM);
216#endif
217 }
218 return rc;
219}
220
221
222/**
223 * Called when a init phase has completed.
224 *
225 * @returns VBox status code.
226 * @param pVM The cross context VM structure.
227 * @param enmWhat The phase that completed.
228 */
229VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
230{
231 /*
232 * Check if GIM needs #UD, since that applies to everyone.
233 */
234 if (enmWhat == VMINITCOMPLETED_RING3)
235 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
236 pVM->aCpus[iCpu].nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(&pVM->aCpus[iCpu]);
237
238 /*
239 * Call native code.
240 */
241 int rc = VINF_SUCCESS;
242#ifdef VBOX_WITH_NATIVE_NEM
243 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
244 rc = nemR3NativeInitCompleted(pVM, enmWhat);
245#else
246 RT_NOREF(pVM, enmWhat);
247#endif
248 return rc;
249}
250
251
252/**
253 *
254 * @returns VBox status code.
255 * @param pVM The cross context VM structure.
256 */
257VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
258{
259 AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
260 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
261 AssertReturn(pVM->aCpus[iCpu].nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
262
263 /* Do native termination. */
264 int rc = VINF_SUCCESS;
265#ifdef VBOX_WITH_NATIVE_NEM
266 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
267 rc = nemR3NativeTerm(pVM);
268#endif
269
270 /* Mark it as terminated. */
271 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
272 pVM->aCpus[iCpu].nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
273 pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
274 return rc;
275}
276
277/**
278 * External interface for querying whether native execution API is used.
279 *
280 * @returns true if NEM is being used, otherwise false.
281 * @param pUVM The user mode VM handle.
282 * @sa HMR3IsEnabled
283 */
284VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
285{
286 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
287 PVM pVM = pUVM->pVM;
288 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
289 return VM_IS_NEM_ENABLED(pVM);
290}
291
292
293/**
294 * The VM is being reset.
295 *
296 * @param pVM The cross context VM structure.
297 */
298VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
299{
300#ifdef VBOX_WITH_NATIVE_NEM
301 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
302 nemR3NativeReset(pVM);
303#else
304 RT_NOREF(pVM);
305#endif
306}
307
308
309/**
310 * Resets a virtual CPU.
311 *
312 * Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
313 *
314 * @param pVCpu The cross context virtual CPU structure to reset.
315 * @param fInitIpi Set if being reset due to INIT IPI.
316 */
317VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
318{
319#ifdef VBOX_WITH_NATIVE_NEM
320 if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
321 nemR3NativeResetCpu(pVCpu, fInitIpi);
322#else
323 RT_NOREF(pVCpu, fInitIpi);
324#endif
325}
326
327
328/**
329 * Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
330 *
331 * @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
332 * @param pVM The cross context VM structure.
333 */
334VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
335{
336#ifdef VBOX_WITH_NATIVE_NEM
337# ifdef RT_OS_WINDOWS
338 if (VM_IS_NEM_ENABLED(pVM))
339 return true;
340# endif
341#else
342 RT_NOREF(pVM);
343#endif
344 return false;
345}
346
347
348/**
349 * Gets the name of a generic NEM exit code.
350 *
351 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
352 * @param uExit The NEM exit to name.
353 */
354VMMR3DECL(const char *) NEMR3GetExitName(uint32_t uExit)
355{
356 switch ((NEMEXITTYPE)uExit)
357 {
358 case NEMEXITTYPE_UNRECOVERABLE_EXCEPTION: return "NEM unrecoverable exception";
359 case NEMEXITTYPE_INVALID_VP_REGISTER_VALUE: return "NEM invalid vp register value";
360 case NEMEXITTYPE_INTTERRUPT_WINDOW: return "NEM interrupt window";
361 case NEMEXITTYPE_HALT: return "NEM halt";
362 case NEMEXITTYPE_XCPT_UD: return "NEM #UD";
363 case NEMEXITTYPE_XCPT_DB: return "NEM #DB";
364 case NEMEXITTYPE_XCPT_BP: return "NEM #BP";
365 case NEMEXITTYPE_CANCELED: return "NEM canceled";
366 case NEMEXITTYPE_MEMORY_ACCESS: return "NEM memory access";
367 }
368
369 return NULL;
370}
371
372
373VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
374{
375 Assert(VM_IS_NEM_ENABLED(pVM));
376#ifdef VBOX_WITH_NATIVE_NEM
377 return nemR3NativeRunGC(pVM, pVCpu);
378#else
379 NOREF(pVM); NOREF(pVCpu);
380 return VERR_INTERNAL_ERROR_3;
381#endif
382}
383
384
385VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
386{
387 Assert(VM_IS_NEM_ENABLED(pVM));
388#ifdef VBOX_WITH_NATIVE_NEM
389 return nemR3NativeCanExecuteGuest(pVM, pVCpu);
390#else
391 NOREF(pVM); NOREF(pVCpu);
392 return false;
393#endif
394}
395
396
397VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
398{
399 Assert(VM_IS_NEM_ENABLED(pVM));
400#ifdef VBOX_WITH_NATIVE_NEM
401 return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
402#else
403 NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
404 return false;
405#endif
406}
407
408
409VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
410{
411 AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
412#ifdef VBOX_WITH_NATIVE_NEM
413 nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
414#else
415 RT_NOREF(pVM, pVCpu, fFlags);
416#endif
417}
418
419
420
421
422VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
423{
424 int rc = VINF_SUCCESS;
425#ifdef VBOX_WITH_NATIVE_NEM
426 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
427 rc = nemR3NativeNotifyPhysRamRegister(pVM, GCPhys, cb);
428#else
429 NOREF(pVM); NOREF(GCPhys); NOREF(cb);
430#endif
431 return rc;
432}
433
434
435VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvMmio2)
436{
437 int rc = VINF_SUCCESS;
438#ifdef VBOX_WITH_NATIVE_NEM
439 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
440 rc = nemR3NativeNotifyPhysMmioExMap(pVM, GCPhys, cb, fFlags, pvMmio2);
441#else
442 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags); NOREF(pvMmio2);
443#endif
444 return rc;
445}
446
447
448VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
449{
450 int rc = VINF_SUCCESS;
451#ifdef VBOX_WITH_NATIVE_NEM
452 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
453 rc = nemR3NativeNotifyPhysMmioExUnmap(pVM, GCPhys, cb, fFlags);
454#else
455 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
456#endif
457 return rc;
458}
459
460
461VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
462{
463 int rc = VINF_SUCCESS;
464#ifdef VBOX_WITH_NATIVE_NEM
465 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
466 rc = nemR3NativeNotifyPhysRomRegisterEarly(pVM, GCPhys, cb, fFlags);
467#else
468 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
469#endif
470 return rc;
471}
472
473
474/**
475 * Called after the ROM range has been fully completed.
476 *
477 * This will be preceeded by a NEMR3NotifyPhysRomRegisterEarly() call as well a
478 * number of NEMHCNotifyPhysPageProtChanged calls.
479 *
480 * @returns VBox status code
481 * @param pVM The cross context VM structure.
482 * @param GCPhys The ROM address (page aligned).
483 * @param cb The size (page aligned).
484 * @param fFlags NEM_NOTIFY_PHYS_ROM_F_XXX.
485 */
486VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
487{
488 int rc = VINF_SUCCESS;
489#ifdef VBOX_WITH_NATIVE_NEM
490 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
491 rc = nemR3NativeNotifyPhysRomRegisterLate(pVM, GCPhys, cb, fFlags);
492#else
493 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
494#endif
495 return rc;
496}
497
498
499VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
500{
501#ifdef VBOX_WITH_NATIVE_NEM
502 if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
503 nemR3NativeNotifySetA20(pVCpu, fEnabled);
504#else
505 NOREF(pVCpu); NOREF(fEnabled);
506#endif
507}
508
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