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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3.cpp@ 72924

Last change on this file since 72924 was 72924, checked in by vboxsync, 6 years ago

NEM/win: Make it possible to select between ring-0 runloop hypercalls+VID.SYS and ring-3 runloop using WHv API via CFGM setting. bugref:9044
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1/* $Id: NEMR3.cpp 72924 2018-07-05 16:14:26Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager.
4 */
5
6/*
7 * Copyright (C) 2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_nem NEM - Native Execution Manager.
19 *
20 * This is an alternative execution manage to HM and raw-mode. On one host
21 * (Windows) we're forced to use this, on the others we just do it because we
22 * can. Since this is host specific in nature, information about an
23 * implementation is contained in the NEMR3Native-xxxx.cpp files.
24 *
25 * @ref pg_nem_win
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_NEM
33#include <VBox/vmm/nem.h>
34#include <VBox/vmm/gim.h>
35#include "NEMInternal.h"
36#include <VBox/vmm/vm.h>
37#include <VBox/vmm/uvm.h>
38
39#include <iprt/asm.h>
40
41
42
43/**
44 * Basic init and configuration reading.
45 *
46 * Always call NEMR3Term after calling this.
47 *
48 * @returns VBox status code.
49 * @param pVM The cross context VM structure.
50 */
51VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
52{
53 LogFlow(("NEMR3Init\n"));
54
55 /*
56 * Assert alignment and sizes.
57 */
58 AssertCompileMemberAlignment(VM, nem.s, 64);
59 AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
60
61 /*
62 * Initialize state info so NEMR3Term will always be happy.
63 * No returning prior to setting magics!
64 */
65 pVM->nem.s.u32Magic = NEM_MAGIC;
66 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
67 pVM->aCpus[iCpu].nem.s.u32Magic = NEMCPU_MAGIC;
68
69 /*
70 * Read configuration.
71 */
72 PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
73
74 /*
75 * Validate the NEM settings.
76 */
77 int rc = CFGMR3ValidateConfig(pCfgNem,
78 "/NEM/",
79 "Enabled"
80 "|Allow64BitGuests"
81#ifdef RT_OS_WINDOWS
82 "|UseRing0Runloop"
83#endif
84 ,
85 "" /* pszValidNodes */, "NEM" /* pszWho */, 0 /* uInstance */);
86 if (RT_FAILURE(rc))
87 return rc;
88
89 /** @cfgm{/NEM/NEMEnabled, bool, true}
90 * Whether NEM is enabled. */
91 rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
92 AssertLogRelRCReturn(rc, rc);
93
94
95#ifdef VBOX_WITH_64_BITS_GUESTS
96 /** @cfgm{/NEM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
97 * Enables AMD64 CPU features.
98 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
99 * already have the support. */
100 rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
101 AssertLogRelRCReturn(rc, rc);
102#else
103 pVM->nem.s.fAllow64BitGuests = false;
104#endif
105
106#ifdef RT_OS_WINDOWS
107 /** @cfgm{/NEM/UseRing0Runloop, bool, true}
108 * Whether to use the ring-0 runloop (if enabled in the build) or the ring-3 one.
109 * The latter is generally slower. This option serves as a way out in case
110 * something breaks in the ring-0 loop. */
111# ifdef NEM_WIN_USE_RING0_RUNLOOP_BY_DEFAULT
112 bool fUseRing0Runloop = true;
113# else
114 bool fUseRing0Runloop = false;
115# endif
116 rc = CFGMR3QueryBoolDef(pCfgNem, "UseRing0Runloop", &fUseRing0Runloop, fUseRing0Runloop);
117 AssertLogRelRCReturn(rc, rc);
118 pVM->nem.s.fUseRing0Runloop = fUseRing0Runloop;
119#endif
120
121 return VINF_SUCCESS;
122}
123
124
125/**
126 * This is called by HMR3Init() when HM cannot be used.
127 *
128 * Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
129 * native hypervisor API to execute the VM.
130 *
131 * @returns VBox status code.
132 * @param pVM The cross context VM structure.
133 * @param fFallback Whether this is a fallback call. Cleared if the VM is
134 * configured to use NEM instead of HM.
135 * @param fForced Whether /HM/HMForced was set. If set and we fail to
136 * enable NEM, we'll return a failure status code.
137 * Otherwise we'll assume HMR3Init falls back on raw-mode.
138 */
139VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
140{
141 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
142 int rc;
143 if (pVM->nem.s.fEnabled)
144 {
145#ifdef VBOX_WITH_NATIVE_NEM
146 rc = nemR3NativeInit(pVM, fFallback, fForced);
147 ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
148#else
149 RT_NOREF(fFallback);
150 rc = VINF_SUCCESS;
151#endif
152 if (RT_SUCCESS(rc))
153 {
154 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
155 LogRel(("NEM: NEMR3Init: Active.\n"));
156 else
157 {
158 LogRel(("NEM: NEMR3Init: Not available.\n"));
159 if (fForced)
160 rc = VERR_NEM_NOT_AVAILABLE;
161 }
162 }
163 else
164 LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
165 }
166 else
167 {
168 LogRel(("NEM: NEMR3Init: Disabled.\n"));
169 rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
170 }
171 return rc;
172}
173
174
175/**
176 * Perform initialization that depends on CPUM working.
177 *
178 * This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
179 *
180 * @returns VBox status code.
181 * @param pVM The cross context VM structure.
182 */
183VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
184{
185 int rc = VINF_SUCCESS;
186 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
187 {
188 /*
189 * Enable CPU features making general ASSUMPTIONS (there are two similar
190 * blocks of code in HM.cpp), to avoid duplicating this code. The
191 * native backend can make check capabilities and adjust as needed.
192 */
193 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
194 if (CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD)
195 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
196 if (pVM->nem.s.fAllow64BitGuests)
197 {
198 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
199 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
200 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
201 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
202 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
203 }
204 /* Turn on NXE if PAE has been enabled. */
205 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
206 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
207
208 /*
209 * Do native after-CPUM init.
210 */
211#ifdef VBOX_WITH_NATIVE_NEM
212 rc = nemR3NativeInitAfterCPUM(pVM);
213#else
214 RT_NOREF(pVM);
215#endif
216 }
217 return rc;
218}
219
220
221/**
222 * Called when a init phase has completed.
223 *
224 * @returns VBox status code.
225 * @param pVM The cross context VM structure.
226 * @param enmWhat The phase that completed.
227 */
228VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
229{
230 /*
231 * Check if GIM needs #UD, since that applies to everyone.
232 */
233 if (enmWhat == VMINITCOMPLETED_RING3)
234 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
235 pVM->aCpus[iCpu].nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(&pVM->aCpus[iCpu]);
236
237 /*
238 * Call native code.
239 */
240 int rc = VINF_SUCCESS;
241#ifdef VBOX_WITH_NATIVE_NEM
242 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
243 rc = nemR3NativeInitCompleted(pVM, enmWhat);
244#else
245 RT_NOREF(pVM, enmWhat);
246#endif
247 return rc;
248}
249
250
251/**
252 *
253 * @returns VBox status code.
254 * @param pVM The cross context VM structure.
255 */
256VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
257{
258 AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
259 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
260 AssertReturn(pVM->aCpus[iCpu].nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
261
262 /* Do native termination. */
263 int rc = VINF_SUCCESS;
264#ifdef VBOX_WITH_NATIVE_NEM
265 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
266 rc = nemR3NativeTerm(pVM);
267#endif
268
269 /* Mark it as terminated. */
270 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
271 pVM->aCpus[iCpu].nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
272 pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
273 return rc;
274}
275
276/**
277 * External interface for querying whether native execution API is used.
278 *
279 * @returns true if NEM is being used, otherwise false.
280 * @param pUVM The user mode VM handle.
281 * @sa HMR3IsEnabled
282 */
283VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
284{
285 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
286 PVM pVM = pUVM->pVM;
287 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
288 return VM_IS_NEM_ENABLED(pVM);
289}
290
291
292/**
293 * The VM is being reset.
294 *
295 * @param pVM The cross context VM structure.
296 */
297VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
298{
299#ifdef VBOX_WITH_NATIVE_NEM
300 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
301 nemR3NativeReset(pVM);
302#else
303 RT_NOREF(pVM);
304#endif
305}
306
307
308/**
309 * Resets a virtual CPU.
310 *
311 * Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
312 *
313 * @param pVCpu The cross context virtual CPU structure to reset.
314 * @param fInitIpi Set if being reset due to INIT IPI.
315 */
316VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
317{
318#ifdef VBOX_WITH_NATIVE_NEM
319 if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
320 nemR3NativeResetCpu(pVCpu, fInitIpi);
321#else
322 RT_NOREF(pVCpu, fInitIpi);
323#endif
324}
325
326
327/**
328 * Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
329 *
330 * @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
331 * @param pVM The cross context VM structure.
332 */
333VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
334{
335#ifdef VBOX_WITH_NATIVE_NEM
336# ifdef RT_OS_WINDOWS
337 if (VM_IS_NEM_ENABLED(pVM))
338 return true;
339# endif
340#else
341 RT_NOREF(pVM);
342#endif
343 return false;
344}
345
346
347/**
348 * Gets the name of a generic NEM exit code.
349 *
350 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
351 * @param uExit The NEM exit to name.
352 */
353VMMR3DECL(const char *) NEMR3GetExitName(uint32_t uExit)
354{
355 switch ((NEMEXITTYPE)uExit)
356 {
357 case NEMEXITTYPE_UNRECOVERABLE_EXCEPTION: return "NEM unrecoverable exception";
358 case NEMEXITTYPE_INVALID_VP_REGISTER_VALUE: return "NEM invalid vp register value";
359 case NEMEXITTYPE_INTTERRUPT_WINDOW: return "NEM interrupt window";
360 case NEMEXITTYPE_HALT: return "NEM halt";
361 case NEMEXITTYPE_XCPT_UD: return "NEM #UD";
362 case NEMEXITTYPE_XCPT_DB: return "NEM #DB";
363 case NEMEXITTYPE_XCPT_BP: return "NEM #BP";
364 case NEMEXITTYPE_CANCELED: return "NEM canceled";
365 case NEMEXITTYPE_MEMORY_ACCESS: return "NEM memory access";
366 }
367
368 return NULL;
369}
370
371
372VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
373{
374 Assert(VM_IS_NEM_ENABLED(pVM));
375#ifdef VBOX_WITH_NATIVE_NEM
376 return nemR3NativeRunGC(pVM, pVCpu);
377#else
378 NOREF(pVM); NOREF(pVCpu);
379 return VERR_INTERNAL_ERROR_3;
380#endif
381}
382
383
384VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
385{
386 Assert(VM_IS_NEM_ENABLED(pVM));
387#ifdef VBOX_WITH_NATIVE_NEM
388 return nemR3NativeCanExecuteGuest(pVM, pVCpu);
389#else
390 NOREF(pVM); NOREF(pVCpu);
391 return false;
392#endif
393}
394
395
396VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
397{
398 Assert(VM_IS_NEM_ENABLED(pVM));
399#ifdef VBOX_WITH_NATIVE_NEM
400 return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
401#else
402 NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
403 return false;
404#endif
405}
406
407
408VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
409{
410 AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
411#ifdef VBOX_WITH_NATIVE_NEM
412 nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
413#else
414 RT_NOREF(pVM, pVCpu, fFlags);
415#endif
416}
417
418
419
420
421VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
422{
423 int rc = VINF_SUCCESS;
424#ifdef VBOX_WITH_NATIVE_NEM
425 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
426 rc = nemR3NativeNotifyPhysRamRegister(pVM, GCPhys, cb);
427#else
428 NOREF(pVM); NOREF(GCPhys); NOREF(cb);
429#endif
430 return rc;
431}
432
433
434VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvMmio2)
435{
436 int rc = VINF_SUCCESS;
437#ifdef VBOX_WITH_NATIVE_NEM
438 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
439 rc = nemR3NativeNotifyPhysMmioExMap(pVM, GCPhys, cb, fFlags, pvMmio2);
440#else
441 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags); NOREF(pvMmio2);
442#endif
443 return rc;
444}
445
446
447VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
448{
449 int rc = VINF_SUCCESS;
450#ifdef VBOX_WITH_NATIVE_NEM
451 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
452 rc = nemR3NativeNotifyPhysMmioExUnmap(pVM, GCPhys, cb, fFlags);
453#else
454 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
455#endif
456 return rc;
457}
458
459
460VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
461{
462 int rc = VINF_SUCCESS;
463#ifdef VBOX_WITH_NATIVE_NEM
464 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
465 rc = nemR3NativeNotifyPhysRomRegisterEarly(pVM, GCPhys, cb, fFlags);
466#else
467 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
468#endif
469 return rc;
470}
471
472
473/**
474 * Called after the ROM range has been fully completed.
475 *
476 * This will be preceeded by a NEMR3NotifyPhysRomRegisterEarly() call as well a
477 * number of NEMHCNotifyPhysPageProtChanged calls.
478 *
479 * @returns VBox status code
480 * @param pVM The cross context VM structure.
481 * @param GCPhys The ROM address (page aligned).
482 * @param cb The size (page aligned).
483 * @param fFlags NEM_NOTIFY_PHYS_ROM_F_XXX.
484 */
485VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
486{
487 int rc = VINF_SUCCESS;
488#ifdef VBOX_WITH_NATIVE_NEM
489 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
490 rc = nemR3NativeNotifyPhysRomRegisterLate(pVM, GCPhys, cb, fFlags);
491#else
492 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
493#endif
494 return rc;
495}
496
497
498VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
499{
500#ifdef VBOX_WITH_NATIVE_NEM
501 if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
502 nemR3NativeNotifySetA20(pVCpu, fEnabled);
503#else
504 NOREF(pVCpu); NOREF(fEnabled);
505#endif
506}
507
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