[70918] | 1 | /* $Id: NEMR3.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
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| 2 | /** @file
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| 3 | * NEM - Native execution manager.
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| 4 | */
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| 5 |
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| 6 | /*
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[76553] | 7 | * Copyright (C) 2018-2019 Oracle Corporation
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[70918] | 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 | /** @page pg_nem NEM - Native Execution Manager.
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| 19 | *
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[71283] | 20 | * This is an alternative execution manage to HM and raw-mode. On one host
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| 21 | * (Windows) we're forced to use this, on the others we just do it because we
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| 22 | * can. Since this is host specific in nature, information about an
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| 23 | * implementation is contained in the NEMR3Native-xxxx.cpp files.
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[70918] | 24 | *
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[71284] | 25 | * @ref pg_nem_win
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[70918] | 26 | */
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| 27 |
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| 28 |
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| 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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| 32 | #define LOG_GROUP LOG_GROUP_NEM
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| 33 | #include <VBox/vmm/nem.h>
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[72470] | 34 | #include <VBox/vmm/gim.h>
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[70918] | 35 | #include "NEMInternal.h"
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| 36 | #include <VBox/vmm/vm.h>
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[72267] | 37 | #include <VBox/vmm/uvm.h>
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[76397] | 38 | #include <VBox/err.h>
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[70918] | 39 |
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[70948] | 40 | #include <iprt/asm.h>
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[70918] | 41 |
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| 42 |
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[70948] | 43 |
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[70918] | 44 | /**
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| 45 | * Basic init and configuration reading.
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| 46 | *
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| 47 | * Always call NEMR3Term after calling this.
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| 48 | *
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| 49 | * @returns VBox status code.
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[70945] | 50 | * @param pVM The cross context VM structure.
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[70918] | 51 | */
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| 52 | VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
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| 53 | {
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| 54 | LogFlow(("NEMR3Init\n"));
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| 55 |
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| 56 | /*
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| 57 | * Assert alignment and sizes.
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| 58 | */
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| 59 | AssertCompileMemberAlignment(VM, nem.s, 64);
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| 60 | AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
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| 61 |
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| 62 | /*
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| 63 | * Initialize state info so NEMR3Term will always be happy.
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| 64 | * No returning prior to setting magics!
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| 65 | */
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| 66 | pVM->nem.s.u32Magic = NEM_MAGIC;
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| 67 | for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
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| 68 | pVM->aCpus[iCpu].nem.s.u32Magic = NEMCPU_MAGIC;
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| 69 |
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| 70 | /*
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| 71 | * Read configuration.
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| 72 | */
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| 73 | PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
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| 74 |
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| 75 | /*
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| 76 | * Validate the NEM settings.
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| 77 | */
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| 78 | int rc = CFGMR3ValidateConfig(pCfgNem,
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| 79 | "/NEM/",
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[72343] | 80 | "Enabled"
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[72924] | 81 | "|Allow64BitGuests"
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| 82 | #ifdef RT_OS_WINDOWS
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| 83 | "|UseRing0Runloop"
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| 84 | #endif
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| 85 | ,
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[70918] | 86 | "" /* pszValidNodes */, "NEM" /* pszWho */, 0 /* uInstance */);
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| 87 | if (RT_FAILURE(rc))
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| 88 | return rc;
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| 89 |
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| 90 | /** @cfgm{/NEM/NEMEnabled, bool, true}
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| 91 | * Whether NEM is enabled. */
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| 92 | rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
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| 93 | AssertLogRelRCReturn(rc, rc);
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| 94 |
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[72343] | 95 |
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| 96 | #ifdef VBOX_WITH_64_BITS_GUESTS
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[72924] | 97 | /** @cfgm{/NEM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
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[72343] | 98 | * Enables AMD64 CPU features.
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| 99 | * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
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| 100 | * already have the support. */
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| 101 | rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
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| 102 | AssertLogRelRCReturn(rc, rc);
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| 103 | #else
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| 104 | pVM->nem.s.fAllow64BitGuests = false;
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| 105 | #endif
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| 106 |
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[72924] | 107 | #ifdef RT_OS_WINDOWS
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| 108 | /** @cfgm{/NEM/UseRing0Runloop, bool, true}
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| 109 | * Whether to use the ring-0 runloop (if enabled in the build) or the ring-3 one.
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| 110 | * The latter is generally slower. This option serves as a way out in case
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| 111 | * something breaks in the ring-0 loop. */
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| 112 | # ifdef NEM_WIN_USE_RING0_RUNLOOP_BY_DEFAULT
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| 113 | bool fUseRing0Runloop = true;
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| 114 | # else
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| 115 | bool fUseRing0Runloop = false;
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| 116 | # endif
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| 117 | rc = CFGMR3QueryBoolDef(pCfgNem, "UseRing0Runloop", &fUseRing0Runloop, fUseRing0Runloop);
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| 118 | AssertLogRelRCReturn(rc, rc);
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| 119 | pVM->nem.s.fUseRing0Runloop = fUseRing0Runloop;
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| 120 | #endif
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[72343] | 121 |
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[70918] | 122 | return VINF_SUCCESS;
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| 123 | }
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| 124 |
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| 125 |
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| 126 | /**
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| 127 | * This is called by HMR3Init() when HM cannot be used.
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| 128 | *
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[70948] | 129 | * Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
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| 130 | * native hypervisor API to execute the VM.
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[70918] | 131 | *
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| 132 | * @returns VBox status code.
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[70945] | 133 | * @param pVM The cross context VM structure.
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[70918] | 134 | * @param fFallback Whether this is a fallback call. Cleared if the VM is
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| 135 | * configured to use NEM instead of HM.
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| 136 | * @param fForced Whether /HM/HMForced was set. If set and we fail to
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| 137 | * enable NEM, we'll return a failure status code.
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| 138 | * Otherwise we'll assume HMR3Init falls back on raw-mode.
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| 139 | */
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| 140 | VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
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| 141 | {
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[70948] | 142 | Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
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[70918] | 143 | int rc;
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| 144 | if (pVM->nem.s.fEnabled)
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| 145 | {
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| 146 | #ifdef VBOX_WITH_NATIVE_NEM
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| 147 | rc = nemR3NativeInit(pVM, fFallback, fForced);
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[70948] | 148 | ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
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[70918] | 149 | #else
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| 150 | RT_NOREF(fFallback);
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| 151 | rc = VINF_SUCCESS;
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| 152 | #endif
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| 153 | if (RT_SUCCESS(rc))
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| 154 | {
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[70948] | 155 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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[70918] | 156 | LogRel(("NEM: NEMR3Init: Active.\n"));
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| 157 | else
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| 158 | {
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| 159 | LogRel(("NEM: NEMR3Init: Not available.\n"));
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| 160 | if (fForced)
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| 161 | rc = VERR_NEM_NOT_AVAILABLE;
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| 162 | }
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| 163 | }
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| 164 | else
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| 165 | LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
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| 166 | }
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| 167 | else
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| 168 | {
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| 169 | LogRel(("NEM: NEMR3Init: Disabled.\n"));
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| 170 | rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
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| 171 | }
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| 172 | return rc;
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| 173 | }
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| 174 |
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| 175 |
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| 176 | /**
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[70945] | 177 | * Perform initialization that depends on CPUM working.
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| 178 | *
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| 179 | * This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
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| 180 | *
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| 181 | * @returns VBox status code.
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| 182 | * @param pVM The cross context VM structure.
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| 183 | */
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| 184 | VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
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| 185 | {
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| 186 | int rc = VINF_SUCCESS;
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[72343] | 187 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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| 188 | {
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| 189 | /*
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| 190 | * Enable CPU features making general ASSUMPTIONS (there are two similar
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| 191 | * blocks of code in HM.cpp), to avoid duplicating this code. The
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| 192 | * native backend can make check capabilities and adjust as needed.
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| 193 | */
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| 194 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
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| 195 | if (CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD)
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| 196 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
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| 197 | if (pVM->nem.s.fAllow64BitGuests)
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| 198 | {
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| 199 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
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| 200 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
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| 201 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
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| 202 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
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| 203 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
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| 204 | }
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| 205 | /* Turn on NXE if PAE has been enabled. */
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| 206 | else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
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| 207 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
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| 208 |
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| 209 | /*
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| 210 | * Do native after-CPUM init.
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| 211 | */
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[70945] | 212 | #ifdef VBOX_WITH_NATIVE_NEM
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| 213 | rc = nemR3NativeInitAfterCPUM(pVM);
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[70946] | 214 | #else
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[72343] | 215 | RT_NOREF(pVM);
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[70945] | 216 | #endif
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[72343] | 217 | }
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[70945] | 218 | return rc;
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| 219 | }
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| 220 |
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| 221 |
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| 222 | /**
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[70918] | 223 | * Called when a init phase has completed.
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| 224 | *
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| 225 | * @returns VBox status code.
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[70945] | 226 | * @param pVM The cross context VM structure.
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| 227 | * @param enmWhat The phase that completed.
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[70918] | 228 | */
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| 229 | VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
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| 230 | {
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[72470] | 231 | /*
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| 232 | * Check if GIM needs #UD, since that applies to everyone.
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| 233 | */
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| 234 | if (enmWhat == VMINITCOMPLETED_RING3)
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| 235 | for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
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| 236 | pVM->aCpus[iCpu].nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(&pVM->aCpus[iCpu]);
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| 237 |
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| 238 | /*
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| 239 | * Call native code.
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| 240 | */
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[70918] | 241 | int rc = VINF_SUCCESS;
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| 242 | #ifdef VBOX_WITH_NATIVE_NEM
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[70948] | 243 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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[70918] | 244 | rc = nemR3NativeInitCompleted(pVM, enmWhat);
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| 245 | #else
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| 246 | RT_NOREF(pVM, enmWhat);
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| 247 | #endif
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| 248 | return rc;
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| 249 | }
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| 250 |
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| 251 |
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| 252 | /**
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| 253 | *
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| 254 | * @returns VBox status code.
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[70945] | 255 | * @param pVM The cross context VM structure.
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[70918] | 256 | */
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| 257 | VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
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| 258 | {
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| 259 | AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
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| 260 | for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
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| 261 | AssertReturn(pVM->aCpus[iCpu].nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
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| 262 |
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| 263 | /* Do native termination. */
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| 264 | int rc = VINF_SUCCESS;
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| 265 | #ifdef VBOX_WITH_NATIVE_NEM
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[70948] | 266 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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[70918] | 267 | rc = nemR3NativeTerm(pVM);
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| 268 | #endif
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| 269 |
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| 270 | /* Mark it as terminated. */
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| 271 | for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
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| 272 | pVM->aCpus[iCpu].nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
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| 273 | pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
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| 274 | return rc;
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| 275 | }
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| 276 |
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[72267] | 277 | /**
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| 278 | * External interface for querying whether native execution API is used.
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| 279 | *
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| 280 | * @returns true if NEM is being used, otherwise false.
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| 281 | * @param pUVM The user mode VM handle.
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| 282 | * @sa HMR3IsEnabled
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| 283 | */
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| 284 | VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
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| 285 | {
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| 286 | UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
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| 287 | PVM pVM = pUVM->pVM;
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| 288 | VM_ASSERT_VALID_EXT_RETURN(pVM, false);
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| 289 | return VM_IS_NEM_ENABLED(pVM);
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| 290 | }
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[70918] | 291 |
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[72267] | 292 |
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[70918] | 293 | /**
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| 294 | * The VM is being reset.
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| 295 | *
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| 296 | * @param pVM The cross context VM structure.
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| 297 | */
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| 298 | VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
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| 299 | {
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| 300 | #ifdef VBOX_WITH_NATIVE_NEM
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[70948] | 301 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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[70918] | 302 | nemR3NativeReset(pVM);
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| 303 | #else
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| 304 | RT_NOREF(pVM);
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| 305 | #endif
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| 306 | }
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| 307 |
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| 308 |
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| 309 | /**
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| 310 | * Resets a virtual CPU.
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| 311 | *
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| 312 | * Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
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| 313 | *
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[71040] | 314 | * @param pVCpu The cross context virtual CPU structure to reset.
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| 315 | * @param fInitIpi Set if being reset due to INIT IPI.
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[70918] | 316 | */
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[71040] | 317 | VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
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[70918] | 318 | {
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| 319 | #ifdef VBOX_WITH_NATIVE_NEM
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[70948] | 320 | if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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[71040] | 321 | nemR3NativeResetCpu(pVCpu, fInitIpi);
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[70918] | 322 | #else
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[71040] | 323 | RT_NOREF(pVCpu, fInitIpi);
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[70918] | 324 | #endif
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| 325 | }
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| 326 |
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[70954] | 327 |
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[72526] | 328 | /**
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| 329 | * Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
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| 330 | *
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| 331 | * @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
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| 332 | * @param pVM The cross context VM structure.
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| 333 | */
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| 334 | VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
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| 335 | {
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| 336 | #ifdef VBOX_WITH_NATIVE_NEM
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| 337 | # ifdef RT_OS_WINDOWS
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| 338 | if (VM_IS_NEM_ENABLED(pVM))
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| 339 | return true;
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| 340 | # endif
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| 341 | #else
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| 342 | RT_NOREF(pVM);
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| 343 | #endif
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| 344 | return false;
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| 345 | }
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| 346 |
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| 347 |
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[72555] | 348 | /**
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| 349 | * Gets the name of a generic NEM exit code.
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| 350 | *
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| 351 | * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
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| 352 | * @param uExit The NEM exit to name.
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| 353 | */
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| 354 | VMMR3DECL(const char *) NEMR3GetExitName(uint32_t uExit)
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| 355 | {
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| 356 | switch ((NEMEXITTYPE)uExit)
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| 357 | {
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| 358 | case NEMEXITTYPE_UNRECOVERABLE_EXCEPTION: return "NEM unrecoverable exception";
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| 359 | case NEMEXITTYPE_INVALID_VP_REGISTER_VALUE: return "NEM invalid vp register value";
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| 360 | case NEMEXITTYPE_INTTERRUPT_WINDOW: return "NEM interrupt window";
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| 361 | case NEMEXITTYPE_HALT: return "NEM halt";
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| 362 | case NEMEXITTYPE_XCPT_UD: return "NEM #UD";
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| 363 | case NEMEXITTYPE_XCPT_DB: return "NEM #DB";
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| 364 | case NEMEXITTYPE_XCPT_BP: return "NEM #BP";
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| 365 | case NEMEXITTYPE_CANCELED: return "NEM canceled";
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[72575] | 366 | case NEMEXITTYPE_MEMORY_ACCESS: return "NEM memory access";
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[72555] | 367 | }
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[72526] | 368 |
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[72555] | 369 | return NULL;
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| 370 | }
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| 371 |
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| 372 |
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[70979] | 373 | VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
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| 374 | {
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| 375 | Assert(VM_IS_NEM_ENABLED(pVM));
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[70980] | 376 | #ifdef VBOX_WITH_NATIVE_NEM
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[70979] | 377 | return nemR3NativeRunGC(pVM, pVCpu);
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[70980] | 378 | #else
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| 379 | NOREF(pVM); NOREF(pVCpu);
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| 380 | return VERR_INTERNAL_ERROR_3;
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| 381 | #endif
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[70979] | 382 | }
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| 383 |
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| 384 |
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[72634] | 385 | VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
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[70979] | 386 | {
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| 387 | Assert(VM_IS_NEM_ENABLED(pVM));
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[70980] | 388 | #ifdef VBOX_WITH_NATIVE_NEM
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[72634] | 389 | return nemR3NativeCanExecuteGuest(pVM, pVCpu);
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[70980] | 390 | #else
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[72634] | 391 | NOREF(pVM); NOREF(pVCpu);
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[70980] | 392 | return false;
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| 393 | #endif
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[70979] | 394 | }
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| 395 |
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| 396 |
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| 397 | VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
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| 398 | {
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| 399 | Assert(VM_IS_NEM_ENABLED(pVM));
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[70980] | 400 | #ifdef VBOX_WITH_NATIVE_NEM
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[70979] | 401 | return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
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[70980] | 402 | #else
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| 403 | NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
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| 404 | return false;
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| 405 | #endif
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[70979] | 406 | }
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| 407 |
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| 408 |
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[71040] | 409 | VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
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| 410 | {
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| 411 | AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
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| 412 | #ifdef VBOX_WITH_NATIVE_NEM
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| 413 | nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
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| 414 | #else
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| 415 | RT_NOREF(pVM, pVCpu, fFlags);
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| 416 | #endif
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| 417 | }
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[70979] | 418 |
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[71040] | 419 |
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| 420 |
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| 421 |
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[70954] | 422 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
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| 423 | {
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| 424 | int rc = VINF_SUCCESS;
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| 425 | #ifdef VBOX_WITH_NATIVE_NEM
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| 426 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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| 427 | rc = nemR3NativeNotifyPhysRamRegister(pVM, GCPhys, cb);
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| 428 | #else
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| 429 | NOREF(pVM); NOREF(GCPhys); NOREF(cb);
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| 430 | #endif
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| 431 | return rc;
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| 432 | }
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| 433 |
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| 434 |
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[70977] | 435 | VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvMmio2)
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[70954] | 436 | {
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| 437 | int rc = VINF_SUCCESS;
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| 438 | #ifdef VBOX_WITH_NATIVE_NEM
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| 439 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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[70977] | 440 | rc = nemR3NativeNotifyPhysMmioExMap(pVM, GCPhys, cb, fFlags, pvMmio2);
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[70954] | 441 | #else
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[70977] | 442 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags); NOREF(pvMmio2);
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[70954] | 443 | #endif
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| 444 | return rc;
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| 445 | }
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| 446 |
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| 447 |
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| 448 | VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
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| 449 | {
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| 450 | int rc = VINF_SUCCESS;
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| 451 | #ifdef VBOX_WITH_NATIVE_NEM
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| 452 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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| 453 | rc = nemR3NativeNotifyPhysMmioExUnmap(pVM, GCPhys, cb, fFlags);
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| 454 | #else
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| 455 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
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| 456 | #endif
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| 457 | return rc;
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| 458 | }
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| 459 |
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| 460 |
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[70977] | 461 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
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[70954] | 462 | {
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| 463 | int rc = VINF_SUCCESS;
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| 464 | #ifdef VBOX_WITH_NATIVE_NEM
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| 465 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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| 466 | rc = nemR3NativeNotifyPhysRomRegisterEarly(pVM, GCPhys, cb, fFlags);
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| 467 | #else
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| 468 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
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| 469 | #endif
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| 470 | return rc;
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| 471 | }
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| 472 |
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| 473 |
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[70977] | 474 | /**
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| 475 | * Called after the ROM range has been fully completed.
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| 476 | *
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| 477 | * This will be preceeded by a NEMR3NotifyPhysRomRegisterEarly() call as well a
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| 478 | * number of NEMHCNotifyPhysPageProtChanged calls.
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| 479 | *
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| 480 | * @returns VBox status code
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| 481 | * @param pVM The cross context VM structure.
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| 482 | * @param GCPhys The ROM address (page aligned).
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| 483 | * @param cb The size (page aligned).
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| 484 | * @param fFlags NEM_NOTIFY_PHYS_ROM_F_XXX.
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| 485 | */
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| 486 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
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[70954] | 487 | {
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| 488 | int rc = VINF_SUCCESS;
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| 489 | #ifdef VBOX_WITH_NATIVE_NEM
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| 490 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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| 491 | rc = nemR3NativeNotifyPhysRomRegisterLate(pVM, GCPhys, cb, fFlags);
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| 492 | #else
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| 493 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
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| 494 | #endif
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| 495 | return rc;
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| 496 | }
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| 497 |
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| 498 |
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| 499 | VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
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| 500 | {
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| 501 | #ifdef VBOX_WITH_NATIVE_NEM
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| 502 | if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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| 503 | nemR3NativeNotifySetA20(pVCpu, fEnabled);
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| 504 | #else
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| 505 | NOREF(pVCpu); NOREF(fEnabled);
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| 506 | #endif
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| 507 | }
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| 508 |
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