VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 99740

Last change on this file since 99740 was 98993, checked in by vboxsync, 20 months ago

VMM: More ARMv8 x86/amd64 separation work, getting to PGM now, bugref:10385
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1/* $Id: IEMR3.cpp 98993 2023-03-15 18:41:59Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_EM
33#include <VBox/vmm/iem.h>
34#include <VBox/vmm/cpum.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/vmm/mm.h>
37#if defined(VBOX_VMM_TARGET_ARMV8)
38# include "IEMInternal-armv8.h"
39#else
40# include "IEMInternal.h"
41#endif
42#include <VBox/vmm/vm.h>
43#include <VBox/vmm/vmapi.h>
44#include <VBox/err.h>
45#ifdef VBOX_WITH_DEBUGGER
46# include <VBox/dbg.h>
47#endif
48
49#include <iprt/assert.h>
50#include <iprt/getopt.h>
51#include <iprt/string.h>
52
53
54/*********************************************************************************************************************************
55* Internal Functions *
56*********************************************************************************************************************************/
57static FNDBGFINFOARGVINT iemR3InfoITlb;
58static FNDBGFINFOARGVINT iemR3InfoDTlb;
59#ifdef VBOX_WITH_DEBUGGER
60static void iemR3RegisterDebuggerCommands(void);
61#endif
62
63
64#if !defined(VBOX_VMM_TARGET_ARMV8)
65static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
66{
67 switch (enmTargetCpu)
68 {
69#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
70 CASE_RET_STR(IEMTARGETCPU_8086);
71 CASE_RET_STR(IEMTARGETCPU_V20);
72 CASE_RET_STR(IEMTARGETCPU_186);
73 CASE_RET_STR(IEMTARGETCPU_286);
74 CASE_RET_STR(IEMTARGETCPU_386);
75 CASE_RET_STR(IEMTARGETCPU_486);
76 CASE_RET_STR(IEMTARGETCPU_PENTIUM);
77 CASE_RET_STR(IEMTARGETCPU_PPRO);
78 CASE_RET_STR(IEMTARGETCPU_CURRENT);
79#undef CASE_RET_STR
80 default: return "Unknown";
81 }
82}
83#endif
84
85
86/**
87 * Initializes the interpreted execution manager.
88 *
89 * This must be called after CPUM as we're quering information from CPUM about
90 * the guest and host CPUs.
91 *
92 * @returns VBox status code.
93 * @param pVM The cross context VM structure.
94 */
95VMMR3DECL(int) IEMR3Init(PVM pVM)
96{
97#if !defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)
98 /*
99 * Read configuration.
100 */
101 PCFGMNODE pIem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "IEM");
102
103 /** @cfgm{/IEM/CpuIdHostCall, boolean, false}
104 * Controls whether the custom VBox specific CPUID host call interface is
105 * enabled or not. */
106# ifdef DEBUG_bird
107 int rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, true);
108# else
109 int rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, false);
110# endif
111 AssertLogRelRCReturn(rc, rc);
112#endif
113
114 /*
115 * Initialize per-CPU data and register statistics.
116 */
117 uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
118 uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
119
120 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
121 {
122 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
123 AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
124
125 pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
126 pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
127
128 STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
129 "Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
130 STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
131 "Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
132 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
133 "Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
134 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
135 "VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
136 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
137 "VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
138 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
139 "Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
140 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
141 "Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
142 STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
143 "Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
144 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
145 "Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
146
147#ifdef VBOX_WITH_STATISTICS
148 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
149 "Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
150 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
151 "Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
152#endif
153 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
154 "Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
155 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
156 "Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
157 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
158 "Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
159 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
160 "Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
161
162 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
163 "Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
164 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
165 "Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
166 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
167 "Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
168
169 for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
170 STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
171 "", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
172 for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
173 STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
174 "", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
175
176#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
177 /* Instruction statistics: */
178# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
179 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
180 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
181 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
182 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
183# include "IEMInstructionStatisticsTmpl.h"
184# undef IEM_DO_INSTR_STAT
185#endif
186
187 /*
188 * Host and guest CPU information.
189 */
190 if (idCpu == 0)
191 {
192 pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
193 pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
194#if !defined(VBOX_VMM_TARGET_ARMV8)
195 pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
196 || pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /*??*/
197 ? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
198# if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
199 if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
200 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
201 else
202# endif
203 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
204#else
205 pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
206 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
207#endif
208
209#if !defined(VBOX_VMM_TARGET_ARMV8) && (IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC)
210 switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
211 {
212 case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
213 case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
214 case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
215 case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
216 case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
217 case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
218 case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
219 case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
220 case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
221 default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
222 }
223 LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
224 iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
225 pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
226#else
227 LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
228 CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
229 pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
230#endif
231 }
232 else
233 {
234 pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
235 pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
236 pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
237 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
238#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
239 pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
240#endif
241 }
242
243 /*
244 * Mark all buffers free.
245 */
246 uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
247 while (iMemMap-- > 0)
248 pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
249 }
250
251#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX)
252 /*
253 * Register the per-VM VMX APIC-access page handler type.
254 */
255 if (pVM->cpum.ro.GuestFeatures.fVmx)
256 {
257 rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, PGMPHYSHANDLER_F_NOT_IN_HM,
258 iemVmxApicAccessPageHandler,
259 "VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
260 AssertLogRelRCReturn(rc, rc);
261 }
262#endif
263
264 DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
265 DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
266#ifdef VBOX_WITH_DEBUGGER
267 iemR3RegisterDebuggerCommands();
268#endif
269
270 return VINF_SUCCESS;
271}
272
273
274VMMR3DECL(int) IEMR3Term(PVM pVM)
275{
276 NOREF(pVM);
277 return VINF_SUCCESS;
278}
279
280
281VMMR3DECL(void) IEMR3Relocate(PVM pVM)
282{
283 RT_NOREF(pVM);
284}
285
286
287/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
288static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb, bool *pfHeader)
289{
290 if (*pfHeader)
291 return;
292 pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
293 *pfHeader = true;
294}
295
296
297/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
298static void iemR3InfoTlbPrintSlot(PCDBGFINFOHLP pHlp, IEMTLB const *pTlb, IEMTLBENTRY const *pTlbe, uint32_t uSlot)
299{
300 pHlp->pfnPrintf(pHlp, "%02x: %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s/%s%s%s/%s %s\n",
301 uSlot,
302 (pTlbe->uTag & IEMTLB_REVISION_MASK) == pTlb->uTlbRevision ? "valid "
303 : (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
304 : "expired",
305 (pTlbe->uTag & ~IEMTLB_REVISION_MASK) << X86_PAGE_SHIFT,
306 pTlbe->GCPhys, pTlbe->pbMappingR3,
307 (uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
308 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "NX" : " X",
309 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "RO" : "RW",
310 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
311 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
312 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
313 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
314 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "U" : "-",
315 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "S" : "M",
316 (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
317 : (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired");
318}
319
320
321/** Displays one or more TLB slots. */
322static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
323 uint32_t uSlot, uint32_t cSlots, bool *pfHeader)
324{
325 if (uSlot < RT_ELEMENTS(pTlb->aEntries))
326 {
327 if (cSlots > RT_ELEMENTS(pTlb->aEntries))
328 {
329 pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
330 cSlots, RT_ELEMENTS(pTlb->aEntries));
331 cSlots = RT_ELEMENTS(pTlb->aEntries);
332 }
333
334 iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
335 while (cSlots-- > 0)
336 {
337 IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
338 iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
339 uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
340 }
341 }
342 else
343 pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
344 uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
345}
346
347
348/** Displays the TLB slot for the given address. */
349static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
350 uint64_t uAddress, bool *pfHeader)
351{
352 iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
353
354 uint64_t const uTag = (uAddress << 16) >> (X86_PAGE_SHIFT + 16);
355 uint32_t const uSlot = (uint8_t)uTag;
356 IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
357 pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
358 Tlbe.uTag == (uTag | pTlb->uTlbRevision) ? "match"
359 : (Tlbe.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
360 iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
361}
362
363
364/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
365static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
366{
367 /*
368 * This is entirely argument driven.
369 */
370 static RTGETOPTDEF const s_aOptions[] =
371 {
372 { "--cpu", 'c', RTGETOPT_REQ_UINT32 },
373 { "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
374 { "all", 'A', RTGETOPT_REQ_NOTHING },
375 { "--all", 'A', RTGETOPT_REQ_NOTHING },
376 { "--address", 'a', RTGETOPT_REQ_UINT64 | RTGETOPT_FLAG_HEX },
377 { "--range", 'r', RTGETOPT_REQ_UINT32_PAIR | RTGETOPT_FLAG_HEX },
378 { "--slot", 's', RTGETOPT_REQ_UINT32 | RTGETOPT_FLAG_HEX },
379 };
380
381 char szDefault[] = "-A";
382 char *papszDefaults[2] = { szDefault, NULL };
383 if (cArgs == 0)
384 {
385 cArgs = 1;
386 papszArgs = papszDefaults;
387 }
388
389 RTGETOPTSTATE State;
390 int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /*iFirst*/, 0 /*fFlags*/);
391 AssertRCReturnVoid(rc);
392
393 bool fNeedHeader = true;
394 bool fAddressMode = true;
395 PVMCPU pVCpu = VMMGetCpu(pVM);
396 if (!pVCpu)
397 pVCpu = VMMGetCpuById(pVM, 0);
398
399 RTGETOPTUNION ValueUnion;
400 while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
401 {
402 switch (rc)
403 {
404 case 'c':
405 if (ValueUnion.u32 >= pVM->cCpus)
406 pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
407 else if (!pVCpu || pVCpu->idCpu != ValueUnion.u32)
408 {
409 pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
410 fNeedHeader = true;
411 }
412 break;
413
414 case 'a':
415 iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
416 ValueUnion.u64, &fNeedHeader);
417 fAddressMode = true;
418 break;
419
420 case 'A':
421 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
422 0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), &fNeedHeader);
423 break;
424
425 case 'r':
426 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
427 ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, &fNeedHeader);
428 fAddressMode = false;
429 break;
430
431 case 's':
432 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
433 ValueUnion.u32, 1, &fNeedHeader);
434 fAddressMode = false;
435 break;
436
437 case VINF_GETOPT_NOT_OPTION:
438 if (fAddressMode)
439 {
440 uint64_t uAddr;
441 rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
442 if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
443 iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
444 uAddr, &fNeedHeader);
445 else
446 pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
447 }
448 else
449 {
450 uint32_t uSlot;
451 rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
452 if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
453 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
454 uSlot, 1, &fNeedHeader);
455 else
456 pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
457 }
458 break;
459
460 case 'h':
461 pHlp->pfnPrintf(pHlp,
462 "Usage: info %ctlb [options]\n"
463 "\n"
464 "Options:\n"
465 " -c<n>, --cpu=<n>, --vcpu=<n>\n"
466 " Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
467 " -A, --all, all\n"
468 " Display all the TLB entries (default if no other args).\n"
469 " -a<virt>, --address=<virt>\n"
470 " Shows the TLB entry for the specified guest virtual address.\n"
471 " -r<slot:count>, --range=<slot:count>\n"
472 " Shows the TLB entries for the specified slot range.\n"
473 " -s<slot>,--slot=<slot>\n"
474 " Shows the given TLB slot.\n"
475 "\n"
476 "Non-options are interpreted according to the last -a, -r or -s option,\n"
477 "defaulting to addresses if not preceeded by any of those options.\n"
478 , fITlb ? 'i' : 'd');
479 return;
480
481 default:
482 pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
483 return;
484 }
485 }
486}
487
488
489/**
490 * @callback_method_impl{FNDBGFINFOARGVINT, itlb}
491 */
492static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
493{
494 return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /*fITlb*/);
495}
496
497
498/**
499 * @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
500 */
501static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
502{
503 return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /*fITlb*/);
504}
505
506
507#ifdef VBOX_WITH_DEBUGGER
508
509/** @callback_method_impl{FNDBGCCMD,
510 * Implements the '.alliem' command. }
511 */
512static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
513{
514 VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
515 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
516 if (pVCpu)
517 {
518 VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAll, 1, pVCpu);
519 return VINF_SUCCESS;
520 }
521 RT_NOREF(paArgs, cArgs);
522 return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
523}
524
525
526/**
527 * Called by IEMR3Init to register debugger commands.
528 */
529static void iemR3RegisterDebuggerCommands(void)
530{
531 /*
532 * Register debugger commands.
533 */
534 static DBGCCMD const s_aCmds[] =
535 {
536 {
537 /* .pszCmd = */ "iemflushtlb",
538 /* .cArgsMin = */ 0,
539 /* .cArgsMax = */ 0,
540 /* .paArgDescs = */ NULL,
541 /* .cArgDescs = */ 0,
542 /* .fFlags = */ 0,
543 /* .pfnHandler = */ iemR3DbgFlushTlbs,
544 /* .pszSyntax = */ "",
545 /* .pszDescription = */ "Flushed the code and data TLBs"
546 },
547 };
548
549 int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
550 AssertLogRelRC(rc);
551}
552
553#endif
554
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